./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 54858612 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ab3c8e786b7a020c9c7c3a4249de38e06543ca10 .................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.0-5485861 [2020-10-26 05:48:10,536 INFO L177 SettingsManager]: Resetting all preferences to default values... [2020-10-26 05:48:10,539 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2020-10-26 05:48:10,575 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2020-10-26 05:48:10,575 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2020-10-26 05:48:10,577 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2020-10-26 05:48:10,579 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2020-10-26 05:48:10,581 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2020-10-26 05:48:10,583 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2020-10-26 05:48:10,585 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2020-10-26 05:48:10,586 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2020-10-26 05:48:10,588 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2020-10-26 05:48:10,589 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2020-10-26 05:48:10,590 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2020-10-26 05:48:10,592 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2020-10-26 05:48:10,594 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2020-10-26 05:48:10,595 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2020-10-26 05:48:10,596 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2020-10-26 05:48:10,598 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2020-10-26 05:48:10,600 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2020-10-26 05:48:10,602 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2020-10-26 05:48:10,604 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2020-10-26 05:48:10,606 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2020-10-26 05:48:10,607 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2020-10-26 05:48:10,610 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2020-10-26 05:48:10,613 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2020-10-26 05:48:10,616 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2020-10-26 05:48:10,617 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2020-10-26 05:48:10,618 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2020-10-26 05:48:10,618 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2020-10-26 05:48:10,619 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2020-10-26 05:48:10,620 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2020-10-26 05:48:10,620 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2020-10-26 05:48:10,621 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2020-10-26 05:48:10,623 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2020-10-26 05:48:10,623 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2020-10-26 05:48:10,626 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2020-10-26 05:48:10,626 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2020-10-26 05:48:10,626 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2020-10-26 05:48:10,628 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2020-10-26 05:48:10,630 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2020-10-26 05:48:10,631 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2020-10-26 05:48:10,695 INFO L113 SettingsManager]: Loading preferences was successful [2020-10-26 05:48:10,698 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2020-10-26 05:48:10,699 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2020-10-26 05:48:10,700 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2020-10-26 05:48:10,700 INFO L138 SettingsManager]: * Use SBE=true [2020-10-26 05:48:10,700 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2020-10-26 05:48:10,700 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2020-10-26 05:48:10,700 INFO L138 SettingsManager]: * Use old map elimination=false [2020-10-26 05:48:10,701 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2020-10-26 05:48:10,701 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2020-10-26 05:48:10,701 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2020-10-26 05:48:10,701 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2020-10-26 05:48:10,701 INFO L138 SettingsManager]: * sizeof long=4 [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * sizeof POINTER=4 [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2020-10-26 05:48:10,702 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2020-10-26 05:48:10,703 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2020-10-26 05:48:10,703 INFO L138 SettingsManager]: * sizeof long double=12 [2020-10-26 05:48:10,703 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2020-10-26 05:48:10,703 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2020-10-26 05:48:10,704 INFO L138 SettingsManager]: * Use constant arrays=true [2020-10-26 05:48:10,704 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2020-10-26 05:48:10,704 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2020-10-26 05:48:10,704 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2020-10-26 05:48:10,704 INFO L138 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2020-10-26 05:48:10,705 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2020-10-26 05:48:10,705 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2020-10-26 05:48:10,705 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2020-10-26 05:48:10,705 INFO L138 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2020-10-26 05:48:10,706 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2020-10-26 05:48:10,707 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ab3c8e786b7a020c9c7c3a4249de38e06543ca10 [2020-10-26 05:48:11,074 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2020-10-26 05:48:11,110 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2020-10-26 05:48:11,115 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2020-10-26 05:48:11,117 INFO L271 PluginConnector]: Initializing CDTParser... [2020-10-26 05:48:11,118 INFO L275 PluginConnector]: CDTParser initialized [2020-10-26 05:48:11,119 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.05.cil.c [2020-10-26 05:48:11,215 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202696125/b5d5dcd1a576458d9f8bb3748c18fcef/FLAG4a9b48e93 [2020-10-26 05:48:11,874 INFO L306 CDTParser]: Found 1 translation units. [2020-10-26 05:48:11,880 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.05.cil.c [2020-10-26 05:48:11,905 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202696125/b5d5dcd1a576458d9f8bb3748c18fcef/FLAG4a9b48e93 [2020-10-26 05:48:12,239 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/202696125/b5d5dcd1a576458d9f8bb3748c18fcef [2020-10-26 05:48:12,245 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2020-10-26 05:48:12,254 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2020-10-26 05:48:12,256 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2020-10-26 05:48:12,256 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2020-10-26 05:48:12,260 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2020-10-26 05:48:12,261 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,269 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@c12c7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12, skipping insertion in model container [2020-10-26 05:48:12,270 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,278 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2020-10-26 05:48:12,368 INFO L178 MainTranslator]: Built tables and reachable declarations [2020-10-26 05:48:12,611 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:48:12,623 INFO L203 MainTranslator]: Completed pre-run [2020-10-26 05:48:12,693 INFO L206 PostProcessor]: Analyzing one entry point: main [2020-10-26 05:48:12,721 INFO L208 MainTranslator]: Completed translation [2020-10-26 05:48:12,721 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12 WrapperNode [2020-10-26 05:48:12,722 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2020-10-26 05:48:12,723 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2020-10-26 05:48:12,723 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2020-10-26 05:48:12,723 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2020-10-26 05:48:12,732 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,744 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,822 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2020-10-26 05:48:12,823 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2020-10-26 05:48:12,823 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2020-10-26 05:48:12,823 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2020-10-26 05:48:12,836 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,836 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,843 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,843 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,864 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,881 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,886 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... [2020-10-26 05:48:12,897 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2020-10-26 05:48:12,901 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2020-10-26 05:48:12,901 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2020-10-26 05:48:12,901 INFO L275 PluginConnector]: RCFGBuilder initialized [2020-10-26 05:48:12,902 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2020-10-26 05:48:12,996 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2020-10-26 05:48:12,996 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2020-10-26 05:48:12,997 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2020-10-26 05:48:12,997 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2020-10-26 05:48:14,484 INFO L293 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2020-10-26 05:48:14,484 INFO L298 CfgBuilder]: Removed 183 assume(true) statements. [2020-10-26 05:48:14,487 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:14 BoogieIcfgContainer [2020-10-26 05:48:14,487 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2020-10-26 05:48:14,488 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2020-10-26 05:48:14,489 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2020-10-26 05:48:14,492 INFO L275 PluginConnector]: BuchiAutomizer initialized [2020-10-26 05:48:14,493 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:14,493 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 26.10 05:48:12" (1/3) ... [2020-10-26 05:48:14,495 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2dfda103 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:48:14, skipping insertion in model container [2020-10-26 05:48:14,495 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:14,495 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.10 05:48:12" (2/3) ... [2020-10-26 05:48:14,495 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2dfda103 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 26.10 05:48:14, skipping insertion in model container [2020-10-26 05:48:14,496 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2020-10-26 05:48:14,496 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:14" (3/3) ... [2020-10-26 05:48:14,497 INFO L373 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2020-10-26 05:48:14,544 INFO L359 BuchiCegarLoop]: Interprodecural is true [2020-10-26 05:48:14,544 INFO L360 BuchiCegarLoop]: Hoare is false [2020-10-26 05:48:14,545 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2020-10-26 05:48:14,545 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2020-10-26 05:48:14,545 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2020-10-26 05:48:14,545 INFO L364 BuchiCegarLoop]: Difference is false [2020-10-26 05:48:14,545 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2020-10-26 05:48:14,545 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2020-10-26 05:48:14,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 486 states. [2020-10-26 05:48:14,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 [2020-10-26 05:48:14,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:14,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:14,667 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,667 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,667 INFO L427 BuchiCegarLoop]: ======== Iteration 1============ [2020-10-26 05:48:14,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 486 states. [2020-10-26 05:48:14,682 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 [2020-10-26 05:48:14,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:14,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:14,687 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,687 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:14,697 INFO L794 eck$LassoCheckResult]: Stem: 339#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 276#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 357#L855true havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 200#L386true assume !(1 == ~m_i~0);~m_st~0 := 2; 458#L393-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 147#L398-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 393#L403-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 201#L408-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 97#L413-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 345#L418-1true assume !(0 == ~M_E~0); 106#L578-1true assume !(0 == ~T1_E~0); 349#L583-1true assume !(0 == ~T2_E~0); 9#L588-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 310#L593-1true assume !(0 == ~T4_E~0); 75#L598-1true assume !(0 == ~T5_E~0); 439#L603-1true assume !(0 == ~E_1~0); 245#L608-1true assume !(0 == ~E_2~0); 471#L613-1true assume !(0 == ~E_3~0); 157#L618-1true assume !(0 == ~E_4~0); 410#L623-1true assume !(0 == ~E_5~0); 207#L628-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 372#L271true assume 1 == ~m_pc~0; 452#L272true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 374#L282true is_master_triggered_#res := is_master_triggered_~__retres1~0; 453#L283true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 484#L712true assume !(0 != activate_threads_~tmp~1); 485#L712-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 63#L290true assume 1 == ~t1_pc~0; 142#L291true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 64#L301true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143#L302true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18#L720true assume !(0 != activate_threads_~tmp___0~0); 3#L720-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 204#L309true assume !(1 == ~t2_pc~0); 190#L309-2true is_transmit2_triggered_~__retres1~2 := 0; 203#L320true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 151#L321true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 173#L728true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 175#L728-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 329#L328true assume 1 == ~t3_pc~0; 279#L329true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 328#L339true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 277#L340true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 315#L736true assume !(0 != activate_threads_~tmp___2~0); 303#L736-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 101#L347true assume !(1 == ~t4_pc~0); 84#L347-2true is_transmit4_triggered_~__retres1~4 := 0; 100#L358true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 394#L359true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 421#L744true assume !(0 != activate_threads_~tmp___3~0); 423#L744-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 231#L366true assume 1 == ~t5_pc~0; 67#L367true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 229#L377true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 66#L378true activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 80#L752true assume !(0 != activate_threads_~tmp___4~0); 69#L752-2true assume !(1 == ~M_E~0); 244#L641-1true assume !(1 == ~T1_E~0); 487#L646-1true assume !(1 == ~T2_E~0); 178#L651-1true assume !(1 == ~T3_E~0); 426#L656-1true assume !(1 == ~T4_E~0); 206#L661-1true assume !(1 == ~T5_E~0); 103#L666-1true assume 1 == ~E_1~0;~E_1~0 := 2; 347#L671-1true assume !(1 == ~E_2~0); 4#L676-1true assume !(1 == ~E_3~0); 305#L681-1true assume !(1 == ~E_4~0); 70#L686-1true assume !(1 == ~E_5~0); 337#L892-1true [2020-10-26 05:48:14,699 INFO L796 eck$LassoCheckResult]: Loop: 337#L892-1true assume !false; 180#L893true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 238#L553true assume !true; 412#L568true start_simulation_~kernel_st~0 := 2; 202#L386-1true start_simulation_~kernel_st~0 := 3; 107#L578-2true assume 0 == ~M_E~0;~M_E~0 := 1; 93#L578-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 342#L583-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 128#L588-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 294#L593-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 58#L598-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 435#L603-3true assume !(0 == ~E_1~0); 241#L608-3true assume 0 == ~E_2~0;~E_2~0 := 1; 478#L613-3true assume 0 == ~E_3~0;~E_3~0 := 1; 162#L618-3true assume 0 == ~E_4~0;~E_4~0 := 1; 415#L623-3true assume 0 == ~E_5~0;~E_5~0 := 1; 209#L628-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 480#L271-18true assume 1 == ~m_pc~0; 456#L272-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 363#L282-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 457#L283-6true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 455#L712-18true assume !(0 != activate_threads_~tmp~1); 444#L712-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5#L290-18true assume 1 == ~t1_pc~0; 114#L291-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24#L301-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 115#L302-6true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 119#L720-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 120#L720-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 172#L309-18true assume 1 == ~t2_pc~0; 263#L310-6true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 196#L320-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 262#L321-6true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 261#L728-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 247#L728-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 314#L328-18true assume 1 == ~t3_pc~0; 270#L329-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 323#L339-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 268#L340-6true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 269#L736-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 274#L736-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 419#L347-18true assume !(1 == ~t4_pc~0); 422#L347-20true is_transmit4_triggered_~__retres1~4 := 0; 90#L358-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 382#L359-6true activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 384#L744-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 365#L744-20true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 79#L366-18true assume 1 == ~t5_pc~0; 32#L367-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 222#L377-6true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31#L378-6true activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 33#L752-18true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 38#L752-20true assume 1 == ~M_E~0;~M_E~0 := 2; 240#L641-3true assume !(1 == ~T1_E~0); 474#L646-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 160#L651-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 413#L656-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 208#L661-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 104#L666-3true assume 1 == ~E_1~0;~E_1~0 := 2; 348#L671-3true assume 1 == ~E_2~0;~E_2~0 := 2; 8#L676-3true assume 1 == ~E_3~0;~E_3~0 := 2; 308#L681-3true assume !(1 == ~E_4~0); 74#L686-3true assume 1 == ~E_5~0;~E_5~0 := 2; 438#L691-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 145#L431-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 198#L463-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 169#L464-1true start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 447#L911true assume !(0 == start_simulation_~tmp~3); 440#L911-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 149#L431-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 199#L463-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 146#L464-2true stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 356#L866true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 77#L873true stop_simulation_#res := stop_simulation_~__retres2~0; 29#L874true start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 354#L924true assume !(0 != start_simulation_~tmp___0~1); 337#L892-1true [2020-10-26 05:48:14,707 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:14,707 INFO L82 PathProgramCache]: Analyzing trace with hash -1450413925, now seen corresponding path program 1 times [2020-10-26 05:48:14,718 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:14,718 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862216419] [2020-10-26 05:48:14,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:14,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,003 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862216419] [2020-10-26 05:48:15,004 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,004 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,005 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71764464] [2020-10-26 05:48:15,013 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:15,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1138414586, now seen corresponding path program 1 times [2020-10-26 05:48:15,016 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,017 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414354394] [2020-10-26 05:48:15,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,096 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,097 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414354394] [2020-10-26 05:48:15,098 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,098 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:15,098 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412756621] [2020-10-26 05:48:15,102 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,104 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,120 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,122 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,123 INFO L87 Difference]: Start difference. First operand 486 states. Second operand 3 states. [2020-10-26 05:48:15,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,187 INFO L93 Difference]: Finished difference Result 485 states and 733 transitions. [2020-10-26 05:48:15,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 485 states and 733 transitions. [2020-10-26 05:48:15,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 485 states to 480 states and 728 transitions. [2020-10-26 05:48:15,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:15,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:15,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 728 transitions. [2020-10-26 05:48:15,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,214 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2020-10-26 05:48:15,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 728 transitions. [2020-10-26 05:48:15,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:15,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:15,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 728 transitions. [2020-10-26 05:48:15,280 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2020-10-26 05:48:15,281 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 728 transitions. [2020-10-26 05:48:15,281 INFO L427 BuchiCegarLoop]: ======== Iteration 2============ [2020-10-26 05:48:15,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 728 transitions. [2020-10-26 05:48:15,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,296 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,296 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,297 INFO L794 eck$LassoCheckResult]: Stem: 1377#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1335#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1336#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1269#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 1270#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1200#L398-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1201#L403-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1271#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1143#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1144#L418-1 assume !(0 == ~M_E~0); 1161#L578-1 assume !(0 == ~T1_E~0); 1162#L583-1 assume !(0 == ~T2_E~0); 993#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 994#L593-1 assume !(0 == ~T4_E~0); 1107#L598-1 assume !(0 == ~T5_E~0); 1108#L603-1 assume !(0 == ~E_1~0); 1304#L608-1 assume !(0 == ~E_2~0); 1305#L613-1 assume !(0 == ~E_3~0); 1220#L618-1 assume !(0 == ~E_4~0); 1221#L623-1 assume !(0 == ~E_5~0); 1274#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1275#L271 assume 1 == ~m_pc~0; 1404#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1407#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1408#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1448#L712 assume !(0 != activate_threads_~tmp~1); 1459#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1090#L290 assume 1 == ~t1_pc~0; 1091#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1082#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1092#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1011#L720 assume !(0 != activate_threads_~tmp___0~0); 980#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 981#L309 assume !(1 == ~t2_pc~0); 1211#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 1210#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1207#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1208#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1245#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1247#L328 assume 1 == ~t3_pc~0; 1341#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1342#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1337#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1338#L736 assume !(0 != activate_threads_~tmp___2~0); 1372#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1151#L347 assume !(1 == ~t4_pc~0); 1114#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 1115#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1150#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1429#L744 assume !(0 != activate_threads_~tmp___3~0); 1439#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1293#L366 assume 1 == ~t5_pc~0; 1095#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1096#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1093#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1094#L752 assume !(0 != activate_threads_~tmp___4~0); 1099#L752-2 assume !(1 == ~M_E~0); 1100#L641-1 assume !(1 == ~T1_E~0); 1303#L646-1 assume !(1 == ~T2_E~0); 1249#L651-1 assume !(1 == ~T3_E~0); 1250#L656-1 assume !(1 == ~T4_E~0); 1273#L661-1 assume !(1 == ~T5_E~0); 1154#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1155#L671-1 assume !(1 == ~E_2~0); 982#L676-1 assume !(1 == ~E_3~0); 983#L681-1 assume !(1 == ~E_4~0); 1101#L686-1 assume !(1 == ~E_5~0); 1102#L892-1 [2020-10-26 05:48:15,300 INFO L796 eck$LassoCheckResult]: Loop: 1102#L892-1 assume !false; 1253#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1160#L553 assume !false; 1279#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1235#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1136#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1233#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1186#L478 assume !(0 != eval_~tmp~0); 1188#L568 start_simulation_~kernel_st~0 := 2; 1272#L386-1 start_simulation_~kernel_st~0 := 3; 1163#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1133#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1134#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1184#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1185#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1083#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1084#L603-3 assume !(0 == ~E_1~0); 1297#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1298#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1229#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1230#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1277#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1278#L271-18 assume 1 == ~m_pc~0; 1450#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1392#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1393#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1449#L712-18 assume !(0 != activate_threads_~tmp~1); 1443#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 984#L290-18 assume 1 == ~t1_pc~0; 985#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1012#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1020#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1171#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1174#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1175#L309-18 assume !(1 == ~t2_pc~0); 1243#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 1246#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1267#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1317#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1308#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1309#L328-18 assume 1 == ~t3_pc~0; 1324#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1325#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1321#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1322#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1323#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1333#L347-18 assume 1 == ~t4_pc~0; 1419#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1126#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1127#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1418#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1394#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1110#L366-18 assume 1 == ~t5_pc~0; 1033#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1034#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1031#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1032#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1036#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1046#L641-3 assume !(1 == ~T1_E~0); 1296#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1226#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1227#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1276#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1156#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1157#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 991#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 992#L681-3 assume !(1 == ~E_4~0); 1105#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1106#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1197#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1141#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1237#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1238#L911 assume !(0 == start_simulation_~tmp~3); 1008#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1204#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1148#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1198#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 1199#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1109#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 1028#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1029#L924 assume !(0 != start_simulation_~tmp___0~1); 1102#L892-1 [2020-10-26 05:48:15,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,301 INFO L82 PathProgramCache]: Analyzing trace with hash -1396021027, now seen corresponding path program 1 times [2020-10-26 05:48:15,301 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,302 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882890119] [2020-10-26 05:48:15,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,405 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882890119] [2020-10-26 05:48:15,405 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,405 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,406 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175900405] [2020-10-26 05:48:15,406 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:15,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,407 INFO L82 PathProgramCache]: Analyzing trace with hash 2117196334, now seen corresponding path program 1 times [2020-10-26 05:48:15,407 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,407 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639090921] [2020-10-26 05:48:15,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,494 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639090921] [2020-10-26 05:48:15,494 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,495 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,495 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310751362] [2020-10-26 05:48:15,495 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,496 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,497 INFO L87 Difference]: Start difference. First operand 480 states and 728 transitions. cyclomatic complexity: 249 Second operand 3 states. [2020-10-26 05:48:15,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,516 INFO L93 Difference]: Finished difference Result 480 states and 727 transitions. [2020-10-26 05:48:15,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 727 transitions. [2020-10-26 05:48:15,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 727 transitions. [2020-10-26 05:48:15,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:15,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:15,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 727 transitions. [2020-10-26 05:48:15,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,531 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2020-10-26 05:48:15,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 727 transitions. [2020-10-26 05:48:15,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:15,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:15,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 727 transitions. [2020-10-26 05:48:15,549 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2020-10-26 05:48:15,549 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 727 transitions. [2020-10-26 05:48:15,550 INFO L427 BuchiCegarLoop]: ======== Iteration 3============ [2020-10-26 05:48:15,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 727 transitions. [2020-10-26 05:48:15,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,555 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,555 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,556 INFO L794 eck$LassoCheckResult]: Stem: 2344#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2302#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2303#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2236#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 2237#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2167#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2168#L403-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2238#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2110#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2111#L418-1 assume !(0 == ~M_E~0); 2128#L578-1 assume !(0 == ~T1_E~0); 2129#L583-1 assume !(0 == ~T2_E~0); 1960#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1961#L593-1 assume !(0 == ~T4_E~0); 2074#L598-1 assume !(0 == ~T5_E~0); 2075#L603-1 assume !(0 == ~E_1~0); 2271#L608-1 assume !(0 == ~E_2~0); 2272#L613-1 assume !(0 == ~E_3~0); 2187#L618-1 assume !(0 == ~E_4~0); 2188#L623-1 assume !(0 == ~E_5~0); 2241#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2242#L271 assume 1 == ~m_pc~0; 2371#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2374#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2375#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2415#L712 assume !(0 != activate_threads_~tmp~1); 2426#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2057#L290 assume 1 == ~t1_pc~0; 2058#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2049#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2059#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1978#L720 assume !(0 != activate_threads_~tmp___0~0); 1947#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1948#L309 assume !(1 == ~t2_pc~0); 2178#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 2177#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2174#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2175#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2212#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2214#L328 assume 1 == ~t3_pc~0; 2308#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2309#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2304#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2305#L736 assume !(0 != activate_threads_~tmp___2~0); 2339#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2118#L347 assume !(1 == ~t4_pc~0); 2081#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 2082#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2117#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2396#L744 assume !(0 != activate_threads_~tmp___3~0); 2406#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2260#L366 assume 1 == ~t5_pc~0; 2062#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2063#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2060#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2061#L752 assume !(0 != activate_threads_~tmp___4~0); 2066#L752-2 assume !(1 == ~M_E~0); 2067#L641-1 assume !(1 == ~T1_E~0); 2270#L646-1 assume !(1 == ~T2_E~0); 2216#L651-1 assume !(1 == ~T3_E~0); 2217#L656-1 assume !(1 == ~T4_E~0); 2240#L661-1 assume !(1 == ~T5_E~0); 2121#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2122#L671-1 assume !(1 == ~E_2~0); 1949#L676-1 assume !(1 == ~E_3~0); 1950#L681-1 assume !(1 == ~E_4~0); 2068#L686-1 assume !(1 == ~E_5~0); 2069#L892-1 [2020-10-26 05:48:15,556 INFO L796 eck$LassoCheckResult]: Loop: 2069#L892-1 assume !false; 2220#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2127#L553 assume !false; 2246#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2202#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2103#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2200#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2153#L478 assume !(0 != eval_~tmp~0); 2155#L568 start_simulation_~kernel_st~0 := 2; 2239#L386-1 start_simulation_~kernel_st~0 := 3; 2130#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2100#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2101#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2151#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2152#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2050#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2051#L603-3 assume !(0 == ~E_1~0); 2264#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2265#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2196#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2197#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2244#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2245#L271-18 assume 1 == ~m_pc~0; 2417#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2359#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2360#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2416#L712-18 assume !(0 != activate_threads_~tmp~1); 2410#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1951#L290-18 assume 1 == ~t1_pc~0; 1952#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1979#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1987#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2138#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2141#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2142#L309-18 assume !(1 == ~t2_pc~0); 2210#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 2213#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2234#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2284#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2275#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2276#L328-18 assume 1 == ~t3_pc~0; 2291#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2292#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2288#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2289#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2290#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2300#L347-18 assume 1 == ~t4_pc~0; 2386#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2093#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2094#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2385#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2361#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2077#L366-18 assume 1 == ~t5_pc~0; 2000#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2001#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1998#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1999#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2003#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2013#L641-3 assume !(1 == ~T1_E~0); 2263#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2193#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2194#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2243#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2123#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2124#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1958#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1959#L681-3 assume !(1 == ~E_4~0); 2072#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2073#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2164#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2108#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2204#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2205#L911 assume !(0 == start_simulation_~tmp~3); 1975#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2171#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2115#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2165#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 2166#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2076#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 1995#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1996#L924 assume !(0 != start_simulation_~tmp___0~1); 2069#L892-1 [2020-10-26 05:48:15,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,557 INFO L82 PathProgramCache]: Analyzing trace with hash -2075293281, now seen corresponding path program 1 times [2020-10-26 05:48:15,557 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,557 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954066462] [2020-10-26 05:48:15,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,630 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954066462] [2020-10-26 05:48:15,631 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,631 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,631 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254319203] [2020-10-26 05:48:15,631 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:15,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,632 INFO L82 PathProgramCache]: Analyzing trace with hash 2117196334, now seen corresponding path program 2 times [2020-10-26 05:48:15,632 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,633 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499000264] [2020-10-26 05:48:15,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,702 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499000264] [2020-10-26 05:48:15,702 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,702 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,703 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847692740] [2020-10-26 05:48:15,703 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,704 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,704 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,704 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,705 INFO L87 Difference]: Start difference. First operand 480 states and 727 transitions. cyclomatic complexity: 248 Second operand 3 states. [2020-10-26 05:48:15,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,722 INFO L93 Difference]: Finished difference Result 480 states and 726 transitions. [2020-10-26 05:48:15,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 726 transitions. [2020-10-26 05:48:15,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 726 transitions. [2020-10-26 05:48:15,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:15,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:15,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 726 transitions. [2020-10-26 05:48:15,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,734 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2020-10-26 05:48:15,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 726 transitions. [2020-10-26 05:48:15,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:15,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:15,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 726 transitions. [2020-10-26 05:48:15,750 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2020-10-26 05:48:15,750 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 726 transitions. [2020-10-26 05:48:15,750 INFO L427 BuchiCegarLoop]: ======== Iteration 4============ [2020-10-26 05:48:15,752 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 726 transitions. [2020-10-26 05:48:15,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,758 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,758 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,758 INFO L794 eck$LassoCheckResult]: Stem: 3311#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3269#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3270#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3203#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 3204#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3134#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3135#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3205#L408-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3077#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3078#L418-1 assume !(0 == ~M_E~0); 3095#L578-1 assume !(0 == ~T1_E~0); 3096#L583-1 assume !(0 == ~T2_E~0); 2927#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2928#L593-1 assume !(0 == ~T4_E~0); 3041#L598-1 assume !(0 == ~T5_E~0); 3042#L603-1 assume !(0 == ~E_1~0); 3238#L608-1 assume !(0 == ~E_2~0); 3239#L613-1 assume !(0 == ~E_3~0); 3154#L618-1 assume !(0 == ~E_4~0); 3155#L623-1 assume !(0 == ~E_5~0); 3208#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3209#L271 assume 1 == ~m_pc~0; 3338#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3341#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3342#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3382#L712 assume !(0 != activate_threads_~tmp~1); 3393#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3024#L290 assume 1 == ~t1_pc~0; 3025#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3016#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3026#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2945#L720 assume !(0 != activate_threads_~tmp___0~0); 2914#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2915#L309 assume !(1 == ~t2_pc~0); 3145#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 3144#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3141#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3142#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3179#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3181#L328 assume 1 == ~t3_pc~0; 3275#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3276#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3271#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3272#L736 assume !(0 != activate_threads_~tmp___2~0); 3306#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3085#L347 assume !(1 == ~t4_pc~0); 3048#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 3049#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3084#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3363#L744 assume !(0 != activate_threads_~tmp___3~0); 3373#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3227#L366 assume 1 == ~t5_pc~0; 3029#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3030#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3027#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3028#L752 assume !(0 != activate_threads_~tmp___4~0); 3033#L752-2 assume !(1 == ~M_E~0); 3034#L641-1 assume !(1 == ~T1_E~0); 3237#L646-1 assume !(1 == ~T2_E~0); 3183#L651-1 assume !(1 == ~T3_E~0); 3184#L656-1 assume !(1 == ~T4_E~0); 3207#L661-1 assume !(1 == ~T5_E~0); 3088#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3089#L671-1 assume !(1 == ~E_2~0); 2916#L676-1 assume !(1 == ~E_3~0); 2917#L681-1 assume !(1 == ~E_4~0); 3035#L686-1 assume !(1 == ~E_5~0); 3036#L892-1 [2020-10-26 05:48:15,759 INFO L796 eck$LassoCheckResult]: Loop: 3036#L892-1 assume !false; 3187#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3094#L553 assume !false; 3213#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3169#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3070#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3167#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3120#L478 assume !(0 != eval_~tmp~0); 3122#L568 start_simulation_~kernel_st~0 := 2; 3206#L386-1 start_simulation_~kernel_st~0 := 3; 3097#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3067#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3068#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3118#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3119#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3017#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3018#L603-3 assume !(0 == ~E_1~0); 3231#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3232#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3163#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3164#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3211#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3212#L271-18 assume 1 == ~m_pc~0; 3384#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3326#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3327#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3383#L712-18 assume !(0 != activate_threads_~tmp~1); 3377#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2918#L290-18 assume 1 == ~t1_pc~0; 2919#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2946#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2954#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3105#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3108#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3109#L309-18 assume !(1 == ~t2_pc~0); 3177#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 3180#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3201#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3251#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3242#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3243#L328-18 assume 1 == ~t3_pc~0; 3258#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3259#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3255#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3256#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3257#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3267#L347-18 assume 1 == ~t4_pc~0; 3353#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3060#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3061#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3352#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3328#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3044#L366-18 assume 1 == ~t5_pc~0; 2967#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2968#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2965#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2966#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2970#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2980#L641-3 assume !(1 == ~T1_E~0); 3230#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3160#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3161#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3210#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3090#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3091#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2925#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2926#L681-3 assume !(1 == ~E_4~0); 3039#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3040#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3131#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3075#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3171#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3172#L911 assume !(0 == start_simulation_~tmp~3); 2942#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3138#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3082#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3132#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 3133#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3043#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 2962#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2963#L924 assume !(0 != start_simulation_~tmp___0~1); 3036#L892-1 [2020-10-26 05:48:15,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,759 INFO L82 PathProgramCache]: Analyzing trace with hash 258099357, now seen corresponding path program 1 times [2020-10-26 05:48:15,760 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,760 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93100877] [2020-10-26 05:48:15,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,797 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93100877] [2020-10-26 05:48:15,797 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,797 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,797 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938841984] [2020-10-26 05:48:15,798 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:15,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,799 INFO L82 PathProgramCache]: Analyzing trace with hash 2117196334, now seen corresponding path program 3 times [2020-10-26 05:48:15,799 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,799 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889428223] [2020-10-26 05:48:15,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:15,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:15,896 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889428223] [2020-10-26 05:48:15,897 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:15,897 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:15,897 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991362890] [2020-10-26 05:48:15,898 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:15,898 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:15,899 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:15,899 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:15,899 INFO L87 Difference]: Start difference. First operand 480 states and 726 transitions. cyclomatic complexity: 247 Second operand 3 states. [2020-10-26 05:48:15,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:15,913 INFO L93 Difference]: Finished difference Result 480 states and 725 transitions. [2020-10-26 05:48:15,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:15,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 725 transitions. [2020-10-26 05:48:15,919 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 725 transitions. [2020-10-26 05:48:15,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:15,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:15,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 725 transitions. [2020-10-26 05:48:15,926 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:15,927 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2020-10-26 05:48:15,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 725 transitions. [2020-10-26 05:48:15,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:15,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:15,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 725 transitions. [2020-10-26 05:48:15,940 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2020-10-26 05:48:15,943 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 725 transitions. [2020-10-26 05:48:15,943 INFO L427 BuchiCegarLoop]: ======== Iteration 5============ [2020-10-26 05:48:15,943 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 725 transitions. [2020-10-26 05:48:15,947 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:15,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:15,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:15,952 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,952 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:15,953 INFO L794 eck$LassoCheckResult]: Stem: 4278#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4236#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4237#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4170#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 4171#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4101#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4102#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4172#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4044#L413-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4045#L418-1 assume !(0 == ~M_E~0); 4062#L578-1 assume !(0 == ~T1_E~0); 4063#L583-1 assume !(0 == ~T2_E~0); 3894#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3895#L593-1 assume !(0 == ~T4_E~0); 4008#L598-1 assume !(0 == ~T5_E~0); 4009#L603-1 assume !(0 == ~E_1~0); 4205#L608-1 assume !(0 == ~E_2~0); 4206#L613-1 assume !(0 == ~E_3~0); 4121#L618-1 assume !(0 == ~E_4~0); 4122#L623-1 assume !(0 == ~E_5~0); 4175#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4176#L271 assume 1 == ~m_pc~0; 4305#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4308#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4309#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4349#L712 assume !(0 != activate_threads_~tmp~1); 4360#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3991#L290 assume 1 == ~t1_pc~0; 3992#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3983#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3993#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3912#L720 assume !(0 != activate_threads_~tmp___0~0); 3881#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3882#L309 assume !(1 == ~t2_pc~0); 4112#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 4111#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4108#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4109#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4146#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4148#L328 assume 1 == ~t3_pc~0; 4242#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4243#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4238#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4239#L736 assume !(0 != activate_threads_~tmp___2~0); 4273#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4052#L347 assume !(1 == ~t4_pc~0); 4015#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 4016#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4051#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4330#L744 assume !(0 != activate_threads_~tmp___3~0); 4340#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4194#L366 assume 1 == ~t5_pc~0; 3996#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3997#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3994#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3995#L752 assume !(0 != activate_threads_~tmp___4~0); 4000#L752-2 assume !(1 == ~M_E~0); 4001#L641-1 assume !(1 == ~T1_E~0); 4204#L646-1 assume !(1 == ~T2_E~0); 4150#L651-1 assume !(1 == ~T3_E~0); 4151#L656-1 assume !(1 == ~T4_E~0); 4174#L661-1 assume !(1 == ~T5_E~0); 4055#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4056#L671-1 assume !(1 == ~E_2~0); 3883#L676-1 assume !(1 == ~E_3~0); 3884#L681-1 assume !(1 == ~E_4~0); 4002#L686-1 assume !(1 == ~E_5~0); 4003#L892-1 [2020-10-26 05:48:15,961 INFO L796 eck$LassoCheckResult]: Loop: 4003#L892-1 assume !false; 4154#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4061#L553 assume !false; 4180#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4136#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4037#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4134#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4087#L478 assume !(0 != eval_~tmp~0); 4089#L568 start_simulation_~kernel_st~0 := 2; 4173#L386-1 start_simulation_~kernel_st~0 := 3; 4064#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4034#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4035#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4085#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4086#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3984#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3985#L603-3 assume !(0 == ~E_1~0); 4198#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4199#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4130#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4131#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4178#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4179#L271-18 assume !(1 == ~m_pc~0); 4352#L271-20 is_master_triggered_~__retres1~0 := 0; 4293#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4294#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4350#L712-18 assume !(0 != activate_threads_~tmp~1); 4344#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3885#L290-18 assume 1 == ~t1_pc~0; 3886#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3913#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3921#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4072#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4075#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4076#L309-18 assume !(1 == ~t2_pc~0); 4144#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 4147#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4168#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4218#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4209#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4210#L328-18 assume 1 == ~t3_pc~0; 4225#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4226#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4222#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4223#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4224#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4234#L347-18 assume 1 == ~t4_pc~0; 4320#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4027#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4028#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4319#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4295#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4011#L366-18 assume !(1 == ~t5_pc~0); 3936#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 3935#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3932#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3933#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3937#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L641-3 assume !(1 == ~T1_E~0); 4197#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4127#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4128#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4177#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4057#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4058#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3892#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3893#L681-3 assume !(1 == ~E_4~0); 4006#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4007#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4098#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4042#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4138#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4139#L911 assume !(0 == start_simulation_~tmp~3); 3909#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4105#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4049#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4099#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 4100#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4010#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 3929#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3930#L924 assume !(0 != start_simulation_~tmp___0~1); 4003#L892-1 [2020-10-26 05:48:15,962 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:15,962 INFO L82 PathProgramCache]: Analyzing trace with hash 56275423, now seen corresponding path program 1 times [2020-10-26 05:48:15,966 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:15,966 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878311176] [2020-10-26 05:48:15,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:15,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,019 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878311176] [2020-10-26 05:48:16,019 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,019 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,020 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820823720] [2020-10-26 05:48:16,020 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:16,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,021 INFO L82 PathProgramCache]: Analyzing trace with hash 114190832, now seen corresponding path program 1 times [2020-10-26 05:48:16,021 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,021 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456473018] [2020-10-26 05:48:16,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,066 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456473018] [2020-10-26 05:48:16,066 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,066 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,066 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982454419] [2020-10-26 05:48:16,067 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:16,067 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,067 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:16,068 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:16,068 INFO L87 Difference]: Start difference. First operand 480 states and 725 transitions. cyclomatic complexity: 246 Second operand 3 states. [2020-10-26 05:48:16,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,082 INFO L93 Difference]: Finished difference Result 480 states and 724 transitions. [2020-10-26 05:48:16,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 724 transitions. [2020-10-26 05:48:16,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:16,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 724 transitions. [2020-10-26 05:48:16,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:16,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:16,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 724 transitions. [2020-10-26 05:48:16,102 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,102 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2020-10-26 05:48:16,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 724 transitions. [2020-10-26 05:48:16,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:16,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:16,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 724 transitions. [2020-10-26 05:48:16,113 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2020-10-26 05:48:16,113 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 724 transitions. [2020-10-26 05:48:16,113 INFO L427 BuchiCegarLoop]: ======== Iteration 6============ [2020-10-26 05:48:16,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 724 transitions. [2020-10-26 05:48:16,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:16,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,118 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,118 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,119 INFO L794 eck$LassoCheckResult]: Stem: 5245#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5203#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5204#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5137#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 5138#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5068#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5069#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5139#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5011#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5012#L418-1 assume !(0 == ~M_E~0); 5029#L578-1 assume !(0 == ~T1_E~0); 5030#L583-1 assume !(0 == ~T2_E~0); 4861#L588-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4862#L593-1 assume !(0 == ~T4_E~0); 4975#L598-1 assume !(0 == ~T5_E~0); 4976#L603-1 assume !(0 == ~E_1~0); 5172#L608-1 assume !(0 == ~E_2~0); 5173#L613-1 assume !(0 == ~E_3~0); 5088#L618-1 assume !(0 == ~E_4~0); 5089#L623-1 assume !(0 == ~E_5~0); 5142#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5143#L271 assume 1 == ~m_pc~0; 5272#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5275#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5276#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5316#L712 assume !(0 != activate_threads_~tmp~1); 5327#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4958#L290 assume 1 == ~t1_pc~0; 4959#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4950#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4960#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4879#L720 assume !(0 != activate_threads_~tmp___0~0); 4848#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4849#L309 assume !(1 == ~t2_pc~0); 5079#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 5078#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5075#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5076#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5113#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5115#L328 assume 1 == ~t3_pc~0; 5209#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5210#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5205#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5206#L736 assume !(0 != activate_threads_~tmp___2~0); 5240#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5019#L347 assume !(1 == ~t4_pc~0); 4982#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 4983#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5018#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5297#L744 assume !(0 != activate_threads_~tmp___3~0); 5307#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5161#L366 assume 1 == ~t5_pc~0; 4963#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4964#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4961#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4962#L752 assume !(0 != activate_threads_~tmp___4~0); 4967#L752-2 assume !(1 == ~M_E~0); 4968#L641-1 assume !(1 == ~T1_E~0); 5171#L646-1 assume !(1 == ~T2_E~0); 5117#L651-1 assume !(1 == ~T3_E~0); 5118#L656-1 assume !(1 == ~T4_E~0); 5141#L661-1 assume !(1 == ~T5_E~0); 5022#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5023#L671-1 assume !(1 == ~E_2~0); 4850#L676-1 assume !(1 == ~E_3~0); 4851#L681-1 assume !(1 == ~E_4~0); 4969#L686-1 assume !(1 == ~E_5~0); 4970#L892-1 [2020-10-26 05:48:16,119 INFO L796 eck$LassoCheckResult]: Loop: 4970#L892-1 assume !false; 5121#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5028#L553 assume !false; 5147#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5103#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5004#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5101#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5054#L478 assume !(0 != eval_~tmp~0); 5056#L568 start_simulation_~kernel_st~0 := 2; 5140#L386-1 start_simulation_~kernel_st~0 := 3; 5031#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5001#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5002#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5052#L588-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5053#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4951#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4952#L603-3 assume !(0 == ~E_1~0); 5165#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5166#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5097#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5098#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5145#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5146#L271-18 assume 1 == ~m_pc~0; 5318#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5260#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5261#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5317#L712-18 assume !(0 != activate_threads_~tmp~1); 5311#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4852#L290-18 assume 1 == ~t1_pc~0; 4853#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4880#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4888#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5039#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5042#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5043#L309-18 assume !(1 == ~t2_pc~0); 5111#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 5114#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5135#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5185#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5176#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5177#L328-18 assume 1 == ~t3_pc~0; 5192#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5193#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5189#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5190#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5191#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5201#L347-18 assume 1 == ~t4_pc~0; 5287#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4994#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4995#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5286#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5262#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4978#L366-18 assume 1 == ~t5_pc~0; 4901#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4902#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4899#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4900#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4904#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4914#L641-3 assume !(1 == ~T1_E~0); 5164#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5094#L651-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5095#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5144#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5024#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5025#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4859#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4860#L681-3 assume !(1 == ~E_4~0); 4973#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4974#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5065#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5009#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5105#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5106#L911 assume !(0 == start_simulation_~tmp~3); 4876#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5072#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5016#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5066#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 5067#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4977#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 4896#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4897#L924 assume !(0 != start_simulation_~tmp___0~1); 4970#L892-1 [2020-10-26 05:48:16,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,120 INFO L82 PathProgramCache]: Analyzing trace with hash -504424355, now seen corresponding path program 1 times [2020-10-26 05:48:16,120 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,120 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367123146] [2020-10-26 05:48:16,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,161 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367123146] [2020-10-26 05:48:16,161 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,161 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:16,161 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674439421] [2020-10-26 05:48:16,162 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:16,162 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,162 INFO L82 PathProgramCache]: Analyzing trace with hash 2117196334, now seen corresponding path program 4 times [2020-10-26 05:48:16,162 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,163 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355885072] [2020-10-26 05:48:16,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,201 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355885072] [2020-10-26 05:48:16,201 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,201 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,201 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761236131] [2020-10-26 05:48:16,202 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:16,202 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:16,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:16,203 INFO L87 Difference]: Start difference. First operand 480 states and 724 transitions. cyclomatic complexity: 245 Second operand 3 states. [2020-10-26 05:48:16,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,228 INFO L93 Difference]: Finished difference Result 480 states and 719 transitions. [2020-10-26 05:48:16,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 719 transitions. [2020-10-26 05:48:16,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:16,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 719 transitions. [2020-10-26 05:48:16,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2020-10-26 05:48:16,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2020-10-26 05:48:16,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 719 transitions. [2020-10-26 05:48:16,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,239 INFO L691 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2020-10-26 05:48:16,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 719 transitions. [2020-10-26 05:48:16,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 480. [2020-10-26 05:48:16,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 480 states. [2020-10-26 05:48:16,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 480 states to 480 states and 719 transitions. [2020-10-26 05:48:16,249 INFO L714 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2020-10-26 05:48:16,249 INFO L594 BuchiCegarLoop]: Abstraction has 480 states and 719 transitions. [2020-10-26 05:48:16,249 INFO L427 BuchiCegarLoop]: ======== Iteration 7============ [2020-10-26 05:48:16,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 480 states and 719 transitions. [2020-10-26 05:48:16,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 407 [2020-10-26 05:48:16,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,261 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,262 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,262 INFO L794 eck$LassoCheckResult]: Stem: 6212#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6170#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6171#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6104#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 6105#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6035#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6036#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6106#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5978#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5979#L418-1 assume !(0 == ~M_E~0); 5996#L578-1 assume !(0 == ~T1_E~0); 5997#L583-1 assume !(0 == ~T2_E~0); 5828#L588-1 assume !(0 == ~T3_E~0); 5829#L593-1 assume !(0 == ~T4_E~0); 5942#L598-1 assume !(0 == ~T5_E~0); 5943#L603-1 assume !(0 == ~E_1~0); 6139#L608-1 assume !(0 == ~E_2~0); 6140#L613-1 assume !(0 == ~E_3~0); 6055#L618-1 assume !(0 == ~E_4~0); 6056#L623-1 assume !(0 == ~E_5~0); 6109#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6110#L271 assume 1 == ~m_pc~0; 6239#L272 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6242#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6243#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6283#L712 assume !(0 != activate_threads_~tmp~1); 6294#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5925#L290 assume 1 == ~t1_pc~0; 5926#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5917#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5927#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5846#L720 assume !(0 != activate_threads_~tmp___0~0); 5815#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5816#L309 assume !(1 == ~t2_pc~0); 6046#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 6045#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6042#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6043#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6080#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6082#L328 assume 1 == ~t3_pc~0; 6176#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6177#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6172#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6173#L736 assume !(0 != activate_threads_~tmp___2~0); 6207#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5986#L347 assume !(1 == ~t4_pc~0); 5949#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 5950#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5985#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6264#L744 assume !(0 != activate_threads_~tmp___3~0); 6274#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6128#L366 assume 1 == ~t5_pc~0; 5930#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5931#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5928#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5929#L752 assume !(0 != activate_threads_~tmp___4~0); 5934#L752-2 assume !(1 == ~M_E~0); 5935#L641-1 assume !(1 == ~T1_E~0); 6138#L646-1 assume !(1 == ~T2_E~0); 6084#L651-1 assume !(1 == ~T3_E~0); 6085#L656-1 assume !(1 == ~T4_E~0); 6108#L661-1 assume !(1 == ~T5_E~0); 5989#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5990#L671-1 assume !(1 == ~E_2~0); 5817#L676-1 assume !(1 == ~E_3~0); 5818#L681-1 assume !(1 == ~E_4~0); 5936#L686-1 assume !(1 == ~E_5~0); 5937#L892-1 [2020-10-26 05:48:16,262 INFO L796 eck$LassoCheckResult]: Loop: 5937#L892-1 assume !false; 6088#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5995#L553 assume !false; 6114#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6070#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5971#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6068#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6021#L478 assume !(0 != eval_~tmp~0); 6023#L568 start_simulation_~kernel_st~0 := 2; 6107#L386-1 start_simulation_~kernel_st~0 := 3; 5998#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5968#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5969#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6019#L588-3 assume !(0 == ~T3_E~0); 6020#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5918#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5919#L603-3 assume !(0 == ~E_1~0); 6132#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6133#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6064#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6065#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6112#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6113#L271-18 assume 1 == ~m_pc~0; 6285#L272-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6227#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6228#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6284#L712-18 assume !(0 != activate_threads_~tmp~1); 6278#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5819#L290-18 assume 1 == ~t1_pc~0; 5820#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5847#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5855#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6006#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6009#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6010#L309-18 assume !(1 == ~t2_pc~0); 6078#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 6081#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6102#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6152#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6143#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6144#L328-18 assume !(1 == ~t3_pc~0); 6161#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 6160#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6156#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6157#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6158#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6168#L347-18 assume 1 == ~t4_pc~0; 6254#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5961#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5962#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6253#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6229#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5945#L366-18 assume 1 == ~t5_pc~0; 5868#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5869#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5866#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5867#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5871#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5881#L641-3 assume !(1 == ~T1_E~0); 6131#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6061#L651-3 assume !(1 == ~T3_E~0); 6062#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6111#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5991#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5992#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5826#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5827#L681-3 assume !(1 == ~E_4~0); 5940#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5941#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6032#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5976#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6072#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 6073#L911 assume !(0 == start_simulation_~tmp~3); 5843#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6039#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5983#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6033#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 6034#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5944#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 5863#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5864#L924 assume !(0 != start_simulation_~tmp___0~1); 5937#L892-1 [2020-10-26 05:48:16,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,263 INFO L82 PathProgramCache]: Analyzing trace with hash 882361055, now seen corresponding path program 1 times [2020-10-26 05:48:16,263 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,263 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911974589] [2020-10-26 05:48:16,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,324 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1911974589] [2020-10-26 05:48:16,324 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,324 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:16,324 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1451852811] [2020-10-26 05:48:16,325 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:16,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,326 INFO L82 PathProgramCache]: Analyzing trace with hash -1286303697, now seen corresponding path program 1 times [2020-10-26 05:48:16,326 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,326 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753910131] [2020-10-26 05:48:16,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,366 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753910131] [2020-10-26 05:48:16,367 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,367 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,369 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1550654694] [2020-10-26 05:48:16,369 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:16,369 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,370 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:16,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:16,371 INFO L87 Difference]: Start difference. First operand 480 states and 719 transitions. cyclomatic complexity: 240 Second operand 3 states. [2020-10-26 05:48:16,445 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,445 INFO L93 Difference]: Finished difference Result 878 states and 1299 transitions. [2020-10-26 05:48:16,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:16,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 878 states and 1299 transitions. [2020-10-26 05:48:16,454 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 805 [2020-10-26 05:48:16,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 878 states to 878 states and 1299 transitions. [2020-10-26 05:48:16,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 878 [2020-10-26 05:48:16,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 878 [2020-10-26 05:48:16,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 878 states and 1299 transitions. [2020-10-26 05:48:16,464 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,464 INFO L691 BuchiCegarLoop]: Abstraction has 878 states and 1299 transitions. [2020-10-26 05:48:16,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 878 states and 1299 transitions. [2020-10-26 05:48:16,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 878 to 836. [2020-10-26 05:48:16,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 836 states. [2020-10-26 05:48:16,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 836 states to 836 states and 1241 transitions. [2020-10-26 05:48:16,495 INFO L714 BuchiCegarLoop]: Abstraction has 836 states and 1241 transitions. [2020-10-26 05:48:16,495 INFO L594 BuchiCegarLoop]: Abstraction has 836 states and 1241 transitions. [2020-10-26 05:48:16,495 INFO L427 BuchiCegarLoop]: ======== Iteration 8============ [2020-10-26 05:48:16,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 836 states and 1241 transitions. [2020-10-26 05:48:16,502 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 763 [2020-10-26 05:48:16,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,504 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,504 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,504 INFO L794 eck$LassoCheckResult]: Stem: 7586#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 7541#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7542#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7470#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 7471#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7401#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7402#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7472#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7343#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7344#L418-1 assume !(0 == ~M_E~0); 7361#L578-1 assume !(0 == ~T1_E~0); 7362#L583-1 assume !(0 == ~T2_E~0); 7193#L588-1 assume !(0 == ~T3_E~0); 7194#L593-1 assume !(0 == ~T4_E~0); 7307#L598-1 assume !(0 == ~T5_E~0); 7308#L603-1 assume !(0 == ~E_1~0); 7508#L608-1 assume !(0 == ~E_2~0); 7509#L613-1 assume !(0 == ~E_3~0); 7421#L618-1 assume !(0 == ~E_4~0); 7422#L623-1 assume !(0 == ~E_5~0); 7475#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7476#L271 assume !(1 == ~m_pc~0); 7612#L271-2 is_master_triggered_~__retres1~0 := 0; 7614#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7615#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7656#L712 assume !(0 != activate_threads_~tmp~1); 7681#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7290#L290 assume 1 == ~t1_pc~0; 7291#L291 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7282#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7292#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7211#L720 assume !(0 != activate_threads_~tmp___0~0); 7180#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7181#L309 assume !(1 == ~t2_pc~0); 7412#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 7411#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7408#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7409#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7446#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7448#L328 assume 1 == ~t3_pc~0; 7547#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7548#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7543#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7544#L736 assume !(0 != activate_threads_~tmp___2~0); 7579#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7351#L347 assume !(1 == ~t4_pc~0); 7314#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 7315#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7350#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7636#L744 assume !(0 != activate_threads_~tmp___3~0); 7646#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7496#L366 assume 1 == ~t5_pc~0; 7295#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7296#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7293#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7294#L752 assume !(0 != activate_threads_~tmp___4~0); 7299#L752-2 assume !(1 == ~M_E~0); 7300#L641-1 assume !(1 == ~T1_E~0); 7507#L646-1 assume !(1 == ~T2_E~0); 7450#L651-1 assume !(1 == ~T3_E~0); 7451#L656-1 assume !(1 == ~T4_E~0); 7474#L661-1 assume !(1 == ~T5_E~0); 7354#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7355#L671-1 assume !(1 == ~E_2~0); 7182#L676-1 assume !(1 == ~E_3~0); 7183#L681-1 assume !(1 == ~E_4~0); 7301#L686-1 assume !(1 == ~E_5~0); 7302#L892-1 [2020-10-26 05:48:16,505 INFO L796 eck$LassoCheckResult]: Loop: 7302#L892-1 assume !false; 7454#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7360#L553 assume !false; 7480#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7436#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7336#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7434#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7386#L478 assume !(0 != eval_~tmp~0); 7388#L568 start_simulation_~kernel_st~0 := 2; 7978#L386-1 start_simulation_~kernel_st~0 := 3; 7976#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7974#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7972#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7970#L588-3 assume !(0 == ~T3_E~0); 7575#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7283#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7284#L603-3 assume !(0 == ~E_1~0); 7501#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7502#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7430#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7431#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7478#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7479#L271-18 assume !(1 == ~m_pc~0); 7679#L271-20 is_master_triggered_~__retres1~0 := 0; 7602#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7603#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7657#L712-18 assume !(0 != activate_threads_~tmp~1); 7650#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7184#L290-18 assume 1 == ~t1_pc~0; 7185#L291-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7212#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7220#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7371#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7374#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7375#L309-18 assume !(1 == ~t2_pc~0); 7444#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 7447#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7468#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7521#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7512#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7513#L328-18 assume 1 == ~t3_pc~0; 7529#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7530#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7526#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7527#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7528#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7538#L347-18 assume 1 == ~t4_pc~0; 7626#L348-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7326#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7327#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7625#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7604#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7310#L366-18 assume 1 == ~t5_pc~0; 7233#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7234#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7231#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7232#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7236#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7246#L641-3 assume !(1 == ~T1_E~0); 7500#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7427#L651-3 assume !(1 == ~T3_E~0); 7428#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7477#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7356#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7357#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7191#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7192#L681-3 assume !(1 == ~E_4~0); 7305#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7306#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7398#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7341#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7438#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 7439#L911 assume !(0 == start_simulation_~tmp~3); 7208#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7405#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7348#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7399#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 7400#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7309#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 7228#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7229#L924 assume !(0 != start_simulation_~tmp___0~1); 7302#L892-1 [2020-10-26 05:48:16,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,505 INFO L82 PathProgramCache]: Analyzing trace with hash -425643714, now seen corresponding path program 1 times [2020-10-26 05:48:16,506 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,506 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971149934] [2020-10-26 05:48:16,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,548 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971149934] [2020-10-26 05:48:16,548 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,548 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,549 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25794266] [2020-10-26 05:48:16,549 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:16,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1832459793, now seen corresponding path program 1 times [2020-10-26 05:48:16,550 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,551 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214533719] [2020-10-26 05:48:16,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,587 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214533719] [2020-10-26 05:48:16,587 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:16,587 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:16,587 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942718734] [2020-10-26 05:48:16,588 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:16,588 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:16,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:48:16,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:48:16,589 INFO L87 Difference]: Start difference. First operand 836 states and 1241 transitions. cyclomatic complexity: 407 Second operand 4 states. [2020-10-26 05:48:16,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:16,818 INFO L93 Difference]: Finished difference Result 1920 states and 2814 transitions. [2020-10-26 05:48:16,818 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:48:16,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1920 states and 2814 transitions. [2020-10-26 05:48:16,840 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1798 [2020-10-26 05:48:16,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1920 states to 1920 states and 2814 transitions. [2020-10-26 05:48:16,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1920 [2020-10-26 05:48:16,866 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1920 [2020-10-26 05:48:16,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1920 states and 2814 transitions. [2020-10-26 05:48:16,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:16,872 INFO L691 BuchiCegarLoop]: Abstraction has 1920 states and 2814 transitions. [2020-10-26 05:48:16,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1920 states and 2814 transitions. [2020-10-26 05:48:16,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1920 to 1499. [2020-10-26 05:48:16,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1499 states. [2020-10-26 05:48:16,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2212 transitions. [2020-10-26 05:48:16,918 INFO L714 BuchiCegarLoop]: Abstraction has 1499 states and 2212 transitions. [2020-10-26 05:48:16,919 INFO L594 BuchiCegarLoop]: Abstraction has 1499 states and 2212 transitions. [2020-10-26 05:48:16,919 INFO L427 BuchiCegarLoop]: ======== Iteration 9============ [2020-10-26 05:48:16,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2212 transitions. [2020-10-26 05:48:16,936 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1426 [2020-10-26 05:48:16,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:16,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:16,939 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,939 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:16,940 INFO L794 eck$LassoCheckResult]: Stem: 10358#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 10318#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 10319#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10247#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 10248#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10181#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10182#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10249#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10106#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10107#L418-1 assume !(0 == ~M_E~0); 10122#L578-1 assume !(0 == ~T1_E~0); 10123#L583-1 assume !(0 == ~T2_E~0); 9959#L588-1 assume !(0 == ~T3_E~0); 9960#L593-1 assume !(0 == ~T4_E~0); 10068#L598-1 assume !(0 == ~T5_E~0); 10069#L603-1 assume !(0 == ~E_1~0); 10283#L608-1 assume !(0 == ~E_2~0); 10284#L613-1 assume !(0 == ~E_3~0); 10198#L618-1 assume !(0 == ~E_4~0); 10199#L623-1 assume !(0 == ~E_5~0); 10252#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10253#L271 assume !(1 == ~m_pc~0); 10386#L271-2 is_master_triggered_~__retres1~0 := 0; 10391#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10392#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10432#L712 assume !(0 != activate_threads_~tmp~1); 10457#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10052#L290 assume !(1 == ~t1_pc~0); 10045#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 10046#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10053#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9974#L720 assume !(0 != activate_threads_~tmp___0~0); 9946#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9947#L309 assume !(1 == ~t2_pc~0); 10189#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 10188#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10185#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10186#L728 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10223#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10225#L328 assume 1 == ~t3_pc~0; 10322#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10323#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10320#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10321#L736 assume !(0 != activate_threads_~tmp___2~0); 10353#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10112#L347 assume !(1 == ~t4_pc~0); 10075#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 10076#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10111#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10411#L744 assume !(0 != activate_threads_~tmp___3~0); 10422#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10271#L366 assume 1 == ~t5_pc~0; 10056#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10057#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10054#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10055#L752 assume !(0 != activate_threads_~tmp___4~0); 10060#L752-2 assume !(1 == ~M_E~0); 10061#L641-1 assume !(1 == ~T1_E~0); 10282#L646-1 assume !(1 == ~T2_E~0); 10227#L651-1 assume !(1 == ~T3_E~0); 10228#L656-1 assume !(1 == ~T4_E~0); 10251#L661-1 assume !(1 == ~T5_E~0); 10115#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10116#L671-1 assume !(1 == ~E_2~0); 9950#L676-1 assume !(1 == ~E_3~0); 9951#L681-1 assume !(1 == ~E_4~0); 10063#L686-1 assume !(1 == ~E_5~0); 10064#L892-1 [2020-10-26 05:48:16,940 INFO L796 eck$LassoCheckResult]: Loop: 10064#L892-1 assume !false; 10231#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10121#L553 assume !false; 10257#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10213#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10097#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10211#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 10159#L478 assume !(0 != eval_~tmp~0); 10161#L568 start_simulation_~kernel_st~0 := 2; 10250#L386-1 start_simulation_~kernel_st~0 := 3; 10124#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10094#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10095#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10157#L588-3 assume !(0 == ~T3_E~0); 10158#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10043#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10044#L603-3 assume !(0 == ~E_1~0); 10276#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10277#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10207#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10208#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10255#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10256#L271-18 assume !(1 == ~m_pc~0); 10454#L271-20 is_master_triggered_~__retres1~0 := 0; 10374#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10375#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10433#L712-18 assume !(0 != activate_threads_~tmp~1); 10426#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9948#L290-18 assume !(1 == ~t1_pc~0); 9949#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 9975#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9984#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10138#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10144#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10145#L309-18 assume !(1 == ~t2_pc~0); 10221#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 10224#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10245#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10296#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10287#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10288#L328-18 assume 1 == ~t3_pc~0; 10305#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10306#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10302#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10303#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10304#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10314#L347-18 assume !(1 == ~t4_pc~0); 10400#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 10087#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10088#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10398#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10376#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10071#L366-18 assume 1 == ~t5_pc~0; 9997#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9998#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9995#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9996#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10000#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 10009#L641-3 assume !(1 == ~T1_E~0); 10275#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10204#L651-3 assume !(1 == ~T3_E~0); 10205#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10254#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10117#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10118#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9956#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9957#L681-3 assume !(1 == ~E_4~0); 10066#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10067#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10175#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10102#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10215#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 10216#L911 assume !(0 == start_simulation_~tmp~3); 9972#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10180#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10109#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10176#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 10177#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10070#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 9992#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 9993#L924 assume !(0 != start_simulation_~tmp___0~1); 10064#L892-1 [2020-10-26 05:48:16,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:16,941 INFO L82 PathProgramCache]: Analyzing trace with hash -25652515, now seen corresponding path program 1 times [2020-10-26 05:48:16,942 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:16,942 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943063084] [2020-10-26 05:48:16,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:16,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:16,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:16,999 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943063084] [2020-10-26 05:48:16,999 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:17,000 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:17,000 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137535315] [2020-10-26 05:48:17,001 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:17,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,001 INFO L82 PathProgramCache]: Analyzing trace with hash -1054789199, now seen corresponding path program 1 times [2020-10-26 05:48:17,002 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,002 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936330576] [2020-10-26 05:48:17,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:17,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:17,049 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936330576] [2020-10-26 05:48:17,050 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:17,050 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:17,050 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527637493] [2020-10-26 05:48:17,051 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:17,051 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:17,052 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:48:17,052 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:48:17,052 INFO L87 Difference]: Start difference. First operand 1499 states and 2212 transitions. cyclomatic complexity: 715 Second operand 5 states. [2020-10-26 05:48:17,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:17,401 INFO L93 Difference]: Finished difference Result 3890 states and 5753 transitions. [2020-10-26 05:48:17,401 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:48:17,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3890 states and 5753 transitions. [2020-10-26 05:48:17,441 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3746 [2020-10-26 05:48:17,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3890 states to 3890 states and 5753 transitions. [2020-10-26 05:48:17,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3890 [2020-10-26 05:48:17,487 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3890 [2020-10-26 05:48:17,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3890 states and 5753 transitions. [2020-10-26 05:48:17,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:17,496 INFO L691 BuchiCegarLoop]: Abstraction has 3890 states and 5753 transitions. [2020-10-26 05:48:17,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3890 states and 5753 transitions. [2020-10-26 05:48:17,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3890 to 1574. [2020-10-26 05:48:17,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1574 states. [2020-10-26 05:48:17,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1574 states to 1574 states and 2287 transitions. [2020-10-26 05:48:17,588 INFO L714 BuchiCegarLoop]: Abstraction has 1574 states and 2287 transitions. [2020-10-26 05:48:17,588 INFO L594 BuchiCegarLoop]: Abstraction has 1574 states and 2287 transitions. [2020-10-26 05:48:17,589 INFO L427 BuchiCegarLoop]: ======== Iteration 10============ [2020-10-26 05:48:17,589 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1574 states and 2287 transitions. [2020-10-26 05:48:17,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1498 [2020-10-26 05:48:17,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:17,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:17,602 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:17,602 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:17,602 INFO L794 eck$LassoCheckResult]: Stem: 15798#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15755#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15756#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15665#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 15666#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15578#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15579#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15667#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15512#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15513#L418-1 assume !(0 == ~M_E~0); 15530#L578-1 assume !(0 == ~T1_E~0); 15531#L583-1 assume !(0 == ~T2_E~0); 15360#L588-1 assume !(0 == ~T3_E~0); 15361#L593-1 assume !(0 == ~T4_E~0); 15476#L598-1 assume !(0 == ~T5_E~0); 15477#L603-1 assume !(0 == ~E_1~0); 15706#L608-1 assume !(0 == ~E_2~0); 15707#L613-1 assume !(0 == ~E_3~0); 15598#L618-1 assume !(0 == ~E_4~0); 15599#L623-1 assume !(0 == ~E_5~0); 15672#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15673#L271 assume !(1 == ~m_pc~0); 15829#L271-2 is_master_triggered_~__retres1~0 := 0; 15831#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15832#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15877#L712 assume !(0 != activate_threads_~tmp~1); 15904#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15459#L290 assume !(1 == ~t1_pc~0); 15450#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 15451#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15460#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15378#L720 assume !(0 != activate_threads_~tmp___0~0); 15348#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15349#L309 assume !(1 == ~t2_pc~0); 15589#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 15652#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15669#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15626#L728 assume !(0 != activate_threads_~tmp___1~0); 15627#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15630#L328 assume 1 == ~t3_pc~0; 15761#L329 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15762#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15757#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15758#L736 assume !(0 != activate_threads_~tmp___2~0); 15792#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15520#L347 assume !(1 == ~t4_pc~0); 15483#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 15484#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15519#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15853#L744 assume !(0 != activate_threads_~tmp___3~0); 15864#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15695#L366 assume 1 == ~t5_pc~0; 15464#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15465#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15462#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15463#L752 assume !(0 != activate_threads_~tmp___4~0); 15468#L752-2 assume !(1 == ~M_E~0); 15469#L641-1 assume !(1 == ~T1_E~0); 15705#L646-1 assume !(1 == ~T2_E~0); 15634#L651-1 assume !(1 == ~T3_E~0); 15635#L656-1 assume !(1 == ~T4_E~0); 15671#L661-1 assume !(1 == ~T5_E~0); 15523#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15524#L671-1 assume !(1 == ~E_2~0); 15350#L676-1 assume !(1 == ~E_3~0); 15351#L681-1 assume !(1 == ~E_4~0); 15470#L686-1 assume !(1 == ~E_5~0); 15471#L892-1 [2020-10-26 05:48:17,603 INFO L796 eck$LassoCheckResult]: Loop: 15471#L892-1 assume !false; 16506#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 16503#L553 assume !false; 16501#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15615#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15505#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15613#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15559#L478 assume !(0 != eval_~tmp~0); 15561#L568 start_simulation_~kernel_st~0 := 2; 16803#L386-1 start_simulation_~kernel_st~0 := 3; 16802#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16801#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16800#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16789#L588-3 assume !(0 == ~T3_E~0); 16777#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16775#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16773#L603-3 assume !(0 == ~E_1~0); 16770#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16768#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16766#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16764#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16762#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16761#L271-18 assume !(1 == ~m_pc~0); 16760#L271-20 is_master_triggered_~__retres1~0 := 0; 16759#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16758#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16757#L712-18 assume !(0 != activate_threads_~tmp~1); 16756#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15352#L290-18 assume !(1 == ~t1_pc~0); 15353#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 16911#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16910#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16909#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16908#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15623#L309-18 assume !(1 == ~t2_pc~0); 15624#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 16907#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16905#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16903#L728-18 assume !(0 != activate_threads_~tmp___1~0); 16901#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16900#L328-18 assume 1 == ~t3_pc~0; 16898#L329-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16897#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16896#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16895#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16894#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16893#L347-18 assume !(1 == ~t4_pc~0); 16885#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 16884#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16883#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16882#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16881#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16880#L366-18 assume 1 == ~t5_pc~0; 16878#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15688#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15400#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15401#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15405#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 15415#L641-3 assume !(1 == ~T1_E~0); 15698#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15604#L651-3 assume !(1 == ~T3_E~0); 15605#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15674#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15525#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15526#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15358#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15359#L681-3 assume !(1 == ~E_4~0); 15474#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15475#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15575#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15510#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15617#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 15618#L911 assume !(0 == start_simulation_~tmp~3); 15872#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16557#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16549#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16544#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 16537#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16531#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 16524#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 16518#L924 assume !(0 != start_simulation_~tmp___0~1); 15471#L892-1 [2020-10-26 05:48:17,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,604 INFO L82 PathProgramCache]: Analyzing trace with hash -3020261, now seen corresponding path program 1 times [2020-10-26 05:48:17,605 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,605 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433839119] [2020-10-26 05:48:17,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:17,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:17,655 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433839119] [2020-10-26 05:48:17,656 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:17,656 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:17,656 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [735882235] [2020-10-26 05:48:17,656 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:17,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:17,657 INFO L82 PathProgramCache]: Analyzing trace with hash -1952182477, now seen corresponding path program 1 times [2020-10-26 05:48:17,657 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:17,657 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211456356] [2020-10-26 05:48:17,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:17,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:17,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:17,691 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [211456356] [2020-10-26 05:48:17,691 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:17,691 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:17,691 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528569455] [2020-10-26 05:48:17,692 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:17,692 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:17,692 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:48:17,692 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:48:17,693 INFO L87 Difference]: Start difference. First operand 1574 states and 2287 transitions. cyclomatic complexity: 715 Second operand 4 states. [2020-10-26 05:48:17,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:17,951 INFO L93 Difference]: Finished difference Result 3636 states and 5230 transitions. [2020-10-26 05:48:17,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:48:17,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3636 states and 5230 transitions. [2020-10-26 05:48:17,986 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3456 [2020-10-26 05:48:18,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3636 states to 3636 states and 5230 transitions. [2020-10-26 05:48:18,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3636 [2020-10-26 05:48:18,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3636 [2020-10-26 05:48:18,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3636 states and 5230 transitions. [2020-10-26 05:48:18,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:18,029 INFO L691 BuchiCegarLoop]: Abstraction has 3636 states and 5230 transitions. [2020-10-26 05:48:18,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3636 states and 5230 transitions. [2020-10-26 05:48:18,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3636 to 2865. [2020-10-26 05:48:18,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2865 states. [2020-10-26 05:48:18,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2865 states to 2865 states and 4146 transitions. [2020-10-26 05:48:18,104 INFO L714 BuchiCegarLoop]: Abstraction has 2865 states and 4146 transitions. [2020-10-26 05:48:18,105 INFO L594 BuchiCegarLoop]: Abstraction has 2865 states and 4146 transitions. [2020-10-26 05:48:18,105 INFO L427 BuchiCegarLoop]: ======== Iteration 11============ [2020-10-26 05:48:18,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2865 states and 4146 transitions. [2020-10-26 05:48:18,122 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2788 [2020-10-26 05:48:18,123 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:18,123 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:18,124 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,125 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,125 INFO L794 eck$LassoCheckResult]: Stem: 21005#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 20950#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 20951#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20873#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 20874#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20798#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20799#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20875#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20730#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20731#L418-1 assume !(0 == ~M_E~0); 20748#L578-1 assume !(0 == ~T1_E~0); 20749#L583-1 assume !(0 == ~T2_E~0); 20580#L588-1 assume !(0 == ~T3_E~0); 20581#L593-1 assume !(0 == ~T4_E~0); 20694#L598-1 assume !(0 == ~T5_E~0); 20695#L603-1 assume !(0 == ~E_1~0); 20908#L608-1 assume !(0 == ~E_2~0); 20909#L613-1 assume !(0 == ~E_3~0); 20818#L618-1 assume !(0 == ~E_4~0); 20819#L623-1 assume !(0 == ~E_5~0); 20878#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20879#L271 assume !(1 == ~m_pc~0); 21031#L271-2 is_master_triggered_~__retres1~0 := 0; 21033#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21034#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21080#L712 assume !(0 != activate_threads_~tmp~1); 21113#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20678#L290 assume !(1 == ~t1_pc~0); 20669#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 20670#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20679#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20597#L720 assume !(0 != activate_threads_~tmp___0~0); 20568#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20569#L309 assume !(1 == ~t2_pc~0); 20809#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 20864#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21116#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20843#L728 assume !(0 != activate_threads_~tmp___1~0); 20844#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20846#L328 assume !(1 == ~t3_pc~0); 21001#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 21000#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20952#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20953#L736 assume !(0 != activate_threads_~tmp___2~0); 20986#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20738#L347 assume !(1 == ~t4_pc~0); 20702#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 20703#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20737#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21056#L744 assume !(0 != activate_threads_~tmp___3~0); 21067#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20897#L366 assume 1 == ~t5_pc~0; 20682#L367 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20683#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20680#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20681#L752 assume !(0 != activate_threads_~tmp___4~0); 20686#L752-2 assume !(1 == ~M_E~0); 20687#L641-1 assume !(1 == ~T1_E~0); 20907#L646-1 assume !(1 == ~T2_E~0); 20848#L651-1 assume !(1 == ~T3_E~0); 20849#L656-1 assume !(1 == ~T4_E~0); 20877#L661-1 assume !(1 == ~T5_E~0); 20741#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20742#L671-1 assume !(1 == ~E_2~0); 20570#L676-1 assume !(1 == ~E_3~0); 20571#L681-1 assume !(1 == ~E_4~0); 20688#L686-1 assume !(1 == ~E_5~0); 20689#L892-1 [2020-10-26 05:48:18,125 INFO L796 eck$LassoCheckResult]: Loop: 20689#L892-1 assume !false; 20852#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 20747#L553 assume !false; 20883#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 20833#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 20724#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 20831#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 20780#L478 assume !(0 != eval_~tmp~0); 20782#L568 start_simulation_~kernel_st~0 := 2; 23425#L386-1 start_simulation_~kernel_st~0 := 3; 23424#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23423#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23422#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23421#L588-3 assume !(0 == ~T3_E~0); 23420#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23419#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23418#L603-3 assume !(0 == ~E_1~0); 23411#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23410#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23409#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23407#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23404#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21111#L271-18 assume !(1 == ~m_pc~0); 21112#L271-20 is_master_triggered_~__retres1~0 := 0; 23388#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21085#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21081#L712-18 assume !(0 != activate_threads_~tmp~1); 21073#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20572#L290-18 assume !(1 == ~t1_pc~0); 20573#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 23352#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23351#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23350#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23348#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23346#L309-18 assume 1 == ~t2_pc~0; 23344#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23345#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23353#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23334#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23332#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23330#L328-18 assume !(1 == ~t3_pc~0); 22705#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 23326#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23324#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23323#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23321#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23319#L347-18 assume !(1 == ~t4_pc~0); 23316#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 23314#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23312#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 23311#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23310#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23309#L366-18 assume 1 == ~t5_pc~0; 23306#L367-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23305#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23304#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 23303#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23301#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 23299#L641-3 assume !(1 == ~T1_E~0); 23297#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23295#L651-3 assume !(1 == ~T3_E~0); 23291#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23289#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23287#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23285#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23282#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20990#L681-3 assume !(1 == ~E_4~0); 20692#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20693#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23045#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22942#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22941#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22936#L911 assume !(0 == start_simulation_~tmp~3); 22934#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 22927#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 22923#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 22919#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 22913#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22911#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 20616#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 20617#L924 assume !(0 != start_simulation_~tmp___0~1); 20689#L892-1 [2020-10-26 05:48:18,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,126 INFO L82 PathProgramCache]: Analyzing trace with hash -311459270, now seen corresponding path program 1 times [2020-10-26 05:48:18,126 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,127 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848198080] [2020-10-26 05:48:18,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:18,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:18,175 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848198080] [2020-10-26 05:48:18,176 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:18,176 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:18,176 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246064972] [2020-10-26 05:48:18,176 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:18,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,177 INFO L82 PathProgramCache]: Analyzing trace with hash 353478257, now seen corresponding path program 1 times [2020-10-26 05:48:18,177 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,178 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412281465] [2020-10-26 05:48:18,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:18,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:18,226 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412281465] [2020-10-26 05:48:18,226 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:18,226 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:18,227 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1159756589] [2020-10-26 05:48:18,227 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:18,227 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:18,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2020-10-26 05:48:18,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2020-10-26 05:48:18,228 INFO L87 Difference]: Start difference. First operand 2865 states and 4146 transitions. cyclomatic complexity: 1283 Second operand 4 states. [2020-10-26 05:48:18,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:18,458 INFO L93 Difference]: Finished difference Result 7042 states and 10057 transitions. [2020-10-26 05:48:18,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2020-10-26 05:48:18,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7042 states and 10057 transitions. [2020-10-26 05:48:18,510 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6758 [2020-10-26 05:48:18,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7042 states to 7042 states and 10057 transitions. [2020-10-26 05:48:18,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7042 [2020-10-26 05:48:18,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7042 [2020-10-26 05:48:18,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7042 states and 10057 transitions. [2020-10-26 05:48:18,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:18,579 INFO L691 BuchiCegarLoop]: Abstraction has 7042 states and 10057 transitions. [2020-10-26 05:48:18,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7042 states and 10057 transitions. [2020-10-26 05:48:18,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7042 to 5580. [2020-10-26 05:48:18,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5580 states. [2020-10-26 05:48:18,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 8011 transitions. [2020-10-26 05:48:18,758 INFO L714 BuchiCegarLoop]: Abstraction has 5580 states and 8011 transitions. [2020-10-26 05:48:18,758 INFO L594 BuchiCegarLoop]: Abstraction has 5580 states and 8011 transitions. [2020-10-26 05:48:18,758 INFO L427 BuchiCegarLoop]: ======== Iteration 12============ [2020-10-26 05:48:18,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 8011 transitions. [2020-10-26 05:48:18,784 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:18,784 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:18,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:18,786 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,786 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:18,786 INFO L794 eck$LassoCheckResult]: Stem: 30933#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 30879#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 30880#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30792#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 30793#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30720#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30721#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30794#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30650#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30651#L418-1 assume !(0 == ~M_E~0); 30668#L578-1 assume !(0 == ~T1_E~0); 30669#L583-1 assume !(0 == ~T2_E~0); 30497#L588-1 assume !(0 == ~T3_E~0); 30498#L593-1 assume !(0 == ~T4_E~0); 30611#L598-1 assume !(0 == ~T5_E~0); 30612#L603-1 assume !(0 == ~E_1~0); 30838#L608-1 assume !(0 == ~E_2~0); 30839#L613-1 assume !(0 == ~E_3~0); 30740#L618-1 assume !(0 == ~E_4~0); 30741#L623-1 assume !(0 == ~E_5~0); 30798#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30799#L271 assume !(1 == ~m_pc~0); 30960#L271-2 is_master_triggered_~__retres1~0 := 0; 30962#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30963#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31013#L712 assume !(0 != activate_threads_~tmp~1); 31044#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30595#L290 assume !(1 == ~t1_pc~0); 30586#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 30587#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30596#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30514#L720 assume !(0 != activate_threads_~tmp___0~0); 30485#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30486#L309 assume !(1 == ~t2_pc~0); 30731#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 30785#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30796#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30765#L728 assume !(0 != activate_threads_~tmp___1~0); 30766#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30768#L328 assume !(1 == ~t3_pc~0); 30929#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 30928#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30881#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30882#L736 assume !(0 != activate_threads_~tmp___2~0); 30913#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30658#L347 assume !(1 == ~t4_pc~0); 30622#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 30623#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30657#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30986#L744 assume !(0 != activate_threads_~tmp___3~0); 30997#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30826#L366 assume !(1 == ~t5_pc~0); 30827#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 30823#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30597#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30598#L752 assume !(0 != activate_threads_~tmp___4~0); 30601#L752-2 assume !(1 == ~M_E~0); 30602#L641-1 assume !(1 == ~T1_E~0); 30837#L646-1 assume !(1 == ~T2_E~0); 30770#L651-1 assume !(1 == ~T3_E~0); 30771#L656-1 assume !(1 == ~T4_E~0); 30797#L661-1 assume !(1 == ~T5_E~0); 30661#L666-1 assume 1 == ~E_1~0;~E_1~0 := 2; 30662#L671-1 assume !(1 == ~E_2~0); 30487#L676-1 assume !(1 == ~E_3~0); 30488#L681-1 assume !(1 == ~E_4~0); 30603#L686-1 assume !(1 == ~E_5~0); 30604#L892-1 [2020-10-26 05:48:18,787 INFO L796 eck$LassoCheckResult]: Loop: 30604#L892-1 assume !false; 30774#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 30667#L553 assume !false; 30803#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 30755#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 30644#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 30753#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30702#L478 assume !(0 != eval_~tmp~0); 30704#L568 start_simulation_~kernel_st~0 := 2; 30795#L386-1 start_simulation_~kernel_st~0 := 3; 30670#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30641#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30642#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30700#L588-3 assume !(0 == ~T3_E~0); 30701#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30588#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30589#L603-3 assume !(0 == ~E_1~0); 30831#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30832#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30749#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30750#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30801#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30802#L271-18 assume !(1 == ~m_pc~0); 31042#L271-20 is_master_triggered_~__retres1~0 := 0; 30949#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30950#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31015#L712-18 assume !(0 != activate_threads_~tmp~1); 31004#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30489#L290-18 assume !(1 == ~t1_pc~0); 30490#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 30515#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30523#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30684#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30689#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30690#L309-18 assume !(1 == ~t2_pc~0); 30763#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 30767#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30790#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30857#L728-18 assume !(0 != activate_threads_~tmp___1~0); 30842#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30843#L328-18 assume !(1 == ~t3_pc~0); 30919#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 36037#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36035#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36033#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36031#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36029#L347-18 assume !(1 == ~t4_pc~0); 36026#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 36024#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36022#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36020#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36018#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36016#L366-18 assume !(1 == ~t5_pc~0); 33650#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 36013#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36011#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36009#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36007#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 36006#L641-3 assume !(1 == ~T1_E~0); 36005#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36004#L651-3 assume !(1 == ~T3_E~0); 36003#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36002#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36001#L666-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36000#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35999#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35997#L681-3 assume !(1 == ~E_4~0); 35995#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35993#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35814#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35807#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35806#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 35804#L911 assume !(0 == start_simulation_~tmp~3); 35801#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35792#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35788#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35787#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 35764#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35763#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 35762#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 35761#L924 assume !(0 != start_simulation_~tmp___0~1); 30604#L892-1 [2020-10-26 05:48:18,787 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,787 INFO L82 PathProgramCache]: Analyzing trace with hash 865145049, now seen corresponding path program 1 times [2020-10-26 05:48:18,787 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,788 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301149577] [2020-10-26 05:48:18,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:18,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:18,825 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301149577] [2020-10-26 05:48:18,825 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:18,825 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:18,826 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291954773] [2020-10-26 05:48:18,826 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:18,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:18,827 INFO L82 PathProgramCache]: Analyzing trace with hash 885935413, now seen corresponding path program 1 times [2020-10-26 05:48:18,827 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:18,827 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057136441] [2020-10-26 05:48:18,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:18,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:18,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:18,860 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1057136441] [2020-10-26 05:48:18,860 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:18,860 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:18,860 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396459282] [2020-10-26 05:48:18,861 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:18,861 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:18,861 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:18,861 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:18,861 INFO L87 Difference]: Start difference. First operand 5580 states and 8011 transitions. cyclomatic complexity: 2433 Second operand 3 states. [2020-10-26 05:48:18,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:18,929 INFO L93 Difference]: Finished difference Result 5580 states and 7917 transitions. [2020-10-26 05:48:18,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:18,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5580 states and 7917 transitions. [2020-10-26 05:48:19,011 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:19,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5580 states to 5580 states and 7917 transitions. [2020-10-26 05:48:19,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5580 [2020-10-26 05:48:19,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5580 [2020-10-26 05:48:19,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5580 states and 7917 transitions. [2020-10-26 05:48:19,053 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:19,054 INFO L691 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2020-10-26 05:48:19,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5580 states and 7917 transitions. [2020-10-26 05:48:19,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5580 to 5580. [2020-10-26 05:48:19,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5580 states. [2020-10-26 05:48:19,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 7917 transitions. [2020-10-26 05:48:19,165 INFO L714 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2020-10-26 05:48:19,165 INFO L594 BuchiCegarLoop]: Abstraction has 5580 states and 7917 transitions. [2020-10-26 05:48:19,165 INFO L427 BuchiCegarLoop]: ======== Iteration 13============ [2020-10-26 05:48:19,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 7917 transitions. [2020-10-26 05:48:19,252 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:19,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:19,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:19,256 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,256 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,256 INFO L794 eck$LassoCheckResult]: Stem: 42099#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 42040#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 42041#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41954#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 41955#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41881#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41882#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41956#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41812#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41813#L418-1 assume !(0 == ~M_E~0); 41830#L578-1 assume !(0 == ~T1_E~0); 41831#L583-1 assume !(0 == ~T2_E~0); 41664#L588-1 assume !(0 == ~T3_E~0); 41665#L593-1 assume !(0 == ~T4_E~0); 41776#L598-1 assume !(0 == ~T5_E~0); 41777#L603-1 assume !(0 == ~E_1~0); 41997#L608-1 assume !(0 == ~E_2~0); 41998#L613-1 assume !(0 == ~E_3~0); 41900#L618-1 assume !(0 == ~E_4~0); 41901#L623-1 assume !(0 == ~E_5~0); 41960#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41961#L271 assume !(1 == ~m_pc~0); 42131#L271-2 is_master_triggered_~__retres1~0 := 0; 42133#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42134#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 42190#L712 assume !(0 != activate_threads_~tmp~1); 42210#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41761#L290 assume !(1 == ~t1_pc~0); 41752#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 41753#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41762#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41682#L720 assume !(0 != activate_threads_~tmp___0~0); 41652#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41653#L309 assume !(1 == ~t2_pc~0); 41891#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 41946#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41958#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41925#L728 assume !(0 != activate_threads_~tmp___1~0); 41926#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41928#L328 assume !(1 == ~t3_pc~0); 42094#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 42093#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42042#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42043#L736 assume !(0 != activate_threads_~tmp___2~0); 42077#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41820#L347 assume !(1 == ~t4_pc~0); 41784#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 41785#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41819#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42160#L744 assume !(0 != activate_threads_~tmp___3~0); 42174#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41984#L366 assume !(1 == ~t5_pc~0); 41985#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 41983#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 41764#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 41765#L752 assume !(0 != activate_threads_~tmp___4~0); 41768#L752-2 assume !(1 == ~M_E~0); 41769#L641-1 assume !(1 == ~T1_E~0); 41996#L646-1 assume !(1 == ~T2_E~0); 41931#L651-1 assume !(1 == ~T3_E~0); 41932#L656-1 assume !(1 == ~T4_E~0); 41959#L661-1 assume !(1 == ~T5_E~0); 41823#L666-1 assume !(1 == ~E_1~0); 41824#L671-1 assume !(1 == ~E_2~0); 41654#L676-1 assume !(1 == ~E_3~0); 41655#L681-1 assume !(1 == ~E_4~0); 41770#L686-1 assume !(1 == ~E_5~0); 41771#L892-1 [2020-10-26 05:48:19,257 INFO L796 eck$LassoCheckResult]: Loop: 41771#L892-1 assume !false; 43773#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 43765#L553 assume !false; 43761#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 43716#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 43712#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43710#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 43697#L478 assume !(0 != eval_~tmp~0); 43698#L568 start_simulation_~kernel_st~0 := 2; 46857#L386-1 start_simulation_~kernel_st~0 := 3; 46855#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 46853#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46851#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46849#L588-3 assume !(0 == ~T3_E~0); 46845#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46843#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46841#L603-3 assume !(0 == ~E_1~0); 46839#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46836#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46834#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46833#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46832#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46831#L271-18 assume !(1 == ~m_pc~0); 46141#L271-20 is_master_triggered_~__retres1~0 := 0; 46140#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46139#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 46138#L712-18 assume !(0 != activate_threads_~tmp~1); 46137#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46136#L290-18 assume !(1 == ~t1_pc~0); 44828#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 46134#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46132#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 46130#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 46129#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46128#L309-18 assume 1 == ~t2_pc~0; 46122#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 46118#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46113#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46075#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 46070#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46067#L328-18 assume !(1 == ~t3_pc~0); 45421#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 46063#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46061#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 46058#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 46055#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46052#L347-18 assume !(1 == ~t4_pc~0); 46043#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 46038#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46034#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 46031#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 46028#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44809#L366-18 assume !(1 == ~t5_pc~0); 44807#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 44805#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44803#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 44800#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 44798#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 44796#L641-3 assume !(1 == ~T1_E~0); 44795#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44793#L651-3 assume !(1 == ~T3_E~0); 44791#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44789#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44787#L666-3 assume !(1 == ~E_1~0); 44785#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44782#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44780#L681-3 assume !(1 == ~E_4~0); 44779#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44778#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44773#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 44766#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 44764#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 44727#L911 assume !(0 == start_simulation_~tmp~3); 44724#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44695#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 44682#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 44677#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 44670#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44663#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 44655#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 44647#L924 assume !(0 != start_simulation_~tmp___0~1); 41771#L892-1 [2020-10-26 05:48:19,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,258 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 1 times [2020-10-26 05:48:19,258 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,259 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029507521] [2020-10-26 05:48:19,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,279 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:19,294 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:19,350 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:19,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,352 INFO L82 PathProgramCache]: Analyzing trace with hash 1682626160, now seen corresponding path program 1 times [2020-10-26 05:48:19,352 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,352 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639347235] [2020-10-26 05:48:19,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:19,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:19,400 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639347235] [2020-10-26 05:48:19,401 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:19,401 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:19,402 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597010158] [2020-10-26 05:48:19,402 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:19,403 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:19,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:19,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:19,408 INFO L87 Difference]: Start difference. First operand 5580 states and 7917 transitions. cyclomatic complexity: 2339 Second operand 3 states. [2020-10-26 05:48:19,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:19,470 INFO L93 Difference]: Finished difference Result 6496 states and 9195 transitions. [2020-10-26 05:48:19,470 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:19,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6496 states and 9195 transitions. [2020-10-26 05:48:19,513 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6364 [2020-10-26 05:48:19,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6496 states to 6496 states and 9195 transitions. [2020-10-26 05:48:19,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6496 [2020-10-26 05:48:19,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6496 [2020-10-26 05:48:19,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6496 states and 9195 transitions. [2020-10-26 05:48:19,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:19,567 INFO L691 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2020-10-26 05:48:19,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6496 states and 9195 transitions. [2020-10-26 05:48:19,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6496 to 6496. [2020-10-26 05:48:19,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6496 states. [2020-10-26 05:48:19,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6496 states to 6496 states and 9195 transitions. [2020-10-26 05:48:19,706 INFO L714 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2020-10-26 05:48:19,707 INFO L594 BuchiCegarLoop]: Abstraction has 6496 states and 9195 transitions. [2020-10-26 05:48:19,707 INFO L427 BuchiCegarLoop]: ======== Iteration 14============ [2020-10-26 05:48:19,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6496 states and 9195 transitions. [2020-10-26 05:48:19,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6364 [2020-10-26 05:48:19,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:19,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:19,744 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,745 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:19,745 INFO L794 eck$LassoCheckResult]: Stem: 54211#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 54146#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 54147#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 54051#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 54052#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53976#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53977#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54053#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53900#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53901#L418-1 assume !(0 == ~M_E~0); 53918#L578-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53919#L583-1 assume !(0 == ~T2_E~0); 53746#L588-1 assume !(0 == ~T3_E~0); 53747#L593-1 assume !(0 == ~T4_E~0); 53859#L598-1 assume !(0 == ~T5_E~0); 53860#L603-1 assume !(0 == ~E_1~0); 54103#L608-1 assume !(0 == ~E_2~0); 54104#L613-1 assume !(0 == ~E_3~0); 53993#L618-1 assume !(0 == ~E_4~0); 53994#L623-1 assume !(0 == ~E_5~0); 54062#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54063#L271 assume !(1 == ~m_pc~0); 54277#L271-2 is_master_triggered_~__retres1~0 := 0; 54278#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54313#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54314#L712 assume !(0 != activate_threads_~tmp~1); 54346#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 54347#L290 assume !(1 == ~t1_pc~0); 53835#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 53836#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53968#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53969#L720 assume !(0 != activate_threads_~tmp___0~0); 53734#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53735#L309 assume !(1 == ~t2_pc~0); 53984#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 54042#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54357#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 54356#L728 assume !(0 != activate_threads_~tmp___1~0); 54022#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 54023#L328 assume !(1 == ~t3_pc~0); 54207#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 54208#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54148#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 54149#L736 assume !(0 != activate_threads_~tmp___2~0); 54181#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54182#L347 assume !(1 == ~t4_pc~0); 53869#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 53870#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54271#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 54272#L744 assume !(0 != activate_threads_~tmp___3~0); 54292#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54293#L366 assume !(1 == ~t5_pc~0); 54092#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 54088#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54089#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 54349#L752 assume !(0 != activate_threads_~tmp___4~0); 53850#L752-2 assume !(1 == ~M_E~0); 53851#L641-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54102#L646-1 assume !(1 == ~T2_E~0); 54026#L651-1 assume !(1 == ~T3_E~0); 54027#L656-1 assume !(1 == ~T4_E~0); 54061#L661-1 assume !(1 == ~T5_E~0); 53911#L666-1 assume !(1 == ~E_1~0); 53912#L671-1 assume !(1 == ~E_2~0); 53738#L676-1 assume !(1 == ~E_3~0); 53739#L681-1 assume !(1 == ~E_4~0); 53853#L686-1 assume !(1 == ~E_5~0); 53854#L892-1 [2020-10-26 05:48:19,745 INFO L796 eck$LassoCheckResult]: Loop: 53854#L892-1 assume !false; 57005#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 57004#L553 assume !false; 57003#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56741#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56733#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56731#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 56728#L478 assume !(0 != eval_~tmp~0); 56729#L568 start_simulation_~kernel_st~0 := 2; 54054#L386-1 start_simulation_~kernel_st~0 := 3; 54055#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 60009#L578-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60008#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60006#L588-3 assume !(0 == ~T3_E~0); 60004#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60002#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60000#L603-3 assume !(0 == ~E_1~0); 59998#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59996#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59994#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59992#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 59990#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59987#L271-18 assume !(1 == ~m_pc~0); 59985#L271-20 is_master_triggered_~__retres1~0 := 0; 59935#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54320#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54316#L712-18 assume !(0 != activate_threads_~tmp~1); 54304#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53736#L290-18 assume !(1 == ~t1_pc~0); 53737#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 59918#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59916#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 59914#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 59912#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59910#L309-18 assume 1 == ~t2_pc~0; 59908#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 59906#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59904#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 59900#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 59898#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59896#L328-18 assume !(1 == ~t3_pc~0); 58331#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 59893#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59889#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 59887#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 59885#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 59883#L347-18 assume !(1 == ~t4_pc~0); 59879#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 59877#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59875#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 59874#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 54231#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54232#L366-18 assume !(1 == ~t5_pc~0); 58658#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 58656#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 58654#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 58652#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 58650#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 58647#L641-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58644#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58642#L651-3 assume !(1 == ~T3_E~0); 58640#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58638#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58636#L666-3 assume !(1 == ~E_1~0); 58634#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58632#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 58630#L681-3 assume !(1 == ~E_4~0); 58628#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 58626#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 57057#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 57050#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 57049#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 57044#L911 assume !(0 == start_simulation_~tmp~3); 57041#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 57032#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 57029#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 57025#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 57023#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 57022#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 57021#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 57020#L924 assume !(0 != start_simulation_~tmp___0~1); 53854#L892-1 [2020-10-26 05:48:19,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,747 INFO L82 PathProgramCache]: Analyzing trace with hash -898149, now seen corresponding path program 1 times [2020-10-26 05:48:19,749 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,749 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759724754] [2020-10-26 05:48:19,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:19,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:19,815 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759724754] [2020-10-26 05:48:19,816 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:19,817 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:19,817 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [971508925] [2020-10-26 05:48:19,818 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:19,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:19,818 INFO L82 PathProgramCache]: Analyzing trace with hash -806902802, now seen corresponding path program 1 times [2020-10-26 05:48:19,819 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:19,820 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918885530] [2020-10-26 05:48:19,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:19,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:19,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:19,866 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [918885530] [2020-10-26 05:48:19,867 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:19,867 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:19,868 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344379032] [2020-10-26 05:48:19,868 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:19,868 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:19,870 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:19,871 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:19,871 INFO L87 Difference]: Start difference. First operand 6496 states and 9195 transitions. cyclomatic complexity: 2701 Second operand 3 states. [2020-10-26 05:48:19,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:19,920 INFO L93 Difference]: Finished difference Result 5580 states and 7867 transitions. [2020-10-26 05:48:19,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:19,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5580 states and 7867 transitions. [2020-10-26 05:48:19,951 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:19,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5580 states to 5580 states and 7867 transitions. [2020-10-26 05:48:19,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5580 [2020-10-26 05:48:19,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5580 [2020-10-26 05:48:19,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5580 states and 7867 transitions. [2020-10-26 05:48:19,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:19,985 INFO L691 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2020-10-26 05:48:19,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5580 states and 7867 transitions. [2020-10-26 05:48:20,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5580 to 5580. [2020-10-26 05:48:20,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5580 states. [2020-10-26 05:48:20,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 7867 transitions. [2020-10-26 05:48:20,081 INFO L714 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2020-10-26 05:48:20,081 INFO L594 BuchiCegarLoop]: Abstraction has 5580 states and 7867 transitions. [2020-10-26 05:48:20,082 INFO L427 BuchiCegarLoop]: ======== Iteration 15============ [2020-10-26 05:48:20,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 7867 transitions. [2020-10-26 05:48:20,100 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:20,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:20,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:20,103 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,103 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,103 INFO L794 eck$LassoCheckResult]: Stem: 66276#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 66216#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 66217#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66128#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 66129#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 66049#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66050#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66130#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65981#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65982#L418-1 assume !(0 == ~M_E~0); 66000#L578-1 assume !(0 == ~T1_E~0); 66001#L583-1 assume !(0 == ~T2_E~0); 65829#L588-1 assume !(0 == ~T3_E~0); 65830#L593-1 assume !(0 == ~T4_E~0); 65943#L598-1 assume !(0 == ~T5_E~0); 65944#L603-1 assume !(0 == ~E_1~0); 66172#L608-1 assume !(0 == ~E_2~0); 66173#L613-1 assume !(0 == ~E_3~0); 66069#L618-1 assume !(0 == ~E_4~0); 66070#L623-1 assume !(0 == ~E_5~0); 66134#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66135#L271 assume !(1 == ~m_pc~0); 66306#L271-2 is_master_triggered_~__retres1~0 := 0; 66308#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66309#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 66368#L712 assume !(0 != activate_threads_~tmp~1); 66399#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65928#L290 assume !(1 == ~t1_pc~0); 65919#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 65920#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65929#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65847#L720 assume !(0 != activate_threads_~tmp___0~0); 65817#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65818#L309 assume !(1 == ~t2_pc~0); 66060#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 66120#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66132#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66097#L728 assume !(0 != activate_threads_~tmp___1~0); 66098#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66100#L328 assume !(1 == ~t3_pc~0); 66273#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 66272#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66218#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 66219#L736 assume !(0 != activate_threads_~tmp___2~0); 66255#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65989#L347 assume !(1 == ~t4_pc~0); 65953#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 65954#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65988#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66333#L744 assume !(0 != activate_threads_~tmp___3~0); 66349#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 66158#L366 assume !(1 == ~t5_pc~0); 66159#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 66155#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65930#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 65931#L752 assume !(0 != activate_threads_~tmp___4~0); 65934#L752-2 assume !(1 == ~M_E~0); 65935#L641-1 assume !(1 == ~T1_E~0); 66171#L646-1 assume !(1 == ~T2_E~0); 66102#L651-1 assume !(1 == ~T3_E~0); 66103#L656-1 assume !(1 == ~T4_E~0); 66133#L661-1 assume !(1 == ~T5_E~0); 65993#L666-1 assume !(1 == ~E_1~0); 65994#L671-1 assume !(1 == ~E_2~0); 65819#L676-1 assume !(1 == ~E_3~0); 65820#L681-1 assume !(1 == ~E_4~0); 65936#L686-1 assume !(1 == ~E_5~0); 65937#L892-1 [2020-10-26 05:48:20,104 INFO L796 eck$LassoCheckResult]: Loop: 65937#L892-1 assume !false; 68696#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 68694#L553 assume !false; 68691#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 68681#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 68677#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 68675#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 68672#L478 assume !(0 != eval_~tmp~0); 68673#L568 start_simulation_~kernel_st~0 := 2; 70968#L386-1 start_simulation_~kernel_st~0 := 3; 70966#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70964#L578-4 assume !(0 == ~T1_E~0); 70962#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70960#L588-3 assume !(0 == ~T3_E~0); 70958#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70956#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70954#L603-3 assume !(0 == ~E_1~0); 70952#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70950#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70948#L618-3 assume 0 == ~E_4~0;~E_4~0 := 1; 70947#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70946#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70944#L271-18 assume !(1 == ~m_pc~0); 70942#L271-20 is_master_triggered_~__retres1~0 := 0; 70940#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70938#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 70936#L712-18 assume !(0 != activate_threads_~tmp~1); 70934#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70933#L290-18 assume !(1 == ~t1_pc~0); 70471#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 70930#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70928#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70926#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70923#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70921#L309-18 assume 1 == ~t2_pc~0; 70919#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 70920#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70973#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 70911#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 70909#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70908#L328-18 assume !(1 == ~t3_pc~0); 70906#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 70905#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70904#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 70903#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70902#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70901#L347-18 assume !(1 == ~t4_pc~0); 70899#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 70898#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70897#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70896#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 70895#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69979#L366-18 assume !(1 == ~t5_pc~0); 69977#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 69975#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69973#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 69972#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 69968#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 69959#L641-3 assume !(1 == ~T1_E~0); 69958#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69949#L651-3 assume !(1 == ~T3_E~0); 69944#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69937#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69935#L666-3 assume !(1 == ~E_1~0); 69930#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69928#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69923#L681-3 assume !(1 == ~E_4~0); 69921#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69532#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 69469#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 69459#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 69454#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 69446#L911 assume !(0 == start_simulation_~tmp~3); 69440#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 69320#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 69316#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 69305#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 69287#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 69259#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 69244#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 69235#L924 assume !(0 != start_simulation_~tmp___0~1); 65937#L892-1 [2020-10-26 05:48:20,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,104 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 2 times [2020-10-26 05:48:20,105 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,107 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26799084] [2020-10-26 05:48:20,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,121 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:20,149 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:20,182 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:20,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,183 INFO L82 PathProgramCache]: Analyzing trace with hash -703883346, now seen corresponding path program 1 times [2020-10-26 05:48:20,184 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,184 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554173567] [2020-10-26 05:48:20,184 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:20,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:20,220 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554173567] [2020-10-26 05:48:20,220 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:20,221 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:20,221 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960883050] [2020-10-26 05:48:20,221 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:20,222 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:20,222 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:20,222 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:20,223 INFO L87 Difference]: Start difference. First operand 5580 states and 7867 transitions. cyclomatic complexity: 2289 Second operand 3 states. [2020-10-26 05:48:20,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:20,351 INFO L93 Difference]: Finished difference Result 9824 states and 13727 transitions. [2020-10-26 05:48:20,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:20,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9824 states and 13727 transitions. [2020-10-26 05:48:20,409 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9684 [2020-10-26 05:48:20,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9824 states to 9824 states and 13727 transitions. [2020-10-26 05:48:20,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9824 [2020-10-26 05:48:20,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9824 [2020-10-26 05:48:20,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9824 states and 13727 transitions. [2020-10-26 05:48:20,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:20,478 INFO L691 BuchiCegarLoop]: Abstraction has 9824 states and 13727 transitions. [2020-10-26 05:48:20,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9824 states and 13727 transitions. [2020-10-26 05:48:20,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9824 to 9816. [2020-10-26 05:48:20,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9816 states. [2020-10-26 05:48:20,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9816 states to 9816 states and 13719 transitions. [2020-10-26 05:48:20,701 INFO L714 BuchiCegarLoop]: Abstraction has 9816 states and 13719 transitions. [2020-10-26 05:48:20,701 INFO L594 BuchiCegarLoop]: Abstraction has 9816 states and 13719 transitions. [2020-10-26 05:48:20,701 INFO L427 BuchiCegarLoop]: ======== Iteration 16============ [2020-10-26 05:48:20,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9816 states and 13719 transitions. [2020-10-26 05:48:20,738 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9676 [2020-10-26 05:48:20,738 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:20,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:20,742 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,742 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:20,742 INFO L794 eck$LassoCheckResult]: Stem: 81711#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 81639#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81640#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81546#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 81547#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81464#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81465#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81548#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81394#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81395#L418-1 assume !(0 == ~M_E~0); 81413#L578-1 assume !(0 == ~T1_E~0); 81414#L583-1 assume !(0 == ~T2_E~0); 81239#L588-1 assume !(0 == ~T3_E~0); 81240#L593-1 assume !(0 == ~T4_E~0); 81354#L598-1 assume !(0 == ~T5_E~0); 81355#L603-1 assume !(0 == ~E_1~0); 81598#L608-1 assume !(0 == ~E_2~0); 81599#L613-1 assume !(0 == ~E_3~0); 81484#L618-1 assume 0 == ~E_4~0;~E_4~0 := 1; 81485#L623-1 assume !(0 == ~E_5~0); 81789#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81741#L271 assume !(1 == ~m_pc~0); 81742#L271-2 is_master_triggered_~__retres1~0 := 0; 81744#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81745#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 81883#L712 assume !(0 != activate_threads_~tmp~1); 81882#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81881#L290 assume !(1 == ~t1_pc~0); 81327#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 81328#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81338#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81256#L720 assume !(0 != activate_threads_~tmp___0~0); 81227#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81228#L309 assume !(1 == ~t2_pc~0); 81475#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 81535#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81871#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81511#L728 assume !(0 != activate_threads_~tmp___1~0); 81512#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81704#L328 assume !(1 == ~t3_pc~0); 81705#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 81703#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81641#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 81642#L736 assume !(0 != activate_threads_~tmp___2~0); 81681#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81402#L347 assume !(1 == ~t4_pc~0); 81403#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 81773#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81770#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81771#L744 assume !(0 != activate_threads_~tmp___3~0); 81799#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81581#L366 assume !(1 == ~t5_pc~0); 81582#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 81584#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81340#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81341#L752 assume !(0 != activate_threads_~tmp___4~0); 81344#L752-2 assume !(1 == ~M_E~0); 81345#L641-1 assume !(1 == ~T1_E~0); 81597#L646-1 assume !(1 == ~T2_E~0); 81518#L651-1 assume !(1 == ~T3_E~0); 81519#L656-1 assume !(1 == ~T4_E~0); 81551#L661-1 assume !(1 == ~T5_E~0); 81406#L666-1 assume !(1 == ~E_1~0); 81407#L671-1 assume !(1 == ~E_2~0); 81229#L676-1 assume !(1 == ~E_3~0); 81230#L681-1 assume 1 == ~E_4~0;~E_4~0 := 2; 81346#L686-1 assume !(1 == ~E_5~0); 81347#L892-1 [2020-10-26 05:48:20,743 INFO L796 eck$LassoCheckResult]: Loop: 81347#L892-1 assume !false; 85483#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 85482#L553 assume !false; 85480#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 85467#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 85463#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 85459#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 85456#L478 assume !(0 != eval_~tmp~0); 85457#L568 start_simulation_~kernel_st~0 := 2; 90961#L386-1 start_simulation_~kernel_st~0 := 3; 90958#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 90955#L578-4 assume !(0 == ~T1_E~0); 90952#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 90949#L588-3 assume !(0 == ~T3_E~0); 90945#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90943#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90941#L603-3 assume !(0 == ~E_1~0); 90939#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 90935#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 90932#L618-3 assume !(0 == ~E_4~0); 90929#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 90927#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90925#L271-18 assume !(1 == ~m_pc~0); 90924#L271-20 is_master_triggered_~__retres1~0 := 0; 90923#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 90922#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90921#L712-18 assume !(0 != activate_threads_~tmp~1); 90920#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90918#L290-18 assume !(1 == ~t1_pc~0); 87217#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 90917#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90916#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90915#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 90914#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90913#L309-18 assume 1 == ~t2_pc~0; 90911#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 90912#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90919#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90903#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 90901#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 85735#L328-18 assume !(1 == ~t3_pc~0); 85734#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 85727#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85725#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 85723#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 85720#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85715#L347-18 assume !(1 == ~t4_pc~0); 85713#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 85712#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 85710#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 85706#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 85703#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 85701#L366-18 assume !(1 == ~t5_pc~0); 85699#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 85696#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 85694#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 85692#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 85690#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 85688#L641-3 assume !(1 == ~T1_E~0); 85686#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85684#L651-3 assume !(1 == ~T3_E~0); 85682#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85680#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85678#L666-3 assume !(1 == ~E_1~0); 85676#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 85674#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85666#L681-3 assume !(1 == ~E_4~0); 85665#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85663#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 85660#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 85653#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 85651#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 85648#L911 assume !(0 == start_simulation_~tmp~3); 85645#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 85522#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 85516#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 85514#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 85512#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 85509#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 85507#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 85505#L924 assume !(0 != start_simulation_~tmp___0~1); 81347#L892-1 [2020-10-26 05:48:20,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,743 INFO L82 PathProgramCache]: Analyzing trace with hash 882510747, now seen corresponding path program 1 times [2020-10-26 05:48:20,744 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,744 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103038086] [2020-10-26 05:48:20,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:20,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:20,782 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103038086] [2020-10-26 05:48:20,782 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:20,782 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:20,783 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1326661271] [2020-10-26 05:48:20,783 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:20,783 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:20,784 INFO L82 PathProgramCache]: Analyzing trace with hash -24611092, now seen corresponding path program 1 times [2020-10-26 05:48:20,784 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:20,784 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954979672] [2020-10-26 05:48:20,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:20,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:20,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:20,843 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954979672] [2020-10-26 05:48:20,843 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:20,843 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:20,844 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086709658] [2020-10-26 05:48:20,844 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:20,844 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:20,845 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:20,845 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:20,845 INFO L87 Difference]: Start difference. First operand 9816 states and 13719 transitions. cyclomatic complexity: 3905 Second operand 3 states. [2020-10-26 05:48:20,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:20,910 INFO L93 Difference]: Finished difference Result 5580 states and 7728 transitions. [2020-10-26 05:48:20,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:20,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5580 states and 7728 transitions. [2020-10-26 05:48:20,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:20,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5580 states to 5580 states and 7728 transitions. [2020-10-26 05:48:20,958 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5580 [2020-10-26 05:48:20,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5580 [2020-10-26 05:48:20,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5580 states and 7728 transitions. [2020-10-26 05:48:20,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:20,974 INFO L691 BuchiCegarLoop]: Abstraction has 5580 states and 7728 transitions. [2020-10-26 05:48:20,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5580 states and 7728 transitions. [2020-10-26 05:48:21,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5580 to 5580. [2020-10-26 05:48:21,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5580 states. [2020-10-26 05:48:21,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5580 states to 5580 states and 7728 transitions. [2020-10-26 05:48:21,075 INFO L714 BuchiCegarLoop]: Abstraction has 5580 states and 7728 transitions. [2020-10-26 05:48:21,075 INFO L594 BuchiCegarLoop]: Abstraction has 5580 states and 7728 transitions. [2020-10-26 05:48:21,075 INFO L427 BuchiCegarLoop]: ======== Iteration 17============ [2020-10-26 05:48:21,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5580 states and 7728 transitions. [2020-10-26 05:48:21,092 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5500 [2020-10-26 05:48:21,093 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:21,093 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:21,145 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:21,145 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:21,145 INFO L794 eck$LassoCheckResult]: Stem: 97089#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 97033#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 97034#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 96943#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 96944#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96864#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96865#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96945#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96790#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96791#L418-1 assume !(0 == ~M_E~0); 96808#L578-1 assume !(0 == ~T1_E~0); 96809#L583-1 assume !(0 == ~T2_E~0); 96644#L588-1 assume !(0 == ~T3_E~0); 96645#L593-1 assume !(0 == ~T4_E~0); 96753#L598-1 assume !(0 == ~T5_E~0); 96754#L603-1 assume !(0 == ~E_1~0); 96991#L608-1 assume !(0 == ~E_2~0); 96992#L613-1 assume !(0 == ~E_3~0); 96884#L618-1 assume !(0 == ~E_4~0); 96885#L623-1 assume !(0 == ~E_5~0); 96949#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96950#L271 assume !(1 == ~m_pc~0); 97121#L271-2 is_master_triggered_~__retres1~0 := 0; 97123#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97124#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 97174#L712 assume !(0 != activate_threads_~tmp~1); 97201#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96738#L290 assume !(1 == ~t1_pc~0); 96729#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 96730#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96739#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 96661#L720 assume !(0 != activate_threads_~tmp___0~0); 96632#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96633#L309 assume !(1 == ~t2_pc~0); 96875#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 96933#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96947#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 96910#L728 assume !(0 != activate_threads_~tmp___1~0); 96911#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96913#L328 assume !(1 == ~t3_pc~0); 97086#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 97085#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97035#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 97036#L736 assume !(0 != activate_threads_~tmp___2~0); 97070#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96798#L347 assume !(1 == ~t4_pc~0); 96762#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 96763#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 96797#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 97145#L744 assume !(0 != activate_threads_~tmp___3~0); 97160#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 96978#L366 assume !(1 == ~t5_pc~0); 96979#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 96975#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 96740#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 96741#L752 assume !(0 != activate_threads_~tmp___4~0); 96744#L752-2 assume !(1 == ~M_E~0); 96745#L641-1 assume !(1 == ~T1_E~0); 96990#L646-1 assume !(1 == ~T2_E~0); 96916#L651-1 assume !(1 == ~T3_E~0); 96917#L656-1 assume !(1 == ~T4_E~0); 96948#L661-1 assume !(1 == ~T5_E~0); 96801#L666-1 assume !(1 == ~E_1~0); 96802#L671-1 assume !(1 == ~E_2~0); 96634#L676-1 assume !(1 == ~E_3~0); 96635#L681-1 assume !(1 == ~E_4~0); 96746#L686-1 assume !(1 == ~E_5~0); 96747#L892-1 [2020-10-26 05:48:21,145 INFO L796 eck$LassoCheckResult]: Loop: 96747#L892-1 assume !false; 99312#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 99311#L553 assume !false; 99309#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 99206#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 99202#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 99191#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 99184#L478 assume !(0 != eval_~tmp~0); 99185#L568 start_simulation_~kernel_st~0 := 2; 101860#L386-1 start_simulation_~kernel_st~0 := 3; 101856#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 101852#L578-4 assume !(0 == ~T1_E~0); 101848#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 101845#L588-3 assume !(0 == ~T3_E~0); 101841#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101834#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100640#L603-3 assume !(0 == ~E_1~0); 100641#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100634#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100635#L618-3 assume !(0 == ~E_4~0); 100628#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 100629#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100621#L271-18 assume !(1 == ~m_pc~0); 100622#L271-20 is_master_triggered_~__retres1~0 := 0; 100615#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100616#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 100599#L712-18 assume !(0 != activate_threads_~tmp~1); 100600#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 100594#L290-18 assume !(1 == ~t1_pc~0); 100592#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 100589#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 100587#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 100584#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 100583#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100582#L309-18 assume !(1 == ~t2_pc~0); 100577#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 100575#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100573#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 100571#L728-18 assume !(0 != activate_threads_~tmp___1~0); 100569#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 100568#L328-18 assume !(1 == ~t3_pc~0); 100184#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 100565#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 100563#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 100561#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 100559#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 100555#L347-18 assume !(1 == ~t4_pc~0); 100554#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 100552#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 100549#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 100544#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 100451#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 99528#L366-18 assume !(1 == ~t5_pc~0); 99523#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 99518#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 99512#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 99507#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 99480#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 99478#L641-3 assume !(1 == ~T1_E~0); 99476#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 99474#L651-3 assume !(1 == ~T3_E~0); 99472#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99470#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99468#L666-3 assume !(1 == ~E_1~0); 99466#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 99464#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 99462#L681-3 assume !(1 == ~E_4~0); 99460#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99458#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 99456#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 99438#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 99431#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 99423#L911 assume !(0 == start_simulation_~tmp~3); 99419#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 99372#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 99366#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 99362#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 99357#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 99352#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 99348#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 99345#L924 assume !(0 != start_simulation_~tmp___0~1); 96747#L892-1 [2020-10-26 05:48:21,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:21,146 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 3 times [2020-10-26 05:48:21,146 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:21,146 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393226908] [2020-10-26 05:48:21,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:21,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:21,168 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:21,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:21,179 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:21,204 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:21,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:21,205 INFO L82 PathProgramCache]: Analyzing trace with hash 1479520751, now seen corresponding path program 1 times [2020-10-26 05:48:21,205 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:21,205 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197193617] [2020-10-26 05:48:21,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:21,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:21,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:21,244 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197193617] [2020-10-26 05:48:21,248 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:21,248 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:21,248 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [221862571] [2020-10-26 05:48:21,249 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:21,249 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:21,249 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:48:21,250 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:48:21,250 INFO L87 Difference]: Start difference. First operand 5580 states and 7728 transitions. cyclomatic complexity: 2150 Second operand 5 states. [2020-10-26 05:48:21,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:21,415 INFO L93 Difference]: Finished difference Result 9904 states and 13544 transitions. [2020-10-26 05:48:21,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2020-10-26 05:48:21,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9904 states and 13544 transitions. [2020-10-26 05:48:21,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9816 [2020-10-26 05:48:21,502 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9904 states to 9904 states and 13544 transitions. [2020-10-26 05:48:21,502 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9904 [2020-10-26 05:48:21,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9904 [2020-10-26 05:48:21,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9904 states and 13544 transitions. [2020-10-26 05:48:21,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:21,533 INFO L691 BuchiCegarLoop]: Abstraction has 9904 states and 13544 transitions. [2020-10-26 05:48:21,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9904 states and 13544 transitions. [2020-10-26 05:48:21,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9904 to 5628. [2020-10-26 05:48:21,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5628 states. [2020-10-26 05:48:21,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5628 states to 5628 states and 7776 transitions. [2020-10-26 05:48:21,660 INFO L714 BuchiCegarLoop]: Abstraction has 5628 states and 7776 transitions. [2020-10-26 05:48:21,660 INFO L594 BuchiCegarLoop]: Abstraction has 5628 states and 7776 transitions. [2020-10-26 05:48:21,660 INFO L427 BuchiCegarLoop]: ======== Iteration 18============ [2020-10-26 05:48:21,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5628 states and 7776 transitions. [2020-10-26 05:48:21,681 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5548 [2020-10-26 05:48:21,682 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:21,682 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:21,685 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:21,685 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:21,686 INFO L794 eck$LassoCheckResult]: Stem: 112581#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 112528#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 112529#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 112439#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 112440#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112364#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112365#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112441#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112291#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112292#L418-1 assume !(0 == ~M_E~0); 112309#L578-1 assume !(0 == ~T1_E~0); 112310#L583-1 assume !(0 == ~T2_E~0); 112144#L588-1 assume !(0 == ~T3_E~0); 112145#L593-1 assume !(0 == ~T4_E~0); 112252#L598-1 assume !(0 == ~T5_E~0); 112253#L603-1 assume !(0 == ~E_1~0); 112487#L608-1 assume !(0 == ~E_2~0); 112488#L613-1 assume !(0 == ~E_3~0); 112384#L618-1 assume !(0 == ~E_4~0); 112385#L623-1 assume !(0 == ~E_5~0); 112445#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 112446#L271 assume !(1 == ~m_pc~0); 112610#L271-2 is_master_triggered_~__retres1~0 := 0; 112612#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 112613#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 112672#L712 assume !(0 != activate_threads_~tmp~1); 112703#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 112237#L290 assume !(1 == ~t1_pc~0); 112228#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 112229#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 112238#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 112160#L720 assume !(0 != activate_threads_~tmp___0~0); 112132#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 112133#L309 assume !(1 == ~t2_pc~0); 112375#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 112431#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 112443#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 112410#L728 assume !(0 != activate_threads_~tmp___1~0); 112411#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 112413#L328 assume !(1 == ~t3_pc~0); 112578#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 112577#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 112530#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 112531#L736 assume !(0 != activate_threads_~tmp___2~0); 112565#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112299#L347 assume !(1 == ~t4_pc~0); 112263#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 112264#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 112298#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 112634#L744 assume !(0 != activate_threads_~tmp___3~0); 112650#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 112473#L366 assume !(1 == ~t5_pc~0); 112474#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 112470#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 112239#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 112240#L752 assume !(0 != activate_threads_~tmp___4~0); 112243#L752-2 assume !(1 == ~M_E~0); 112244#L641-1 assume !(1 == ~T1_E~0); 112486#L646-1 assume !(1 == ~T2_E~0); 112415#L651-1 assume !(1 == ~T3_E~0); 112416#L656-1 assume !(1 == ~T4_E~0); 112444#L661-1 assume !(1 == ~T5_E~0); 112302#L666-1 assume !(1 == ~E_1~0); 112303#L671-1 assume !(1 == ~E_2~0); 112134#L676-1 assume !(1 == ~E_3~0); 112135#L681-1 assume !(1 == ~E_4~0); 112245#L686-1 assume !(1 == ~E_5~0); 112246#L892-1 [2020-10-26 05:48:21,686 INFO L796 eck$LassoCheckResult]: Loop: 112246#L892-1 assume !false; 112419#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 112308#L553 assume !false; 116867#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116826#L431 assume !(0 == ~m_st~0); 116827#L435 assume !(0 == ~t1_st~0); 116829#L439 assume !(0 == ~t2_st~0); 116824#L443 assume !(0 == ~t3_st~0); 116825#L447 assume !(0 == ~t4_st~0); 116828#L451 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 116830#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 112397#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 112398#L478 assume !(0 != eval_~tmp~0); 116801#L568 start_simulation_~kernel_st~0 := 2; 117104#L386-1 start_simulation_~kernel_st~0 := 3; 117103#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 117102#L578-4 assume !(0 == ~T1_E~0); 117101#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 117100#L588-3 assume !(0 == ~T3_E~0); 117099#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117098#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 112656#L603-3 assume !(0 == ~E_1~0); 112480#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 112481#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117096#L618-3 assume !(0 == ~E_4~0); 112647#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112648#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 112702#L271-18 assume !(1 == ~m_pc~0); 112698#L271-20 is_master_triggered_~__retres1~0 := 0; 112599#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 112600#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 112674#L712-18 assume !(0 != activate_threads_~tmp~1); 112663#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 112664#L290-18 assume !(1 == ~t1_pc~0); 112732#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 117092#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117091#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 112330#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 112331#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 112332#L309-18 assume 1 == ~t2_pc~0; 112409#L310-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 112436#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 112437#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 117446#L728-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 112491#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 112492#L328-18 assume !(1 == ~t3_pc~0); 112563#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 112564#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 112512#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 112513#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 112525#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112526#L347-18 assume !(1 == ~t4_pc~0); 112651#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 112275#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 112276#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 112622#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 112601#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 112257#L366-18 assume !(1 == ~t5_pc~0); 112258#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 112260#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 112181#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 112182#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 112186#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 112195#L641-3 assume !(1 == ~T1_E~0); 112479#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112390#L651-3 assume !(1 == ~T3_E~0); 112391#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112447#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112304#L666-3 assume !(1 == ~E_1~0); 112305#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 112142#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112143#L681-3 assume !(1 == ~E_4~0); 112250#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112251#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 112361#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 112289#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 112402#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 112403#L911 assume !(0 == start_simulation_~tmp~3); 112158#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 112659#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117722#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117721#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 117719#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 117717#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 117715#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 117713#L924 assume !(0 != start_simulation_~tmp___0~1); 112246#L892-1 [2020-10-26 05:48:21,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:21,687 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 4 times [2020-10-26 05:48:21,688 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:21,688 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249719201] [2020-10-26 05:48:21,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:21,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:21,703 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:21,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:21,718 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:21,742 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:21,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:21,744 INFO L82 PathProgramCache]: Analyzing trace with hash -2117164847, now seen corresponding path program 1 times [2020-10-26 05:48:21,744 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:21,744 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452176993] [2020-10-26 05:48:21,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:21,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:21,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:21,814 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452176993] [2020-10-26 05:48:21,815 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:21,815 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:21,815 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1631953302] [2020-10-26 05:48:21,815 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:21,816 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:21,818 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:21,818 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:21,819 INFO L87 Difference]: Start difference. First operand 5628 states and 7776 transitions. cyclomatic complexity: 2150 Second operand 3 states. [2020-10-26 05:48:21,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:21,916 INFO L93 Difference]: Finished difference Result 10456 states and 14208 transitions. [2020-10-26 05:48:21,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:21,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10456 states and 14208 transitions. [2020-10-26 05:48:21,979 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10376 [2020-10-26 05:48:22,028 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10456 states to 10456 states and 14208 transitions. [2020-10-26 05:48:22,028 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10456 [2020-10-26 05:48:22,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10456 [2020-10-26 05:48:22,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10456 states and 14208 transitions. [2020-10-26 05:48:22,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:22,057 INFO L691 BuchiCegarLoop]: Abstraction has 10456 states and 14208 transitions. [2020-10-26 05:48:22,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10456 states and 14208 transitions. [2020-10-26 05:48:22,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10456 to 10140. [2020-10-26 05:48:22,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10140 states. [2020-10-26 05:48:22,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10140 states to 10140 states and 13804 transitions. [2020-10-26 05:48:22,277 INFO L714 BuchiCegarLoop]: Abstraction has 10140 states and 13804 transitions. [2020-10-26 05:48:22,277 INFO L594 BuchiCegarLoop]: Abstraction has 10140 states and 13804 transitions. [2020-10-26 05:48:22,277 INFO L427 BuchiCegarLoop]: ======== Iteration 19============ [2020-10-26 05:48:22,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10140 states and 13804 transitions. [2020-10-26 05:48:22,316 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10060 [2020-10-26 05:48:22,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:22,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:22,319 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:22,319 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:22,320 INFO L794 eck$LassoCheckResult]: Stem: 128686#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 128627#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 128628#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 128537#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 128538#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128454#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128455#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128539#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128383#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 128384#L418-1 assume !(0 == ~M_E~0); 128401#L578-1 assume !(0 == ~T1_E~0); 128402#L583-1 assume !(0 == ~T2_E~0); 128234#L588-1 assume !(0 == ~T3_E~0); 128235#L593-1 assume !(0 == ~T4_E~0); 128344#L598-1 assume !(0 == ~T5_E~0); 128345#L603-1 assume !(0 == ~E_1~0); 128587#L608-1 assume !(0 == ~E_2~0); 128588#L613-1 assume !(0 == ~E_3~0); 128474#L618-1 assume !(0 == ~E_4~0); 128475#L623-1 assume !(0 == ~E_5~0); 128544#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128545#L271 assume !(1 == ~m_pc~0); 128715#L271-2 is_master_triggered_~__retres1~0 := 0; 128717#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 128718#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 128770#L712 assume !(0 != activate_threads_~tmp~1); 128806#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 128329#L290 assume !(1 == ~t1_pc~0); 128320#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 128321#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 128330#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 128250#L720 assume !(0 != activate_threads_~tmp___0~0); 128222#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128223#L309 assume !(1 == ~t2_pc~0); 128465#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 128525#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 128541#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 128503#L728 assume !(0 != activate_threads_~tmp___1~0); 128504#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 128506#L328 assume !(1 == ~t3_pc~0); 128682#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 128681#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128629#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 128630#L736 assume !(0 != activate_threads_~tmp___2~0); 128664#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 128391#L347 assume !(1 == ~t4_pc~0); 128355#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 128356#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 128390#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 128739#L744 assume !(0 != activate_threads_~tmp___3~0); 128754#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128573#L366 assume !(1 == ~t5_pc~0); 128574#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 128570#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 128331#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 128332#L752 assume !(0 != activate_threads_~tmp___4~0); 128335#L752-2 assume !(1 == ~M_E~0); 128336#L641-1 assume !(1 == ~T1_E~0); 128586#L646-1 assume !(1 == ~T2_E~0); 128508#L651-1 assume !(1 == ~T3_E~0); 128509#L656-1 assume !(1 == ~T4_E~0); 128543#L661-1 assume !(1 == ~T5_E~0); 128394#L666-1 assume !(1 == ~E_1~0); 128395#L671-1 assume !(1 == ~E_2~0); 128224#L676-1 assume !(1 == ~E_3~0); 128225#L681-1 assume !(1 == ~E_4~0); 128337#L686-1 assume !(1 == ~E_5~0); 128338#L892-1 [2020-10-26 05:48:22,321 INFO L796 eck$LassoCheckResult]: Loop: 128338#L892-1 assume !false; 137899#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 135027#L553 assume !false; 137892#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 137891#L431 assume !(0 == ~m_st~0); 128376#L435 assume !(0 == ~t1_st~0); 128378#L439 assume !(0 == ~t2_st~0); 128582#L443 assume !(0 == ~t3_st~0); 128583#L447 assume !(0 == ~t4_st~0); 128689#L451 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 128690#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 138270#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 138269#L478 assume !(0 != eval_~tmp~0); 128751#L568 start_simulation_~kernel_st~0 := 2; 128540#L386-1 start_simulation_~kernel_st~0 := 3; 128403#L578-2 assume 0 == ~M_E~0;~M_E~0 := 1; 128374#L578-4 assume !(0 == ~T1_E~0); 128375#L583-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 128433#L588-3 assume !(0 == ~T3_E~0); 128434#L593-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128322#L598-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128323#L603-3 assume !(0 == ~E_1~0); 128580#L608-3 assume 0 == ~E_2~0;~E_2~0 := 1; 128581#L613-3 assume 0 == ~E_3~0;~E_3~0 := 1; 128483#L618-3 assume !(0 == ~E_4~0); 128484#L623-3 assume 0 == ~E_5~0;~E_5~0 := 1; 128547#L628-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128548#L271-18 assume !(1 == ~m_pc~0); 128800#L271-20 is_master_triggered_~__retres1~0 := 0; 128703#L282-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 128704#L283-6 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 128772#L712-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 128774#L712-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 137874#L290-18 assume !(1 == ~t1_pc~0); 137872#L290-20 is_transmit1_triggered_~__retres1~1 := 0; 137870#L301-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 137868#L302-6 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 137865#L720-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 137862#L720-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 137859#L309-18 assume !(1 == ~t2_pc~0); 137856#L309-20 is_transmit2_triggered_~__retres1~2 := 0; 137851#L320-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 137846#L321-6 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 137841#L728-18 assume !(0 != activate_threads_~tmp___1~0); 137836#L728-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 137833#L328-18 assume !(1 == ~t3_pc~0); 137832#L328-20 is_transmit3_triggered_~__retres1~3 := 0; 137830#L339-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 137828#L340-6 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 137826#L736-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 137824#L736-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 137821#L347-18 assume !(1 == ~t4_pc~0); 137820#L347-20 is_transmit4_triggered_~__retres1~4 := 0; 137819#L358-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 137818#L359-6 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 137817#L744-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 137816#L744-20 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 137815#L366-18 assume !(1 == ~t5_pc~0); 135091#L366-20 is_transmit5_triggered_~__retres1~5 := 0; 137814#L377-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 137813#L378-6 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 137812#L752-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 137811#L752-20 assume 1 == ~M_E~0;~M_E~0 := 2; 137810#L641-3 assume !(1 == ~T1_E~0); 137808#L646-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137806#L651-3 assume !(1 == ~T3_E~0); 137804#L656-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137802#L661-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137799#L666-3 assume !(1 == ~E_1~0); 137797#L671-3 assume 1 == ~E_2~0;~E_2~0 := 2; 137795#L676-3 assume 1 == ~E_3~0;~E_3~0 := 2; 137794#L681-3 assume !(1 == ~E_4~0); 137792#L686-3 assume 1 == ~E_5~0;~E_5~0 := 2; 137790#L691-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 137787#L431-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 137788#L463-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 128495#L464-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 128496#L911 assume !(0 == start_simulation_~tmp~3); 137945#L911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 137930#L431-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 137907#L463-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 137906#L464-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 137904#L866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 137902#L873 stop_simulation_#res := stop_simulation_~__retres2~0; 137901#L874 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 137900#L924 assume !(0 != start_simulation_~tmp___0~1); 128338#L892-1 [2020-10-26 05:48:22,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:22,322 INFO L82 PathProgramCache]: Analyzing trace with hash 866992091, now seen corresponding path program 5 times [2020-10-26 05:48:22,322 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:22,322 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689700649] [2020-10-26 05:48:22,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:22,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:22,334 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:22,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:22,346 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:22,373 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:22,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:22,375 INFO L82 PathProgramCache]: Analyzing trace with hash -1999818414, now seen corresponding path program 1 times [2020-10-26 05:48:22,375 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:22,376 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517096301] [2020-10-26 05:48:22,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:22,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:22,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:22,460 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517096301] [2020-10-26 05:48:22,460 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:22,461 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2020-10-26 05:48:22,461 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229587089] [2020-10-26 05:48:22,463 INFO L811 eck$LassoCheckResult]: loop already infeasible [2020-10-26 05:48:22,463 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:22,463 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2020-10-26 05:48:22,464 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2020-10-26 05:48:22,464 INFO L87 Difference]: Start difference. First operand 10140 states and 13804 transitions. cyclomatic complexity: 3666 Second operand 5 states. [2020-10-26 05:48:22,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:22,756 INFO L93 Difference]: Finished difference Result 16494 states and 22355 transitions. [2020-10-26 05:48:22,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2020-10-26 05:48:22,757 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16494 states and 22355 transitions. [2020-10-26 05:48:22,853 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16412 [2020-10-26 05:48:22,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16494 states to 16494 states and 22355 transitions. [2020-10-26 05:48:22,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16494 [2020-10-26 05:48:22,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16494 [2020-10-26 05:48:22,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16494 states and 22355 transitions. [2020-10-26 05:48:22,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:22,975 INFO L691 BuchiCegarLoop]: Abstraction has 16494 states and 22355 transitions. [2020-10-26 05:48:22,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16494 states and 22355 transitions. [2020-10-26 05:48:23,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16494 to 9454. [2020-10-26 05:48:23,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9454 states. [2020-10-26 05:48:23,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9454 states to 9454 states and 12733 transitions. [2020-10-26 05:48:23,176 INFO L714 BuchiCegarLoop]: Abstraction has 9454 states and 12733 transitions. [2020-10-26 05:48:23,176 INFO L594 BuchiCegarLoop]: Abstraction has 9454 states and 12733 transitions. [2020-10-26 05:48:23,176 INFO L427 BuchiCegarLoop]: ======== Iteration 20============ [2020-10-26 05:48:23,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9454 states and 12733 transitions. [2020-10-26 05:48:23,210 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 9372 [2020-10-26 05:48:23,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:23,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:23,212 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:23,212 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:23,212 INFO L794 eck$LassoCheckResult]: Stem: 155328#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 155271#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 155272#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 155182#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 155183#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 155104#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 155105#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 155184#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 155034#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 155035#L418-1 assume !(0 == ~M_E~0); 155052#L578-1 assume !(0 == ~T1_E~0); 155053#L583-1 assume !(0 == ~T2_E~0); 154881#L588-1 assume !(0 == ~T3_E~0); 154882#L593-1 assume !(0 == ~T4_E~0); 154995#L598-1 assume !(0 == ~T5_E~0); 154996#L603-1 assume !(0 == ~E_1~0); 155228#L608-1 assume !(0 == ~E_2~0); 155229#L613-1 assume !(0 == ~E_3~0); 155124#L618-1 assume !(0 == ~E_4~0); 155125#L623-1 assume !(0 == ~E_5~0); 155188#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 155189#L271 assume !(1 == ~m_pc~0); 155361#L271-2 is_master_triggered_~__retres1~0 := 0; 155363#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 155364#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 155424#L712 assume !(0 != activate_threads_~tmp~1); 155458#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154980#L290 assume !(1 == ~t1_pc~0); 154970#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 154971#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 154981#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 154899#L720 assume !(0 != activate_threads_~tmp___0~0); 154869#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 154870#L309 assume !(1 == ~t2_pc~0); 155115#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 155173#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 155186#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 155152#L728 assume !(0 != activate_threads_~tmp___1~0); 155153#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 155155#L328 assume !(1 == ~t3_pc~0); 155324#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 155323#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 155273#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 155274#L736 assume !(0 != activate_threads_~tmp___2~0); 155308#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 155042#L347 assume !(1 == ~t4_pc~0); 155006#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 155007#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 155041#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 155388#L744 assume !(0 != activate_threads_~tmp___3~0); 155406#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155216#L366 assume !(1 == ~t5_pc~0); 155217#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 155213#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 154982#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 154983#L752 assume !(0 != activate_threads_~tmp___4~0); 154986#L752-2 assume !(1 == ~M_E~0); 154987#L641-1 assume !(1 == ~T1_E~0); 155227#L646-1 assume !(1 == ~T2_E~0); 155157#L651-1 assume !(1 == ~T3_E~0); 155158#L656-1 assume !(1 == ~T4_E~0); 155187#L661-1 assume !(1 == ~T5_E~0); 155045#L666-1 assume !(1 == ~E_1~0); 155046#L671-1 assume !(1 == ~E_2~0); 154871#L676-1 assume !(1 == ~E_3~0); 154872#L681-1 assume !(1 == ~E_4~0); 154988#L686-1 assume !(1 == ~E_5~0); 154989#L892-1 assume !false; 156737#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 156473#L553 [2020-10-26 05:48:23,213 INFO L796 eck$LassoCheckResult]: Loop: 156473#L553 assume !false; 156725#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 156718#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 156714#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156708#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 156705#L478 assume 0 != eval_~tmp~0; 156692#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 156593#L486 assume !(0 != eval_~tmp_ndt_1~0); 156584#L483 assume !(0 == ~t1_st~0); 156578#L497 assume !(0 == ~t2_st~0); 156570#L511 assume !(0 == ~t3_st~0); 156496#L525 assume !(0 == ~t4_st~0); 156478#L539 assume !(0 == ~t5_st~0); 156473#L553 [2020-10-26 05:48:23,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:23,215 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 1 times [2020-10-26 05:48:23,215 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:23,215 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504012621] [2020-10-26 05:48:23,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:23,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:23,228 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:23,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:23,242 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:23,266 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:23,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:23,267 INFO L82 PathProgramCache]: Analyzing trace with hash 346179053, now seen corresponding path program 1 times [2020-10-26 05:48:23,267 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:23,267 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563950551] [2020-10-26 05:48:23,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:23,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:23,272 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:23,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:23,275 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:23,277 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:23,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:23,278 INFO L82 PathProgramCache]: Analyzing trace with hash -956602927, now seen corresponding path program 1 times [2020-10-26 05:48:23,278 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:23,278 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [602743992] [2020-10-26 05:48:23,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:23,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:23,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:23,326 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [602743992] [2020-10-26 05:48:23,326 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:23,327 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:23,327 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [17663072] [2020-10-26 05:48:23,432 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:23,432 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:23,433 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:23,433 INFO L87 Difference]: Start difference. First operand 9454 states and 12733 transitions. cyclomatic complexity: 3282 Second operand 3 states. [2020-10-26 05:48:23,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:23,550 INFO L93 Difference]: Finished difference Result 17835 states and 23796 transitions. [2020-10-26 05:48:23,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:23,551 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17835 states and 23796 transitions. [2020-10-26 05:48:23,724 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17676 [2020-10-26 05:48:23,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17835 states to 17835 states and 23796 transitions. [2020-10-26 05:48:23,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17835 [2020-10-26 05:48:23,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17835 [2020-10-26 05:48:23,796 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17835 states and 23796 transitions. [2020-10-26 05:48:23,812 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:23,813 INFO L691 BuchiCegarLoop]: Abstraction has 17835 states and 23796 transitions. [2020-10-26 05:48:23,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17835 states and 23796 transitions. [2020-10-26 05:48:24,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17835 to 17307. [2020-10-26 05:48:24,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17307 states. [2020-10-26 05:48:24,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17307 states to 17307 states and 23124 transitions. [2020-10-26 05:48:24,052 INFO L714 BuchiCegarLoop]: Abstraction has 17307 states and 23124 transitions. [2020-10-26 05:48:24,052 INFO L594 BuchiCegarLoop]: Abstraction has 17307 states and 23124 transitions. [2020-10-26 05:48:24,052 INFO L427 BuchiCegarLoop]: ======== Iteration 21============ [2020-10-26 05:48:24,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17307 states and 23124 transitions. [2020-10-26 05:48:24,109 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2020-10-26 05:48:24,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:24,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:24,110 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:24,110 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:24,110 INFO L794 eck$LassoCheckResult]: Stem: 182643#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 182581#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 182582#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 182494#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 182495#L393-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 182408#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 182409#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 182496#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 182331#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 182332#L418-1 assume !(0 == ~M_E~0); 182348#L578-1 assume !(0 == ~T1_E~0); 182349#L583-1 assume !(0 == ~T2_E~0); 182178#L588-1 assume !(0 == ~T3_E~0); 182179#L593-1 assume !(0 == ~T4_E~0); 182296#L598-1 assume !(0 == ~T5_E~0); 182297#L603-1 assume !(0 == ~E_1~0); 182541#L608-1 assume !(0 == ~E_2~0); 182542#L613-1 assume !(0 == ~E_3~0); 182428#L618-1 assume !(0 == ~E_4~0); 182429#L623-1 assume !(0 == ~E_5~0); 182500#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 182501#L271 assume !(1 == ~m_pc~0); 182674#L271-2 is_master_triggered_~__retres1~0 := 0; 182676#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 182677#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 182731#L712 assume !(0 != activate_threads_~tmp~1); 182767#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 182280#L290 assume !(1 == ~t1_pc~0); 182270#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 182271#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 182281#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 182196#L720 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 182197#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 187106#L309 assume !(1 == ~t2_pc~0); 182483#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 182484#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 182498#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 182773#L728 assume !(0 != activate_threads_~tmp___1~0); 182463#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 182464#L328 assume !(1 == ~t3_pc~0); 182640#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 182639#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 182583#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 182584#L736 assume !(0 != activate_threads_~tmp___2~0); 186144#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 186143#L347 assume !(1 == ~t4_pc~0); 186141#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 186140#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 186139#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 186138#L744 assume !(0 != activate_threads_~tmp___3~0); 186137#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 186136#L366 assume !(1 == ~t5_pc~0); 186135#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 186134#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 186133#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 186132#L752 assume !(0 != activate_threads_~tmp___4~0); 186131#L752-2 assume !(1 == ~M_E~0); 186130#L641-1 assume !(1 == ~T1_E~0); 186129#L646-1 assume !(1 == ~T2_E~0); 182466#L651-1 assume !(1 == ~T3_E~0); 182467#L656-1 assume !(1 == ~T4_E~0); 182499#L661-1 assume !(1 == ~T5_E~0); 182341#L666-1 assume !(1 == ~E_1~0); 182342#L671-1 assume !(1 == ~E_2~0); 182168#L676-1 assume !(1 == ~E_3~0); 182169#L681-1 assume !(1 == ~E_4~0); 182289#L686-1 assume !(1 == ~E_5~0); 182290#L892-1 assume !false; 193289#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 193031#L553 [2020-10-26 05:48:24,111 INFO L796 eck$LassoCheckResult]: Loop: 193031#L553 assume !false; 193286#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 193283#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 193281#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 193279#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 193277#L478 assume 0 != eval_~tmp~0; 193274#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 182442#L486 assume !(0 != eval_~tmp_ndt_1~0); 182443#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 186087#L500 assume !(0 != eval_~tmp_ndt_2~0); 193070#L497 assume !(0 == ~t2_st~0); 193064#L511 assume !(0 == ~t3_st~0); 193038#L525 assume !(0 == ~t4_st~0); 193034#L539 assume !(0 == ~t5_st~0); 193031#L553 [2020-10-26 05:48:24,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:24,111 INFO L82 PathProgramCache]: Analyzing trace with hash -701066143, now seen corresponding path program 1 times [2020-10-26 05:48:24,111 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:24,112 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121505630] [2020-10-26 05:48:24,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:24,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:24,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:24,132 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121505630] [2020-10-26 05:48:24,132 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:24,132 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:24,132 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443889493] [2020-10-26 05:48:24,132 INFO L799 eck$LassoCheckResult]: stem already infeasible [2020-10-26 05:48:24,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:24,133 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896486, now seen corresponding path program 1 times [2020-10-26 05:48:24,133 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:24,133 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172026287] [2020-10-26 05:48:24,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:24,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,137 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,139 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,141 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:24,241 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:24,242 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:24,242 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:24,242 INFO L87 Difference]: Start difference. First operand 17307 states and 23124 transitions. cyclomatic complexity: 5820 Second operand 3 states. [2020-10-26 05:48:24,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:24,309 INFO L93 Difference]: Finished difference Result 17238 states and 23032 transitions. [2020-10-26 05:48:24,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:24,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17238 states and 23032 transitions. [2020-10-26 05:48:24,386 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2020-10-26 05:48:24,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17238 states to 17238 states and 23032 transitions. [2020-10-26 05:48:24,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17238 [2020-10-26 05:48:24,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17238 [2020-10-26 05:48:24,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17238 states and 23032 transitions. [2020-10-26 05:48:24,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:24,479 INFO L691 BuchiCegarLoop]: Abstraction has 17238 states and 23032 transitions. [2020-10-26 05:48:24,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17238 states and 23032 transitions. [2020-10-26 05:48:24,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17238 to 17238. [2020-10-26 05:48:24,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17238 states. [2020-10-26 05:48:24,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17238 states to 17238 states and 23032 transitions. [2020-10-26 05:48:24,687 INFO L714 BuchiCegarLoop]: Abstraction has 17238 states and 23032 transitions. [2020-10-26 05:48:24,687 INFO L594 BuchiCegarLoop]: Abstraction has 17238 states and 23032 transitions. [2020-10-26 05:48:24,687 INFO L427 BuchiCegarLoop]: ======== Iteration 22============ [2020-10-26 05:48:24,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17238 states and 23032 transitions. [2020-10-26 05:48:24,744 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17148 [2020-10-26 05:48:24,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:24,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:24,745 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:24,745 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:24,746 INFO L794 eck$LassoCheckResult]: Stem: 217188#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 217129#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 217130#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 217040#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 217041#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 216955#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 216956#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 217042#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 216878#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 216879#L418-1 assume !(0 == ~M_E~0); 216895#L578-1 assume !(0 == ~T1_E~0); 216896#L583-1 assume !(0 == ~T2_E~0); 216729#L588-1 assume !(0 == ~T3_E~0); 216730#L593-1 assume !(0 == ~T4_E~0); 216841#L598-1 assume !(0 == ~T5_E~0); 216842#L603-1 assume !(0 == ~E_1~0); 217089#L608-1 assume !(0 == ~E_2~0); 217090#L613-1 assume !(0 == ~E_3~0); 216975#L618-1 assume !(0 == ~E_4~0); 216976#L623-1 assume !(0 == ~E_5~0); 217047#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 217048#L271 assume !(1 == ~m_pc~0); 217221#L271-2 is_master_triggered_~__retres1~0 := 0; 217223#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217224#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 217282#L712 assume !(0 != activate_threads_~tmp~1); 217316#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 216825#L290 assume !(1 == ~t1_pc~0); 216816#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 216817#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 216826#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 216745#L720 assume !(0 != activate_threads_~tmp___0~0); 216717#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 216718#L309 assume !(1 == ~t2_pc~0); 216966#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 217030#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217044#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 217006#L728 assume !(0 != activate_threads_~tmp___1~0); 217007#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 217009#L328 assume !(1 == ~t3_pc~0); 217183#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 217182#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 217131#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 217132#L736 assume !(0 != activate_threads_~tmp___2~0); 217168#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 216885#L347 assume !(1 == ~t4_pc~0); 216852#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 216853#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 216884#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 217247#L744 assume !(0 != activate_threads_~tmp___3~0); 217263#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 217075#L366 assume !(1 == ~t5_pc~0); 217076#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 217071#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 216827#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 216828#L752 assume !(0 != activate_threads_~tmp___4~0); 216831#L752-2 assume !(1 == ~M_E~0); 216832#L641-1 assume !(1 == ~T1_E~0); 217088#L646-1 assume !(1 == ~T2_E~0); 217012#L651-1 assume !(1 == ~T3_E~0); 217013#L656-1 assume !(1 == ~T4_E~0); 217046#L661-1 assume !(1 == ~T5_E~0); 216888#L666-1 assume !(1 == ~E_1~0); 216889#L671-1 assume !(1 == ~E_2~0); 216719#L676-1 assume !(1 == ~E_3~0); 216720#L681-1 assume !(1 == ~E_4~0); 216833#L686-1 assume !(1 == ~E_5~0); 216834#L892-1 assume !false; 224912#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 224913#L553 [2020-10-26 05:48:24,746 INFO L796 eck$LassoCheckResult]: Loop: 224913#L553 assume !false; 225065#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 225063#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 225062#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 225061#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 225060#L478 assume 0 != eval_~tmp~0; 225058#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 224889#L486 assume !(0 != eval_~tmp_ndt_1~0); 223192#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 223188#L500 assume !(0 != eval_~tmp_ndt_2~0); 223189#L497 assume !(0 == ~t2_st~0); 224824#L511 assume !(0 == ~t3_st~0); 224822#L525 assume !(0 == ~t4_st~0); 225068#L539 assume !(0 == ~t5_st~0); 224913#L553 [2020-10-26 05:48:24,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:24,746 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 2 times [2020-10-26 05:48:24,746 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:24,747 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220835717] [2020-10-26 05:48:24,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:24,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,757 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,766 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,782 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:24,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:24,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1252896486, now seen corresponding path program 2 times [2020-10-26 05:48:24,783 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:24,783 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737963672] [2020-10-26 05:48:24,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:24,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,786 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:24,789 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:24,791 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:24,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:24,791 INFO L82 PathProgramCache]: Analyzing trace with hash -478639230, now seen corresponding path program 1 times [2020-10-26 05:48:24,791 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:24,792 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809240404] [2020-10-26 05:48:24,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:24,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:24,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:24,831 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809240404] [2020-10-26 05:48:24,831 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:24,831 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:24,831 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1230855301] [2020-10-26 05:48:24,928 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:24,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:24,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:24,928 INFO L87 Difference]: Start difference. First operand 17238 states and 23032 transitions. cyclomatic complexity: 5797 Second operand 3 states. [2020-10-26 05:48:25,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:25,190 INFO L93 Difference]: Finished difference Result 31478 states and 41880 transitions. [2020-10-26 05:48:25,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:25,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31478 states and 41880 transitions. [2020-10-26 05:48:25,335 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 31372 [2020-10-26 05:48:25,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31478 states to 31478 states and 41880 transitions. [2020-10-26 05:48:25,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31478 [2020-10-26 05:48:25,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31478 [2020-10-26 05:48:25,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31478 states and 41880 transitions. [2020-10-26 05:48:25,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:25,526 INFO L691 BuchiCegarLoop]: Abstraction has 31478 states and 41880 transitions. [2020-10-26 05:48:25,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31478 states and 41880 transitions. [2020-10-26 05:48:25,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31478 to 30006. [2020-10-26 05:48:25,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30006 states. [2020-10-26 05:48:25,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30006 states to 30006 states and 40024 transitions. [2020-10-26 05:48:25,905 INFO L714 BuchiCegarLoop]: Abstraction has 30006 states and 40024 transitions. [2020-10-26 05:48:25,905 INFO L594 BuchiCegarLoop]: Abstraction has 30006 states and 40024 transitions. [2020-10-26 05:48:25,905 INFO L427 BuchiCegarLoop]: ======== Iteration 23============ [2020-10-26 05:48:25,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30006 states and 40024 transitions. [2020-10-26 05:48:25,994 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 29900 [2020-10-26 05:48:25,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:25,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:25,995 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:25,995 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:25,996 INFO L794 eck$LassoCheckResult]: Stem: 265941#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 265869#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 265870#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 265769#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 265770#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 265687#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 265688#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265771#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265608#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265609#L418-1 assume !(0 == ~M_E~0); 265625#L578-1 assume !(0 == ~T1_E~0); 265626#L583-1 assume !(0 == ~T2_E~0); 265453#L588-1 assume !(0 == ~T3_E~0); 265454#L593-1 assume !(0 == ~T4_E~0); 265570#L598-1 assume !(0 == ~T5_E~0); 265571#L603-1 assume !(0 == ~E_1~0); 265822#L608-1 assume !(0 == ~E_2~0); 265823#L613-1 assume !(0 == ~E_3~0); 265707#L618-1 assume !(0 == ~E_4~0); 265708#L623-1 assume !(0 == ~E_5~0); 265775#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 265776#L271 assume !(1 == ~m_pc~0); 265976#L271-2 is_master_triggered_~__retres1~0 := 0; 265978#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 265979#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 266049#L712 assume !(0 != activate_threads_~tmp~1); 266081#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 265556#L290 assume !(1 == ~t1_pc~0); 265546#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 265547#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 265557#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 265471#L720 assume !(0 != activate_threads_~tmp___0~0); 265441#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 265442#L309 assume !(1 == ~t2_pc~0); 265697#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 265758#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 265773#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 265735#L728 assume !(0 != activate_threads_~tmp___1~0); 265736#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 265738#L328 assume !(1 == ~t3_pc~0); 265936#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 265935#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 265871#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 265872#L736 assume !(0 != activate_threads_~tmp___2~0); 265913#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 265615#L347 assume !(1 == ~t4_pc~0); 265581#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 265582#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 265614#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 266005#L744 assume !(0 != activate_threads_~tmp___3~0); 266025#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 265803#L366 assume !(1 == ~t5_pc~0); 265804#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 265802#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 265558#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 265559#L752 assume !(0 != activate_threads_~tmp___4~0); 265562#L752-2 assume !(1 == ~M_E~0); 265563#L641-1 assume !(1 == ~T1_E~0); 265821#L646-1 assume !(1 == ~T2_E~0); 265741#L651-1 assume !(1 == ~T3_E~0); 265742#L656-1 assume !(1 == ~T4_E~0); 265774#L661-1 assume !(1 == ~T5_E~0); 265618#L666-1 assume !(1 == ~E_1~0); 265619#L671-1 assume !(1 == ~E_2~0); 265443#L676-1 assume !(1 == ~E_3~0); 265444#L681-1 assume !(1 == ~E_4~0); 265564#L686-1 assume !(1 == ~E_5~0); 265565#L892-1 assume !false; 266233#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 266229#L553 [2020-10-26 05:48:25,996 INFO L796 eck$LassoCheckResult]: Loop: 266229#L553 assume !false; 266227#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 266223#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 266221#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 266219#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 266217#L478 assume 0 != eval_~tmp~0; 266213#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 266208#L486 assume !(0 != eval_~tmp_ndt_1~0); 266209#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 273851#L500 assume !(0 != eval_~tmp_ndt_2~0); 273852#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 281985#L514 assume !(0 != eval_~tmp_ndt_3~0); 282014#L511 assume !(0 == ~t3_st~0); 266256#L525 assume !(0 == ~t4_st~0); 266236#L539 assume !(0 == ~t5_st~0); 266229#L553 [2020-10-26 05:48:25,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:25,996 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 3 times [2020-10-26 05:48:25,997 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:25,997 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733098698] [2020-10-26 05:48:25,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:26,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:26,007 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:26,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:26,016 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:26,032 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:26,033 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:26,033 INFO L82 PathProgramCache]: Analyzing trace with hash 17875240, now seen corresponding path program 1 times [2020-10-26 05:48:26,033 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:26,033 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784185540] [2020-10-26 05:48:26,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:26,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:26,037 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:26,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:26,040 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:26,042 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:26,042 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:26,042 INFO L82 PathProgramCache]: Analyzing trace with hash -2120124404, now seen corresponding path program 1 times [2020-10-26 05:48:26,042 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:26,042 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1781244874] [2020-10-26 05:48:26,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:26,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:26,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:26,081 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1781244874] [2020-10-26 05:48:26,081 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:26,081 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:26,082 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473761957] [2020-10-26 05:48:26,204 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:26,204 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:26,204 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:26,204 INFO L87 Difference]: Start difference. First operand 30006 states and 40024 transitions. cyclomatic complexity: 10021 Second operand 3 states. [2020-10-26 05:48:26,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:26,596 INFO L93 Difference]: Finished difference Result 55798 states and 74120 transitions. [2020-10-26 05:48:26,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:26,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55798 states and 74120 transitions. [2020-10-26 05:48:26,877 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 55660 [2020-10-26 05:48:27,350 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55798 states to 55798 states and 74120 transitions. [2020-10-26 05:48:27,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55798 [2020-10-26 05:48:27,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55798 [2020-10-26 05:48:27,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55798 states and 74120 transitions. [2020-10-26 05:48:27,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:27,446 INFO L691 BuchiCegarLoop]: Abstraction has 55798 states and 74120 transitions. [2020-10-26 05:48:27,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55798 states and 74120 transitions. [2020-10-26 05:48:28,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55798 to 54742. [2020-10-26 05:48:28,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54742 states. [2020-10-26 05:48:28,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54742 states to 54742 states and 72808 transitions. [2020-10-26 05:48:28,315 INFO L714 BuchiCegarLoop]: Abstraction has 54742 states and 72808 transitions. [2020-10-26 05:48:28,315 INFO L594 BuchiCegarLoop]: Abstraction has 54742 states and 72808 transitions. [2020-10-26 05:48:28,315 INFO L427 BuchiCegarLoop]: ======== Iteration 24============ [2020-10-26 05:48:28,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54742 states and 72808 transitions. [2020-10-26 05:48:28,812 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 54604 [2020-10-26 05:48:28,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:28,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:28,820 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:28,820 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:28,820 INFO L794 eck$LassoCheckResult]: Stem: 351775#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 351697#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 351698#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 351591#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 351592#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 351497#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 351498#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 351593#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 351416#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 351417#L418-1 assume !(0 == ~M_E~0); 351433#L578-1 assume !(0 == ~T1_E~0); 351434#L583-1 assume !(0 == ~T2_E~0); 351265#L588-1 assume !(0 == ~T3_E~0); 351266#L593-1 assume !(0 == ~T4_E~0); 351379#L598-1 assume !(0 == ~T5_E~0); 351380#L603-1 assume !(0 == ~E_1~0); 351644#L608-1 assume !(0 == ~E_2~0); 351645#L613-1 assume !(0 == ~E_3~0); 351518#L618-1 assume !(0 == ~E_4~0); 351519#L623-1 assume !(0 == ~E_5~0); 351598#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 351599#L271 assume !(1 == ~m_pc~0); 351819#L271-2 is_master_triggered_~__retres1~0 := 0; 351821#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 351822#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 351894#L712 assume !(0 != activate_threads_~tmp~1); 351931#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 351362#L290 assume !(1 == ~t1_pc~0); 351351#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 351352#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 351363#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 351280#L720 assume !(0 != activate_threads_~tmp___0~0); 351253#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 351254#L309 assume !(1 == ~t2_pc~0); 351508#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 351579#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 351596#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 351549#L728 assume !(0 != activate_threads_~tmp___1~0); 351550#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 351553#L328 assume !(1 == ~t3_pc~0); 351769#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 351768#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 351699#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 351700#L736 assume !(0 != activate_threads_~tmp___2~0); 351747#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 351423#L347 assume !(1 == ~t4_pc~0); 351390#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 351391#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 351422#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 351846#L744 assume !(0 != activate_threads_~tmp___3~0); 351873#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 351628#L366 assume !(1 == ~t5_pc~0); 351629#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 351625#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 351366#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 351367#L752 assume !(0 != activate_threads_~tmp___4~0); 351370#L752-2 assume !(1 == ~M_E~0); 351371#L641-1 assume !(1 == ~T1_E~0); 351643#L646-1 assume !(1 == ~T2_E~0); 351557#L651-1 assume !(1 == ~T3_E~0); 351558#L656-1 assume !(1 == ~T4_E~0); 351597#L661-1 assume !(1 == ~T5_E~0); 351426#L666-1 assume !(1 == ~E_1~0); 351427#L671-1 assume !(1 == ~E_2~0); 351255#L676-1 assume !(1 == ~E_3~0); 351256#L681-1 assume !(1 == ~E_4~0); 351372#L686-1 assume !(1 == ~E_5~0); 351373#L892-1 assume !false; 358822#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 358818#L553 [2020-10-26 05:48:28,821 INFO L796 eck$LassoCheckResult]: Loop: 358818#L553 assume !false; 358814#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 358735#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 358733#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 358730#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 358725#L478 assume 0 != eval_~tmp~0; 358717#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 358713#L486 assume !(0 != eval_~tmp_ndt_1~0); 356825#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 356450#L500 assume !(0 != eval_~tmp_ndt_2~0); 356451#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 357465#L514 assume !(0 != eval_~tmp_ndt_3~0); 357479#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 357959#L528 assume !(0 != eval_~tmp_ndt_4~0); 358833#L525 assume !(0 == ~t4_st~0); 358825#L539 assume !(0 == ~t5_st~0); 358818#L553 [2020-10-26 05:48:28,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:28,822 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 4 times [2020-10-26 05:48:28,822 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:28,822 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483494377] [2020-10-26 05:48:28,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:28,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:28,835 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:28,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:28,844 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:28,860 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:28,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:28,862 INFO L82 PathProgramCache]: Analyzing trace with hash 548744107, now seen corresponding path program 1 times [2020-10-26 05:48:28,862 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:28,862 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830833316] [2020-10-26 05:48:28,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:28,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:28,872 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:28,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:28,875 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:28,877 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:28,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:28,878 INFO L82 PathProgramCache]: Analyzing trace with hash -1304735417, now seen corresponding path program 1 times [2020-10-26 05:48:28,878 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:28,878 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217917567] [2020-10-26 05:48:28,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:28,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:28,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:28,927 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217917567] [2020-10-26 05:48:28,927 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:28,927 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2020-10-26 05:48:28,927 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735781797] [2020-10-26 05:48:29,147 WARN L193 SmtUtils]: Spent 217.00 ms on a formula simplification. DAG size of input: 41 DAG size of output: 39 [2020-10-26 05:48:29,198 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:29,198 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:29,198 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:29,199 INFO L87 Difference]: Start difference. First operand 54742 states and 72808 transitions. cyclomatic complexity: 18069 Second operand 3 states. [2020-10-26 05:48:29,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:29,582 INFO L93 Difference]: Finished difference Result 95878 states and 127400 transitions. [2020-10-26 05:48:29,583 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:29,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95878 states and 127400 transitions. [2020-10-26 05:48:30,174 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 95676 [2020-10-26 05:48:30,654 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95878 states to 95878 states and 127400 transitions. [2020-10-26 05:48:30,654 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95878 [2020-10-26 05:48:30,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95878 [2020-10-26 05:48:30,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95878 states and 127400 transitions. [2020-10-26 05:48:30,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:30,817 INFO L691 BuchiCegarLoop]: Abstraction has 95878 states and 127400 transitions. [2020-10-26 05:48:30,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95878 states and 127400 transitions. [2020-10-26 05:48:31,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95878 to 93446. [2020-10-26 05:48:31,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93446 states. [2020-10-26 05:48:32,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93446 states to 93446 states and 124456 transitions. [2020-10-26 05:48:32,053 INFO L714 BuchiCegarLoop]: Abstraction has 93446 states and 124456 transitions. [2020-10-26 05:48:32,053 INFO L594 BuchiCegarLoop]: Abstraction has 93446 states and 124456 transitions. [2020-10-26 05:48:32,053 INFO L427 BuchiCegarLoop]: ======== Iteration 25============ [2020-10-26 05:48:32,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93446 states and 124456 transitions. [2020-10-26 05:48:32,715 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 93244 [2020-10-26 05:48:32,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:32,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:32,716 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:32,716 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:32,717 INFO L794 eck$LassoCheckResult]: Stem: 502412#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 502325#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 502326#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 502216#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 502217#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 502125#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 502126#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 502218#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 502048#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 502049#L418-1 assume !(0 == ~M_E~0); 502066#L578-1 assume !(0 == ~T1_E~0); 502067#L583-1 assume !(0 == ~T2_E~0); 501893#L588-1 assume !(0 == ~T3_E~0); 501894#L593-1 assume !(0 == ~T4_E~0); 502008#L598-1 assume !(0 == ~T5_E~0); 502009#L603-1 assume !(0 == ~E_1~0); 502271#L608-1 assume !(0 == ~E_2~0); 502272#L613-1 assume !(0 == ~E_3~0); 502145#L618-1 assume !(0 == ~E_4~0); 502146#L623-1 assume !(0 == ~E_5~0); 502225#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 502226#L271 assume !(1 == ~m_pc~0); 502451#L271-2 is_master_triggered_~__retres1~0 := 0; 502453#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 502454#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 502529#L712 assume !(0 != activate_threads_~tmp~1); 502569#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 501993#L290 assume !(1 == ~t1_pc~0); 501984#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 501985#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 501994#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 501909#L720 assume !(0 != activate_threads_~tmp___0~0); 501881#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 501882#L309 assume !(1 == ~t2_pc~0); 502136#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 502206#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 502221#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 502177#L728 assume !(0 != activate_threads_~tmp___1~0); 502178#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 502181#L328 assume !(1 == ~t3_pc~0); 502405#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 502404#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 502327#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 502328#L736 assume !(0 != activate_threads_~tmp___2~0); 502376#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 502055#L347 assume !(1 == ~t4_pc~0); 502022#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 502023#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 502054#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 502484#L744 assume !(0 != activate_threads_~tmp___3~0); 502506#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 502254#L366 assume !(1 == ~t5_pc~0); 502255#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 502251#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 501996#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 501997#L752 assume !(0 != activate_threads_~tmp___4~0); 502000#L752-2 assume !(1 == ~M_E~0); 502001#L641-1 assume !(1 == ~T1_E~0); 502270#L646-1 assume !(1 == ~T2_E~0); 502187#L651-1 assume !(1 == ~T3_E~0); 502188#L656-1 assume !(1 == ~T4_E~0); 502224#L661-1 assume !(1 == ~T5_E~0); 502059#L666-1 assume !(1 == ~E_1~0); 502060#L671-1 assume !(1 == ~E_2~0); 501883#L676-1 assume !(1 == ~E_3~0); 501884#L681-1 assume !(1 == ~E_4~0); 502002#L686-1 assume !(1 == ~E_5~0); 502003#L892-1 assume !false; 543638#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 543626#L553 [2020-10-26 05:48:32,717 INFO L796 eck$LassoCheckResult]: Loop: 543626#L553 assume !false; 543627#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 543607#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 543608#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 543589#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 543590#L478 assume 0 != eval_~tmp~0; 543569#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 543571#L486 assume !(0 != eval_~tmp_ndt_1~0); 531189#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 531190#L500 assume !(0 != eval_~tmp_ndt_2~0); 543367#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 536340#L514 assume !(0 != eval_~tmp_ndt_3~0); 536329#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 536326#L528 assume !(0 != eval_~tmp_ndt_4~0); 536327#L525 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 543660#L542 assume !(0 != eval_~tmp_ndt_5~0); 543661#L539 assume !(0 == ~t5_st~0); 543626#L553 [2020-10-26 05:48:32,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:32,717 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 5 times [2020-10-26 05:48:32,718 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:32,718 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768813501] [2020-10-26 05:48:32,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:32,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:32,727 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:32,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:32,743 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:32,758 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:32,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:32,759 INFO L82 PathProgramCache]: Analyzing trace with hash -168970141, now seen corresponding path program 1 times [2020-10-26 05:48:32,759 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:32,759 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387756504] [2020-10-26 05:48:32,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:32,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:32,763 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:32,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:32,765 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:32,767 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:32,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:32,768 INFO L82 PathProgramCache]: Analyzing trace with hash -1792260537, now seen corresponding path program 1 times [2020-10-26 05:48:32,768 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:32,768 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097778352] [2020-10-26 05:48:32,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:32,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2020-10-26 05:48:32,810 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2020-10-26 05:48:32,811 INFO L353 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097778352] [2020-10-26 05:48:32,811 INFO L219 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2020-10-26 05:48:32,811 INFO L232 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2020-10-26 05:48:32,811 INFO L155 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1460407336] [2020-10-26 05:48:32,956 INFO L142 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2020-10-26 05:48:32,956 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2020-10-26 05:48:32,956 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2020-10-26 05:48:32,957 INFO L87 Difference]: Start difference. First operand 93446 states and 124456 transitions. cyclomatic complexity: 31013 Second operand 3 states. [2020-10-26 05:48:33,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2020-10-26 05:48:33,896 INFO L93 Difference]: Finished difference Result 179750 states and 238744 transitions. [2020-10-26 05:48:33,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2020-10-26 05:48:33,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 179750 states and 238744 transitions. [2020-10-26 05:48:34,926 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 179420 [2020-10-26 05:48:35,340 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 179750 states to 179750 states and 238744 transitions. [2020-10-26 05:48:35,341 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 179750 [2020-10-26 05:48:35,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 179750 [2020-10-26 05:48:35,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 179750 states and 238744 transitions. [2020-10-26 05:48:35,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2020-10-26 05:48:35,597 INFO L691 BuchiCegarLoop]: Abstraction has 179750 states and 238744 transitions. [2020-10-26 05:48:35,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179750 states and 238744 transitions. [2020-10-26 05:48:37,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179750 to 179750. [2020-10-26 05:48:37,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179750 states. [2020-10-26 05:48:38,013 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179750 states to 179750 states and 238744 transitions. [2020-10-26 05:48:38,013 INFO L714 BuchiCegarLoop]: Abstraction has 179750 states and 238744 transitions. [2020-10-26 05:48:38,013 INFO L594 BuchiCegarLoop]: Abstraction has 179750 states and 238744 transitions. [2020-10-26 05:48:38,014 INFO L427 BuchiCegarLoop]: ======== Iteration 26============ [2020-10-26 05:48:38,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 179750 states and 238744 transitions. [2020-10-26 05:48:39,354 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 179420 [2020-10-26 05:48:39,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2020-10-26 05:48:39,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2020-10-26 05:48:39,356 INFO L852 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:39,356 INFO L853 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2020-10-26 05:48:39,356 INFO L794 eck$LassoCheckResult]: Stem: 775566#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 775501#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 775502#L855 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 775408#L386 assume 1 == ~m_i~0;~m_st~0 := 0; 775409#L393-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 775325#L398-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 775326#L403-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 775410#L408-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 775251#L413-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 775252#L418-1 assume !(0 == ~M_E~0); 775269#L578-1 assume !(0 == ~T1_E~0); 775270#L583-1 assume !(0 == ~T2_E~0); 775097#L588-1 assume !(0 == ~T3_E~0); 775098#L593-1 assume !(0 == ~T4_E~0); 775214#L598-1 assume !(0 == ~T5_E~0); 775215#L603-1 assume !(0 == ~E_1~0); 775457#L608-1 assume !(0 == ~E_2~0); 775458#L613-1 assume !(0 == ~E_3~0); 775345#L618-1 assume !(0 == ~E_4~0); 775346#L623-1 assume !(0 == ~E_5~0); 775416#L628-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 775417#L271 assume !(1 == ~m_pc~0); 775604#L271-2 is_master_triggered_~__retres1~0 := 0; 775606#L282 is_master_triggered_#res := is_master_triggered_~__retres1~0; 775607#L283 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 775684#L712 assume !(0 != activate_threads_~tmp~1); 775729#L712-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 775197#L290 assume !(1 == ~t1_pc~0); 775188#L290-2 is_transmit1_triggered_~__retres1~1 := 0; 775189#L301 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 775198#L302 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 775114#L720 assume !(0 != activate_threads_~tmp___0~0); 775085#L720-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 775086#L309 assume !(1 == ~t2_pc~0); 775336#L309-2 is_transmit2_triggered_~__retres1~2 := 0; 775398#L320 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 775413#L321 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 775374#L728 assume !(0 != activate_threads_~tmp___1~0); 775375#L728-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 775377#L328 assume !(1 == ~t3_pc~0); 775560#L328-2 is_transmit3_triggered_~__retres1~3 := 0; 775559#L339 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 775503#L340 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 775504#L736 assume !(0 != activate_threads_~tmp___2~0); 775546#L736-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 775258#L347 assume !(1 == ~t4_pc~0); 775225#L347-2 is_transmit4_triggered_~__retres1~4 := 0; 775226#L358 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 775257#L359 activate_threads_#t~ret18 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 775634#L744 assume !(0 != activate_threads_~tmp___3~0); 775658#L744-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 775443#L366 assume !(1 == ~t5_pc~0); 775444#L366-2 is_transmit5_triggered_~__retres1~5 := 0; 775440#L377 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 775200#L378 activate_threads_#t~ret19 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 775201#L752 assume !(0 != activate_threads_~tmp___4~0); 775204#L752-2 assume !(1 == ~M_E~0); 775205#L641-1 assume !(1 == ~T1_E~0); 775456#L646-1 assume !(1 == ~T2_E~0); 775381#L651-1 assume !(1 == ~T3_E~0); 775382#L656-1 assume !(1 == ~T4_E~0); 775415#L661-1 assume !(1 == ~T5_E~0); 775262#L666-1 assume !(1 == ~E_1~0); 775263#L671-1 assume !(1 == ~E_2~0); 775087#L676-1 assume !(1 == ~E_3~0); 775088#L681-1 assume !(1 == ~E_4~0); 775206#L686-1 assume !(1 == ~E_5~0); 775207#L892-1 assume !false; 903070#L893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 825425#L553 [2020-10-26 05:48:39,356 INFO L796 eck$LassoCheckResult]: Loop: 825425#L553 assume !false; 903068#L474 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 903063#L431 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 903061#L463 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 903059#L464 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 903057#L478 assume 0 != eval_~tmp~0; 903053#L478-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 903050#L486 assume !(0 != eval_~tmp_ndt_1~0); 903048#L483 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 892790#L500 assume !(0 != eval_~tmp_ndt_2~0); 903046#L497 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 902887#L514 assume !(0 != eval_~tmp_ndt_3~0); 903044#L511 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 871055#L528 assume !(0 != eval_~tmp_ndt_4~0); 896124#L525 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 887248#L542 assume !(0 != eval_~tmp_ndt_5~0); 876384#L539 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 825424#L556 assume !(0 != eval_~tmp_ndt_6~0); 825425#L553 [2020-10-26 05:48:39,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:39,357 INFO L82 PathProgramCache]: Analyzing trace with hash -44245603, now seen corresponding path program 6 times [2020-10-26 05:48:39,357 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:39,357 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400087030] [2020-10-26 05:48:39,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:39,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,367 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,375 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,391 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:39,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:39,392 INFO L82 PathProgramCache]: Analyzing trace with hash -943106960, now seen corresponding path program 1 times [2020-10-26 05:48:39,392 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:39,392 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737073801] [2020-10-26 05:48:39,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:39,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,396 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,398 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,400 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:39,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2020-10-26 05:48:39,401 INFO L82 PathProgramCache]: Analyzing trace with hash 274498316, now seen corresponding path program 1 times [2020-10-26 05:48:39,401 INFO L162 FreeRefinementEngine]: Executing refinement strategy CAMEL [2020-10-26 05:48:39,401 INFO L353 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039363057] [2020-10-26 05:48:39,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2020-10-26 05:48:39,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,411 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2020-10-26 05:48:39,420 INFO L221 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2020-10-26 05:48:39,443 INFO L173 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2020-10-26 05:48:39,554 WARN L193 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2020-10-26 05:48:41,131 WARN L193 SmtUtils]: Spent 1.51 s on a formula simplification. DAG size of input: 241 DAG size of output: 173 [2020-10-26 05:48:41,536 WARN L193 SmtUtils]: Spent 355.00 ms on a formula simplification that was a NOOP. DAG size: 147 [2020-10-26 05:48:41,624 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 26.10 05:48:41 BoogieIcfgContainer [2020-10-26 05:48:41,627 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2020-10-26 05:48:41,628 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2020-10-26 05:48:41,628 INFO L271 PluginConnector]: Initializing Witness Printer... [2020-10-26 05:48:41,629 INFO L275 PluginConnector]: Witness Printer initialized [2020-10-26 05:48:41,629 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.10 05:48:14" (3/4) ... [2020-10-26 05:48:41,634 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2020-10-26 05:48:41,775 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2020-10-26 05:48:41,775 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2020-10-26 05:48:41,777 INFO L168 Benchmark]: Toolchain (without parser) took 29528.11 ms. Allocated memory was 48.2 MB in the beginning and 10.3 GB in the end (delta: 10.2 GB). Free memory was 25.1 MB in the beginning and 8.4 GB in the end (delta: -8.4 GB). Peak memory consumption was 1.8 GB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,777 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 35.7 MB. Free memory was 18.3 MB in the beginning and 18.3 MB in the end (delta: 26.5 kB). There was no memory consumed. Max. memory is 16.1 GB. [2020-10-26 05:48:41,777 INFO L168 Benchmark]: CACSL2BoogieTranslator took 465.73 ms. Allocated memory is still 48.2 MB. Free memory was 24.5 MB in the beginning and 19.3 MB in the end (delta: 5.2 MB). Peak memory consumption was 3.5 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,778 INFO L168 Benchmark]: Boogie Procedure Inliner took 98.79 ms. Allocated memory is still 48.2 MB. Free memory was 19.3 MB in the beginning and 30.2 MB in the end (delta: -10.9 MB). Peak memory consumption was 7.6 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,778 INFO L168 Benchmark]: Boogie Preprocessor took 74.62 ms. Allocated memory is still 48.2 MB. Free memory was 30.0 MB in the beginning and 25.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,779 INFO L168 Benchmark]: RCFGBuilder took 1586.27 ms. Allocated memory was 48.2 MB in the beginning and 75.5 MB in the end (delta: 27.3 MB). Free memory was 25.8 MB in the beginning and 52.7 MB in the end (delta: -26.9 MB). Peak memory consumption was 23.6 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,779 INFO L168 Benchmark]: BuchiAutomizer took 27139.05 ms. Allocated memory was 75.5 MB in the beginning and 10.3 GB in the end (delta: 10.2 GB). Free memory was 52.7 MB in the beginning and 8.4 GB in the end (delta: -8.3 GB). Peak memory consumption was 1.8 GB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,780 INFO L168 Benchmark]: Witness Printer took 147.27 ms. Allocated memory is still 10.3 GB. Free memory was 8.4 GB in the beginning and 8.4 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2020-10-26 05:48:41,782 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 35.7 MB. Free memory was 18.3 MB in the beginning and 18.3 MB in the end (delta: 26.5 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 465.73 ms. Allocated memory is still 48.2 MB. Free memory was 24.5 MB in the beginning and 19.3 MB in the end (delta: 5.2 MB). Peak memory consumption was 3.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 98.79 ms. Allocated memory is still 48.2 MB. Free memory was 19.3 MB in the beginning and 30.2 MB in the end (delta: -10.9 MB). Peak memory consumption was 7.6 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 74.62 ms. Allocated memory is still 48.2 MB. Free memory was 30.0 MB in the beginning and 25.8 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1586.27 ms. Allocated memory was 48.2 MB in the beginning and 75.5 MB in the end (delta: 27.3 MB). Free memory was 25.8 MB in the beginning and 52.7 MB in the end (delta: -26.9 MB). Peak memory consumption was 23.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 27139.05 ms. Allocated memory was 75.5 MB in the beginning and 10.3 GB in the end (delta: 10.2 GB). Free memory was 52.7 MB in the beginning and 8.4 GB in the end (delta: -8.3 GB). Peak memory consumption was 1.8 GB. Max. memory is 16.1 GB. * Witness Printer took 147.27 ms. Allocated memory is still 10.3 GB. Free memory was 8.4 GB in the beginning and 8.4 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (25 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.25 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 179750 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 27.0s and 26 iterations. TraceHistogramMax:1. Analysis of lassos took 6.0s. Construction of modules took 1.4s. Büchi inclusion checks took 2.9s. Highest rank in rank-based complementation 0. Minimization of det autom 25. Minimization of nondet autom 0. Automata minimization 7.1s AutomataMinimizationTime, 25 MinimizatonAttempts, 22140 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 5.0s Buchi closure took 0.3s. Biggest automaton had 179750 states and ocurred in iteration 25. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 18599 SDtfs, 21871 SDslu, 17520 SDs, 0 SdLazy, 685 SolverSat, 333 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.4s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc5 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 473]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=8510} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=8510, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@14d4c113=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@357b376f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6bb26e56=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ba40cf4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5230488f=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@38f6aac2=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@346e1069=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2abc1352=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f774eb6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@62c3a504=0, NULL=8512, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d6b43d6=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c92625b=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, NULL=8513, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=8511, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b4e3c4f=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@784a3ef9=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6eff3a25=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 473]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int t5_pc = 0; [L23] int m_st ; [L24] int t1_st ; [L25] int t2_st ; [L26] int t3_st ; [L27] int t4_st ; [L28] int t5_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int M_E = 2; [L36] int T1_E = 2; [L37] int T2_E = 2; [L38] int T3_E = 2; [L39] int T4_E = 2; [L40] int T5_E = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L937] int __retres1 ; [L848] m_i = 1 [L849] t1_i = 1 [L850] t2_i = 1 [L851] t3_i = 1 [L852] t4_i = 1 [L853] t5_i = 1 [L878] int kernel_st ; [L879] int tmp ; [L880] int tmp___0 ; [L884] kernel_st = 0 [L393] COND TRUE m_i == 1 [L394] m_st = 0 [L398] COND TRUE t1_i == 1 [L399] t1_st = 0 [L403] COND TRUE t2_i == 1 [L404] t2_st = 0 [L408] COND TRUE t3_i == 1 [L409] t3_st = 0 [L413] COND TRUE t4_i == 1 [L414] t4_st = 0 [L418] COND TRUE t5_i == 1 [L419] t5_st = 0 [L578] COND FALSE !(M_E == 0) [L583] COND FALSE !(T1_E == 0) [L588] COND FALSE !(T2_E == 0) [L593] COND FALSE !(T3_E == 0) [L598] COND FALSE !(T4_E == 0) [L603] COND FALSE !(T5_E == 0) [L608] COND FALSE !(E_1 == 0) [L613] COND FALSE !(E_2 == 0) [L618] COND FALSE !(E_3 == 0) [L623] COND FALSE !(E_4 == 0) [L628] COND FALSE !(E_5 == 0) [L701] int tmp ; [L702] int tmp___0 ; [L703] int tmp___1 ; [L704] int tmp___2 ; [L705] int tmp___3 ; [L706] int tmp___4 ; [L268] int __retres1 ; [L271] COND FALSE !(m_pc == 1) [L281] __retres1 = 0 [L283] return (__retres1); [L710] tmp = is_master_triggered() [L712] COND FALSE !(\read(tmp)) [L287] int __retres1 ; [L290] COND FALSE !(t1_pc == 1) [L300] __retres1 = 0 [L302] return (__retres1); [L718] tmp___0 = is_transmit1_triggered() [L720] COND FALSE !(\read(tmp___0)) [L306] int __retres1 ; [L309] COND FALSE !(t2_pc == 1) [L319] __retres1 = 0 [L321] return (__retres1); [L726] tmp___1 = is_transmit2_triggered() [L728] COND FALSE !(\read(tmp___1)) [L325] int __retres1 ; [L328] COND FALSE !(t3_pc == 1) [L338] __retres1 = 0 [L340] return (__retres1); [L734] tmp___2 = is_transmit3_triggered() [L736] COND FALSE !(\read(tmp___2)) [L344] int __retres1 ; [L347] COND FALSE !(t4_pc == 1) [L357] __retres1 = 0 [L359] return (__retres1); [L742] tmp___3 = is_transmit4_triggered() [L744] COND FALSE !(\read(tmp___3)) [L363] int __retres1 ; [L366] COND FALSE !(t5_pc == 1) [L376] __retres1 = 0 [L378] return (__retres1); [L750] tmp___4 = is_transmit5_triggered() [L752] COND FALSE !(\read(tmp___4)) [L641] COND FALSE !(M_E == 1) [L646] COND FALSE !(T1_E == 1) [L651] COND FALSE !(T2_E == 1) [L656] COND FALSE !(T3_E == 1) [L661] COND FALSE !(T4_E == 1) [L666] COND FALSE !(T5_E == 1) [L671] COND FALSE !(E_1 == 1) [L676] COND FALSE !(E_2 == 1) [L681] COND FALSE !(E_3 == 1) [L686] COND FALSE !(E_4 == 1) [L691] COND FALSE !(E_5 == 1) [L892] COND TRUE 1 [L895] kernel_st = 1 [L469] int tmp ; Loop: [L473] COND TRUE 1 [L428] int __retres1 ; [L431] COND TRUE m_st == 0 [L432] __retres1 = 1 [L464] return (__retres1); [L476] tmp = exists_runnable_thread() [L478] COND TRUE \read(tmp) [L483] COND TRUE m_st == 0 [L484] int tmp_ndt_1; [L485] tmp_ndt_1 = __VERIFIER_nondet_int() [L486] COND FALSE !(\read(tmp_ndt_1)) [L497] COND TRUE t1_st == 0 [L498] int tmp_ndt_2; [L499] tmp_ndt_2 = __VERIFIER_nondet_int() [L500] COND FALSE !(\read(tmp_ndt_2)) [L511] COND TRUE t2_st == 0 [L512] int tmp_ndt_3; [L513] tmp_ndt_3 = __VERIFIER_nondet_int() [L514] COND FALSE !(\read(tmp_ndt_3)) [L525] COND TRUE t3_st == 0 [L526] int tmp_ndt_4; [L527] tmp_ndt_4 = __VERIFIER_nondet_int() [L528] COND FALSE !(\read(tmp_ndt_4)) [L539] COND TRUE t4_st == 0 [L540] int tmp_ndt_5; [L541] tmp_ndt_5 = __VERIFIER_nondet_int() [L542] COND FALSE !(\read(tmp_ndt_5)) [L553] COND TRUE t5_st == 0 [L554] int tmp_ndt_6; [L555] tmp_ndt_6 = __VERIFIER_nondet_int() [L556] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...