./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8d31f386 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c23fa9fd10aa70a52586ccd054da306bf699445a .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-wip.dd.multireach-323-8d31f38 [2021-07-06 20:41:36,942 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-07-06 20:41:36,944 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-07-06 20:41:36,977 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-07-06 20:41:36,977 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-07-06 20:41:36,982 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-07-06 20:41:36,983 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-07-06 20:41:36,996 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-07-06 20:41:36,998 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-07-06 20:41:37,003 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-07-06 20:41:37,004 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-07-06 20:41:37,006 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-07-06 20:41:37,006 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-07-06 20:41:37,009 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-07-06 20:41:37,010 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-07-06 20:41:37,011 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-07-06 20:41:37,014 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-07-06 20:41:37,015 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-07-06 20:41:37,017 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-07-06 20:41:37,023 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-07-06 20:41:37,025 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-07-06 20:41:37,026 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-07-06 20:41:37,028 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-07-06 20:41:37,029 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-07-06 20:41:37,031 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-07-06 20:41:37,032 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-07-06 20:41:37,032 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-07-06 20:41:37,034 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-07-06 20:41:37,034 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-07-06 20:41:37,035 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-07-06 20:41:37,035 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-07-06 20:41:37,036 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-07-06 20:41:37,037 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-07-06 20:41:37,037 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-07-06 20:41:37,038 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-07-06 20:41:37,038 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-07-06 20:41:37,039 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-07-06 20:41:37,039 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-07-06 20:41:37,039 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-07-06 20:41:37,041 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-07-06 20:41:37,042 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-07-06 20:41:37,042 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-07-06 20:41:37,081 INFO L113 SettingsManager]: Loading preferences was successful [2021-07-06 20:41:37,081 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-07-06 20:41:37,084 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-07-06 20:41:37,084 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-07-06 20:41:37,084 INFO L138 SettingsManager]: * Use SBE=true [2021-07-06 20:41:37,084 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-07-06 20:41:37,084 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-07-06 20:41:37,085 INFO L138 SettingsManager]: * Use old map elimination=false [2021-07-06 20:41:37,085 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-07-06 20:41:37,085 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-07-06 20:41:37,086 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-07-06 20:41:37,086 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-07-06 20:41:37,086 INFO L138 SettingsManager]: * sizeof long=4 [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-07-06 20:41:37,087 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * sizeof long double=12 [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * Use constant arrays=true [2021-07-06 20:41:37,088 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-07-06 20:41:37,089 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-07-06 20:41:37,089 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-07-06 20:41:37,089 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-07-06 20:41:37,089 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-07-06 20:41:37,089 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-07-06 20:41:37,091 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-07-06 20:41:37,091 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c23fa9fd10aa70a52586ccd054da306bf699445a [2021-07-06 20:41:37,398 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-07-06 20:41:37,429 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-07-06 20:41:37,432 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-07-06 20:41:37,433 INFO L271 PluginConnector]: Initializing CDTParser... [2021-07-06 20:41:37,433 INFO L275 PluginConnector]: CDTParser initialized [2021-07-06 20:41:37,434 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-07-06 20:41:37,493 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69220b703/ae8fe513e88443a6898c3f1c0d0b7219/FLAG8e0111b0b [2021-07-06 20:41:37,993 INFO L306 CDTParser]: Found 1 translation units. [2021-07-06 20:41:37,993 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-07-06 20:41:38,011 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69220b703/ae8fe513e88443a6898c3f1c0d0b7219/FLAG8e0111b0b [2021-07-06 20:41:38,330 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/69220b703/ae8fe513e88443a6898c3f1c0d0b7219 [2021-07-06 20:41:38,333 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-07-06 20:41:38,334 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-07-06 20:41:38,335 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-07-06 20:41:38,335 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-07-06 20:41:38,338 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-07-06 20:41:38,339 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,340 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1cb2383d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38, skipping insertion in model container [2021-07-06 20:41:38,340 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,346 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-07-06 20:41:38,378 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-07-06 20:41:38,476 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-07-06 20:41:38,585 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:41:38,605 INFO L203 MainTranslator]: Completed pre-run [2021-07-06 20:41:38,615 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-07-06 20:41:38,673 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:41:38,703 INFO L208 MainTranslator]: Completed translation [2021-07-06 20:41:38,704 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38 WrapperNode [2021-07-06 20:41:38,704 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-07-06 20:41:38,706 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-07-06 20:41:38,706 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-07-06 20:41:38,706 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-07-06 20:41:38,712 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,732 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,788 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-07-06 20:41:38,795 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-07-06 20:41:38,795 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-07-06 20:41:38,796 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-07-06 20:41:38,802 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,803 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,812 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,812 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,832 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,856 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,875 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,884 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-07-06 20:41:38,887 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-07-06 20:41:38,887 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-07-06 20:41:38,887 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-07-06 20:41:38,889 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (1/1) ... [2021-07-06 20:41:38,894 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-07-06 20:41:38,900 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-07-06 20:41:38,914 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-07-06 20:41:38,933 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-07-06 20:41:38,973 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-07-06 20:41:38,974 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-07-06 20:41:38,974 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-07-06 20:41:38,974 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-07-06 20:41:40,190 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-07-06 20:41:40,191 INFO L299 CfgBuilder]: Removed 196 assume(true) statements. [2021-07-06 20:41:40,193 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40 BoogieIcfgContainer [2021-07-06 20:41:40,193 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-07-06 20:41:40,194 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-07-06 20:41:40,195 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-07-06 20:41:40,198 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-07-06 20:41:40,199 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,199 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.07 08:41:38" (1/3) ... [2021-07-06 20:41:40,200 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75eeeef2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:41:40, skipping insertion in model container [2021-07-06 20:41:40,200 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,200 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:38" (2/3) ... [2021-07-06 20:41:40,201 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@75eeeef2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:41:40, skipping insertion in model container [2021-07-06 20:41:40,201 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,201 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40" (3/3) ... [2021-07-06 20:41:40,202 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2021-07-06 20:41:40,244 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-07-06 20:41:40,244 INFO L360 BuchiCegarLoop]: Hoare is false [2021-07-06 20:41:40,245 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-07-06 20:41:40,245 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-07-06 20:41:40,245 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-07-06 20:41:40,245 INFO L364 BuchiCegarLoop]: Difference is false [2021-07-06 20:41:40,245 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-07-06 20:41:40,245 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-07-06 20:41:40,273 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-07-06 20:41:40,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,323 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-07-06 20:41:40,325 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,338 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-07-06 20:41:40,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,347 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,350 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,361 INFO L791 eck$LassoCheckResult]: Stem: 366#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 260#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 248#L883true havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 240#L399true assume !(1 == ~m_i~0);~m_st~0 := 2; 274#L406-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 46#L411-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 462#L416-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 219#L421-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 502#L426-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 154#L431-1true assume !(0 == ~M_E~0); 522#L591-1true assume !(0 == ~T1_E~0); 157#L596-1true assume !(0 == ~T2_E~0); 420#L601-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 191#L606-1true assume !(0 == ~T4_E~0); 101#L611-1true assume !(0 == ~T5_E~0); 387#L616-1true assume !(0 == ~E_M~0); 7#L621-1true assume !(0 == ~E_1~0); 277#L626-1true assume !(0 == ~E_2~0); 51#L631-1true assume !(0 == ~E_3~0); 470#L636-1true assume !(0 == ~E_4~0); 244#L641-1true assume 0 == ~E_5~0;~E_5~0 := 1; 533#L646-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 308#L284true assume 1 == ~m_pc~0; 258#L285true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 309#L295true is_master_triggered_#res := is_master_triggered_~__retres1~0; 259#L296true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 481#L735true assume !(0 != activate_threads_~tmp~1); 465#L735-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60#L303true assume !(1 == ~t1_pc~0); 89#L303-2true is_transmit1_triggered_~__retres1~1 := 0; 95#L314true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 413#L315true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 109#L743true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 112#L743-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224#L322true assume 1 == ~t2_pc~0; 27#L323true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 223#L333true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26#L334true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 250#L751true assume !(0 != activate_threads_~tmp___1~0); 241#L751-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 382#L341true assume !(1 == ~t3_pc~0); 367#L341-2true is_transmit3_triggered_~__retres1~3 := 0; 381#L352true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184#L353true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 392#L759true assume !(0 != activate_threads_~tmp___2~0); 393#L759-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 507#L360true assume 1 == ~t4_pc~0; 317#L361true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 505#L371true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 314#L372true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 398#L767true assume !(0 != activate_threads_~tmp___3~0); 530#L767-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 151#L379true assume !(1 == ~t5_pc~0); 132#L379-2true is_transmit5_triggered_~__retres1~5 := 0; 149#L390true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83#L391true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13#L775true assume !(0 != activate_threads_~tmp___4~0); 15#L775-2true assume !(1 == ~M_E~0); 275#L659-1true assume !(1 == ~T1_E~0); 50#L664-1true assume !(1 == ~T2_E~0); 466#L669-1true assume !(1 == ~T3_E~0); 243#L674-1true assume !(1 == ~T4_E~0); 532#L679-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 163#L684-1true assume !(1 == ~E_M~0); 432#L689-1true assume !(1 == ~E_1~0); 345#L694-1true assume !(1 == ~E_2~0); 113#L699-1true assume !(1 == ~E_3~0); 394#L704-1true assume !(1 == ~E_4~0); 3#L709-1true assume !(1 == ~E_5~0); 437#L920-1true [2021-07-06 20:41:40,363 INFO L793 eck$LassoCheckResult]: Loop: 437#L920-1true assume !false; 396#L921true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9#L566true assume !true; 473#L581true start_simulation_~kernel_st~0 := 2; 221#L399-1true start_simulation_~kernel_st~0 := 3; 524#L591-2true assume 0 == ~M_E~0;~M_E~0 := 1; 527#L591-4true assume !(0 == ~T1_E~0); 160#L596-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 425#L601-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 193#L606-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 105#L611-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 389#L616-3true assume 0 == ~E_M~0;~E_M~0 := 1; 11#L621-3true assume 0 == ~E_1~0;~E_1~0 := 1; 282#L626-3true assume 0 == ~E_2~0;~E_2~0 := 1; 36#L631-3true assume !(0 == ~E_3~0); 454#L636-3true assume 0 == ~E_4~0;~E_4~0 := 1; 233#L641-3true assume 0 == ~E_5~0;~E_5~0 := 1; 523#L646-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 272#L284-21true assume 1 == ~m_pc~0; 263#L285-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 319#L295-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 264#L296-7true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 313#L735-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 291#L735-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 433#L303-21true assume 1 == ~t1_pc~0; 400#L304-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 446#L314-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 399#L315-7true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 448#L743-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 452#L743-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49#L322-21true assume !(1 == ~t2_pc~0); 52#L322-23true is_transmit2_triggered_~__retres1~2 := 0; 214#L333-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22#L334-7true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 218#L751-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 197#L751-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 344#L341-21true assume 1 == ~t3_pc~0; 180#L342-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 354#L352-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 179#L353-7true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 359#L759-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 361#L759-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 464#L360-21true assume 1 == ~t4_pc~0; 307#L361-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 494#L371-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 306#L372-7true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 498#L767-21true assume !(0 != activate_threads_~tmp___3~0); 482#L767-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 111#L379-21true assume !(1 == ~t5_pc~0); 98#L379-23true is_transmit5_triggered_~__retres1~5 := 0; 144#L390-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76#L391-7true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 126#L775-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 128#L775-23true assume 1 == ~M_E~0;~M_E~0 := 2; 279#L659-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 53#L664-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 475#L669-3true assume !(1 == ~T3_E~0); 246#L674-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 519#L679-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 156#L684-3true assume 1 == ~E_M~0;~E_M~0 := 2; 419#L689-3true assume 1 == ~E_1~0;~E_1~0 := 2; 190#L694-3true assume 1 == ~E_2~0;~E_2~0 := 2; 100#L699-3true assume 1 == ~E_3~0;~E_3~0 := 2; 385#L704-3true assume 1 == ~E_4~0;~E_4~0 := 2; 6#L709-3true assume !(1 == ~E_5~0); 276#L714-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 44#L444-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 238#L476-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 43#L477-1true start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 201#L939true assume !(0 == start_simulation_~tmp~3); 205#L939-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47#L444-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 239#L476-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45#L477-2true stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 247#L894true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 295#L901true stop_simulation_#res := stop_simulation_~__retres2~0; 395#L902true start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 114#L952true assume !(0 != start_simulation_~tmp___0~1); 437#L920-1true [2021-07-06 20:41:40,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,371 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-07-06 20:41:40,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,379 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018980847] [2021-07-06 20:41:40,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,380 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:40,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:40,524 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,525 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,525 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,527 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:40,536 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,537 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:40,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:40,539 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018980847] [2021-07-06 20:41:40,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018980847] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:40,540 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:40,541 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:40,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937207221] [2021-07-06 20:41:40,551 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:40,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,552 INFO L82 PathProgramCache]: Analyzing trace with hash -2114634143, now seen corresponding path program 1 times [2021-07-06 20:41:40,553 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,553 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032072403] [2021-07-06 20:41:40,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,554 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:40,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:40,605 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,607 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,608 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,608 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:40,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:40,610 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032072403] [2021-07-06 20:41:40,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032072403] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:40,610 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:40,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:40,611 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912508268] [2021-07-06 20:41:40,612 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:40,618 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:40,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:40,631 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:40,633 INFO L87 Difference]: Start difference. First operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:40,691 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-07-06 20:41:40,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:40,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-07-06 20:41:40,699 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:40,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2021-07-06 20:41:40,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-07-06 20:41:40,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-07-06 20:41:40,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2021-07-06 20:41:40,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:40,715 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-07-06 20:41:40,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2021-07-06 20:41:40,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-07-06 20:41:40,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5161290322580645) internal successors, (799), 526 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2021-07-06 20:41:40,776 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-07-06 20:41:40,776 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-07-06 20:41:40,776 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-07-06 20:41:40,776 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2021-07-06 20:41:40,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:40,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,782 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,782 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,783 INFO L791 eck$LassoCheckResult]: Stem: 1547#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1442#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1417#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1404#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1405#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1164#L411-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1165#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1392#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1393#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1307#L431-1 assume !(0 == ~M_E~0); 1308#L591-1 assume !(0 == ~T1_E~0); 1312#L596-1 assume !(0 == ~T2_E~0); 1313#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1379#L606-1 assume !(0 == ~T4_E~0); 1262#L611-1 assume !(0 == ~T5_E~0); 1263#L616-1 assume !(0 == ~E_M~0); 1080#L621-1 assume !(0 == ~E_1~0); 1081#L626-1 assume !(0 == ~E_2~0); 1172#L631-1 assume !(0 == ~E_3~0); 1173#L636-1 assume !(0 == ~E_4~0); 1411#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1412#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1493#L284 assume 1 == ~m_pc~0; 1437#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1438#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1440#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1441#L735 assume !(0 != activate_threads_~tmp~1); 1589#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1181#L303 assume !(1 == ~t1_pc~0); 1182#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1242#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1251#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1274#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1275#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1277#L322 assume 1 == ~t2_pc~0; 1121#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1122#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1119#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1120#L751 assume !(0 != activate_threads_~tmp___1~0); 1406#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1407#L341 assume !(1 == ~t3_pc~0); 1368#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1369#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1365#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1366#L759 assume !(0 != activate_threads_~tmp___2~0); 1556#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1557#L360 assume 1 == ~t4_pc~0; 1504#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1505#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1500#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1501#L767 assume !(0 != activate_threads_~tmp___3~0); 1559#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1306#L379 assume !(1 == ~t5_pc~0); 1235#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1234#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1230#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1094#L775 assume !(0 != activate_threads_~tmp___4~0); 1095#L775-2 assume !(1 == ~M_E~0); 1096#L659-1 assume !(1 == ~T1_E~0); 1170#L664-1 assume !(1 == ~T2_E~0); 1171#L669-1 assume !(1 == ~T3_E~0); 1409#L674-1 assume !(1 == ~T4_E~0); 1410#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1322#L684-1 assume !(1 == ~E_M~0); 1323#L689-1 assume !(1 == ~E_1~0); 1536#L694-1 assume !(1 == ~E_2~0); 1278#L699-1 assume !(1 == ~E_3~0); 1279#L704-1 assume !(1 == ~E_4~0); 1073#L709-1 assume !(1 == ~E_5~0); 1074#L920-1 [2021-07-06 20:41:40,783 INFO L793 eck$LassoCheckResult]: Loop: 1074#L920-1 assume !false; 1558#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1084#L566 assume !false; 1085#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1154#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1155#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1152#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1153#L491 assume !(0 != eval_~tmp~0); 1583#L581 start_simulation_~kernel_st~0 := 2; 1396#L399-1 start_simulation_~kernel_st~0 := 3; 1397#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1598#L591-4 assume !(0 == ~T1_E~0); 1318#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1319#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1380#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1268#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1269#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1089#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1090#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1144#L631-3 assume !(0 == ~E_3~0); 1145#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1401#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1402#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1468#L284-21 assume 1 == ~m_pc~0; 1448#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1449#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1451#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1452#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1471#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1472#L303-21 assume 1 == ~t1_pc~0; 1562#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1563#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1560#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1561#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1587#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1169#L322-21 assume 1 == ~t2_pc~0; 1111#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1112#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1109#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1110#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1382#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1383#L341-21 assume !(1 == ~t3_pc~0); 1361#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 1360#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1357#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1358#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1543#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1544#L360-21 assume 1 == ~t4_pc~0; 1490#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1491#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1488#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1489#L767-21 assume !(0 != activate_threads_~tmp___3~0); 1591#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1276#L379-21 assume 1 == ~t5_pc~0; 1222#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1223#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1216#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1217#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1290#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1291#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1174#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1175#L669-3 assume !(1 == ~T3_E~0); 1414#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1415#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1310#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1311#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1377#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1260#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1261#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1078#L709-3 assume !(1 == ~E_5~0); 1079#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1159#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1160#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1157#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1158#L939 assume !(0 == start_simulation_~tmp~3); 1385#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1166#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1167#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1162#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1163#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1416#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 1475#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1280#L952 assume !(0 != start_simulation_~tmp___0~1); 1074#L920-1 [2021-07-06 20:41:40,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,784 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-07-06 20:41:40,784 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,784 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1128478060] [2021-07-06 20:41:40,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,785 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:40,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:40,829 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,830 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,831 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,832 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:40,839 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,840 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,841 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:40,842 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:40,842 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1128478060] [2021-07-06 20:41:40,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1128478060] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:40,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:40,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:40,844 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409664186] [2021-07-06 20:41:40,845 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:40,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,845 INFO L82 PathProgramCache]: Analyzing trace with hash -2014669991, now seen corresponding path program 1 times [2021-07-06 20:41:40,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877595202] [2021-07-06 20:41:40,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,846 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:40,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:40,922 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,923 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,924 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,924 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:40,928 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:40,928 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:40,929 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:40,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:40,929 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877595202] [2021-07-06 20:41:40,930 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877595202] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:40,930 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:40,930 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:40,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595394871] [2021-07-06 20:41:40,931 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:40,931 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:40,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:40,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:40,932 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:40,952 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2021-07-06 20:41:40,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:40,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2021-07-06 20:41:40,957 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:40,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2021-07-06 20:41:40,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-07-06 20:41:40,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-07-06 20:41:40,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2021-07-06 20:41:40,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:40,964 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-07-06 20:41:40,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2021-07-06 20:41:40,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-07-06 20:41:40,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5142314990512333) internal successors, (798), 526 states have internal predecessors, (798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2021-07-06 20:41:40,979 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-07-06 20:41:40,979 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-07-06 20:41:40,979 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-07-06 20:41:40,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2021-07-06 20:41:40,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:40,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,985 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,985 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,986 INFO L791 eck$LassoCheckResult]: Stem: 2608#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2503#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2478#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2465#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 2466#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2228#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2229#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2453#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2454#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2369#L431-1 assume !(0 == ~M_E~0); 2370#L591-1 assume !(0 == ~T1_E~0); 2373#L596-1 assume !(0 == ~T2_E~0); 2374#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2440#L606-1 assume !(0 == ~T4_E~0); 2323#L611-1 assume !(0 == ~T5_E~0); 2324#L616-1 assume !(0 == ~E_M~0); 2141#L621-1 assume !(0 == ~E_1~0); 2142#L626-1 assume !(0 == ~E_2~0); 2233#L631-1 assume !(0 == ~E_3~0); 2234#L636-1 assume !(0 == ~E_4~0); 2472#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2473#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2554#L284 assume 1 == ~m_pc~0; 2498#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2499#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2501#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2502#L735 assume !(0 != activate_threads_~tmp~1); 2650#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2242#L303 assume !(1 == ~t1_pc~0); 2243#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 2303#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2312#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2335#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2336#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2338#L322 assume 1 == ~t2_pc~0; 2182#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2183#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2180#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2181#L751 assume !(0 != activate_threads_~tmp___1~0); 2467#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2468#L341 assume !(1 == ~t3_pc~0); 2429#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 2430#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2426#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2427#L759 assume !(0 != activate_threads_~tmp___2~0); 2617#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2618#L360 assume 1 == ~t4_pc~0; 2565#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2566#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2561#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2562#L767 assume !(0 != activate_threads_~tmp___3~0); 2620#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2367#L379 assume !(1 == ~t5_pc~0); 2296#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 2295#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2291#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2155#L775 assume !(0 != activate_threads_~tmp___4~0); 2156#L775-2 assume !(1 == ~M_E~0); 2157#L659-1 assume !(1 == ~T1_E~0); 2231#L664-1 assume !(1 == ~T2_E~0); 2232#L669-1 assume !(1 == ~T3_E~0); 2470#L674-1 assume !(1 == ~T4_E~0); 2471#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2383#L684-1 assume !(1 == ~E_M~0); 2384#L689-1 assume !(1 == ~E_1~0); 2597#L694-1 assume !(1 == ~E_2~0); 2339#L699-1 assume !(1 == ~E_3~0); 2340#L704-1 assume !(1 == ~E_4~0); 2134#L709-1 assume !(1 == ~E_5~0); 2135#L920-1 [2021-07-06 20:41:40,988 INFO L793 eck$LassoCheckResult]: Loop: 2135#L920-1 assume !false; 2619#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2145#L566 assume !false; 2146#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2217#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2218#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2213#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2214#L491 assume !(0 != eval_~tmp~0); 2644#L581 start_simulation_~kernel_st~0 := 2; 2457#L399-1 start_simulation_~kernel_st~0 := 3; 2458#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2659#L591-4 assume !(0 == ~T1_E~0); 2379#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2380#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2441#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2329#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2330#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2150#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2151#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2205#L631-3 assume !(0 == ~E_3~0); 2206#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2462#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2463#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2529#L284-21 assume 1 == ~m_pc~0; 2509#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2510#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2512#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2513#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2532#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2533#L303-21 assume !(1 == ~t1_pc~0); 2625#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 2624#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2621#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2622#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2648#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2230#L322-21 assume 1 == ~t2_pc~0; 2172#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2173#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2170#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2171#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2443#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2444#L341-21 assume 1 == ~t3_pc~0; 2420#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2421#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2418#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2419#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2604#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2605#L360-21 assume 1 == ~t4_pc~0; 2551#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2552#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2549#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2550#L767-21 assume !(0 != activate_threads_~tmp___3~0); 2652#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2337#L379-21 assume 1 == ~t5_pc~0; 2283#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2284#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2277#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2278#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2351#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2352#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2235#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2236#L669-3 assume !(1 == ~T3_E~0); 2475#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2476#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2371#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2372#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2438#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2321#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2322#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2138#L709-3 assume !(1 == ~E_5~0); 2139#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2220#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2221#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2215#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2216#L939 assume !(0 == start_simulation_~tmp~3); 2446#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2225#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2226#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2223#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2224#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2477#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 2536#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2341#L952 assume !(0 != start_simulation_~tmp___0~1); 2135#L920-1 [2021-07-06 20:41:40,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,989 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-07-06 20:41:40,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,990 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628067596] [2021-07-06 20:41:40,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,990 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,042 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,042 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,043 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,044 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,047 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,048 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,050 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,050 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628067596] [2021-07-06 20:41:41,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628067596] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,051 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,051 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,051 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043098196] [2021-07-06 20:41:41,052 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,052 INFO L82 PathProgramCache]: Analyzing trace with hash 243645657, now seen corresponding path program 1 times [2021-07-06 20:41:41,052 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,053 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776251249] [2021-07-06 20:41:41,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,053 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,112 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,112 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,113 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,113 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,126 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,127 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776251249] [2021-07-06 20:41:41,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776251249] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,129 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805291860] [2021-07-06 20:41:41,129 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,130 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,130 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,145 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2021-07-06 20:41:41,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2021-07-06 20:41:41,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2021-07-06 20:41:41,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-07-06 20:41:41,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-07-06 20:41:41,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2021-07-06 20:41:41,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,154 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-07-06 20:41:41,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2021-07-06 20:41:41,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-07-06 20:41:41,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5123339658444024) internal successors, (797), 526 states have internal predecessors, (797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2021-07-06 20:41:41,166 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-07-06 20:41:41,168 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-07-06 20:41:41,170 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-07-06 20:41:41,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2021-07-06 20:41:41,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,174 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,175 INFO L791 eck$LassoCheckResult]: Stem: 3669#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3564#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3539#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3526#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 3527#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3289#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3290#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3514#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3515#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3430#L431-1 assume !(0 == ~M_E~0); 3431#L591-1 assume !(0 == ~T1_E~0); 3434#L596-1 assume !(0 == ~T2_E~0); 3435#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3501#L606-1 assume !(0 == ~T4_E~0); 3384#L611-1 assume !(0 == ~T5_E~0); 3385#L616-1 assume !(0 == ~E_M~0); 3202#L621-1 assume !(0 == ~E_1~0); 3203#L626-1 assume !(0 == ~E_2~0); 3294#L631-1 assume !(0 == ~E_3~0); 3295#L636-1 assume !(0 == ~E_4~0); 3533#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3534#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3615#L284 assume 1 == ~m_pc~0; 3559#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3560#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3562#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3563#L735 assume !(0 != activate_threads_~tmp~1); 3711#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3305#L303 assume !(1 == ~t1_pc~0); 3306#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 3364#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3373#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3396#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3397#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3399#L322 assume 1 == ~t2_pc~0; 3243#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3244#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3241#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3242#L751 assume !(0 != activate_threads_~tmp___1~0); 3528#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3529#L341 assume !(1 == ~t3_pc~0); 3490#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 3491#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3487#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3488#L759 assume !(0 != activate_threads_~tmp___2~0); 3678#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3679#L360 assume 1 == ~t4_pc~0; 3626#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3627#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3622#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3623#L767 assume !(0 != activate_threads_~tmp___3~0); 3681#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3428#L379 assume !(1 == ~t5_pc~0); 3357#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 3356#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3352#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3216#L775 assume !(0 != activate_threads_~tmp___4~0); 3217#L775-2 assume !(1 == ~M_E~0); 3218#L659-1 assume !(1 == ~T1_E~0); 3292#L664-1 assume !(1 == ~T2_E~0); 3293#L669-1 assume !(1 == ~T3_E~0); 3531#L674-1 assume !(1 == ~T4_E~0); 3532#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3444#L684-1 assume !(1 == ~E_M~0); 3445#L689-1 assume !(1 == ~E_1~0); 3658#L694-1 assume !(1 == ~E_2~0); 3400#L699-1 assume !(1 == ~E_3~0); 3401#L704-1 assume !(1 == ~E_4~0); 3195#L709-1 assume !(1 == ~E_5~0); 3196#L920-1 [2021-07-06 20:41:41,176 INFO L793 eck$LassoCheckResult]: Loop: 3196#L920-1 assume !false; 3680#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3206#L566 assume !false; 3207#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3278#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3279#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3274#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3275#L491 assume !(0 != eval_~tmp~0); 3705#L581 start_simulation_~kernel_st~0 := 2; 3518#L399-1 start_simulation_~kernel_st~0 := 3; 3519#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3720#L591-4 assume !(0 == ~T1_E~0); 3440#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3441#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3502#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3390#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3391#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3211#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3212#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3266#L631-3 assume !(0 == ~E_3~0); 3267#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3523#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3524#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3590#L284-21 assume 1 == ~m_pc~0; 3570#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3571#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3573#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3574#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3593#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3594#L303-21 assume 1 == ~t1_pc~0; 3684#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3685#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3682#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3683#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3709#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3291#L322-21 assume 1 == ~t2_pc~0; 3233#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3234#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3231#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3232#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3504#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3505#L341-21 assume 1 == ~t3_pc~0; 3481#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3482#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3479#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3480#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3665#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3666#L360-21 assume 1 == ~t4_pc~0; 3612#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3613#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3609#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3610#L767-21 assume !(0 != activate_threads_~tmp___3~0); 3713#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3398#L379-21 assume 1 == ~t5_pc~0; 3340#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3341#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3338#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3339#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3411#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3413#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3296#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3297#L669-3 assume !(1 == ~T3_E~0); 3536#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3537#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3432#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3433#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3499#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3382#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3383#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3199#L709-3 assume !(1 == ~E_5~0); 3200#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3281#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3282#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3276#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3277#L939 assume !(0 == start_simulation_~tmp~3); 3507#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3286#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3287#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3284#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 3285#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3538#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 3597#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3402#L952 assume !(0 != start_simulation_~tmp___0~1); 3196#L920-1 [2021-07-06 20:41:41,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,179 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-07-06 20:41:41,182 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,182 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516787616] [2021-07-06 20:41:41,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,182 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,212 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,212 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,213 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,213 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,216 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,217 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,218 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [516787616] [2021-07-06 20:41:41,218 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [516787616] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,218 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,218 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,218 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [937471190] [2021-07-06 20:41:41,219 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,219 INFO L82 PathProgramCache]: Analyzing trace with hash 140844410, now seen corresponding path program 1 times [2021-07-06 20:41:41,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,220 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525819831] [2021-07-06 20:41:41,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,220 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,245 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,261 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,262 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,262 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,265 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,265 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,266 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525819831] [2021-07-06 20:41:41,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525819831] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,267 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439198067] [2021-07-06 20:41:41,267 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,268 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,268 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,268 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,268 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,278 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2021-07-06 20:41:41,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,279 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2021-07-06 20:41:41,282 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2021-07-06 20:41:41,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-07-06 20:41:41,285 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-07-06 20:41:41,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2021-07-06 20:41:41,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,286 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-07-06 20:41:41,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2021-07-06 20:41:41,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-07-06 20:41:41,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5104364326375712) internal successors, (796), 526 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2021-07-06 20:41:41,295 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-07-06 20:41:41,295 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-07-06 20:41:41,295 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-07-06 20:41:41,296 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2021-07-06 20:41:41,298 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,298 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,298 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,299 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,299 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,299 INFO L791 eck$LassoCheckResult]: Stem: 4730#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4625#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4600#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4587#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 4588#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4350#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4351#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4575#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4576#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4491#L431-1 assume !(0 == ~M_E~0); 4492#L591-1 assume !(0 == ~T1_E~0); 4495#L596-1 assume !(0 == ~T2_E~0); 4496#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4562#L606-1 assume !(0 == ~T4_E~0); 4445#L611-1 assume !(0 == ~T5_E~0); 4446#L616-1 assume !(0 == ~E_M~0); 4263#L621-1 assume !(0 == ~E_1~0); 4264#L626-1 assume !(0 == ~E_2~0); 4355#L631-1 assume !(0 == ~E_3~0); 4356#L636-1 assume !(0 == ~E_4~0); 4594#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4595#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4676#L284 assume 1 == ~m_pc~0; 4620#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4621#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4623#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4624#L735 assume !(0 != activate_threads_~tmp~1); 4772#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4366#L303 assume !(1 == ~t1_pc~0); 4367#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 4426#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4437#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4457#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4458#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4460#L322 assume 1 == ~t2_pc~0; 4304#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4305#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4302#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4303#L751 assume !(0 != activate_threads_~tmp___1~0); 4589#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4590#L341 assume !(1 == ~t3_pc~0); 4551#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 4552#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4548#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4549#L759 assume !(0 != activate_threads_~tmp___2~0); 4739#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4740#L360 assume 1 == ~t4_pc~0; 4687#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4688#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4683#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4684#L767 assume !(0 != activate_threads_~tmp___3~0); 4742#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4489#L379 assume !(1 == ~t5_pc~0); 4418#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 4417#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4413#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4277#L775 assume !(0 != activate_threads_~tmp___4~0); 4278#L775-2 assume !(1 == ~M_E~0); 4279#L659-1 assume !(1 == ~T1_E~0); 4353#L664-1 assume !(1 == ~T2_E~0); 4354#L669-1 assume !(1 == ~T3_E~0); 4592#L674-1 assume !(1 == ~T4_E~0); 4593#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4505#L684-1 assume !(1 == ~E_M~0); 4506#L689-1 assume !(1 == ~E_1~0); 4719#L694-1 assume !(1 == ~E_2~0); 4461#L699-1 assume !(1 == ~E_3~0); 4462#L704-1 assume !(1 == ~E_4~0); 4258#L709-1 assume !(1 == ~E_5~0); 4259#L920-1 [2021-07-06 20:41:41,300 INFO L793 eck$LassoCheckResult]: Loop: 4259#L920-1 assume !false; 4741#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4267#L566 assume !false; 4268#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4339#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4340#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4335#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4336#L491 assume !(0 != eval_~tmp~0); 4766#L581 start_simulation_~kernel_st~0 := 2; 4579#L399-1 start_simulation_~kernel_st~0 := 3; 4580#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4781#L591-4 assume !(0 == ~T1_E~0); 4501#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4502#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4563#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4451#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4452#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4272#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4273#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4327#L631-3 assume !(0 == ~E_3~0); 4328#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4584#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4585#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4651#L284-21 assume 1 == ~m_pc~0; 4631#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4632#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4634#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4635#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4654#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4655#L303-21 assume 1 == ~t1_pc~0; 4745#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4746#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4743#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4744#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4770#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4352#L322-21 assume 1 == ~t2_pc~0; 4294#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4295#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4292#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4293#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4565#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4566#L341-21 assume !(1 == ~t3_pc~0); 4544#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 4543#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4540#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4541#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4726#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4727#L360-21 assume 1 == ~t4_pc~0; 4673#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4674#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4670#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4671#L767-21 assume !(0 != activate_threads_~tmp___3~0); 4774#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4459#L379-21 assume 1 == ~t5_pc~0; 4401#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4402#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4399#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4400#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4473#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4474#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4358#L669-3 assume !(1 == ~T3_E~0); 4597#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4598#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4493#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4494#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4560#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4443#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4444#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4261#L709-3 assume !(1 == ~E_5~0); 4262#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4342#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4343#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4337#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4338#L939 assume !(0 == start_simulation_~tmp~3); 4568#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4347#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4348#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4345#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4346#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4599#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 4658#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4463#L952 assume !(0 != start_simulation_~tmp___0~1); 4259#L920-1 [2021-07-06 20:41:41,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,300 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-07-06 20:41:41,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,301 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1761340502] [2021-07-06 20:41:41,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,301 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,320 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,321 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,321 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,322 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,325 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,325 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,326 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1761340502] [2021-07-06 20:41:41,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1761340502] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,326 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,326 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760583945] [2021-07-06 20:41:41,327 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,327 INFO L82 PathProgramCache]: Analyzing trace with hash -2014669991, now seen corresponding path program 2 times [2021-07-06 20:41:41,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,328 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190281913] [2021-07-06 20:41:41,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,328 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,359 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,359 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,360 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,360 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,363 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,363 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,367 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,367 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190281913] [2021-07-06 20:41:41,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190281913] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,367 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,368 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126524946] [2021-07-06 20:41:41,368 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,369 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,369 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,369 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,381 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2021-07-06 20:41:41,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2021-07-06 20:41:41,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2021-07-06 20:41:41,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-07-06 20:41:41,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-07-06 20:41:41,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2021-07-06 20:41:41,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,391 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-07-06 20:41:41,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2021-07-06 20:41:41,397 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-07-06 20:41:41,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.50853889943074) internal successors, (795), 526 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2021-07-06 20:41:41,399 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-07-06 20:41:41,400 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-07-06 20:41:41,400 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-07-06 20:41:41,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2021-07-06 20:41:41,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-07-06 20:41:41,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,403 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,403 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,404 INFO L791 eck$LassoCheckResult]: Stem: 5791#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5686#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5661#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5648#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 5649#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5411#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5412#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5636#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5637#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5552#L431-1 assume !(0 == ~M_E~0); 5553#L591-1 assume !(0 == ~T1_E~0); 5556#L596-1 assume !(0 == ~T2_E~0); 5557#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5623#L606-1 assume !(0 == ~T4_E~0); 5506#L611-1 assume !(0 == ~T5_E~0); 5507#L616-1 assume !(0 == ~E_M~0); 5324#L621-1 assume !(0 == ~E_1~0); 5325#L626-1 assume !(0 == ~E_2~0); 5416#L631-1 assume !(0 == ~E_3~0); 5417#L636-1 assume !(0 == ~E_4~0); 5655#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5656#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5737#L284 assume 1 == ~m_pc~0; 5681#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5682#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5684#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5685#L735 assume !(0 != activate_threads_~tmp~1); 5833#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5427#L303 assume !(1 == ~t1_pc~0); 5428#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 5487#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5498#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5518#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5519#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5521#L322 assume 1 == ~t2_pc~0; 5365#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5366#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5363#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5364#L751 assume !(0 != activate_threads_~tmp___1~0); 5650#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5651#L341 assume !(1 == ~t3_pc~0); 5612#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 5613#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5609#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5610#L759 assume !(0 != activate_threads_~tmp___2~0); 5800#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5801#L360 assume 1 == ~t4_pc~0; 5748#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5749#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5744#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5745#L767 assume !(0 != activate_threads_~tmp___3~0); 5803#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5550#L379 assume !(1 == ~t5_pc~0); 5479#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 5478#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5474#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5338#L775 assume !(0 != activate_threads_~tmp___4~0); 5339#L775-2 assume !(1 == ~M_E~0); 5340#L659-1 assume !(1 == ~T1_E~0); 5414#L664-1 assume !(1 == ~T2_E~0); 5415#L669-1 assume !(1 == ~T3_E~0); 5653#L674-1 assume !(1 == ~T4_E~0); 5654#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5566#L684-1 assume !(1 == ~E_M~0); 5567#L689-1 assume !(1 == ~E_1~0); 5780#L694-1 assume !(1 == ~E_2~0); 5522#L699-1 assume !(1 == ~E_3~0); 5523#L704-1 assume !(1 == ~E_4~0); 5319#L709-1 assume !(1 == ~E_5~0); 5320#L920-1 [2021-07-06 20:41:41,404 INFO L793 eck$LassoCheckResult]: Loop: 5320#L920-1 assume !false; 5802#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5328#L566 assume !false; 5329#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5400#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5401#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5396#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5397#L491 assume !(0 != eval_~tmp~0); 5827#L581 start_simulation_~kernel_st~0 := 2; 5640#L399-1 start_simulation_~kernel_st~0 := 3; 5641#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5842#L591-4 assume !(0 == ~T1_E~0); 5562#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5563#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5624#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5512#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5513#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5333#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5334#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5388#L631-3 assume !(0 == ~E_3~0); 5389#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5645#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5646#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5712#L284-21 assume 1 == ~m_pc~0; 5692#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5693#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5695#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5696#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5715#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5716#L303-21 assume !(1 == ~t1_pc~0); 5808#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 5807#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5804#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5805#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5831#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5413#L322-21 assume 1 == ~t2_pc~0; 5355#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5356#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5353#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5354#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5626#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5627#L341-21 assume 1 == ~t3_pc~0; 5603#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5604#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5601#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5602#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5787#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5788#L360-21 assume 1 == ~t4_pc~0; 5734#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5735#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5731#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5732#L767-21 assume !(0 != activate_threads_~tmp___3~0); 5835#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5520#L379-21 assume 1 == ~t5_pc~0; 5462#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5463#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5460#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5461#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5534#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5535#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5418#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5419#L669-3 assume !(1 == ~T3_E~0); 5658#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5659#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5554#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5555#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5621#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5504#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5505#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5322#L709-3 assume !(1 == ~E_5~0); 5323#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5403#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5404#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5398#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5399#L939 assume !(0 == start_simulation_~tmp~3); 5629#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5408#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5409#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5406#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5407#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5660#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 5719#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5524#L952 assume !(0 != start_simulation_~tmp___0~1); 5320#L920-1 [2021-07-06 20:41:41,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-07-06 20:41:41,405 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,405 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865267703] [2021-07-06 20:41:41,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,405 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,453 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,453 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,456 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,457 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:41,461 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,462 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,464 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,465 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865267703] [2021-07-06 20:41:41,466 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865267703] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,466 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,466 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,466 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005061584] [2021-07-06 20:41:41,467 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,467 INFO L82 PathProgramCache]: Analyzing trace with hash 243645657, now seen corresponding path program 2 times [2021-07-06 20:41:41,467 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,468 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1602867783] [2021-07-06 20:41:41,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,468 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,508 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,509 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,509 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,511 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,516 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,516 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,517 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,517 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,517 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1602867783] [2021-07-06 20:41:41,517 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1602867783] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,517 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,518 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,518 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647129204] [2021-07-06 20:41:41,518 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:41,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:41,521 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,595 INFO L93 Difference]: Finished difference Result 936 states and 1405 transitions. [2021-07-06 20:41:41,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:41,596 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1405 transitions. [2021-07-06 20:41:41,601 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-07-06 20:41:41,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1405 transitions. [2021-07-06 20:41:41,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2021-07-06 20:41:41,607 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2021-07-06 20:41:41,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1405 transitions. [2021-07-06 20:41:41,608 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,630 INFO L681 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-07-06 20:41:41,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1405 transitions. [2021-07-06 20:41:41,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2021-07-06 20:41:41,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 936 states, 936 states have (on average 1.501068376068376) internal successors, (1405), 935 states have internal predecessors, (1405), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1405 transitions. [2021-07-06 20:41:41,649 INFO L704 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-07-06 20:41:41,650 INFO L587 BuchiCegarLoop]: Abstraction has 936 states and 1405 transitions. [2021-07-06 20:41:41,650 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-07-06 20:41:41,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1405 transitions. [2021-07-06 20:41:41,654 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-07-06 20:41:41,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,655 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,655 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,655 INFO L791 eck$LassoCheckResult]: Stem: 7319#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7196#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7171#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7158#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 7159#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6885#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6886#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7148#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7149#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7050#L431-1 assume !(0 == ~M_E~0); 7051#L591-1 assume !(0 == ~T1_E~0); 7054#L596-1 assume !(0 == ~T2_E~0); 7055#L601-1 assume !(0 == ~T3_E~0); 7123#L606-1 assume !(0 == ~T4_E~0); 6985#L611-1 assume !(0 == ~T5_E~0); 6986#L616-1 assume !(0 == ~E_M~0); 6797#L621-1 assume !(0 == ~E_1~0); 6798#L626-1 assume !(0 == ~E_2~0); 6892#L631-1 assume !(0 == ~E_3~0); 6893#L636-1 assume !(0 == ~E_4~0); 7165#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 7166#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7251#L284 assume 1 == ~m_pc~0; 7191#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7192#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7194#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7195#L735 assume !(0 != activate_threads_~tmp~1); 7386#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6903#L303 assume !(1 == ~t1_pc~0); 6904#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 6964#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6976#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6998#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6999#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7003#L322 assume 1 == ~t2_pc~0; 6839#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6840#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6837#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6838#L751 assume !(0 != activate_threads_~tmp___1~0); 7160#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7161#L341 assume !(1 == ~t3_pc~0); 7111#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 7112#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7108#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7109#L759 assume !(0 != activate_threads_~tmp___2~0); 7334#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7335#L360 assume 1 == ~t4_pc~0; 7264#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7265#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7262#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7263#L767 assume !(0 != activate_threads_~tmp___3~0); 7339#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7048#L379 assume !(1 == ~t5_pc~0); 6957#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 6956#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6951#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6811#L775 assume !(0 != activate_threads_~tmp___4~0); 6812#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 6813#L659-1 assume !(1 == ~T1_E~0); 6890#L664-1 assume !(1 == ~T2_E~0); 6891#L669-1 assume !(1 == ~T3_E~0); 7163#L674-1 assume !(1 == ~T4_E~0); 7164#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7065#L684-1 assume !(1 == ~E_M~0); 7066#L689-1 assume !(1 == ~E_1~0); 7301#L694-1 assume !(1 == ~E_2~0); 7302#L699-1 assume !(1 == ~E_3~0); 7336#L704-1 assume !(1 == ~E_4~0); 7337#L709-1 assume !(1 == ~E_5~0); 7476#L920-1 [2021-07-06 20:41:41,656 INFO L793 eck$LassoCheckResult]: Loop: 7476#L920-1 assume !false; 7338#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6801#L566 assume !false; 6802#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6874#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6875#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6870#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6871#L491 assume !(0 != eval_~tmp~0); 7364#L581 start_simulation_~kernel_st~0 := 2; 7390#L399-1 start_simulation_~kernel_st~0 := 3; 7419#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7415#L591-4 assume !(0 == ~T1_E~0); 7061#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7062#L601-3 assume !(0 == ~T3_E~0); 7124#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6991#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6806#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6807#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6862#L631-3 assume !(0 == ~E_3~0); 6863#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7542#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7541#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7540#L284-21 assume 1 == ~m_pc~0; 7538#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7268#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7269#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7258#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7259#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7367#L303-21 assume !(1 == ~t1_pc~0); 7368#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 7535#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7340#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7341#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7379#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7380#L322-21 assume 1 == ~t2_pc~0; 6829#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6830#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6827#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6828#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7127#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7128#L341-21 assume !(1 == ~t3_pc~0); 7104#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 7103#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7100#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7101#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7315#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7316#L360-21 assume 1 == ~t4_pc~0; 7248#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7249#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7246#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7247#L767-21 assume !(0 != activate_threads_~tmp___3~0); 7534#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7000#L379-21 assume 1 == ~t5_pc~0; 7001#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7035#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7036#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7016#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7017#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7019#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7226#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7391#L669-3 assume !(1 == ~T3_E~0); 7392#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7410#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7411#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7533#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7120#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7121#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7328#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7329#L709-3 assume !(1 == ~E_5~0); 7224#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7225#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7499#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7498#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7497#L939 assume !(0 == start_simulation_~tmp~3); 7333#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7486#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7482#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7481#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 7480#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7479#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 7478#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7477#L952 assume !(0 != start_simulation_~tmp___0~1); 7476#L920-1 [2021-07-06 20:41:41,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,656 INFO L82 PathProgramCache]: Analyzing trace with hash -515799174, now seen corresponding path program 1 times [2021-07-06 20:41:41,656 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,657 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109816518] [2021-07-06 20:41:41,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,657 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,681 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,681 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,686 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,687 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:41,691 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,692 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,693 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,693 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,693 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109816518] [2021-07-06 20:41:41,693 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109816518] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,693 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,694 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310606574] [2021-07-06 20:41:41,694 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,695 INFO L82 PathProgramCache]: Analyzing trace with hash -3410954, now seen corresponding path program 1 times [2021-07-06 20:41:41,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321334024] [2021-07-06 20:41:41,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,695 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,721 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,722 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,726 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,726 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,729 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,730 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,731 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,731 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321334024] [2021-07-06 20:41:41,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321334024] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,731 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,732 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,732 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1884213914] [2021-07-06 20:41:41,732 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,733 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,733 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:41,733 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:41,733 INFO L87 Difference]: Start difference. First operand 936 states and 1405 transitions. cyclomatic complexity: 471 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,843 INFO L93 Difference]: Finished difference Result 1656 states and 2478 transitions. [2021-07-06 20:41:41,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:41,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1656 states and 2478 transitions. [2021-07-06 20:41:41,853 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2021-07-06 20:41:41,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1656 states to 1656 states and 2478 transitions. [2021-07-06 20:41:41,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1656 [2021-07-06 20:41:41,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1656 [2021-07-06 20:41:41,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1656 states and 2478 transitions. [2021-07-06 20:41:41,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,865 INFO L681 BuchiCegarLoop]: Abstraction has 1656 states and 2478 transitions. [2021-07-06 20:41:41,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1656 states and 2478 transitions. [2021-07-06 20:41:41,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1656 to 1654. [2021-07-06 20:41:41,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1654 states, 1654 states have (on average 1.4969770253929866) internal successors, (2476), 1653 states have internal predecessors, (2476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1654 states to 1654 states and 2476 transitions. [2021-07-06 20:41:41,929 INFO L704 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2021-07-06 20:41:41,929 INFO L587 BuchiCegarLoop]: Abstraction has 1654 states and 2476 transitions. [2021-07-06 20:41:41,929 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-07-06 20:41:41,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1654 states and 2476 transitions. [2021-07-06 20:41:41,939 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1560 [2021-07-06 20:41:41,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,942 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,942 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,942 INFO L791 eck$LassoCheckResult]: Stem: 9885#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9773#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9748#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9735#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 9736#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9488#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9489#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9725#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9726#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9636#L431-1 assume !(0 == ~M_E~0); 9637#L591-1 assume !(0 == ~T1_E~0); 9640#L596-1 assume !(0 == ~T2_E~0); 9641#L601-1 assume !(0 == ~T3_E~0); 9707#L606-1 assume !(0 == ~T4_E~0); 9587#L611-1 assume !(0 == ~T5_E~0); 9588#L616-1 assume !(0 == ~E_M~0); 9400#L621-1 assume !(0 == ~E_1~0); 9401#L626-1 assume !(0 == ~E_2~0); 9493#L631-1 assume !(0 == ~E_3~0); 9494#L636-1 assume !(0 == ~E_4~0); 9742#L641-1 assume !(0 == ~E_5~0); 9743#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9829#L284 assume 1 == ~m_pc~0; 9768#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9769#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9771#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9772#L735 assume !(0 != activate_threads_~tmp~1); 9935#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9506#L303 assume !(1 == ~t1_pc~0); 9507#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 9567#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9578#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9598#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9599#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9601#L322 assume 1 == ~t2_pc~0; 9442#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9443#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9440#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9441#L751 assume !(0 != activate_threads_~tmp___1~0); 9737#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9738#L341 assume !(1 == ~t3_pc~0); 9696#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 9697#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9693#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9694#L759 assume !(0 != activate_threads_~tmp___2~0); 9895#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9896#L360 assume 1 == ~t4_pc~0; 9840#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9841#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9838#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9839#L767 assume !(0 != activate_threads_~tmp___3~0); 9900#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9634#L379 assume !(1 == ~t5_pc~0); 9560#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 9559#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9556#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9414#L775 assume !(0 != activate_threads_~tmp___4~0); 9415#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 9416#L659-1 assume !(1 == ~T1_E~0); 9491#L664-1 assume !(1 == ~T2_E~0); 9492#L669-1 assume !(1 == ~T3_E~0); 10042#L674-1 assume !(1 == ~T4_E~0); 10038#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10005#L684-1 assume !(1 == ~E_M~0); 10003#L689-1 assume !(1 == ~E_1~0); 10002#L694-1 assume !(1 == ~E_2~0); 10000#L699-1 assume !(1 == ~E_3~0); 9897#L704-1 assume !(1 == ~E_4~0); 9898#L709-1 assume !(1 == ~E_5~0); 9979#L920-1 [2021-07-06 20:41:41,943 INFO L793 eck$LassoCheckResult]: Loop: 9979#L920-1 assume !false; 9974#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9973#L566 assume !false; 9972#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9966#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9965#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9964#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9962#L491 assume !(0 != eval_~tmp~0); 9961#L581 start_simulation_~kernel_st~0 := 2; 9960#L399-1 start_simulation_~kernel_st~0 := 3; 9958#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9959#L591-4 assume !(0 == ~T1_E~0); 10467#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10464#L601-3 assume !(0 == ~T3_E~0); 10461#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10457#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10452#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10448#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10445#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10442#L631-3 assume !(0 == ~E_3~0); 10440#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10438#L641-3 assume !(0 == ~E_5~0); 10431#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10430#L284-21 assume 1 == ~m_pc~0; 10425#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10420#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10416#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10412#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10408#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10405#L303-21 assume !(1 == ~t1_pc~0); 10398#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 10393#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10389#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10385#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10381#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10378#L322-21 assume 1 == ~t2_pc~0; 10371#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10365#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10363#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10361#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10359#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10351#L341-21 assume !(1 == ~t3_pc~0); 10347#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 10342#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10338#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9880#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9881#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9882#L360-21 assume 1 == ~t4_pc~0; 10311#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10309#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10297#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10286#L767-21 assume !(0 != activate_threads_~tmp___3~0); 10284#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10281#L379-21 assume 1 == ~t5_pc~0; 10275#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10272#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10268#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10263#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10259#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9616#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10252#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10248#L669-3 assume !(1 == ~T3_E~0); 10246#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10242#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10239#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10236#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10233#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10230#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10227#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10222#L709-3 assume !(1 == ~E_5~0); 10220#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10217#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10211#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10209#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 10207#L939 assume !(0 == start_simulation_~tmp~3); 9894#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10183#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10175#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10014#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 10012#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9998#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 9996#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9985#L952 assume !(0 != start_simulation_~tmp___0~1); 9979#L920-1 [2021-07-06 20:41:41,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,943 INFO L82 PathProgramCache]: Analyzing trace with hash -531317892, now seen corresponding path program 1 times [2021-07-06 20:41:41,943 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,944 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227156288] [2021-07-06 20:41:41,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,946 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,969 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,970 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,973 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,973 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,973 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,974 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1227156288] [2021-07-06 20:41:41,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1227156288] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,974 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:41,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1956241222] [2021-07-06 20:41:41,975 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,975 INFO L82 PathProgramCache]: Analyzing trace with hash 675861300, now seen corresponding path program 1 times [2021-07-06 20:41:41,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,975 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088524887] [2021-07-06 20:41:41,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,976 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,992 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,992 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,993 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,993 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,996 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,997 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,997 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,999 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088524887] [2021-07-06 20:41:42,001 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088524887] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,001 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,002 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,002 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095489855] [2021-07-06 20:41:42,002 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,002 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,003 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:42,003 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:42,003 INFO L87 Difference]: Start difference. First operand 1654 states and 2476 transitions. cyclomatic complexity: 826 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:42,066 INFO L93 Difference]: Finished difference Result 3178 states and 4699 transitions. [2021-07-06 20:41:42,067 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:42,067 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3178 states and 4699 transitions. [2021-07-06 20:41:42,088 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3081 [2021-07-06 20:41:42,104 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3178 states to 3178 states and 4699 transitions. [2021-07-06 20:41:42,105 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3178 [2021-07-06 20:41:42,107 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3178 [2021-07-06 20:41:42,107 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3178 states and 4699 transitions. [2021-07-06 20:41:42,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:42,112 INFO L681 BuchiCegarLoop]: Abstraction has 3178 states and 4699 transitions. [2021-07-06 20:41:42,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3178 states and 4699 transitions. [2021-07-06 20:41:42,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3178 to 3018. [2021-07-06 20:41:42,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3018 states, 3018 states have (on average 1.4827700463883366) internal successors, (4475), 3017 states have internal predecessors, (4475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3018 states to 3018 states and 4475 transitions. [2021-07-06 20:41:42,199 INFO L704 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2021-07-06 20:41:42,199 INFO L587 BuchiCegarLoop]: Abstraction has 3018 states and 4475 transitions. [2021-07-06 20:41:42,199 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-07-06 20:41:42,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3018 states and 4475 transitions. [2021-07-06 20:41:42,214 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2921 [2021-07-06 20:41:42,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:42,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:42,215 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,215 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,216 INFO L791 eck$LassoCheckResult]: Stem: 14772#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 14630#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14608#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14595#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 14596#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14325#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14326#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14581#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14582#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14484#L431-1 assume !(0 == ~M_E~0); 14485#L591-1 assume !(0 == ~T1_E~0); 14489#L596-1 assume !(0 == ~T2_E~0); 14490#L601-1 assume !(0 == ~T3_E~0); 14555#L606-1 assume !(0 == ~T4_E~0); 14426#L611-1 assume !(0 == ~T5_E~0); 14427#L616-1 assume !(0 == ~E_M~0); 14240#L621-1 assume !(0 == ~E_1~0); 14241#L626-1 assume !(0 == ~E_2~0); 14333#L631-1 assume !(0 == ~E_3~0); 14334#L636-1 assume !(0 == ~E_4~0); 14602#L641-1 assume !(0 == ~E_5~0); 14603#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14701#L284 assume !(1 == ~m_pc~0); 14685#L284-2 is_master_triggered_~__retres1~0 := 0; 14686#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14628#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14629#L735 assume !(0 != activate_threads_~tmp~1); 14842#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14344#L303 assume !(1 == ~t1_pc~0); 14345#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 14406#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14415#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14439#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14440#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14442#L322 assume 1 == ~t2_pc~0; 14282#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14283#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14280#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14281#L751 assume !(0 != activate_threads_~tmp___1~0); 14597#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14598#L341 assume !(1 == ~t3_pc~0); 14545#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 14546#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14542#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14543#L759 assume !(0 != activate_threads_~tmp___2~0); 14787#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14788#L360 assume 1 == ~t4_pc~0; 14714#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14715#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14709#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14710#L767 assume !(0 != activate_threads_~tmp___3~0); 14793#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14483#L379 assume !(1 == ~t5_pc~0); 14399#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 14398#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14394#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14252#L775 assume !(0 != activate_threads_~tmp___4~0); 14253#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 14256#L659-1 assume !(1 == ~T1_E~0); 14331#L664-1 assume !(1 == ~T2_E~0); 14332#L669-1 assume !(1 == ~T3_E~0); 14843#L674-1 assume !(1 == ~T4_E~0); 16657#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16656#L684-1 assume !(1 == ~E_M~0); 16655#L689-1 assume !(1 == ~E_1~0); 16651#L694-1 assume !(1 == ~E_2~0); 16649#L699-1 assume !(1 == ~E_3~0); 16644#L704-1 assume !(1 == ~E_4~0); 14231#L709-1 assume !(1 == ~E_5~0); 14232#L920-1 [2021-07-06 20:41:42,216 INFO L793 eck$LassoCheckResult]: Loop: 14232#L920-1 assume !false; 14968#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 14963#L566 assume !false; 14958#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 14949#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 14945#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 14929#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 14923#L491 assume !(0 != eval_~tmp~0); 14848#L581 start_simulation_~kernel_st~0 := 2; 14585#L399-1 start_simulation_~kernel_st~0 := 3; 14586#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 14871#L591-4 assume !(0 == ~T1_E~0); 14495#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14496#L601-3 assume !(0 == ~T3_E~0); 14559#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14433#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14434#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14249#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14250#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14305#L631-3 assume !(0 == ~E_3~0); 14306#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14592#L641-3 assume !(0 == ~E_5~0); 14593#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14658#L284-21 assume !(1 == ~m_pc~0); 14656#L284-23 is_master_triggered_~__retres1~0 := 0; 14657#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14639#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14640#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14673#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14674#L303-21 assume 1 == ~t1_pc~0; 14796#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14797#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14794#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14795#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14836#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14330#L322-21 assume 1 == ~t2_pc~0; 14272#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14273#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14270#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14271#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14561#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14562#L341-21 assume 1 == ~t3_pc~0; 14536#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14537#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14534#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14535#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14765#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14766#L360-21 assume 1 == ~t4_pc~0; 14698#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14699#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14696#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14697#L767-21 assume !(0 != activate_threads_~tmp___3~0); 14853#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14854#L379-21 assume !(1 == ~t5_pc~0); 17024#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 17021#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17019#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 17017#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17014#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 14460#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17011#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17009#L669-3 assume !(1 == ~T3_E~0); 16600#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17006#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17005#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17002#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17000#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16706#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16704#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16702#L709-3 assume !(1 == ~E_5~0); 14239#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16694#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16686#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16684#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 16683#L939 assume !(0 == start_simulation_~tmp~3); 15062#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16680#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16676#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16675#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 16674#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16673#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 16672#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 14975#L952 assume !(0 != start_simulation_~tmp___0~1); 14232#L920-1 [2021-07-06 20:41:42,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,217 INFO L82 PathProgramCache]: Analyzing trace with hash 1870207229, now seen corresponding path program 1 times [2021-07-06 20:41:42,217 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,217 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471845052] [2021-07-06 20:41:42,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,217 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,242 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,243 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,243 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,243 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,247 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,247 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,251 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,252 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,257 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,258 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,258 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,258 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,260 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471845052] [2021-07-06 20:41:42,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471845052] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,260 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,261 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:42,261 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292953197] [2021-07-06 20:41:42,261 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,262 INFO L82 PathProgramCache]: Analyzing trace with hash 764946036, now seen corresponding path program 1 times [2021-07-06 20:41:42,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786520766] [2021-07-06 20:41:42,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,262 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,283 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,284 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,286 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,286 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,292 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,293 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,298 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,299 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,305 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,306 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,306 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,306 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786520766] [2021-07-06 20:41:42,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786520766] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,307 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:42,307 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320380527] [2021-07-06 20:41:42,307 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,307 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,308 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:42,308 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:42,308 INFO L87 Difference]: Start difference. First operand 3018 states and 4475 transitions. cyclomatic complexity: 1465 Second operand has 5 states, 5 states have (on average 13.8) internal successors, (69), 5 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:42,565 INFO L93 Difference]: Finished difference Result 8208 states and 12147 transitions. [2021-07-06 20:41:42,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-07-06 20:41:42,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8208 states and 12147 transitions. [2021-07-06 20:41:42,614 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7982 [2021-07-06 20:41:42,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8208 states to 8208 states and 12147 transitions. [2021-07-06 20:41:42,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8208 [2021-07-06 20:41:42,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8208 [2021-07-06 20:41:42,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8208 states and 12147 transitions. [2021-07-06 20:41:42,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:42,680 INFO L681 BuchiCegarLoop]: Abstraction has 8208 states and 12147 transitions. [2021-07-06 20:41:42,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8208 states and 12147 transitions. [2021-07-06 20:41:42,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8208 to 3171. [2021-07-06 20:41:42,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3171 states, 3171 states have (on average 1.4594765058341217) internal successors, (4628), 3170 states have internal predecessors, (4628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3171 states to 3171 states and 4628 transitions. [2021-07-06 20:41:42,770 INFO L704 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2021-07-06 20:41:42,771 INFO L587 BuchiCegarLoop]: Abstraction has 3171 states and 4628 transitions. [2021-07-06 20:41:42,771 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-07-06 20:41:42,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3171 states and 4628 transitions. [2021-07-06 20:41:42,780 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3071 [2021-07-06 20:41:42,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:42,780 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:42,781 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,781 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,782 INFO L791 eck$LassoCheckResult]: Stem: 26009#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 25872#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25850#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25837#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 25838#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25568#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25569#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25821#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25822#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25726#L431-1 assume !(0 == ~M_E~0); 25727#L591-1 assume !(0 == ~T1_E~0); 25731#L596-1 assume !(0 == ~T2_E~0); 25732#L601-1 assume !(0 == ~T3_E~0); 25800#L606-1 assume !(0 == ~T4_E~0); 25671#L611-1 assume !(0 == ~T5_E~0); 25672#L616-1 assume !(0 == ~E_M~0); 25481#L621-1 assume !(0 == ~E_1~0); 25482#L626-1 assume !(0 == ~E_2~0); 25576#L631-1 assume !(0 == ~E_3~0); 25577#L636-1 assume !(0 == ~E_4~0); 25844#L641-1 assume !(0 == ~E_5~0); 25845#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25940#L284 assume !(1 == ~m_pc~0); 25925#L284-2 is_master_triggered_~__retres1~0 := 0; 25926#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25870#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25871#L735 assume !(0 != activate_threads_~tmp~1); 26118#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25585#L303 assume !(1 == ~t1_pc~0); 25586#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 25650#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25660#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25684#L743 assume !(0 != activate_threads_~tmp___0~0); 25685#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25687#L322 assume 1 == ~t2_pc~0; 25523#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25524#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25521#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 25522#L751 assume !(0 != activate_threads_~tmp___1~0); 25839#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25840#L341 assume !(1 == ~t3_pc~0); 25789#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 25790#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25786#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25787#L759 assume !(0 != activate_threads_~tmp___2~0); 26028#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26029#L360 assume 1 == ~t4_pc~0; 25953#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 25954#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25947#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25948#L767 assume !(0 != activate_threads_~tmp___3~0); 26033#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25724#L379 assume !(1 == ~t5_pc~0); 25643#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 25642#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25637#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 25493#L775 assume !(0 != activate_threads_~tmp___4~0); 25494#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 25497#L659-1 assume !(1 == ~T1_E~0); 27363#L664-1 assume !(1 == ~T2_E~0); 26119#L669-1 assume !(1 == ~T3_E~0); 26120#L674-1 assume !(1 == ~T4_E~0); 27780#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27753#L684-1 assume !(1 == ~E_M~0); 27746#L689-1 assume !(1 == ~E_1~0); 27738#L694-1 assume !(1 == ~E_2~0); 27729#L699-1 assume !(1 == ~E_3~0); 27722#L704-1 assume !(1 == ~E_4~0); 27714#L709-1 assume !(1 == ~E_5~0); 27148#L920-1 [2021-07-06 20:41:42,782 INFO L793 eck$LassoCheckResult]: Loop: 27148#L920-1 assume !false; 27326#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 27325#L566 assume !false; 27144#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27115#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27105#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27101#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 27098#L491 assume !(0 != eval_~tmp~0); 27099#L581 start_simulation_~kernel_st~0 := 2; 28468#L399-1 start_simulation_~kernel_st~0 := 3; 28466#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 26144#L591-4 assume !(0 == ~T1_E~0); 25738#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25739#L601-3 assume !(0 == ~T3_E~0); 25802#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25678#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25679#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25490#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25491#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25546#L631-3 assume !(0 == ~E_3~0); 25547#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25831#L641-3 assume !(0 == ~E_5~0); 25832#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25900#L284-21 assume !(1 == ~m_pc~0); 25898#L284-23 is_master_triggered_~__retres1~0 := 0; 25899#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25881#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25882#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25912#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25913#L303-21 assume 1 == ~t1_pc~0; 26036#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26037#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26105#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28482#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26106#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28163#L322-21 assume 1 == ~t2_pc~0; 28161#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 28159#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28156#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28036#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28035#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28034#L341-21 assume !(1 == ~t3_pc~0); 28032#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 28030#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28029#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 28027#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28024#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28021#L360-21 assume 1 == ~t4_pc~0; 28017#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27982#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27977#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27972#L767-21 assume !(0 != activate_threads_~tmp___3~0); 27965#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27960#L379-21 assume 1 == ~t5_pc~0; 27954#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 27947#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27942#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27937#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 27930#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 25703#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27921#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27916#L669-3 assume !(1 == ~T3_E~0); 26128#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27908#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27902#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 27898#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27894#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27891#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27872#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27867#L709-3 assume !(1 == ~E_5~0); 27849#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27840#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27831#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27827#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 27823#L939 assume !(0 == start_simulation_~tmp~3); 26027#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27777#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27752#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27745#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 27737#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27728#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 27721#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 27713#L952 assume !(0 != start_simulation_~tmp___0~1); 27148#L920-1 [2021-07-06 20:41:42,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,783 INFO L82 PathProgramCache]: Analyzing trace with hash -1765228545, now seen corresponding path program 1 times [2021-07-06 20:41:42,783 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,783 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1350794783] [2021-07-06 20:41:42,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,783 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,827 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,827 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,831 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,831 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:42,836 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,836 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1350794783] [2021-07-06 20:41:42,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1350794783] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,837 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,837 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,837 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252136939] [2021-07-06 20:41:42,838 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,839 INFO L82 PathProgramCache]: Analyzing trace with hash -1333424140, now seen corresponding path program 1 times [2021-07-06 20:41:42,839 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,839 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13679864] [2021-07-06 20:41:42,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,839 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,852 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,853 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,854 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,854 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:42,857 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,857 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,858 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,858 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [13679864] [2021-07-06 20:41:42,858 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [13679864] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,858 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,858 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,859 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723372648] [2021-07-06 20:41:42,859 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,859 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,860 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:42,860 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:42,860 INFO L87 Difference]: Start difference. First operand 3171 states and 4628 transitions. cyclomatic complexity: 1465 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:43,028 INFO L93 Difference]: Finished difference Result 7450 states and 10744 transitions. [2021-07-06 20:41:43,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:43,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7450 states and 10744 transitions. [2021-07-06 20:41:43,067 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7147 [2021-07-06 20:41:43,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7450 states to 7450 states and 10744 transitions. [2021-07-06 20:41:43,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7450 [2021-07-06 20:41:43,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7450 [2021-07-06 20:41:43,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7450 states and 10744 transitions. [2021-07-06 20:41:43,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:43,141 INFO L681 BuchiCegarLoop]: Abstraction has 7450 states and 10744 transitions. [2021-07-06 20:41:43,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7450 states and 10744 transitions. [2021-07-06 20:41:43,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7450 to 5823. [2021-07-06 20:41:43,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5823 states, 5823 states have (on average 1.451142023012193) internal successors, (8450), 5822 states have internal predecessors, (8450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5823 states to 5823 states and 8450 transitions. [2021-07-06 20:41:43,250 INFO L704 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2021-07-06 20:41:43,251 INFO L587 BuchiCegarLoop]: Abstraction has 5823 states and 8450 transitions. [2021-07-06 20:41:43,251 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-07-06 20:41:43,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5823 states and 8450 transitions. [2021-07-06 20:41:43,288 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5720 [2021-07-06 20:41:43,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:43,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:43,290 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,290 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,290 INFO L791 eck$LassoCheckResult]: Stem: 36621#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36492#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36470#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36457#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 36458#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36199#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36200#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36445#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36446#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36351#L431-1 assume !(0 == ~M_E~0); 36352#L591-1 assume !(0 == ~T1_E~0); 36355#L596-1 assume !(0 == ~T2_E~0); 36356#L601-1 assume !(0 == ~T3_E~0); 36422#L606-1 assume !(0 == ~T4_E~0); 36305#L611-1 assume !(0 == ~T5_E~0); 36306#L616-1 assume !(0 == ~E_M~0); 36111#L621-1 assume !(0 == ~E_1~0); 36112#L626-1 assume !(0 == ~E_2~0); 36207#L631-1 assume !(0 == ~E_3~0); 36208#L636-1 assume !(0 == ~E_4~0); 36464#L641-1 assume !(0 == ~E_5~0); 36465#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36562#L284 assume !(1 == ~m_pc~0); 36547#L284-2 is_master_triggered_~__retres1~0 := 0; 36548#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36490#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36491#L735 assume !(0 != activate_threads_~tmp~1); 36691#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36223#L303 assume !(1 == ~t1_pc~0); 36224#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 36284#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36296#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36316#L743 assume !(0 != activate_threads_~tmp___0~0); 36317#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36319#L322 assume !(1 == ~t2_pc~0); 36451#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 36450#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36151#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36152#L751 assume !(0 != activate_threads_~tmp___1~0); 36459#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36460#L341 assume !(1 == ~t3_pc~0); 36411#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 36412#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36408#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36409#L759 assume !(0 != activate_threads_~tmp___2~0); 36631#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36632#L360 assume 1 == ~t4_pc~0; 36573#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36574#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36571#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36572#L767 assume !(0 != activate_threads_~tmp___3~0); 36636#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36348#L379 assume !(1 == ~t5_pc~0); 36278#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 36277#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36273#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36125#L775 assume !(0 != activate_threads_~tmp___4~0); 36126#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 36127#L659-1 assume !(1 == ~T1_E~0); 36523#L664-1 assume !(1 == ~T2_E~0); 36693#L669-1 assume !(1 == ~T3_E~0); 36694#L674-1 assume !(1 == ~T4_E~0); 36708#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36709#L684-1 assume !(1 == ~E_M~0); 36675#L689-1 assume !(1 == ~E_1~0); 36676#L694-1 assume !(1 == ~E_2~0); 36320#L699-1 assume !(1 == ~E_3~0); 36321#L704-1 assume !(1 == ~E_4~0); 36103#L709-1 assume !(1 == ~E_5~0); 36104#L920-1 [2021-07-06 20:41:43,290 INFO L793 eck$LassoCheckResult]: Loop: 36104#L920-1 assume !false; 36635#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 36115#L566 assume !false; 36116#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36188#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36189#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36184#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 36185#L491 assume !(0 != eval_~tmp~0); 36671#L581 start_simulation_~kernel_st~0 := 2; 36447#L399-1 start_simulation_~kernel_st~0 := 3; 36448#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36706#L591-4 assume !(0 == ~T1_E~0); 36361#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36362#L601-3 assume !(0 == ~T3_E~0); 36423#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36310#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36311#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36120#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36121#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36173#L631-3 assume !(0 == ~E_3~0); 36174#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36454#L641-3 assume !(0 == ~E_5~0); 36455#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36520#L284-21 assume !(1 == ~m_pc~0); 36518#L284-23 is_master_triggered_~__retres1~0 := 0; 36519#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36501#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36502#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 36535#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36536#L303-21 assume !(1 == ~t1_pc~0); 36641#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 36669#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36637#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36638#L743-21 assume !(0 != activate_threads_~tmp___0~0); 36686#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36203#L322-21 assume !(1 == ~t2_pc~0); 36204#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 36209#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36141#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36142#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36428#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36429#L341-21 assume 1 == ~t3_pc~0; 36402#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 36403#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36400#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36401#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36617#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36618#L360-21 assume !(1 == ~t4_pc~0); 36561#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 36560#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36557#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36558#L767-21 assume !(0 != activate_threads_~tmp___3~0); 36695#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36318#L379-21 assume 1 == ~t5_pc~0; 36263#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36264#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36257#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36258#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36330#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 36332#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36210#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36211#L669-3 assume !(1 == ~T3_E~0); 36467#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36468#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36353#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36354#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36420#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36302#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36303#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36107#L709-3 assume !(1 == ~E_5~0); 36108#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36191#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36192#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36186#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 36187#L939 assume !(0 == start_simulation_~tmp~3); 36431#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36196#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36197#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36194#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 36195#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 36469#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 36542#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 36322#L952 assume !(0 != start_simulation_~tmp___0~1); 36104#L920-1 [2021-07-06 20:41:43,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,291 INFO L82 PathProgramCache]: Analyzing trace with hash -713779456, now seen corresponding path program 1 times [2021-07-06 20:41:43,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,291 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092792723] [2021-07-06 20:41:43,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,292 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,309 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,309 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,312 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,313 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:43,317 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,318 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,319 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,319 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092792723] [2021-07-06 20:41:43,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092792723] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,319 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:43,319 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23922783] [2021-07-06 20:41:43,320 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:43,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,320 INFO L82 PathProgramCache]: Analyzing trace with hash 111829360, now seen corresponding path program 1 times [2021-07-06 20:41:43,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384844774] [2021-07-06 20:41:43,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,321 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,335 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,335 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,336 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,336 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:43,340 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,340 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,340 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,341 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,341 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384844774] [2021-07-06 20:41:43,341 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384844774] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,341 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,341 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:43,341 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844004156] [2021-07-06 20:41:43,342 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:43,342 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:43,342 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:43,342 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:43,343 INFO L87 Difference]: Start difference. First operand 5823 states and 8450 transitions. cyclomatic complexity: 2635 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:43,542 INFO L93 Difference]: Finished difference Result 13963 states and 20008 transitions. [2021-07-06 20:41:43,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:43,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13963 states and 20008 transitions. [2021-07-06 20:41:43,613 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13457 [2021-07-06 20:41:43,672 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13963 states to 13963 states and 20008 transitions. [2021-07-06 20:41:43,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13963 [2021-07-06 20:41:43,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13963 [2021-07-06 20:41:43,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13963 states and 20008 transitions. [2021-07-06 20:41:43,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:43,706 INFO L681 BuchiCegarLoop]: Abstraction has 13963 states and 20008 transitions. [2021-07-06 20:41:43,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13963 states and 20008 transitions. [2021-07-06 20:41:43,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13963 to 11074. [2021-07-06 20:41:43,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11074 states, 11074 states have (on average 1.4411233519956654) internal successors, (15959), 11073 states have internal predecessors, (15959), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11074 states to 11074 states and 15959 transitions. [2021-07-06 20:41:43,970 INFO L704 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2021-07-06 20:41:43,971 INFO L587 BuchiCegarLoop]: Abstraction has 11074 states and 15959 transitions. [2021-07-06 20:41:43,971 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-07-06 20:41:43,971 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11074 states and 15959 transitions. [2021-07-06 20:41:44,011 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10964 [2021-07-06 20:41:44,011 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:44,011 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:44,012 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,013 INFO L791 eck$LassoCheckResult]: Stem: 56425#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56293#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56271#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56258#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 56259#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55993#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55994#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56243#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56244#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56150#L431-1 assume !(0 == ~M_E~0); 56151#L591-1 assume !(0 == ~T1_E~0); 56155#L596-1 assume !(0 == ~T2_E~0); 56156#L601-1 assume !(0 == ~T3_E~0); 56221#L606-1 assume !(0 == ~T4_E~0); 56101#L611-1 assume !(0 == ~T5_E~0); 56102#L616-1 assume !(0 == ~E_M~0); 55907#L621-1 assume !(0 == ~E_1~0); 55908#L626-1 assume !(0 == ~E_2~0); 56004#L631-1 assume !(0 == ~E_3~0); 56005#L636-1 assume !(0 == ~E_4~0); 56265#L641-1 assume !(0 == ~E_5~0); 56266#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56364#L284 assume !(1 == ~m_pc~0); 56347#L284-2 is_master_triggered_~__retres1~0 := 0; 56348#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56291#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56292#L735 assume !(0 != activate_threads_~tmp~1); 56498#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56018#L303 assume !(1 == ~t1_pc~0); 56019#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 56080#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56090#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56114#L743 assume !(0 != activate_threads_~tmp___0~0); 56115#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56117#L322 assume !(1 == ~t2_pc~0); 56251#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 56250#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55947#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55948#L751 assume !(0 != activate_threads_~tmp___1~0); 56260#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56261#L341 assume !(1 == ~t3_pc~0); 56211#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 56212#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56208#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56209#L759 assume !(0 != activate_threads_~tmp___2~0); 56434#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56435#L360 assume !(1 == ~t4_pc~0); 56518#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 56516#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56371#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56372#L767 assume !(0 != activate_threads_~tmp___3~0); 56438#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56148#L379 assume !(1 == ~t5_pc~0); 56074#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 56073#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56069#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55919#L775 assume !(0 != activate_threads_~tmp___4~0); 55920#L775-2 assume 1 == ~M_E~0;~M_E~0 := 2; 55923#L659-1 assume !(1 == ~T1_E~0); 56324#L664-1 assume !(1 == ~T2_E~0); 56499#L669-1 assume !(1 == ~T3_E~0); 56263#L674-1 assume !(1 == ~T4_E~0); 56264#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56165#L684-1 assume !(1 == ~E_M~0); 56166#L689-1 assume !(1 == ~E_1~0); 64092#L694-1 assume !(1 == ~E_2~0); 64090#L699-1 assume !(1 == ~E_3~0); 64088#L704-1 assume !(1 == ~E_4~0); 55899#L709-1 assume !(1 == ~E_5~0); 55900#L920-1 [2021-07-06 20:41:44,013 INFO L793 eck$LassoCheckResult]: Loop: 55900#L920-1 assume !false; 56437#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 55911#L566 assume !false; 55912#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55983#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55984#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55981#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 55982#L491 assume !(0 != eval_~tmp~0); 56477#L581 start_simulation_~kernel_st~0 := 2; 56247#L399-1 start_simulation_~kernel_st~0 := 3; 56248#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56522#L591-4 assume !(0 == ~T1_E~0); 56161#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56162#L601-3 assume !(0 == ~T3_E~0); 56223#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56108#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56109#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55916#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55917#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55969#L631-3 assume !(0 == ~E_3~0); 55970#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56255#L641-3 assume !(0 == ~E_5~0); 56256#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56321#L284-21 assume !(1 == ~m_pc~0); 56319#L284-23 is_master_triggered_~__retres1~0 := 0; 56320#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56302#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 56303#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 56334#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56335#L303-21 assume 1 == ~t1_pc~0; 56441#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56442#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66956#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 66852#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56490#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56000#L322-21 assume !(1 == ~t2_pc~0); 56001#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 56006#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55937#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55938#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56225#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56226#L341-21 assume 1 == ~t3_pc~0; 56202#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56203#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56200#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56201#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56421#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56422#L360-21 assume !(1 == ~t4_pc~0); 56497#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 56501#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56359#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56360#L767-21 assume !(0 != activate_threads_~tmp___3~0); 56502#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56116#L379-21 assume 1 == ~t5_pc~0; 56061#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56062#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56055#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56056#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 56129#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 56131#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56007#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56008#L669-3 assume !(1 == ~T3_E~0); 56268#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56269#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56153#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56154#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56220#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56099#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56100#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55905#L709-3 assume !(1 == ~E_5~0); 55906#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55988#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55989#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55986#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 55987#L939 assume !(0 == start_simulation_~tmp~3); 56228#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 55995#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55996#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 55991#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 55992#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56270#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 56342#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 56120#L952 assume !(0 != start_simulation_~tmp___0~1); 55900#L920-1 [2021-07-06 20:41:44,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,014 INFO L82 PathProgramCache]: Analyzing trace with hash 66201473, now seen corresponding path program 1 times [2021-07-06 20:41:44,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,014 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866806790] [2021-07-06 20:41:44,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,014 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,033 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,034 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:44,038 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,038 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,039 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [866806790] [2021-07-06 20:41:44,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [866806790] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,039 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:44,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1276302980] [2021-07-06 20:41:44,040 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:44,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,041 INFO L82 PathProgramCache]: Analyzing trace with hash 490108371, now seen corresponding path program 1 times [2021-07-06 20:41:44,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329891554] [2021-07-06 20:41:44,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,041 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,057 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,057 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,058 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,058 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:44,061 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,063 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,063 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,063 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329891554] [2021-07-06 20:41:44,063 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329891554] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,064 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,064 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:44,064 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355960832] [2021-07-06 20:41:44,064 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:44,064 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:44,065 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:44,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:44,066 INFO L87 Difference]: Start difference. First operand 11074 states and 15959 transitions. cyclomatic complexity: 4893 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:44,198 INFO L93 Difference]: Finished difference Result 13875 states and 19988 transitions. [2021-07-06 20:41:44,199 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:44,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13875 states and 19988 transitions. [2021-07-06 20:41:44,264 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13772 [2021-07-06 20:41:44,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13875 states to 13875 states and 19988 transitions. [2021-07-06 20:41:44,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13875 [2021-07-06 20:41:44,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13875 [2021-07-06 20:41:44,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13875 states and 19988 transitions. [2021-07-06 20:41:44,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:44,337 INFO L681 BuchiCegarLoop]: Abstraction has 13875 states and 19988 transitions. [2021-07-06 20:41:44,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13875 states and 19988 transitions. [2021-07-06 20:41:44,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13875 to 6055. [2021-07-06 20:41:44,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6055 states, 6055 states have (on average 1.4467382328654006) internal successors, (8760), 6054 states have internal predecessors, (8760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8760 transitions. [2021-07-06 20:41:44,523 INFO L704 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2021-07-06 20:41:44,523 INFO L587 BuchiCegarLoop]: Abstraction has 6055 states and 8760 transitions. [2021-07-06 20:41:44,523 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-07-06 20:41:44,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8760 transitions. [2021-07-06 20:41:44,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2021-07-06 20:41:44,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:44,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:44,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,542 INFO L791 eck$LassoCheckResult]: Stem: 81403#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81261#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81239#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81226#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 81227#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80947#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80948#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81209#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81210#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81108#L431-1 assume !(0 == ~M_E~0); 81109#L591-1 assume !(0 == ~T1_E~0); 81113#L596-1 assume !(0 == ~T2_E~0); 81114#L601-1 assume !(0 == ~T3_E~0); 81179#L606-1 assume !(0 == ~T4_E~0); 81055#L611-1 assume !(0 == ~T5_E~0); 81056#L616-1 assume !(0 == ~E_M~0); 80862#L621-1 assume !(0 == ~E_1~0); 80863#L626-1 assume !(0 == ~E_2~0); 80956#L631-1 assume !(0 == ~E_3~0); 80957#L636-1 assume !(0 == ~E_4~0); 81233#L641-1 assume !(0 == ~E_5~0); 81234#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81335#L284 assume !(1 == ~m_pc~0); 81318#L284-2 is_master_triggered_~__retres1~0 := 0; 81319#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81259#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 81260#L735 assume !(0 != activate_threads_~tmp~1); 81482#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80970#L303 assume !(1 == ~t1_pc~0); 80971#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 81033#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 81519#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81067#L743 assume !(0 != activate_threads_~tmp___0~0); 81068#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81070#L322 assume !(1 == ~t2_pc~0); 81217#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 81216#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 80901#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 80902#L751 assume !(0 != activate_threads_~tmp___1~0); 81228#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81229#L341 assume !(1 == ~t3_pc~0); 81169#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 81170#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81166#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81167#L759 assume !(0 != activate_threads_~tmp___2~0); 81420#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81421#L360 assume !(1 == ~t4_pc~0); 81510#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 81508#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81342#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81343#L767 assume !(0 != activate_threads_~tmp___3~0); 81425#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81107#L379 assume !(1 == ~t5_pc~0); 81027#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 81026#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81021#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 80874#L775 assume !(0 != activate_threads_~tmp___4~0); 80875#L775-2 assume !(1 == ~M_E~0); 80878#L659-1 assume !(1 == ~T1_E~0); 80954#L664-1 assume !(1 == ~T2_E~0); 80955#L669-1 assume !(1 == ~T3_E~0); 81231#L674-1 assume !(1 == ~T4_E~0); 81232#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81123#L684-1 assume !(1 == ~E_M~0); 81124#L689-1 assume !(1 == ~E_1~0); 81382#L694-1 assume !(1 == ~E_2~0); 81071#L699-1 assume !(1 == ~E_3~0); 81072#L704-1 assume !(1 == ~E_4~0); 80855#L709-1 assume !(1 == ~E_5~0); 80856#L920-1 [2021-07-06 20:41:44,542 INFO L793 eck$LassoCheckResult]: Loop: 80856#L920-1 assume !false; 86311#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 86310#L566 assume !false; 86309#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86301#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86277#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86273#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 86268#L491 assume !(0 != eval_~tmp~0); 86269#L581 start_simulation_~kernel_st~0 := 2; 86818#L399-1 start_simulation_~kernel_st~0 := 3; 86816#L591-2 assume !(0 == ~M_E~0); 86813#L591-4 assume !(0 == ~T1_E~0); 86811#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 86809#L601-3 assume !(0 == ~T3_E~0); 86807#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86805#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86804#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86800#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86798#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86796#L631-3 assume !(0 == ~E_3~0); 86794#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86791#L641-3 assume !(0 == ~E_5~0); 86789#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86787#L284-21 assume !(1 == ~m_pc~0); 86786#L284-23 is_master_triggered_~__retres1~0 := 0; 86785#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86784#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 86782#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86781#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86778#L303-21 assume !(1 == ~t1_pc~0); 86776#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 86774#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86772#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 86770#L743-21 assume !(0 != activate_threads_~tmp___0~0); 86766#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 80952#L322-21 assume !(1 == ~t2_pc~0); 80953#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 86868#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86866#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 86864#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 81185#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81186#L341-21 assume !(1 == ~t3_pc~0); 86583#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 86581#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86579#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 86576#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86575#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86573#L360-21 assume !(1 == ~t4_pc~0); 82020#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 86569#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86570#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 86574#L767-21 assume !(0 != activate_threads_~tmp___3~0); 86572#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86571#L379-21 assume 1 == ~t5_pc~0; 86567#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 86564#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86562#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 86560#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 86558#L775-23 assume !(1 == ~M_E~0); 82868#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86555#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86547#L669-3 assume !(1 == ~T3_E~0); 86542#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86539#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81111#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 81112#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 81178#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 81053#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 81054#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 81414#L709-3 assume !(1 == ~E_5~0); 81730#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 81686#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 81670#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 81662#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 81659#L939 assume !(0 == start_simulation_~tmp~3); 81660#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86391#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86385#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86370#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 86367#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86366#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 86365#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 86353#L952 assume !(0 != start_simulation_~tmp___0~1); 80856#L920-1 [2021-07-06 20:41:44,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,543 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-07-06 20:41:44,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,543 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097490138] [2021-07-06 20:41:44,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,543 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,559 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,560 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:44,563 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,563 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:44,568 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,568 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,569 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,569 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097490138] [2021-07-06 20:41:44,569 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097490138] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,569 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,569 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:44,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269380137] [2021-07-06 20:41:44,570 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:44,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,570 INFO L82 PathProgramCache]: Analyzing trace with hash 480788307, now seen corresponding path program 1 times [2021-07-06 20:41:44,570 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532151548] [2021-07-06 20:41:44,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,571 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,583 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,583 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,584 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,584 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:44,587 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,588 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,588 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532151548] [2021-07-06 20:41:44,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532151548] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,589 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:44,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436339857] [2021-07-06 20:41:44,589 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:44,589 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:44,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:44,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:44,590 INFO L87 Difference]: Start difference. First operand 6055 states and 8760 transitions. cyclomatic complexity: 2707 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:44,672 INFO L93 Difference]: Finished difference Result 9727 states and 14003 transitions. [2021-07-06 20:41:44,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:44,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9727 states and 14003 transitions. [2021-07-06 20:41:44,780 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9580 [2021-07-06 20:41:44,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9727 states to 9727 states and 14003 transitions. [2021-07-06 20:41:44,856 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9727 [2021-07-06 20:41:44,872 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9727 [2021-07-06 20:41:44,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9727 states and 14003 transitions. [2021-07-06 20:41:44,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:44,896 INFO L681 BuchiCegarLoop]: Abstraction has 9727 states and 14003 transitions. [2021-07-06 20:41:44,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9727 states and 14003 transitions. [2021-07-06 20:41:45,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9727 to 6997. [2021-07-06 20:41:45,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6997 states, 6997 states have (on average 1.443332856938688) internal successors, (10099), 6996 states have internal predecessors, (10099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6997 states to 6997 states and 10099 transitions. [2021-07-06 20:41:45,074 INFO L704 BuchiCegarLoop]: Abstraction has 6997 states and 10099 transitions. [2021-07-06 20:41:45,074 INFO L587 BuchiCegarLoop]: Abstraction has 6997 states and 10099 transitions. [2021-07-06 20:41:45,074 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-07-06 20:41:45,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6997 states and 10099 transitions. [2021-07-06 20:41:45,095 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6860 [2021-07-06 20:41:45,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:45,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:45,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,098 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,098 INFO L791 eck$LassoCheckResult]: Stem: 97189#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 97060#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 97036#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97023#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 97024#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96738#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96739#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96999#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97000#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96900#L431-1 assume !(0 == ~M_E~0); 96901#L591-1 assume !(0 == ~T1_E~0); 96905#L596-1 assume !(0 == ~T2_E~0); 96906#L601-1 assume !(0 == ~T3_E~0); 96971#L606-1 assume !(0 == ~T4_E~0); 96843#L611-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96844#L616-1 assume !(0 == ~E_M~0); 97205#L621-1 assume !(0 == ~E_1~0); 97089#L626-1 assume !(0 == ~E_2~0); 97090#L631-1 assume !(0 == ~E_3~0); 97281#L636-1 assume !(0 == ~E_4~0); 97282#L641-1 assume !(0 == ~E_5~0); 97322#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97323#L284 assume !(1 == ~m_pc~0); 97111#L284-2 is_master_triggered_~__retres1~0 := 0; 97112#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97058#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 97059#L735 assume !(0 != activate_threads_~tmp~1); 97277#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97278#L303 assume !(1 == ~t1_pc~0); 96821#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 96822#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96832#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 96857#L743 assume !(0 != activate_threads_~tmp___0~0); 96858#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97008#L322 assume !(1 == ~t2_pc~0); 97009#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 97006#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97007#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 97039#L751 assume !(0 != activate_threads_~tmp___1~0); 97040#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97200#L341 assume !(1 == ~t3_pc~0); 97201#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 97198#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97199#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 97210#L759 assume !(0 != activate_threads_~tmp___2~0); 97211#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97311#L360 assume !(1 == ~t4_pc~0); 97312#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 97315#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97137#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 97138#L767 assume !(0 != activate_threads_~tmp___3~0); 97318#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97319#L379 assume !(1 == ~t5_pc~0); 96815#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 96814#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 96809#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 96810#L775 assume !(0 != activate_threads_~tmp___4~0); 97327#L775-2 assume !(1 == ~M_E~0); 97088#L659-1 assume !(1 == ~T1_E~0); 96745#L664-1 assume !(1 == ~T2_E~0); 96746#L669-1 assume !(1 == ~T3_E~0); 97028#L674-1 assume !(1 == ~T4_E~0); 97029#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96915#L684-1 assume !(1 == ~E_M~0); 96916#L689-1 assume !(1 == ~E_1~0); 97175#L694-1 assume !(1 == ~E_2~0); 96862#L699-1 assume !(1 == ~E_3~0); 96863#L704-1 assume !(1 == ~E_4~0); 96647#L709-1 assume !(1 == ~E_5~0); 96648#L920-1 [2021-07-06 20:41:45,098 INFO L793 eck$LassoCheckResult]: Loop: 96648#L920-1 assume !false; 102225#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 102223#L566 assume !false; 102221#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 96728#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 96729#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 96726#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 96727#L491 assume !(0 != eval_~tmp~0); 97253#L581 start_simulation_~kernel_st~0 := 2; 103184#L399-1 start_simulation_~kernel_st~0 := 3; 103180#L591-2 assume !(0 == ~M_E~0); 103177#L591-4 assume !(0 == ~T1_E~0); 102989#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 102901#L601-3 assume !(0 == ~T3_E~0); 102900#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96850#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96851#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 103545#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 103544#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 103543#L631-3 assume !(0 == ~E_3~0); 103542#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 103541#L641-3 assume !(0 == ~E_5~0); 103540#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 103539#L284-21 assume !(1 == ~m_pc~0); 103538#L284-23 is_master_triggered_~__retres1~0 := 0; 103537#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 103536#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 103535#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 103534#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 103533#L303-21 assume 1 == ~t1_pc~0; 103531#L304-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 103529#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 103527#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 103525#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 103524#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 103523#L322-21 assume !(1 == ~t2_pc~0); 101214#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 103522#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 103521#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 103520#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 103519#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 103518#L341-21 assume 1 == ~t3_pc~0; 103517#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 103515#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 103514#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 103513#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 103512#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 103511#L360-21 assume !(1 == ~t4_pc~0); 102808#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 103510#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 103509#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 103435#L767-21 assume !(0 != activate_threads_~tmp___3~0); 103436#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 103307#L379-21 assume !(1 == ~t5_pc~0); 103309#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 103300#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 103301#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 103294#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 103295#L775-23 assume !(1 == ~M_E~0); 99894#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103284#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 103280#L669-3 assume !(1 == ~T3_E~0); 103281#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103273#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96903#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 96904#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103434#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103433#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103431#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103429#L709-3 assume !(1 == ~E_5~0); 103427#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 103290#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 103276#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 103272#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 99986#L939 assume !(0 == start_simulation_~tmp~3); 99987#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 102287#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 102282#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 102279#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 102277#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 102275#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 102273#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 102272#L952 assume !(0 != start_simulation_~tmp___0~1); 96648#L920-1 [2021-07-06 20:41:45,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,100 INFO L82 PathProgramCache]: Analyzing trace with hash -1062418499, now seen corresponding path program 1 times [2021-07-06 20:41:45,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,100 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002375618] [2021-07-06 20:41:45,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,101 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,115 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,116 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,119 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,119 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:45,123 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,124 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,124 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002375618] [2021-07-06 20:41:45,124 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002375618] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,125 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278869870] [2021-07-06 20:41:45,125 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:45,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,126 INFO L82 PathProgramCache]: Analyzing trace with hash -1337529802, now seen corresponding path program 1 times [2021-07-06 20:41:45,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,126 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271348890] [2021-07-06 20:41:45,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,127 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,141 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,142 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,143 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,143 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,147 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,147 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,152 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,153 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,158 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,158 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,159 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,159 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,159 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271348890] [2021-07-06 20:41:45,159 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271348890] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,159 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,159 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:45,160 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1588930989] [2021-07-06 20:41:45,160 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:45,160 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:45,162 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:45,162 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:45,162 INFO L87 Difference]: Start difference. First operand 6997 states and 10099 transitions. cyclomatic complexity: 3104 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:45,239 INFO L93 Difference]: Finished difference Result 8779 states and 12594 transitions. [2021-07-06 20:41:45,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:45,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8779 states and 12594 transitions. [2021-07-06 20:41:45,279 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8692 [2021-07-06 20:41:45,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8779 states to 8779 states and 12594 transitions. [2021-07-06 20:41:45,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8779 [2021-07-06 20:41:45,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8779 [2021-07-06 20:41:45,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8779 states and 12594 transitions. [2021-07-06 20:41:45,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:45,329 INFO L681 BuchiCegarLoop]: Abstraction has 8779 states and 12594 transitions. [2021-07-06 20:41:45,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8779 states and 12594 transitions. [2021-07-06 20:41:45,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8779 to 6055. [2021-07-06 20:41:45,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6055 states, 6055 states have (on average 1.4384805945499588) internal successors, (8710), 6054 states have internal predecessors, (8710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6055 states to 6055 states and 8710 transitions. [2021-07-06 20:41:45,539 INFO L704 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2021-07-06 20:41:45,539 INFO L587 BuchiCegarLoop]: Abstraction has 6055 states and 8710 transitions. [2021-07-06 20:41:45,539 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-07-06 20:41:45,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6055 states and 8710 transitions. [2021-07-06 20:41:45,603 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5972 [2021-07-06 20:41:45,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:45,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:45,605 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,605 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,605 INFO L791 eck$LassoCheckResult]: Stem: 112957#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 112830#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 112808#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 112795#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 112796#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 112525#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 112526#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 112781#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 112782#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 112678#L431-1 assume !(0 == ~M_E~0); 112679#L591-1 assume !(0 == ~T1_E~0); 112683#L596-1 assume !(0 == ~T2_E~0); 112684#L601-1 assume !(0 == ~T3_E~0); 112749#L606-1 assume !(0 == ~T4_E~0); 112630#L611-1 assume !(0 == ~T5_E~0); 112631#L616-1 assume !(0 == ~E_M~0); 112442#L621-1 assume !(0 == ~E_1~0); 112443#L626-1 assume !(0 == ~E_2~0); 112536#L631-1 assume !(0 == ~E_3~0); 112537#L636-1 assume !(0 == ~E_4~0); 112802#L641-1 assume !(0 == ~E_5~0); 112803#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 112894#L284 assume !(1 == ~m_pc~0); 112879#L284-2 is_master_triggered_~__retres1~0 := 0; 112880#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 112828#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 112829#L735 assume !(0 != activate_threads_~tmp~1); 113036#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 112548#L303 assume !(1 == ~t1_pc~0); 112549#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 112609#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 112619#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 112642#L743 assume !(0 != activate_threads_~tmp___0~0); 112643#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 112645#L322 assume !(1 == ~t2_pc~0); 112789#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 112788#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 112481#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 112482#L751 assume !(0 != activate_threads_~tmp___1~0); 112797#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 112798#L341 assume !(1 == ~t3_pc~0); 112739#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 112740#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 112736#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 112737#L759 assume !(0 != activate_threads_~tmp___2~0); 112971#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112972#L360 assume !(1 == ~t4_pc~0); 113060#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 113058#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 112901#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 112902#L767 assume !(0 != activate_threads_~tmp___3~0); 112974#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 112677#L379 assume !(1 == ~t5_pc~0); 112603#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 112602#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 112597#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 112454#L775 assume !(0 != activate_threads_~tmp___4~0); 112455#L775-2 assume !(1 == ~M_E~0); 112458#L659-1 assume !(1 == ~T1_E~0); 112534#L664-1 assume !(1 == ~T2_E~0); 112535#L669-1 assume !(1 == ~T3_E~0); 112800#L674-1 assume !(1 == ~T4_E~0); 112801#L679-1 assume !(1 == ~T5_E~0); 112693#L684-1 assume !(1 == ~E_M~0); 112694#L689-1 assume !(1 == ~E_1~0); 112938#L694-1 assume !(1 == ~E_2~0); 112646#L699-1 assume !(1 == ~E_3~0); 112647#L704-1 assume !(1 == ~E_4~0); 112435#L709-1 assume !(1 == ~E_5~0); 112436#L920-1 [2021-07-06 20:41:45,606 INFO L793 eck$LassoCheckResult]: Loop: 112436#L920-1 assume !false; 112973#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 112446#L566 assume !false; 112447#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 112515#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 112516#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 112513#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 112514#L491 assume !(0 != eval_~tmp~0); 113010#L581 start_simulation_~kernel_st~0 := 2; 118306#L399-1 start_simulation_~kernel_st~0 := 3; 118305#L591-2 assume !(0 == ~M_E~0); 118304#L591-4 assume !(0 == ~T1_E~0); 118303#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 118302#L601-3 assume !(0 == ~T3_E~0); 118300#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118299#L611-3 assume !(0 == ~T5_E~0); 118298#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 118297#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 118296#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 118294#L631-3 assume !(0 == ~E_3~0); 118291#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 118289#L641-3 assume !(0 == ~E_5~0); 118287#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 118285#L284-21 assume !(1 == ~m_pc~0); 118283#L284-23 is_master_triggered_~__retres1~0 := 0; 118279#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118277#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 118275#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 118273#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 118267#L303-21 assume !(1 == ~t1_pc~0); 118265#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 118264#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 118263#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 118262#L743-21 assume !(0 != activate_threads_~tmp___0~0); 118260#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 112532#L322-21 assume !(1 == ~t2_pc~0); 112533#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 118317#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 118316#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 118315#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 118314#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118313#L341-21 assume !(1 == ~t3_pc~0); 118311#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 118310#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118309#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 118308#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 112951#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112952#L360-21 assume !(1 == ~t4_pc~0); 116967#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 116965#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116962#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 116960#L767-21 assume !(0 != activate_threads_~tmp___3~0); 116958#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 116956#L379-21 assume 1 == ~t5_pc~0; 116953#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 116951#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 116948#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 116946#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 116944#L775-23 assume !(1 == ~M_E~0); 115921#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116942#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116939#L669-3 assume !(1 == ~T3_E~0); 116938#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116936#L679-3 assume !(1 == ~T5_E~0); 116931#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 116929#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116927#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116926#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 116925#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116924#L709-3 assume !(1 == ~E_5~0); 116923#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116918#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 116912#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 116910#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 115980#L939 assume !(0 == start_simulation_~tmp~3); 115981#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 117777#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117772#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117770#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 117768#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 117766#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 117764#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 117762#L952 assume !(0 != start_simulation_~tmp___0~1); 112436#L920-1 [2021-07-06 20:41:45,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,607 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-07-06 20:41:45,607 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,607 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341804564] [2021-07-06 20:41:45,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,607 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:45,623 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:45,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:45,633 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:45,669 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:45,670 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,670 INFO L82 PathProgramCache]: Analyzing trace with hash 617080015, now seen corresponding path program 1 times [2021-07-06 20:41:45,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,670 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1444952436] [2021-07-06 20:41:45,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,670 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,683 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,684 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,684 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,685 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:45,688 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,689 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,689 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1444952436] [2021-07-06 20:41:45,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1444952436] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,690 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,690 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,690 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802187901] [2021-07-06 20:41:45,690 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:45,690 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:45,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:45,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:45,691 INFO L87 Difference]: Start difference. First operand 6055 states and 8710 transitions. cyclomatic complexity: 2657 Second operand has 3 states, 3 states have (on average 27.666666666666668) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:45,779 INFO L93 Difference]: Finished difference Result 10974 states and 15679 transitions. [2021-07-06 20:41:45,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:45,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10974 states and 15679 transitions. [2021-07-06 20:41:45,829 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10868 [2021-07-06 20:41:45,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10974 states to 10974 states and 15679 transitions. [2021-07-06 20:41:45,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10974 [2021-07-06 20:41:45,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10974 [2021-07-06 20:41:45,872 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10974 states and 15679 transitions. [2021-07-06 20:41:45,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:45,882 INFO L681 BuchiCegarLoop]: Abstraction has 10974 states and 15679 transitions. [2021-07-06 20:41:45,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10974 states and 15679 transitions. [2021-07-06 20:41:45,989 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10974 to 10966. [2021-07-06 20:41:46,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10966 states, 10966 states have (on average 1.4290534378989603) internal successors, (15671), 10965 states have internal predecessors, (15671), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10966 states to 10966 states and 15671 transitions. [2021-07-06 20:41:46,033 INFO L704 BuchiCegarLoop]: Abstraction has 10966 states and 15671 transitions. [2021-07-06 20:41:46,033 INFO L587 BuchiCegarLoop]: Abstraction has 10966 states and 15671 transitions. [2021-07-06 20:41:46,033 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-07-06 20:41:46,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10966 states and 15671 transitions. [2021-07-06 20:41:46,070 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10860 [2021-07-06 20:41:46,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:46,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:46,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,072 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,072 INFO L791 eck$LassoCheckResult]: Stem: 129995#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 129876#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 129854#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 129841#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 129842#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129563#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129564#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129825#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129826#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129728#L431-1 assume !(0 == ~M_E~0); 129729#L591-1 assume !(0 == ~T1_E~0); 129733#L596-1 assume !(0 == ~T2_E~0); 129734#L601-1 assume !(0 == ~T3_E~0); 129800#L606-1 assume !(0 == ~T4_E~0); 129661#L611-1 assume !(0 == ~T5_E~0); 129662#L616-1 assume !(0 == ~E_M~0); 129477#L621-1 assume !(0 == ~E_1~0); 129478#L626-1 assume !(0 == ~E_2~0); 129572#L631-1 assume !(0 == ~E_3~0); 129573#L636-1 assume !(0 == ~E_4~0); 129848#L641-1 assume !(0 == ~E_5~0); 129849#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129936#L284 assume !(1 == ~m_pc~0); 129920#L284-2 is_master_triggered_~__retres1~0 := 0; 129921#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129874#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129875#L735 assume !(0 != activate_threads_~tmp~1); 130066#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129584#L303 assume !(1 == ~t1_pc~0); 129585#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 129639#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130096#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129676#L743 assume !(0 != activate_threads_~tmp___0~0); 129677#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129680#L322 assume !(1 == ~t2_pc~0); 129833#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 129832#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129517#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 129518#L751 assume !(0 != activate_threads_~tmp___1~0); 129843#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 129844#L341 assume !(1 == ~t3_pc~0); 129790#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 129791#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129787#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 129788#L759 assume !(0 != activate_threads_~tmp___2~0); 130007#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130008#L360 assume !(1 == ~t4_pc~0); 130089#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 130087#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129943#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 129944#L767 assume !(0 != activate_threads_~tmp___3~0); 130012#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 129727#L379 assume !(1 == ~t5_pc~0); 129633#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 129708#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 133872#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 133871#L775 assume !(0 != activate_threads_~tmp___4~0); 133870#L775-2 assume !(1 == ~M_E~0); 133869#L659-1 assume !(1 == ~T1_E~0); 133868#L664-1 assume !(1 == ~T2_E~0); 133867#L669-1 assume !(1 == ~T3_E~0); 133866#L674-1 assume !(1 == ~T4_E~0); 133865#L679-1 assume !(1 == ~T5_E~0); 133864#L684-1 assume !(1 == ~E_M~0); 133863#L689-1 assume !(1 == ~E_1~0); 133862#L694-1 assume !(1 == ~E_2~0); 129681#L699-1 assume !(1 == ~E_3~0); 129682#L704-1 assume !(1 == ~E_4~0); 130009#L709-1 assume !(1 == ~E_5~0); 129471#L920-1 [2021-07-06 20:41:46,073 INFO L793 eck$LassoCheckResult]: Loop: 129471#L920-1 assume !false; 133804#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 133799#L566 assume !false; 133794#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133761#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133760#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133759#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 133757#L491 assume !(0 != eval_~tmp~0); 133758#L581 start_simulation_~kernel_st~0 := 2; 134085#L399-1 start_simulation_~kernel_st~0 := 3; 134083#L591-2 assume !(0 == ~M_E~0); 134081#L591-4 assume !(0 == ~T1_E~0); 134079#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134077#L601-3 assume !(0 == ~T3_E~0); 134075#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134073#L611-3 assume !(0 == ~T5_E~0); 134071#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134069#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134067#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134065#L631-3 assume !(0 == ~E_3~0); 134063#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 134061#L641-3 assume !(0 == ~E_5~0); 134059#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134057#L284-21 assume !(1 == ~m_pc~0); 134055#L284-23 is_master_triggered_~__retres1~0 := 0; 134053#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134050#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134048#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 134046#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134045#L303-21 assume !(1 == ~t1_pc~0); 134043#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 134041#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134039#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134038#L743-21 assume !(0 != activate_threads_~tmp___0~0); 134034#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134032#L322-21 assume !(1 == ~t2_pc~0); 130459#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 134030#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134028#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 134026#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 134024#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134022#L341-21 assume !(1 == ~t3_pc~0); 134019#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 134016#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134014#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 134012#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 134010#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134008#L360-21 assume !(1 == ~t4_pc~0); 131454#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 134006#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134004#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 134002#L767-21 assume !(0 != activate_threads_~tmp___3~0); 134000#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 133998#L379-21 assume !(1 == ~t5_pc~0); 133995#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 133992#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 133990#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 133988#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 133986#L775-23 assume !(1 == ~M_E~0); 133980#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133978#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133976#L669-3 assume !(1 == ~T3_E~0); 133974#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133972#L679-3 assume !(1 == ~T5_E~0); 133970#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133968#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133966#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133964#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 133962#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133959#L709-3 assume !(1 == ~E_5~0); 133958#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133956#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133951#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133950#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 133881#L939 assume !(0 == start_simulation_~tmp~3); 133878#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133855#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133851#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133849#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 133847#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 133845#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 133843#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 133818#L952 assume !(0 != start_simulation_~tmp___0~1); 129471#L920-1 [2021-07-06 20:41:46,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,073 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-07-06 20:41:46,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037175661] [2021-07-06 20:41:46,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,075 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,087 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,097 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,121 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:46,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,122 INFO L82 PathProgramCache]: Analyzing trace with hash 559935790, now seen corresponding path program 1 times [2021-07-06 20:41:46,122 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,122 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043801845] [2021-07-06 20:41:46,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,122 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:46,136 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,137 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,142 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,142 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,147 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,147 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,151 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,152 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,156 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,157 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:46,157 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:46,157 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043801845] [2021-07-06 20:41:46,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043801845] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:46,158 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:46,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:46,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192484659] [2021-07-06 20:41:46,158 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:46,158 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:46,159 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:46,159 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:46,159 INFO L87 Difference]: Start difference. First operand 10966 states and 15671 transitions. cyclomatic complexity: 4707 Second operand has 5 states, 5 states have (on average 16.6) internal successors, (83), 5 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:46,383 INFO L93 Difference]: Finished difference Result 19570 states and 27659 transitions. [2021-07-06 20:41:46,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-07-06 20:41:46,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19570 states and 27659 transitions. [2021-07-06 20:41:46,475 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 19448 [2021-07-06 20:41:46,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19570 states to 19570 states and 27659 transitions. [2021-07-06 20:41:46,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19570 [2021-07-06 20:41:46,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19570 [2021-07-06 20:41:46,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19570 states and 27659 transitions. [2021-07-06 20:41:46,573 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:46,573 INFO L681 BuchiCegarLoop]: Abstraction has 19570 states and 27659 transitions. [2021-07-06 20:41:46,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19570 states and 27659 transitions. [2021-07-06 20:41:46,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19570 to 11062. [2021-07-06 20:41:46,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11062 states, 11062 states have (on average 1.4253299584161996) internal successors, (15767), 11061 states have internal predecessors, (15767), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11062 states to 11062 states and 15767 transitions. [2021-07-06 20:41:46,765 INFO L704 BuchiCegarLoop]: Abstraction has 11062 states and 15767 transitions. [2021-07-06 20:41:46,765 INFO L587 BuchiCegarLoop]: Abstraction has 11062 states and 15767 transitions. [2021-07-06 20:41:46,765 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-07-06 20:41:46,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11062 states and 15767 transitions. [2021-07-06 20:41:46,804 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10956 [2021-07-06 20:41:46,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:46,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:46,807 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,807 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,807 INFO L791 eck$LassoCheckResult]: Stem: 160551#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 160426#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 160404#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 160391#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 160392#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160113#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160114#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 160375#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160376#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160281#L431-1 assume !(0 == ~M_E~0); 160282#L591-1 assume !(0 == ~T1_E~0); 160286#L596-1 assume !(0 == ~T2_E~0); 160287#L601-1 assume !(0 == ~T3_E~0); 160353#L606-1 assume !(0 == ~T4_E~0); 160217#L611-1 assume !(0 == ~T5_E~0); 160218#L616-1 assume !(0 == ~E_M~0); 160029#L621-1 assume !(0 == ~E_1~0); 160030#L626-1 assume !(0 == ~E_2~0); 160124#L631-1 assume !(0 == ~E_3~0); 160125#L636-1 assume !(0 == ~E_4~0); 160398#L641-1 assume !(0 == ~E_5~0); 160399#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 160497#L284 assume !(1 == ~m_pc~0); 160481#L284-2 is_master_triggered_~__retres1~0 := 0; 160482#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 160424#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 160425#L735 assume !(0 != activate_threads_~tmp~1); 160624#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 160139#L303 assume !(1 == ~t1_pc~0); 160140#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 160196#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 160658#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 160231#L743 assume !(0 != activate_threads_~tmp___0~0); 160232#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 160236#L322 assume !(1 == ~t2_pc~0); 160383#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 160382#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 160069#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 160070#L751 assume !(0 != activate_threads_~tmp___1~0); 160393#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 160394#L341 assume !(1 == ~t3_pc~0); 160343#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 160344#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 160340#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 160341#L759 assume !(0 != activate_threads_~tmp___2~0); 160563#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 160564#L360 assume !(1 == ~t4_pc~0); 160650#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 160648#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 160504#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 160505#L767 assume !(0 != activate_threads_~tmp___3~0); 160569#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 160280#L379 assume !(1 == ~t5_pc~0); 160190#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 160260#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 160184#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 160185#L775 assume !(0 != activate_threads_~tmp___4~0); 160045#L775-2 assume !(1 == ~M_E~0); 160046#L659-1 assume !(1 == ~T1_E~0); 160122#L664-1 assume !(1 == ~T2_E~0); 160123#L669-1 assume !(1 == ~T3_E~0); 160396#L674-1 assume !(1 == ~T4_E~0); 160397#L679-1 assume !(1 == ~T5_E~0); 160297#L684-1 assume !(1 == ~E_M~0); 160298#L689-1 assume !(1 == ~E_1~0); 160539#L694-1 assume !(1 == ~E_2~0); 160540#L699-1 assume !(1 == ~E_3~0); 160565#L704-1 assume !(1 == ~E_4~0); 160566#L709-1 assume !(1 == ~E_5~0); 160023#L920-1 [2021-07-06 20:41:46,809 INFO L793 eck$LassoCheckResult]: Loop: 160023#L920-1 assume !false; 169744#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 169742#L566 assume !false; 169407#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 168514#L444 assume !(0 == ~m_st~0); 168515#L448 assume !(0 == ~t1_st~0); 168518#L452 assume !(0 == ~t2_st~0); 168520#L456 assume !(0 == ~t3_st~0); 168516#L460 assume !(0 == ~t4_st~0); 168517#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 168519#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 170778#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 170775#L491 assume !(0 != eval_~tmp~0); 170776#L581 start_simulation_~kernel_st~0 := 2; 170827#L399-1 start_simulation_~kernel_st~0 := 3; 160652#L591-2 assume !(0 == ~M_E~0); 160653#L591-4 assume !(0 == ~T1_E~0); 160654#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 170825#L601-3 assume !(0 == ~T3_E~0); 170824#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 170823#L611-3 assume !(0 == ~T5_E~0); 160561#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 160038#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 160039#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 160091#L631-3 assume !(0 == ~E_3~0); 160092#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 160386#L641-3 assume !(0 == ~E_5~0); 160387#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 160454#L284-21 assume !(1 == ~m_pc~0); 160452#L284-23 is_master_triggered_~__retres1~0 := 0; 160453#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 160435#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 160436#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 160470#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 160471#L303-21 assume !(1 == ~t1_pc~0); 160574#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 160601#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 160615#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 160616#L743-21 assume !(0 != activate_threads_~tmp___0~0); 160617#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 160120#L322-21 assume !(1 == ~t2_pc~0); 160121#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 160126#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 160059#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 160060#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 170600#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 170599#L341-21 assume 1 == ~t3_pc~0; 170598#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 170596#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 170595#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 170594#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 170593#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 170592#L360-21 assume !(1 == ~t4_pc~0); 169045#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 160644#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 160492#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 160493#L767-21 assume !(0 != activate_threads_~tmp___3~0); 160632#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 160633#L379-21 assume !(1 == ~t5_pc~0); 170587#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 160270#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 160170#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 160171#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 160256#L775-23 assume !(1 == ~M_E~0); 169487#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 160127#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 160128#L669-3 assume !(1 == ~T3_E~0); 160630#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 170582#L679-3 assume !(1 == ~T5_E~0); 170581#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 160600#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 160352#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 160215#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 160216#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 160558#L709-3 assume !(1 == ~E_5~0); 160028#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 160459#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 168523#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 168524#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 166683#L939 assume !(0 == start_simulation_~tmp~3); 166684#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 169858#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 169854#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 169851#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 169849#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 169847#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 169845#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 169844#L952 assume !(0 != start_simulation_~tmp___0~1); 160023#L920-1 [2021-07-06 20:41:46,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,809 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-07-06 20:41:46,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,810 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90740209] [2021-07-06 20:41:46,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,810 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,819 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,827 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,842 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:46,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,843 INFO L82 PathProgramCache]: Analyzing trace with hash 2037665640, now seen corresponding path program 1 times [2021-07-06 20:41:46,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,844 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310216570] [2021-07-06 20:41:46,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,844 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:46,864 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,865 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,869 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,870 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 7 [2021-07-06 20:41:46,875 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,876 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 7 [2021-07-06 20:41:46,888 INFO L142 QuantifierPusher]: treesize reduction 9, result has 50.0 percent of original size [2021-07-06 20:41:46,889 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 9 [2021-07-06 20:41:46,902 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,902 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:46,903 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:46,903 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310216570] [2021-07-06 20:41:46,903 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310216570] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:46,903 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:46,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:46,904 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460847428] [2021-07-06 20:41:46,904 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:46,904 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:46,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:46,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:46,905 INFO L87 Difference]: Start difference. First operand 11062 states and 15767 transitions. cyclomatic complexity: 4707 Second operand has 5 states, 5 states have (on average 17.6) internal successors, (88), 5 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:47,143 INFO L93 Difference]: Finished difference Result 22034 states and 31186 transitions. [2021-07-06 20:41:47,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-07-06 20:41:47,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22034 states and 31186 transitions. [2021-07-06 20:41:47,381 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 21928 [2021-07-06 20:41:47,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22034 states to 22034 states and 31186 transitions. [2021-07-06 20:41:47,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22034 [2021-07-06 20:41:47,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22034 [2021-07-06 20:41:47,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22034 states and 31186 transitions. [2021-07-06 20:41:47,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:47,507 INFO L681 BuchiCegarLoop]: Abstraction has 22034 states and 31186 transitions. [2021-07-06 20:41:47,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22034 states and 31186 transitions. [2021-07-06 20:41:47,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22034 to 11350. [2021-07-06 20:41:47,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11350 states, 11350 states have (on average 1.4074008810572687) internal successors, (15974), 11349 states have internal predecessors, (15974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11350 states to 11350 states and 15974 transitions. [2021-07-06 20:41:47,708 INFO L704 BuchiCegarLoop]: Abstraction has 11350 states and 15974 transitions. [2021-07-06 20:41:47,708 INFO L587 BuchiCegarLoop]: Abstraction has 11350 states and 15974 transitions. [2021-07-06 20:41:47,708 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-07-06 20:41:47,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11350 states and 15974 transitions. [2021-07-06 20:41:47,746 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11244 [2021-07-06 20:41:47,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:47,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:47,749 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:47,749 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:47,749 INFO L791 eck$LassoCheckResult]: Stem: 193709#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 193552#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 193530#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 193517#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 193518#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 193220#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 193221#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 193498#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193499#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 193390#L431-1 assume !(0 == ~M_E~0); 193391#L591-1 assume !(0 == ~T1_E~0); 193395#L596-1 assume !(0 == ~T2_E~0); 193396#L601-1 assume !(0 == ~T3_E~0); 193464#L606-1 assume !(0 == ~T4_E~0); 193324#L611-1 assume !(0 == ~T5_E~0); 193325#L616-1 assume !(0 == ~E_M~0); 193138#L621-1 assume !(0 == ~E_1~0); 193139#L626-1 assume !(0 == ~E_2~0); 193231#L631-1 assume !(0 == ~E_3~0); 193232#L636-1 assume !(0 == ~E_4~0); 193524#L641-1 assume !(0 == ~E_5~0); 193525#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 193631#L284 assume !(1 == ~m_pc~0); 193612#L284-2 is_master_triggered_~__retres1~0 := 0; 193613#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 193550#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 193551#L735 assume !(0 != activate_threads_~tmp~1); 193789#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 193246#L303 assume !(1 == ~t1_pc~0); 193247#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 193304#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 193830#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 193338#L743 assume !(0 != activate_threads_~tmp___0~0); 193339#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 193341#L322 assume !(1 == ~t2_pc~0); 193506#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 193505#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 193178#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 193179#L751 assume !(0 != activate_threads_~tmp___1~0); 193519#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 193520#L341 assume !(1 == ~t3_pc~0); 193454#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 193455#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 193451#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 193452#L759 assume !(0 != activate_threads_~tmp___2~0); 193720#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 193721#L360 assume !(1 == ~t4_pc~0); 193821#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 193819#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 193639#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 193640#L767 assume !(0 != activate_threads_~tmp___3~0); 193726#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 193389#L379 assume !(1 == ~t5_pc~0); 193298#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 193371#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 193292#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 193293#L775 assume !(0 != activate_threads_~tmp___4~0); 193154#L775-2 assume !(1 == ~M_E~0); 193155#L659-1 assume !(1 == ~T1_E~0); 193229#L664-1 assume !(1 == ~T2_E~0); 193230#L669-1 assume !(1 == ~T3_E~0); 193522#L674-1 assume !(1 == ~T4_E~0); 193523#L679-1 assume !(1 == ~T5_E~0); 193407#L684-1 assume !(1 == ~E_M~0); 193408#L689-1 assume !(1 == ~E_1~0); 193689#L694-1 assume !(1 == ~E_2~0); 193690#L699-1 assume !(1 == ~E_3~0); 193722#L704-1 assume !(1 == ~E_4~0); 193723#L709-1 assume !(1 == ~E_5~0); 193132#L920-1 [2021-07-06 20:41:47,750 INFO L793 eck$LassoCheckResult]: Loop: 193132#L920-1 assume !false; 195205#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 195206#L566 assume !false; 195201#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 195202#L444 assume !(0 == ~m_st~0); 195193#L448 assume !(0 == ~t1_st~0); 195194#L452 assume !(0 == ~t2_st~0); 195199#L456 assume !(0 == ~t3_st~0); 195200#L460 assume !(0 == ~t4_st~0); 195195#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 195196#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 198441#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 198439#L491 assume !(0 != eval_~tmp~0); 198437#L581 start_simulation_~kernel_st~0 := 2; 198435#L399-1 start_simulation_~kernel_st~0 := 3; 198433#L591-2 assume !(0 == ~M_E~0); 198429#L591-4 assume !(0 == ~T1_E~0); 198427#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 198425#L601-3 assume !(0 == ~T3_E~0); 198423#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 198421#L611-3 assume !(0 == ~T5_E~0); 198418#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 198416#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 198414#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 198412#L631-3 assume !(0 == ~E_3~0); 198410#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 198408#L641-3 assume !(0 == ~E_5~0); 198406#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 198404#L284-21 assume !(1 == ~m_pc~0); 198402#L284-23 is_master_triggered_~__retres1~0 := 0; 198400#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 198398#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 198395#L735-21 assume !(0 != activate_threads_~tmp~1); 198394#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 198391#L303-21 assume !(1 == ~t1_pc~0); 198389#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 198388#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 198387#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 198386#L743-21 assume !(0 != activate_threads_~tmp___0~0); 198378#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 198376#L322-21 assume !(1 == ~t2_pc~0); 198223#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 198373#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 198371#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 198369#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 198367#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 198365#L341-21 assume !(1 == ~t3_pc~0); 195728#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 195725#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 195721#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 195636#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 195553#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 195545#L360-21 assume !(1 == ~t4_pc~0); 195543#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 195541#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 195539#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 195537#L767-21 assume !(0 != activate_threads_~tmp___3~0); 195535#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 195533#L379-21 assume !(1 == ~t5_pc~0); 195527#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 195525#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 195523#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 195521#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 195519#L775-23 assume !(1 == ~M_E~0); 195509#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 195510#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 195493#L669-3 assume !(1 == ~T3_E~0); 195494#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 195478#L679-3 assume !(1 == ~T5_E~0); 195479#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 197549#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 197546#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 197544#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 197542#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 197531#L709-3 assume !(1 == ~E_5~0); 195451#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 195452#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 197520#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 195417#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 195418#L939 assume !(0 == start_simulation_~tmp~3); 197458#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 197448#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 197444#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 197443#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 197442#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 197441#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 197440#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 197439#L952 assume !(0 != start_simulation_~tmp___0~1); 193132#L920-1 [2021-07-06 20:41:47,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:47,750 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 4 times [2021-07-06 20:41:47,750 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:47,751 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504308654] [2021-07-06 20:41:47,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:47,751 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,758 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,772 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,789 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:47,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:47,790 INFO L82 PathProgramCache]: Analyzing trace with hash -77174011, now seen corresponding path program 1 times [2021-07-06 20:41:47,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:47,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1900402151] [2021-07-06 20:41:47,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:47,790 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:47,807 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,808 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,809 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,809 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:47,812 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,813 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:47,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:47,813 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1900402151] [2021-07-06 20:41:47,814 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1900402151] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:47,814 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:47,814 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:47,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912948753] [2021-07-06 20:41:47,815 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:47,815 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:47,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:47,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:47,816 INFO L87 Difference]: Start difference. First operand 11350 states and 15974 transitions. cyclomatic complexity: 4626 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:47,910 INFO L93 Difference]: Finished difference Result 18281 states and 25445 transitions. [2021-07-06 20:41:47,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:47,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18281 states and 25445 transitions. [2021-07-06 20:41:48,008 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18181 [2021-07-06 20:41:48,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18281 states to 18281 states and 25445 transitions. [2021-07-06 20:41:48,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18281 [2021-07-06 20:41:48,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18281 [2021-07-06 20:41:48,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18281 states and 25445 transitions. [2021-07-06 20:41:48,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:48,105 INFO L681 BuchiCegarLoop]: Abstraction has 18281 states and 25445 transitions. [2021-07-06 20:41:48,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18281 states and 25445 transitions. [2021-07-06 20:41:48,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18281 to 17673. [2021-07-06 20:41:48,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17673 states, 17673 states have (on average 1.39404741696373) internal successors, (24637), 17672 states have internal predecessors, (24637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:48,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17673 states to 17673 states and 24637 transitions. [2021-07-06 20:41:48,454 INFO L704 BuchiCegarLoop]: Abstraction has 17673 states and 24637 transitions. [2021-07-06 20:41:48,454 INFO L587 BuchiCegarLoop]: Abstraction has 17673 states and 24637 transitions. [2021-07-06 20:41:48,455 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-07-06 20:41:48,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17673 states and 24637 transitions. [2021-07-06 20:41:48,512 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17573 [2021-07-06 20:41:48,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:48,513 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:48,514 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:48,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:48,514 INFO L791 eck$LassoCheckResult]: Stem: 223337#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 223201#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 223179#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 223166#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 223167#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 222858#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222859#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223141#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223142#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223040#L431-1 assume !(0 == ~M_E~0); 223041#L591-1 assume !(0 == ~T1_E~0); 223045#L596-1 assume !(0 == ~T2_E~0); 223046#L601-1 assume !(0 == ~T3_E~0); 223113#L606-1 assume !(0 == ~T4_E~0); 222961#L611-1 assume !(0 == ~T5_E~0); 222962#L616-1 assume !(0 == ~E_M~0); 222776#L621-1 assume !(0 == ~E_1~0); 222777#L626-1 assume !(0 == ~E_2~0); 222868#L631-1 assume !(0 == ~E_3~0); 222869#L636-1 assume !(0 == ~E_4~0); 223173#L641-1 assume !(0 == ~E_5~0); 223174#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 223274#L284 assume !(1 == ~m_pc~0); 223255#L284-2 is_master_triggered_~__retres1~0 := 0; 223256#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 223199#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 223200#L735 assume !(0 != activate_threads_~tmp~1); 223426#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 222883#L303 assume !(1 == ~t1_pc~0); 222884#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 222939#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 223463#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 222977#L743 assume !(0 != activate_threads_~tmp___0~0); 222978#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 222984#L322 assume !(1 == ~t2_pc~0); 223149#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 223148#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 222815#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 222816#L751 assume !(0 != activate_threads_~tmp___1~0); 223168#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 223169#L341 assume !(1 == ~t3_pc~0); 223103#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 223104#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 223100#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 223101#L759 assume !(0 != activate_threads_~tmp___2~0); 223352#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 223353#L360 assume !(1 == ~t4_pc~0); 223453#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 223451#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 223282#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 223283#L767 assume !(0 != activate_threads_~tmp___3~0); 223358#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 223039#L379 assume !(1 == ~t5_pc~0); 222933#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 223015#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 222927#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 222928#L775 assume !(0 != activate_threads_~tmp___4~0); 229033#L775-2 assume !(1 == ~M_E~0); 229031#L659-1 assume !(1 == ~T1_E~0); 229029#L664-1 assume !(1 == ~T2_E~0); 229027#L669-1 assume !(1 == ~T3_E~0); 223171#L674-1 assume !(1 == ~T4_E~0); 223172#L679-1 assume !(1 == ~T5_E~0); 223057#L684-1 assume !(1 == ~E_M~0); 223058#L689-1 assume !(1 == ~E_1~0); 229007#L694-1 assume !(1 == ~E_2~0); 229005#L699-1 assume !(1 == ~E_3~0); 223354#L704-1 assume !(1 == ~E_4~0); 223355#L709-1 assume !(1 == ~E_5~0); 222769#L920-1 assume !false; 228962#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 228956#L566 [2021-07-06 20:41:48,514 INFO L793 eck$LassoCheckResult]: Loop: 228956#L566 assume !false; 228950#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 228945#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 228941#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 228936#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 228933#L491 assume 0 != eval_~tmp~0; 228923#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 228915#L499 assume !(0 != eval_~tmp_ndt_1~0); 228905#L496 assume !(0 == ~t1_st~0); 228899#L510 assume !(0 == ~t2_st~0); 228892#L524 assume !(0 == ~t3_st~0); 228975#L538 assume !(0 == ~t4_st~0); 228966#L552 assume !(0 == ~t5_st~0); 228956#L566 [2021-07-06 20:41:48,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,515 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-07-06 20:41:48,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,515 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179889673] [2021-07-06 20:41:48,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,515 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,526 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,534 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,552 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:48,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,554 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 1 times [2021-07-06 20:41:48,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629381792] [2021-07-06 20:41:48,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,554 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,557 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,559 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,561 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:48,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,562 INFO L82 PathProgramCache]: Analyzing trace with hash 1743073375, now seen corresponding path program 1 times [2021-07-06 20:41:48,562 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,562 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501329973] [2021-07-06 20:41:48,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,563 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:48,583 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,583 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:48,584 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,584 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:48,587 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,591 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:48,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:48,591 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:48,591 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501329973] [2021-07-06 20:41:48,591 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501329973] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:48,592 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:48,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:48,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [384862466] [2021-07-06 20:41:48,639 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,643 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 39 [2021-07-06 20:41:48,691 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:48,691 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:48,691 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:48,692 INFO L87 Difference]: Start difference. First operand 17673 states and 24637 transitions. cyclomatic complexity: 6967 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:48,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:48,833 INFO L93 Difference]: Finished difference Result 32613 states and 45236 transitions. [2021-07-06 20:41:48,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:48,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32613 states and 45236 transitions. [2021-07-06 20:41:48,991 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 32418 [2021-07-06 20:41:49,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32613 states to 32613 states and 45236 transitions. [2021-07-06 20:41:49,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32613 [2021-07-06 20:41:49,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32613 [2021-07-06 20:41:49,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32613 states and 45236 transitions. [2021-07-06 20:41:49,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:49,335 INFO L681 BuchiCegarLoop]: Abstraction has 32613 states and 45236 transitions. [2021-07-06 20:41:49,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32613 states and 45236 transitions. [2021-07-06 20:41:49,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32613 to 30933. [2021-07-06 20:41:49,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30933 states, 30933 states have (on average 1.390877056864837) internal successors, (43024), 30932 states have internal predecessors, (43024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:49,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30933 states to 30933 states and 43024 transitions. [2021-07-06 20:41:49,787 INFO L704 BuchiCegarLoop]: Abstraction has 30933 states and 43024 transitions. [2021-07-06 20:41:49,787 INFO L587 BuchiCegarLoop]: Abstraction has 30933 states and 43024 transitions. [2021-07-06 20:41:49,787 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-07-06 20:41:49,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30933 states and 43024 transitions. [2021-07-06 20:41:49,866 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-07-06 20:41:49,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:49,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:49,867 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:49,867 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:49,867 INFO L791 eck$LassoCheckResult]: Stem: 273623#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 273482#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 273458#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 273445#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 273446#L406-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 273513#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273724#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 273725#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273755#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273756#L431-1 assume !(0 == ~M_E~0); 273772#L591-1 assume !(0 == ~T1_E~0); 273773#L596-1 assume !(0 == ~T2_E~0); 273693#L601-1 assume !(0 == ~T3_E~0); 273694#L606-1 assume !(0 == ~T4_E~0); 273256#L611-1 assume !(0 == ~T5_E~0); 273257#L616-1 assume !(0 == ~E_M~0); 273069#L621-1 assume !(0 == ~E_1~0); 273070#L626-1 assume !(0 == ~E_2~0); 273161#L631-1 assume !(0 == ~E_3~0); 273162#L636-1 assume !(0 == ~E_4~0); 273452#L641-1 assume !(0 == ~E_5~0); 273453#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273561#L284 assume !(1 == ~m_pc~0); 273562#L284-2 is_master_triggered_~__retres1~0 := 0; 273563#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273564#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 273738#L735 assume !(0 != activate_threads_~tmp~1); 273739#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 273178#L303 assume !(1 == ~t1_pc~0); 273179#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 273244#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273245#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 273270#L743 assume !(0 != activate_threads_~tmp___0~0); 273271#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 273431#L322 assume !(1 == ~t2_pc~0); 273432#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 273429#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 273430#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 273461#L751 assume !(0 != activate_threads_~tmp___1~0); 273462#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273632#L341 assume !(1 == ~t3_pc~0); 273633#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 273630#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 273631#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 273645#L759 assume !(0 != activate_threads_~tmp___2~0); 273646#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 273762#L360 assume !(1 == ~t4_pc~0); 273763#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 273759#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 273760#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 273651#L767 assume !(0 != activate_threads_~tmp___3~0); 273652#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 273324#L379 assume !(1 == ~t5_pc~0); 273325#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 287741#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 287737#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 287732#L775 assume !(0 != activate_threads_~tmp___4~0); 287725#L775-2 assume !(1 == ~M_E~0); 287721#L659-1 assume !(1 == ~T1_E~0); 287715#L664-1 assume !(1 == ~T2_E~0); 287707#L669-1 assume !(1 == ~T3_E~0); 287700#L674-1 assume !(1 == ~T4_E~0); 287694#L679-1 assume !(1 == ~T5_E~0); 287687#L684-1 assume !(1 == ~E_M~0); 287662#L689-1 assume !(1 == ~E_1~0); 287651#L694-1 assume !(1 == ~E_2~0); 287649#L699-1 assume !(1 == ~E_3~0); 287647#L704-1 assume !(1 == ~E_4~0); 287619#L709-1 assume !(1 == ~E_5~0); 287610#L920-1 assume !false; 287590#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 287582#L566 [2021-07-06 20:41:49,867 INFO L793 eck$LassoCheckResult]: Loop: 287582#L566 assume !false; 287575#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 287566#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 287560#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 287555#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 287551#L491 assume 0 != eval_~tmp~0; 287545#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 287537#L499 assume !(0 != eval_~tmp_ndt_1~0); 287529#L496 assume !(0 == ~t1_st~0); 287523#L510 assume !(0 == ~t2_st~0); 287518#L524 assume !(0 == ~t3_st~0); 287613#L538 assume !(0 == ~t4_st~0); 287594#L552 assume !(0 == ~t5_st~0); 287582#L566 [2021-07-06 20:41:49,868 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:49,868 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-07-06 20:41:49,868 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:49,868 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463277815] [2021-07-06 20:41:49,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:49,868 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:49,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:49,883 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,883 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:49,885 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,885 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:49,888 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,889 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:49,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:49,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:49,889 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463277815] [2021-07-06 20:41:49,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463277815] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:49,889 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:49,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:49,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975040500] [2021-07-06 20:41:49,890 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:49,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:49,890 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 2 times [2021-07-06 20:41:49,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:49,891 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026440886] [2021-07-06 20:41:49,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:49,891 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:49,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:49,894 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:49,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:49,895 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:49,896 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:49,943 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,944 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 39 [2021-07-06 20:41:49,965 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:49,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:49,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:49,966 INFO L87 Difference]: Start difference. First operand 30933 states and 43024 transitions. cyclomatic complexity: 12094 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:50,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:50,054 INFO L93 Difference]: Finished difference Result 30846 states and 42897 transitions. [2021-07-06 20:41:50,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:50,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30846 states and 42897 transitions. [2021-07-06 20:41:50,200 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-07-06 20:41:50,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30846 states to 30846 states and 42897 transitions. [2021-07-06 20:41:50,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30846 [2021-07-06 20:41:50,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30846 [2021-07-06 20:41:50,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30846 states and 42897 transitions. [2021-07-06 20:41:50,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:50,350 INFO L681 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-07-06 20:41:50,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30846 states and 42897 transitions. [2021-07-06 20:41:50,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30846 to 30846. [2021-07-06 20:41:50,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30846 states, 30846 states have (on average 1.3906827465473643) internal successors, (42897), 30845 states have internal predecessors, (42897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:50,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30846 states to 30846 states and 42897 transitions. [2021-07-06 20:41:50,913 INFO L704 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-07-06 20:41:50,913 INFO L587 BuchiCegarLoop]: Abstraction has 30846 states and 42897 transitions. [2021-07-06 20:41:50,913 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-07-06 20:41:50,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30846 states and 42897 transitions. [2021-07-06 20:41:51,025 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30738 [2021-07-06 20:41:51,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:51,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:51,026 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:51,026 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:51,026 INFO L791 eck$LassoCheckResult]: Stem: 335403#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 335262#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 335240#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 335227#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 335228#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 334937#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 334938#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335210#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335211#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335107#L431-1 assume !(0 == ~M_E~0); 335108#L591-1 assume !(0 == ~T1_E~0); 335112#L596-1 assume !(0 == ~T2_E~0); 335113#L601-1 assume !(0 == ~T3_E~0); 335181#L606-1 assume !(0 == ~T4_E~0); 335038#L611-1 assume !(0 == ~T5_E~0); 335039#L616-1 assume !(0 == ~E_M~0); 334854#L621-1 assume !(0 == ~E_1~0); 334855#L626-1 assume !(0 == ~E_2~0); 334947#L631-1 assume !(0 == ~E_3~0); 334948#L636-1 assume !(0 == ~E_4~0); 335234#L641-1 assume !(0 == ~E_5~0); 335235#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 335342#L284 assume !(1 == ~m_pc~0); 335324#L284-2 is_master_triggered_~__retres1~0 := 0; 335325#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 335260#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 335261#L735 assume !(0 != activate_threads_~tmp~1); 335502#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 334963#L303 assume !(1 == ~t1_pc~0); 334964#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 335017#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 335026#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 335052#L743 assume !(0 != activate_threads_~tmp___0~0); 335053#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 335056#L322 assume !(1 == ~t2_pc~0); 335216#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 335215#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 334893#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 334894#L751 assume !(0 != activate_threads_~tmp___1~0); 335229#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 335230#L341 assume !(1 == ~t3_pc~0); 335171#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 335172#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 335168#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 335169#L759 assume !(0 != activate_threads_~tmp___2~0); 335419#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 335420#L360 assume !(1 == ~t4_pc~0); 335527#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 335525#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 335352#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 335353#L767 assume !(0 != activate_threads_~tmp___3~0); 335423#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 335106#L379 assume !(1 == ~t5_pc~0); 335013#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 335084#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 353479#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 353478#L775 assume !(0 != activate_threads_~tmp___4~0); 353477#L775-2 assume !(1 == ~M_E~0); 353476#L659-1 assume !(1 == ~T1_E~0); 353475#L664-1 assume !(1 == ~T2_E~0); 353474#L669-1 assume !(1 == ~T3_E~0); 353473#L674-1 assume !(1 == ~T4_E~0); 353472#L679-1 assume !(1 == ~T5_E~0); 353471#L684-1 assume !(1 == ~E_M~0); 353470#L689-1 assume !(1 == ~E_1~0); 353469#L694-1 assume !(1 == ~E_2~0); 353468#L699-1 assume !(1 == ~E_3~0); 353467#L704-1 assume !(1 == ~E_4~0); 353466#L709-1 assume !(1 == ~E_5~0); 334850#L920-1 assume !false; 353442#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 353440#L566 [2021-07-06 20:41:51,026 INFO L793 eck$LassoCheckResult]: Loop: 353440#L566 assume !false; 353438#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 353435#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 353433#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 353432#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 353430#L491 assume 0 != eval_~tmp~0; 353427#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 353425#L499 assume !(0 != eval_~tmp_ndt_1~0); 351748#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 351745#L513 assume !(0 != eval_~tmp_ndt_2~0); 351743#L510 assume !(0 == ~t2_st~0); 351741#L524 assume !(0 == ~t3_st~0); 353448#L538 assume !(0 == ~t4_st~0); 353446#L552 assume !(0 == ~t5_st~0); 353440#L566 [2021-07-06 20:41:51,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:51,027 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-07-06 20:41:51,027 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:51,027 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095545783] [2021-07-06 20:41:51,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:51,028 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:51,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:51,035 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:51,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:51,042 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:51,054 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:51,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:51,055 INFO L82 PathProgramCache]: Analyzing trace with hash 706455497, now seen corresponding path program 1 times [2021-07-06 20:41:51,055 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:51,056 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844888808] [2021-07-06 20:41:51,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:51,056 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:51,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:51,059 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:51,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:51,061 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:51,062 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:51,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:51,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1606943435, now seen corresponding path program 1 times [2021-07-06 20:41:51,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:51,063 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070034021] [2021-07-06 20:41:51,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:51,063 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:51,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:51,081 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:51,082 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:51,082 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:51,083 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:51,086 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:51,087 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:51,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:51,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:51,087 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070034021] [2021-07-06 20:41:51,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070034021] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:51,088 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:51,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:51,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249216270] [2021-07-06 20:41:51,295 WARN L205 SmtUtils]: Spent 206.00 ms on a formula simplification. DAG size of input: 35 DAG size of output: 33 [2021-07-06 20:41:51,299 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:51,300 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 44 [2021-07-06 20:41:51,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:51,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:51,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:51,327 INFO L87 Difference]: Start difference. First operand 30846 states and 42897 transitions. cyclomatic complexity: 12054 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:51,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:51,534 INFO L93 Difference]: Finished difference Result 57752 states and 80047 transitions. [2021-07-06 20:41:51,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:51,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57752 states and 80047 transitions. [2021-07-06 20:41:51,785 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 57628 [2021-07-06 20:41:52,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57752 states to 57752 states and 80047 transitions. [2021-07-06 20:41:52,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57752 [2021-07-06 20:41:52,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57752 [2021-07-06 20:41:52,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57752 states and 80047 transitions. [2021-07-06 20:41:52,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:52,251 INFO L681 BuchiCegarLoop]: Abstraction has 57752 states and 80047 transitions. [2021-07-06 20:41:52,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57752 states and 80047 transitions. [2021-07-06 20:41:52,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57752 to 56436. [2021-07-06 20:41:52,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56436 states, 56436 states have (on average 1.3876072010773266) internal successors, (78311), 56435 states have internal predecessors, (78311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:52,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56436 states to 56436 states and 78311 transitions. [2021-07-06 20:41:52,932 INFO L704 BuchiCegarLoop]: Abstraction has 56436 states and 78311 transitions. [2021-07-06 20:41:52,932 INFO L587 BuchiCegarLoop]: Abstraction has 56436 states and 78311 transitions. [2021-07-06 20:41:52,932 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-07-06 20:41:52,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56436 states and 78311 transitions. [2021-07-06 20:41:53,100 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56312 [2021-07-06 20:41:53,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:53,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:53,101 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:53,102 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:53,102 INFO L791 eck$LassoCheckResult]: Stem: 424020#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 423880#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 423858#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 423845#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 423846#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 423545#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 423546#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 423824#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 423825#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 423717#L431-1 assume !(0 == ~M_E~0); 423718#L591-1 assume !(0 == ~T1_E~0); 423721#L596-1 assume !(0 == ~T2_E~0); 423722#L601-1 assume !(0 == ~T3_E~0); 423796#L606-1 assume !(0 == ~T4_E~0); 423645#L611-1 assume !(0 == ~T5_E~0); 423646#L616-1 assume !(0 == ~E_M~0); 423460#L621-1 assume !(0 == ~E_1~0); 423461#L626-1 assume !(0 == ~E_2~0); 423553#L631-1 assume !(0 == ~E_3~0); 423554#L636-1 assume !(0 == ~E_4~0); 423852#L641-1 assume !(0 == ~E_5~0); 423853#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 423956#L284 assume !(1 == ~m_pc~0); 423938#L284-2 is_master_triggered_~__retres1~0 := 0; 423939#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 423878#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 423879#L735 assume !(0 != activate_threads_~tmp~1); 424107#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 423569#L303 assume !(1 == ~t1_pc~0); 423570#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 423625#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 423635#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 423658#L743 assume !(0 != activate_threads_~tmp___0~0); 423659#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 423661#L322 assume !(1 == ~t2_pc~0); 423830#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 423829#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 423500#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 423501#L751 assume !(0 != activate_threads_~tmp___1~0); 423847#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 423848#L341 assume !(1 == ~t3_pc~0); 423784#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 423785#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 423781#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 423782#L759 assume !(0 != activate_threads_~tmp___2~0); 424034#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 424035#L360 assume !(1 == ~t4_pc~0); 424141#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 424139#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 423968#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 423969#L767 assume !(0 != activate_threads_~tmp___3~0); 424040#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 423715#L379 assume !(1 == ~t5_pc~0); 423621#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 423694#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 423613#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 423614#L775 assume !(0 != activate_threads_~tmp___4~0); 423476#L775-2 assume !(1 == ~M_E~0); 423477#L659-1 assume !(1 == ~T1_E~0); 423551#L664-1 assume !(1 == ~T2_E~0); 423552#L669-1 assume !(1 == ~T3_E~0); 423850#L674-1 assume !(1 == ~T4_E~0); 423851#L679-1 assume !(1 == ~T5_E~0); 423734#L684-1 assume !(1 == ~E_M~0); 423735#L689-1 assume !(1 == ~E_1~0); 424005#L694-1 assume !(1 == ~E_2~0); 424006#L699-1 assume !(1 == ~E_3~0); 424036#L704-1 assume !(1 == ~E_4~0); 424037#L709-1 assume !(1 == ~E_5~0); 423456#L920-1 assume !false; 438731#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 438729#L566 [2021-07-06 20:41:53,102 INFO L793 eck$LassoCheckResult]: Loop: 438729#L566 assume !false; 438728#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 438724#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 438720#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 438717#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 438714#L491 assume 0 != eval_~tmp~0; 438711#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 438708#L499 assume !(0 != eval_~tmp_ndt_1~0); 435095#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 435092#L513 assume !(0 != eval_~tmp_ndt_2~0); 430104#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 430101#L527 assume !(0 != eval_~tmp_ndt_3~0); 430102#L524 assume !(0 == ~t3_st~0); 438738#L538 assume !(0 == ~t4_st~0); 438735#L552 assume !(0 == ~t5_st~0); 438729#L566 [2021-07-06 20:41:53,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:53,103 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-07-06 20:41:53,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:53,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485546070] [2021-07-06 20:41:53,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:53,103 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:53,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:53,110 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:53,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:53,117 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:53,341 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:53,341 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:53,342 INFO L82 PathProgramCache]: Analyzing trace with hash 258069692, now seen corresponding path program 1 times [2021-07-06 20:41:53,342 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:53,342 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722486526] [2021-07-06 20:41:53,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:53,342 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:53,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:53,356 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:53,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:53,359 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:53,360 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:53,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:53,361 INFO L82 PathProgramCache]: Analyzing trace with hash -1891575302, now seen corresponding path program 1 times [2021-07-06 20:41:53,361 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:53,361 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040262565] [2021-07-06 20:41:53,362 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:53,362 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:53,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:53,380 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:53,381 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:53,382 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:53,383 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:53,387 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:53,387 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:53,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:53,388 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:53,388 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040262565] [2021-07-06 20:41:53,388 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040262565] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:53,389 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:53,389 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:53,389 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126554940] [2021-07-06 20:41:53,451 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:53,453 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 49 [2021-07-06 20:41:53,490 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:53,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:53,491 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:53,491 INFO L87 Difference]: Start difference. First operand 56436 states and 78311 transitions. cyclomatic complexity: 21878 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:53,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:53,860 INFO L93 Difference]: Finished difference Result 101612 states and 140795 transitions. [2021-07-06 20:41:53,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:53,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101612 states and 140795 transitions. [2021-07-06 20:41:54,352 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 101456 [2021-07-06 20:41:54,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101612 states to 101612 states and 140795 transitions. [2021-07-06 20:41:54,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101612 [2021-07-06 20:41:54,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101612 [2021-07-06 20:41:54,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101612 states and 140795 transitions. [2021-07-06 20:41:55,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:55,041 INFO L681 BuchiCegarLoop]: Abstraction has 101612 states and 140795 transitions. [2021-07-06 20:41:55,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101612 states and 140795 transitions. [2021-07-06 20:41:55,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101612 to 97916. [2021-07-06 20:41:55,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97916 states, 97916 states have (on average 1.3898749948935822) internal successors, (136091), 97915 states have internal predecessors, (136091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:56,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97916 states to 97916 states and 136091 transitions. [2021-07-06 20:41:56,093 INFO L704 BuchiCegarLoop]: Abstraction has 97916 states and 136091 transitions. [2021-07-06 20:41:56,093 INFO L587 BuchiCegarLoop]: Abstraction has 97916 states and 136091 transitions. [2021-07-06 20:41:56,093 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-07-06 20:41:56,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97916 states and 136091 transitions. [2021-07-06 20:41:56,721 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 97760 [2021-07-06 20:41:56,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:56,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:56,721 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:56,722 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:56,722 INFO L791 eck$LassoCheckResult]: Stem: 582081#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 581939#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 581917#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 581904#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 581905#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 581599#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 581600#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 581887#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 581888#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 581772#L431-1 assume !(0 == ~M_E~0); 581773#L591-1 assume !(0 == ~T1_E~0); 581776#L596-1 assume !(0 == ~T2_E~0); 581777#L601-1 assume !(0 == ~T3_E~0); 581854#L606-1 assume !(0 == ~T4_E~0); 581700#L611-1 assume !(0 == ~T5_E~0); 581701#L616-1 assume !(0 == ~E_M~0); 581517#L621-1 assume !(0 == ~E_1~0); 581518#L626-1 assume !(0 == ~E_2~0); 581605#L631-1 assume !(0 == ~E_3~0); 581606#L636-1 assume !(0 == ~E_4~0); 581911#L641-1 assume !(0 == ~E_5~0); 581912#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 582013#L284 assume !(1 == ~m_pc~0); 581995#L284-2 is_master_triggered_~__retres1~0 := 0; 581996#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 581937#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 581938#L735 assume !(0 != activate_threads_~tmp~1); 582181#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 581622#L303 assume !(1 == ~t1_pc~0); 581623#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 581678#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 581690#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 581715#L743 assume !(0 != activate_threads_~tmp___0~0); 581716#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 581718#L322 assume !(1 == ~t2_pc~0); 581893#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 581892#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 581556#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 581557#L751 assume !(0 != activate_threads_~tmp___1~0); 581906#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 581907#L341 assume !(1 == ~t3_pc~0); 581841#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 581842#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 581838#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 581839#L759 assume !(0 != activate_threads_~tmp___2~0); 582096#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 582097#L360 assume !(1 == ~t4_pc~0); 582207#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 582205#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 582022#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 582023#L767 assume !(0 != activate_threads_~tmp___3~0); 582100#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 581769#L379 assume !(1 == ~t5_pc~0); 581674#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 581749#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 611498#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 611497#L775 assume !(0 != activate_threads_~tmp___4~0); 611496#L775-2 assume !(1 == ~M_E~0); 611495#L659-1 assume !(1 == ~T1_E~0); 611494#L664-1 assume !(1 == ~T2_E~0); 611493#L669-1 assume !(1 == ~T3_E~0); 611492#L674-1 assume !(1 == ~T4_E~0); 611491#L679-1 assume !(1 == ~T5_E~0); 611490#L684-1 assume !(1 == ~E_M~0); 611489#L689-1 assume !(1 == ~E_1~0); 611488#L694-1 assume !(1 == ~E_2~0); 611486#L699-1 assume !(1 == ~E_3~0); 611484#L704-1 assume !(1 == ~E_4~0); 611482#L709-1 assume !(1 == ~E_5~0); 581512#L920-1 assume !false; 611361#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 611359#L566 [2021-07-06 20:41:56,722 INFO L793 eck$LassoCheckResult]: Loop: 611359#L566 assume !false; 611357#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 611355#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 611354#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 611353#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 611352#L491 assume 0 != eval_~tmp~0; 611350#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 611348#L499 assume !(0 != eval_~tmp_ndt_1~0); 606487#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 606485#L513 assume !(0 != eval_~tmp_ndt_2~0); 606483#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 603438#L527 assume !(0 != eval_~tmp_ndt_3~0); 606231#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 606229#L541 assume !(0 != eval_~tmp_ndt_4~0); 606228#L538 assume !(0 == ~t4_st~0); 606223#L552 assume !(0 == ~t5_st~0); 611359#L566 [2021-07-06 20:41:56,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:56,723 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-07-06 20:41:56,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:56,723 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952486482] [2021-07-06 20:41:56,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:56,723 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:56,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:56,730 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:56,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:56,737 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:56,748 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:56,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:56,749 INFO L82 PathProgramCache]: Analyzing trace with hash -595166546, now seen corresponding path program 1 times [2021-07-06 20:41:56,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:56,749 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7376740] [2021-07-06 20:41:56,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:56,749 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:56,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:56,752 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:56,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:56,754 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:56,756 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:56,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:56,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1485315376, now seen corresponding path program 1 times [2021-07-06 20:41:56,756 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:56,756 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579796058] [2021-07-06 20:41:56,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:56,757 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:56,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:56,774 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:56,775 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:56,775 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:56,775 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:56,778 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:56,778 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:56,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:56,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:56,779 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579796058] [2021-07-06 20:41:56,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579796058] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:56,779 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:56,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:56,780 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [941062317] [2021-07-06 20:41:56,846 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:56,847 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 54 [2021-07-06 20:41:56,879 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:56,880 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:56,880 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:56,881 INFO L87 Difference]: Start difference. First operand 97916 states and 136091 transitions. cyclomatic complexity: 38178 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:57,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:57,349 INFO L93 Difference]: Finished difference Result 184020 states and 255179 transitions. [2021-07-06 20:41:57,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:57,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184020 states and 255179 transitions. [2021-07-06 20:41:58,538 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 183800 [2021-07-06 20:41:58,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184020 states to 184020 states and 255179 transitions. [2021-07-06 20:41:58,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184020 [2021-07-06 20:41:59,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184020 [2021-07-06 20:41:59,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184020 states and 255179 transitions. [2021-07-06 20:41:59,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:59,202 INFO L681 BuchiCegarLoop]: Abstraction has 184020 states and 255179 transitions. [2021-07-06 20:41:59,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184020 states and 255179 transitions. [2021-07-06 20:42:00,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184020 to 182900. [2021-07-06 20:42:01,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182900 states, 182900 states have (on average 1.387834882449426) internal successors, (253835), 182899 states have internal predecessors, (253835), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:01,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182900 states to 182900 states and 253835 transitions. [2021-07-06 20:42:01,311 INFO L704 BuchiCegarLoop]: Abstraction has 182900 states and 253835 transitions. [2021-07-06 20:42:01,311 INFO L587 BuchiCegarLoop]: Abstraction has 182900 states and 253835 transitions. [2021-07-06 20:42:01,311 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-07-06 20:42:01,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182900 states and 253835 transitions. [2021-07-06 20:42:02,347 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 182680 [2021-07-06 20:42:02,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:42:02,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:42:02,348 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:02,348 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:02,349 INFO L791 eck$LassoCheckResult]: Stem: 864013#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 863874#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 863852#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 863839#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 863840#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 863542#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 863543#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 863820#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 863821#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 863711#L431-1 assume !(0 == ~M_E~0); 863712#L591-1 assume !(0 == ~T1_E~0); 863715#L596-1 assume !(0 == ~T2_E~0); 863716#L601-1 assume !(0 == ~T3_E~0); 863790#L606-1 assume !(0 == ~T4_E~0); 863643#L611-1 assume !(0 == ~T5_E~0); 863644#L616-1 assume !(0 == ~E_M~0); 863460#L621-1 assume !(0 == ~E_1~0); 863461#L626-1 assume !(0 == ~E_2~0); 863548#L631-1 assume !(0 == ~E_3~0); 863549#L636-1 assume !(0 == ~E_4~0); 863846#L641-1 assume !(0 == ~E_5~0); 863847#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 863951#L284 assume !(1 == ~m_pc~0); 863933#L284-2 is_master_triggered_~__retres1~0 := 0; 863934#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 863872#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 863873#L735 assume !(0 != activate_threads_~tmp~1); 864116#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 863566#L303 assume !(1 == ~t1_pc~0); 863567#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 863622#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 863632#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 863658#L743 assume !(0 != activate_threads_~tmp___0~0); 863659#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 863662#L322 assume !(1 == ~t2_pc~0); 863826#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 863825#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 863499#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 863500#L751 assume !(0 != activate_threads_~tmp___1~0); 863841#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 863842#L341 assume !(1 == ~t3_pc~0); 863780#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 863781#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 863777#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 863778#L759 assume !(0 != activate_threads_~tmp___2~0); 864030#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 864031#L360 assume !(1 == ~t4_pc~0); 864157#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 864155#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 863960#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 863961#L767 assume !(0 != activate_threads_~tmp___3~0); 864036#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 863708#L379 assume !(1 == ~t5_pc~0); 863618#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 863691#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 863612#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 863474#L775 assume !(0 != activate_threads_~tmp___4~0); 863475#L775-2 assume !(1 == ~M_E~0); 863476#L659-1 assume !(1 == ~T1_E~0); 863546#L664-1 assume !(1 == ~T2_E~0); 863547#L669-1 assume !(1 == ~T3_E~0); 863844#L674-1 assume !(1 == ~T4_E~0); 863845#L679-1 assume !(1 == ~T5_E~0); 863730#L684-1 assume !(1 == ~E_M~0); 863731#L689-1 assume !(1 == ~E_1~0); 863998#L694-1 assume !(1 == ~E_2~0); 863663#L699-1 assume !(1 == ~E_3~0); 863664#L704-1 assume !(1 == ~E_4~0); 864032#L709-1 assume !(1 == ~E_5~0); 863456#L920-1 assume !false; 910477#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 910474#L566 [2021-07-06 20:42:02,349 INFO L793 eck$LassoCheckResult]: Loop: 910474#L566 assume !false; 910472#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 910469#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 910466#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 910464#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 910463#L491 assume 0 != eval_~tmp~0; 910458#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 910454#L499 assume !(0 != eval_~tmp_ndt_1~0); 909419#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 904978#L513 assume !(0 != eval_~tmp_ndt_2~0); 909418#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 901266#L527 assume !(0 != eval_~tmp_ndt_3~0); 904526#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 904524#L541 assume !(0 != eval_~tmp_ndt_4~0); 904523#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 897936#L555 assume !(0 != eval_~tmp_ndt_5~0); 910481#L552 assume !(0 == ~t5_st~0); 910474#L566 [2021-07-06 20:42:02,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:02,349 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-07-06 20:42:02,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:02,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385548966] [2021-07-06 20:42:02,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:02,350 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:02,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:02,356 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:02,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:02,361 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:02,372 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:02,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:02,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1270466089, now seen corresponding path program 1 times [2021-07-06 20:42:02,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:02,373 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800251761] [2021-07-06 20:42:02,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:02,373 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:02,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:02,376 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:02,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:02,378 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:02,379 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:02,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:02,379 INFO L82 PathProgramCache]: Analyzing trace with hash -1200035947, now seen corresponding path program 1 times [2021-07-06 20:42:02,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:02,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1597345103] [2021-07-06 20:42:02,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:02,380 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:02,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:42:02,396 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:02,397 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:42:02,397 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:02,398 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:42:02,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:42:02,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:42:02,401 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1597345103] [2021-07-06 20:42:02,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1597345103] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:42:02,401 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:42:02,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:42:02,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1730676167] [2021-07-06 20:42:02,471 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:02,472 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 59 [2021-07-06 20:42:02,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:42:02,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:42:02,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:42:02,510 INFO L87 Difference]: Start difference. First operand 182900 states and 253835 transitions. cyclomatic complexity: 70938 Second operand has 3 states, 2 states have (on average 44.0) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:03,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:42:03,824 INFO L93 Difference]: Finished difference Result 311228 states and 432723 transitions. [2021-07-06 20:42:03,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:42:03,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 311228 states and 432723 transitions. [2021-07-06 20:42:05,274 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 310880 [2021-07-06 20:42:06,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 311228 states to 311228 states and 432723 transitions. [2021-07-06 20:42:06,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 311228 [2021-07-06 20:42:06,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 311228 [2021-07-06 20:42:06,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 311228 states and 432723 transitions. [2021-07-06 20:42:06,965 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:42:06,965 INFO L681 BuchiCegarLoop]: Abstraction has 311228 states and 432723 transitions. [2021-07-06 20:42:07,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311228 states and 432723 transitions. [2021-07-06 20:42:09,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311228 to 308540. [2021-07-06 20:42:09,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308540 states, 308540 states have (on average 1.3937739028975173) internal successors, (430035), 308539 states have internal predecessors, (430035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:11,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308540 states to 308540 states and 430035 transitions. [2021-07-06 20:42:11,068 INFO L704 BuchiCegarLoop]: Abstraction has 308540 states and 430035 transitions. [2021-07-06 20:42:11,068 INFO L587 BuchiCegarLoop]: Abstraction has 308540 states and 430035 transitions. [2021-07-06 20:42:11,077 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-07-06 20:42:11,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308540 states and 430035 transitions. [2021-07-06 20:42:11,973 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 308192 [2021-07-06 20:42:11,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:42:11,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:42:11,974 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:11,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:11,975 INFO L791 eck$LassoCheckResult]: Stem: 1358184#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1358028#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1358006#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1357992#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1357993#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1357679#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1357680#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1357969#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1357970#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1357855#L431-1 assume !(0 == ~M_E~0); 1357856#L591-1 assume !(0 == ~T1_E~0); 1357859#L596-1 assume !(0 == ~T2_E~0); 1357860#L601-1 assume !(0 == ~T3_E~0); 1357934#L606-1 assume !(0 == ~T4_E~0); 1357779#L611-1 assume !(0 == ~T5_E~0); 1357780#L616-1 assume !(0 == ~E_M~0); 1357596#L621-1 assume !(0 == ~E_1~0); 1357597#L626-1 assume !(0 == ~E_2~0); 1357685#L631-1 assume !(0 == ~E_3~0); 1357686#L636-1 assume !(0 == ~E_4~0); 1358000#L641-1 assume !(0 == ~E_5~0); 1358001#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1358107#L284 assume !(1 == ~m_pc~0); 1358088#L284-2 is_master_triggered_~__retres1~0 := 0; 1358089#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1358026#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1358027#L735 assume !(0 != activate_threads_~tmp~1); 1358302#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1357700#L303 assume !(1 == ~t1_pc~0); 1357701#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1357757#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1357768#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1357795#L743 assume !(0 != activate_threads_~tmp___0~0); 1357796#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1357799#L322 assume !(1 == ~t2_pc~0); 1357976#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 1357975#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1357636#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1357637#L751 assume !(0 != activate_threads_~tmp___1~0); 1357994#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1357995#L341 assume !(1 == ~t3_pc~0); 1357922#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1357923#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1357919#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1357920#L759 assume !(0 != activate_threads_~tmp___2~0); 1358205#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1358206#L360 assume !(1 == ~t4_pc~0); 1358341#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 1358339#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1358118#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1358119#L767 assume !(0 != activate_threads_~tmp___3~0); 1358210#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1357851#L379 assume !(1 == ~t5_pc~0); 1357753#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1357832#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1464537#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1464536#L775 assume !(0 != activate_threads_~tmp___4~0); 1464535#L775-2 assume !(1 == ~M_E~0); 1464534#L659-1 assume !(1 == ~T1_E~0); 1464533#L664-1 assume !(1 == ~T2_E~0); 1464532#L669-1 assume !(1 == ~T3_E~0); 1357998#L674-1 assume !(1 == ~T4_E~0); 1357999#L679-1 assume !(1 == ~T5_E~0); 1357872#L684-1 assume !(1 == ~E_M~0); 1357873#L689-1 assume !(1 == ~E_1~0); 1358162#L694-1 assume !(1 == ~E_2~0); 1358163#L699-1 assume !(1 == ~E_3~0); 1358207#L704-1 assume !(1 == ~E_4~0); 1358208#L709-1 assume !(1 == ~E_5~0); 1357592#L920-1 assume !false; 1464486#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1433797#L566 [2021-07-06 20:42:11,975 INFO L793 eck$LassoCheckResult]: Loop: 1433797#L566 assume !false; 1464475#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1462254#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1462146#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1437634#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1437631#L491 assume 0 != eval_~tmp~0; 1437628#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1437625#L499 assume !(0 != eval_~tmp_ndt_1~0); 1437621#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1422123#L513 assume !(0 != eval_~tmp_ndt_2~0); 1407197#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1407193#L527 assume !(0 != eval_~tmp_ndt_3~0); 1407194#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 1422023#L541 assume !(0 != eval_~tmp_ndt_4~0); 1422021#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 1422016#L555 assume !(0 != eval_~tmp_ndt_5~0); 1422017#L552 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 1427266#L569 assume !(0 != eval_~tmp_ndt_6~0); 1433797#L566 [2021-07-06 20:42:11,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:11,976 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-07-06 20:42:11,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:11,976 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [989982492] [2021-07-06 20:42:11,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:11,976 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:11,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,983 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,988 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:12,000 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:12,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:12,001 INFO L82 PathProgramCache]: Analyzing trace with hash -729747053, now seen corresponding path program 1 times [2021-07-06 20:42:12,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:12,001 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250259910] [2021-07-06 20:42:12,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:12,001 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:12,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:12,004 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:12,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:12,006 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:12,007 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:12,007 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:12,008 INFO L82 PathProgramCache]: Analyzing trace with hash 1453587349, now seen corresponding path program 1 times [2021-07-06 20:42:12,008 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:12,008 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425380422] [2021-07-06 20:42:12,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:12,008 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:12,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:12,015 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:12,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:12,020 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:12,037 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:12,128 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:12,130 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 64 [2021-07-06 20:42:13,821 WARN L205 SmtUtils]: Spent 1.64 s on a formula simplification. DAG size of input: 251 DAG size of output: 179 [2021-07-06 20:42:13,845 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:13,879 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 257 [2021-07-06 20:42:14,159 WARN L205 SmtUtils]: Spent 278.00 ms on a formula simplification that was a NOOP. DAG size: 153 [2021-07-06 20:42:14,203 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.07 08:42:14 BoogieIcfgContainer [2021-07-06 20:42:14,203 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-07-06 20:42:14,204 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-07-06 20:42:14,204 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-07-06 20:42:14,204 INFO L275 PluginConnector]: Witness Printer initialized [2021-07-06 20:42:14,204 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40" (3/4) ... [2021-07-06 20:42:14,206 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-07-06 20:42:14,243 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-07-06 20:42:14,244 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-07-06 20:42:14,244 INFO L168 Benchmark]: Toolchain (without parser) took 35910.30 ms. Allocated memory was 65.0 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 44.5 MB in the beginning and 10.5 GB in the end (delta: -10.4 GB). Peak memory consumption was 3.4 GB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 65.0 MB. Free memory is still 45.2 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: CACSL2BoogieTranslator took 370.00 ms. Allocated memory is still 65.0 MB. Free memory was 44.2 MB in the beginning and 42.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: Boogie Procedure Inliner took 88.66 ms. Allocated memory is still 65.0 MB. Free memory was 42.1 MB in the beginning and 37.1 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: Boogie Preprocessor took 90.68 ms. Allocated memory is still 65.0 MB. Free memory was 37.1 MB in the beginning and 32.5 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: RCFGBuilder took 1306.60 ms. Allocated memory was 65.0 MB in the beginning and 94.4 MB in the end (delta: 29.4 MB). Free memory was 32.5 MB in the beginning and 42.7 MB in the end (delta: -10.2 MB). Peak memory consumption was 27.0 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,245 INFO L168 Benchmark]: BuchiAutomizer took 34009.21 ms. Allocated memory was 94.4 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 42.2 MB in the beginning and 10.5 GB in the end (delta: -10.4 GB). Peak memory consumption was 3.8 GB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,246 INFO L168 Benchmark]: Witness Printer took 40.16 ms. Allocated memory is still 14.0 GB. Free memory was 10.5 GB in the beginning and 10.5 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:14,246 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 65.0 MB. Free memory is still 45.2 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 370.00 ms. Allocated memory is still 65.0 MB. Free memory was 44.2 MB in the beginning and 42.4 MB in the end (delta: 1.9 MB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 88.66 ms. Allocated memory is still 65.0 MB. Free memory was 42.1 MB in the beginning and 37.1 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 90.68 ms. Allocated memory is still 65.0 MB. Free memory was 37.1 MB in the beginning and 32.5 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1306.60 ms. Allocated memory was 65.0 MB in the beginning and 94.4 MB in the end (delta: 29.4 MB). Free memory was 32.5 MB in the beginning and 42.7 MB in the end (delta: -10.2 MB). Peak memory consumption was 27.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 34009.21 ms. Allocated memory was 94.4 MB in the beginning and 14.0 GB in the end (delta: 13.9 GB). Free memory was 42.2 MB in the beginning and 10.5 GB in the end (delta: -10.4 GB). Peak memory consumption was 3.8 GB. Max. memory is 16.1 GB. * Witness Printer took 40.16 ms. Allocated memory is still 14.0 GB. Free memory was 10.5 GB in the beginning and 10.5 GB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 308540 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 33.9s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 5.1s. Construction of modules took 0.8s. Büchi inclusion checks took 3.7s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 11149.1ms AutomataMinimizationTime, 24 MinimizatonAttempts, 53297 StatesRemovedByMinimization, 17 NontrivialMinimizations. Non-live state removal took 8.2s Buchi closure took 0.5s. Biggest automaton had 308540 states and ocurred in iteration 24. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 21951 SDtfs, 26662 SDslu, 20838 SDs, 0 SdLazy, 790 SolverSat, 330 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 857.0ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 486]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=31632} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=31632, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a5e54c2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bc0bf31=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@628348aa=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6fd0386c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7653d18=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@388edb6c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@689c27b=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16d8b331=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e73ffaf=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@65f7e1d8=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@26e2d5cc=0, NULL=31635, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d075aab=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6dc8ca0=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@289e56de=0, T1_E=2, NULL=31633, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=31634, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3041f2ba=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 486]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L965] int __retres1 ; [L876] m_i = 1 [L877] t1_i = 1 [L878] t2_i = 1 [L879] t3_i = 1 [L880] t4_i = 1 [L881] t5_i = 1 [L906] int kernel_st ; [L907] int tmp ; [L908] int tmp___0 ; [L912] kernel_st = 0 [L406] COND TRUE m_i == 1 [L407] m_st = 0 [L411] COND TRUE t1_i == 1 [L412] t1_st = 0 [L416] COND TRUE t2_i == 1 [L417] t2_st = 0 [L421] COND TRUE t3_i == 1 [L422] t3_st = 0 [L426] COND TRUE t4_i == 1 [L427] t4_st = 0 [L431] COND TRUE t5_i == 1 [L432] t5_st = 0 [L591] COND FALSE !(M_E == 0) [L596] COND FALSE !(T1_E == 0) [L601] COND FALSE !(T2_E == 0) [L606] COND FALSE !(T3_E == 0) [L611] COND FALSE !(T4_E == 0) [L616] COND FALSE !(T5_E == 0) [L621] COND FALSE !(E_M == 0) [L626] COND FALSE !(E_1 == 0) [L631] COND FALSE !(E_2 == 0) [L636] COND FALSE !(E_3 == 0) [L641] COND FALSE !(E_4 == 0) [L646] COND FALSE !(E_5 == 0) [L724] int tmp ; [L725] int tmp___0 ; [L726] int tmp___1 ; [L727] int tmp___2 ; [L728] int tmp___3 ; [L729] int tmp___4 ; [L281] int __retres1 ; [L284] COND FALSE !(m_pc == 1) [L294] __retres1 = 0 [L296] return (__retres1); [L733] tmp = is_master_triggered() [L735] COND FALSE !(\read(tmp)) [L300] int __retres1 ; [L303] COND FALSE !(t1_pc == 1) [L313] __retres1 = 0 [L315] return (__retres1); [L741] tmp___0 = is_transmit1_triggered() [L743] COND FALSE !(\read(tmp___0)) [L319] int __retres1 ; [L322] COND FALSE !(t2_pc == 1) [L332] __retres1 = 0 [L334] return (__retres1); [L749] tmp___1 = is_transmit2_triggered() [L751] COND FALSE !(\read(tmp___1)) [L338] int __retres1 ; [L341] COND FALSE !(t3_pc == 1) [L351] __retres1 = 0 [L353] return (__retres1); [L757] tmp___2 = is_transmit3_triggered() [L759] COND FALSE !(\read(tmp___2)) [L357] int __retres1 ; [L360] COND FALSE !(t4_pc == 1) [L370] __retres1 = 0 [L372] return (__retres1); [L765] tmp___3 = is_transmit4_triggered() [L767] COND FALSE !(\read(tmp___3)) [L376] int __retres1 ; [L379] COND FALSE !(t5_pc == 1) [L389] __retres1 = 0 [L391] return (__retres1); [L773] tmp___4 = is_transmit5_triggered() [L775] COND FALSE !(\read(tmp___4)) [L659] COND FALSE !(M_E == 1) [L664] COND FALSE !(T1_E == 1) [L669] COND FALSE !(T2_E == 1) [L674] COND FALSE !(T3_E == 1) [L679] COND FALSE !(T4_E == 1) [L684] COND FALSE !(T5_E == 1) [L689] COND FALSE !(E_M == 1) [L694] COND FALSE !(E_1 == 1) [L699] COND FALSE !(E_2 == 1) [L704] COND FALSE !(E_3 == 1) [L709] COND FALSE !(E_4 == 1) [L714] COND FALSE !(E_5 == 1) [L920] COND TRUE 1 [L923] kernel_st = 1 [L482] int tmp ; Loop: [L486] COND TRUE 1 [L441] int __retres1 ; [L444] COND TRUE m_st == 0 [L445] __retres1 = 1 [L477] return (__retres1); [L489] tmp = exists_runnable_thread() [L491] COND TRUE \read(tmp) [L496] COND TRUE m_st == 0 [L497] int tmp_ndt_1; [L498] tmp_ndt_1 = __VERIFIER_nondet_int() [L499] COND FALSE !(\read(tmp_ndt_1)) [L510] COND TRUE t1_st == 0 [L511] int tmp_ndt_2; [L512] tmp_ndt_2 = __VERIFIER_nondet_int() [L513] COND FALSE !(\read(tmp_ndt_2)) [L524] COND TRUE t2_st == 0 [L525] int tmp_ndt_3; [L526] tmp_ndt_3 = __VERIFIER_nondet_int() [L527] COND FALSE !(\read(tmp_ndt_3)) [L538] COND TRUE t3_st == 0 [L539] int tmp_ndt_4; [L540] tmp_ndt_4 = __VERIFIER_nondet_int() [L541] COND FALSE !(\read(tmp_ndt_4)) [L552] COND TRUE t4_st == 0 [L553] int tmp_ndt_5; [L554] tmp_ndt_5 = __VERIFIER_nondet_int() [L555] COND FALSE !(\read(tmp_ndt_5)) [L566] COND TRUE t5_st == 0 [L567] int tmp_ndt_6; [L568] tmp_ndt_6 = __VERIFIER_nondet_int() [L569] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-07-06 20:42:14,295 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...