./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8d31f386 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5937481bc19468f59d919de13c534d2ea0f2da0e .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-wip.dd.multireach-323-8d31f38 [2021-07-06 20:41:37,443 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-07-06 20:41:37,445 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-07-06 20:41:37,470 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-07-06 20:41:37,470 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-07-06 20:41:37,471 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-07-06 20:41:37,472 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-07-06 20:41:37,477 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-07-06 20:41:37,484 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-07-06 20:41:37,490 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-07-06 20:41:37,491 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-07-06 20:41:37,493 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-07-06 20:41:37,493 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-07-06 20:41:37,496 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-07-06 20:41:37,497 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-07-06 20:41:37,499 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-07-06 20:41:37,501 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-07-06 20:41:37,502 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-07-06 20:41:37,507 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-07-06 20:41:37,510 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-07-06 20:41:37,514 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-07-06 20:41:37,515 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-07-06 20:41:37,517 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-07-06 20:41:37,518 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-07-06 20:41:37,520 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-07-06 20:41:37,521 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-07-06 20:41:37,521 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-07-06 20:41:37,522 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-07-06 20:41:37,522 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-07-06 20:41:37,523 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-07-06 20:41:37,523 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-07-06 20:41:37,524 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-07-06 20:41:37,524 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-07-06 20:41:37,525 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-07-06 20:41:37,526 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-07-06 20:41:37,526 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-07-06 20:41:37,526 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-07-06 20:41:37,527 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-07-06 20:41:37,527 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-07-06 20:41:37,528 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-07-06 20:41:37,528 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-07-06 20:41:37,530 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-07-06 20:41:37,568 INFO L113 SettingsManager]: Loading preferences was successful [2021-07-06 20:41:37,568 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-07-06 20:41:37,570 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-07-06 20:41:37,571 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-07-06 20:41:37,571 INFO L138 SettingsManager]: * Use SBE=true [2021-07-06 20:41:37,571 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-07-06 20:41:37,571 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-07-06 20:41:37,572 INFO L138 SettingsManager]: * Use old map elimination=false [2021-07-06 20:41:37,572 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-07-06 20:41:37,572 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-07-06 20:41:37,573 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-07-06 20:41:37,573 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-07-06 20:41:37,574 INFO L138 SettingsManager]: * sizeof long=4 [2021-07-06 20:41:37,574 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-07-06 20:41:37,574 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-07-06 20:41:37,574 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-07-06 20:41:37,574 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-07-06 20:41:37,575 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-07-06 20:41:37,575 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-07-06 20:41:37,575 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-07-06 20:41:37,575 INFO L138 SettingsManager]: * sizeof long double=12 [2021-07-06 20:41:37,575 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-07-06 20:41:37,576 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-07-06 20:41:37,576 INFO L138 SettingsManager]: * Use constant arrays=true [2021-07-06 20:41:37,576 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-07-06 20:41:37,576 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-07-06 20:41:37,576 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-07-06 20:41:37,577 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-07-06 20:41:37,577 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-07-06 20:41:37,577 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-07-06 20:41:37,578 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-07-06 20:41:37,578 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5937481bc19468f59d919de13c534d2ea0f2da0e [2021-07-06 20:41:37,917 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-07-06 20:41:37,934 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-07-06 20:41:37,936 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-07-06 20:41:37,937 INFO L271 PluginConnector]: Initializing CDTParser... [2021-07-06 20:41:37,938 INFO L275 PluginConnector]: CDTParser initialized [2021-07-06 20:41:37,938 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-07-06 20:41:37,996 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d6abd8433/8f4fba4fe32c4d7db5e57556523d02d2/FLAG6ae2f4792 [2021-07-06 20:41:38,485 INFO L306 CDTParser]: Found 1 translation units. [2021-07-06 20:41:38,491 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-07-06 20:41:38,504 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d6abd8433/8f4fba4fe32c4d7db5e57556523d02d2/FLAG6ae2f4792 [2021-07-06 20:41:39,015 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d6abd8433/8f4fba4fe32c4d7db5e57556523d02d2 [2021-07-06 20:41:39,017 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-07-06 20:41:39,019 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-07-06 20:41:39,022 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-07-06 20:41:39,023 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-07-06 20:41:39,026 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-07-06 20:41:39,027 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,028 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63999fcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39, skipping insertion in model container [2021-07-06 20:41:39,031 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,041 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-07-06 20:41:39,073 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-07-06 20:41:39,170 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[366,379] [2021-07-06 20:41:39,229 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:41:39,238 INFO L203 MainTranslator]: Completed pre-run [2021-07-06 20:41:39,282 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[366,379] [2021-07-06 20:41:39,332 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:41:39,368 INFO L208 MainTranslator]: Completed translation [2021-07-06 20:41:39,369 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39 WrapperNode [2021-07-06 20:41:39,370 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-07-06 20:41:39,371 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-07-06 20:41:39,371 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-07-06 20:41:39,372 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-07-06 20:41:39,377 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,400 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,458 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-07-06 20:41:39,459 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-07-06 20:41:39,459 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-07-06 20:41:39,460 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-07-06 20:41:39,466 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,466 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,477 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,477 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,500 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,522 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,525 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,529 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-07-06 20:41:39,530 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-07-06 20:41:39,530 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-07-06 20:41:39,530 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-07-06 20:41:39,531 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (1/1) ... [2021-07-06 20:41:39,563 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-07-06 20:41:39,570 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-07-06 20:41:39,582 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-07-06 20:41:39,601 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-07-06 20:41:39,633 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-07-06 20:41:39,634 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-07-06 20:41:39,635 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-07-06 20:41:39,635 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-07-06 20:41:40,781 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-07-06 20:41:40,782 INFO L299 CfgBuilder]: Removed 198 assume(true) statements. [2021-07-06 20:41:40,784 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40 BoogieIcfgContainer [2021-07-06 20:41:40,784 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-07-06 20:41:40,785 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-07-06 20:41:40,785 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-07-06 20:41:40,787 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-07-06 20:41:40,788 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,788 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.07 08:41:39" (1/3) ... [2021-07-06 20:41:40,789 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c2f881e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:41:40, skipping insertion in model container [2021-07-06 20:41:40,789 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,789 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:41:39" (2/3) ... [2021-07-06 20:41:40,790 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c2f881e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:41:40, skipping insertion in model container [2021-07-06 20:41:40,790 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:41:40,790 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40" (3/3) ... [2021-07-06 20:41:40,791 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2021-07-06 20:41:40,824 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-07-06 20:41:40,825 INFO L360 BuchiCegarLoop]: Hoare is false [2021-07-06 20:41:40,825 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-07-06 20:41:40,825 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-07-06 20:41:40,825 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-07-06 20:41:40,825 INFO L364 BuchiCegarLoop]: Difference is false [2021-07-06 20:41:40,825 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-07-06 20:41:40,825 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-07-06 20:41:40,847 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,884 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-07-06 20:41:40,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,896 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-07-06 20:41:40,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:40,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-07-06 20:41:40,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:40,918 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:40,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,927 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:40,937 INFO L791 eck$LassoCheckResult]: Stem: 357#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 251#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 210#L895true havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56#L411true assume !(1 == ~m_i~0);~m_st~0 := 2; 369#L418-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 136#L423-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 283#L428-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 57#L433-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 486#L438-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 216#L443-1true assume !(0 == ~M_E~0); 500#L603-1true assume !(0 == ~T1_E~0); 220#L608-1true assume !(0 == ~T2_E~0); 527#L613-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 149#L618-1true assume !(0 == ~T4_E~0); 448#L623-1true assume !(0 == ~T5_E~0); 203#L628-1true assume !(0 == ~E_M~0); 98#L633-1true assume !(0 == ~E_1~0); 374#L638-1true assume !(0 == ~E_2~0); 5#L643-1true assume !(0 == ~E_3~0); 293#L648-1true assume !(0 == ~E_4~0); 64#L653-1true assume 0 == ~E_5~0;~E_5~0 := 1; 494#L658-1true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 249#L296true assume 1 == ~m_pc~0; 355#L297true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 255#L307true is_master_triggered_#res := is_master_triggered_~__retres1~0; 356#L308true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 305#L747true assume !(0 != activate_threads_~tmp~1); 289#L747-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 438#L315true assume !(1 == ~t1_pc~0); 408#L315-2true is_transmit1_triggered_~__retres1~1 := 0; 436#L326true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 520#L327true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 455#L755true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 458#L755-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37#L334true assume 1 == ~t2_pc~0; 139#L335true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 36#L345true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 138#L346true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70#L763true assume !(0 != activate_threads_~tmp___1~0); 61#L763-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 196#L353true assume !(1 == ~t3_pc~0); 200#L353-2true is_transmit3_triggered_~__retres1~3 := 0; 195#L364true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 141#L365true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 341#L771true assume !(0 != activate_threads_~tmp___2~0); 342#L771-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 324#L372true assume 1 == ~t4_pc~0; 286#L373true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 488#L383true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 284#L384true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 503#L779true assume !(0 != activate_threads_~tmp___3~0); 490#L779-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 89#L391true assume !(1 == ~t5_pc~0); 93#L391-2true is_transmit5_triggered_~__retres1~5 := 0; 87#L402true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 428#L403true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 105#L787true assume !(0 != activate_threads_~tmp___4~0); 107#L787-2true assume !(1 == ~M_E~0); 372#L671-1true assume !(1 == ~T1_E~0); 4#L676-1true assume !(1 == ~T2_E~0); 290#L681-1true assume !(1 == ~T3_E~0); 63#L686-1true assume !(1 == ~T4_E~0); 492#L691-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 218#L696-1true assume !(1 == ~E_M~0); 538#L701-1true assume !(1 == ~E_1~0); 158#L706-1true assume !(1 == ~E_2~0); 459#L711-1true assume !(1 == ~E_3~0); 343#L716-1true assume !(1 == ~E_4~0); 108#L721-1true assume !(1 == ~E_5~0); 392#L932-1true [2021-07-06 20:41:40,939 INFO L793 eck$LassoCheckResult]: Loop: 392#L932-1true assume !false; 505#L933true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 100#L578true assume !true; 295#L593true start_simulation_~kernel_st~0 := 2; 59#L411-1true start_simulation_~kernel_st~0 := 3; 479#L603-2true assume 0 == ~M_E~0;~M_E~0 := 1; 482#L603-4true assume !(0 == ~T1_E~0); 213#L608-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 532#L613-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 151#L618-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 452#L623-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 205#L628-3true assume 0 == ~E_M~0;~E_M~0 := 1; 102#L633-3true assume 0 == ~E_1~0;~E_1~0 := 1; 378#L638-3true assume 0 == ~E_2~0;~E_2~0 := 1; 9#L643-3true assume !(0 == ~E_3~0); 298#L648-3true assume 0 == ~E_4~0;~E_4~0 := 1; 68#L653-3true assume 0 == ~E_5~0;~E_5~0 := 1; 501#L658-3true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 370#L296-21true assume !(1 == ~m_pc~0); 368#L296-23true is_master_triggered_~__retres1~0 := 0; 247#L307-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 350#L308-7true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 248#L747-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 384#L747-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 539#L315-21true assume !(1 == ~t1_pc~0); 528#L315-23true is_transmit1_triggered_~__retres1~1 := 0; 426#L326-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 515#L327-7true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 397#L755-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 401#L755-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3#L334-21true assume 1 == ~t2_pc~0; 115#L335-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 30#L345-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114#L346-7true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 34#L763-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16#L763-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 157#L353-21true assume 1 == ~t3_pc~0; 232#L354-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 191#L364-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 231#L365-7true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 169#L771-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 174#L771-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 307#L372-21true assume 1 == ~t4_pc~0; 240#L373-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 318#L383-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237#L384-7true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 322#L779-21true assume !(0 != activate_threads_~tmp___3~0); 308#L779-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 457#L391-21true assume 1 == ~t5_pc~0; 420#L392-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 80#L402-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 417#L403-7true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 474#L787-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 476#L787-23true assume 1 == ~M_E~0;~M_E~0 := 2; 375#L671-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 7#L676-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 297#L681-3true assume !(1 == ~T3_E~0); 66#L686-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L691-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 219#L696-3true assume 1 == ~E_M~0;~E_M~0 := 2; 540#L701-3true assume 1 == ~E_1~0;~E_1~0 := 2; 160#L706-3true assume 1 == ~E_2~0;~E_2~0 := 2; 447#L711-3true assume 1 == ~E_3~0;~E_3~0 := 2; 201#L716-3true assume 1 == ~E_4~0;~E_4~0 := 2; 97#L721-3true assume !(1 == ~E_5~0); 373#L726-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 134#L456-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 54#L488-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 132#L489-1true start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 20#L951true assume !(0 == start_simulation_~tmp~3); 22#L951-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 137#L456-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 55#L488-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 135#L489-2true stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 209#L906true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 388#L913true stop_simulation_#res := stop_simulation_~__retres2~0; 345#L914true start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 463#L964true assume !(0 != start_simulation_~tmp___0~1); 392#L932-1true [2021-07-06 20:41:40,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:40,946 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-07-06 20:41:40,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:40,954 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967540740] [2021-07-06 20:41:40,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:40,955 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,129 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,137 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,138 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,138 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,148 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,148 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,151 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967540740] [2021-07-06 20:41:41,152 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967540740] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,152 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,152 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,154 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136017096] [2021-07-06 20:41:41,158 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,160 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,160 INFO L82 PathProgramCache]: Analyzing trace with hash 447050465, now seen corresponding path program 1 times [2021-07-06 20:41:41,161 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,161 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957647430] [2021-07-06 20:41:41,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,161 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,207 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,208 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,209 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,209 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,210 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,211 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957647430] [2021-07-06 20:41:41,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957647430] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,211 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,211 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:41,211 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452083851] [2021-07-06 20:41:41,213 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,215 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,226 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,230 INFO L87 Difference]: Start difference. First operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,290 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2021-07-06 20:41:41,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2021-07-06 20:41:41,300 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2021-07-06 20:41:41,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-07-06 20:41:41,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-07-06 20:41:41,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2021-07-06 20:41:41,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,319 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-07-06 20:41:41,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2021-07-06 20:41:41,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-07-06 20:41:41,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.518796992481203) internal successors, (808), 531 states have internal predecessors, (808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2021-07-06 20:41:41,384 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-07-06 20:41:41,384 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-07-06 20:41:41,384 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-07-06 20:41:41,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2021-07-06 20:41:41,388 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,397 INFO L791 eck$LassoCheckResult]: Stem: 1518#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1422#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1368#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1183#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 1184#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1280#L423-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1281#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1185#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1186#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1377#L443-1 assume !(0 == ~M_E~0); 1378#L603-1 assume !(0 == ~T1_E~0); 1383#L608-1 assume !(0 == ~T2_E~0); 1384#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1306#L618-1 assume !(0 == ~T4_E~0); 1307#L623-1 assume !(0 == ~T5_E~0); 1361#L628-1 assume !(0 == ~E_M~0); 1253#L633-1 assume !(0 == ~E_1~0); 1254#L638-1 assume !(0 == ~E_2~0); 1090#L643-1 assume !(0 == ~E_3~0); 1091#L648-1 assume !(0 == ~E_4~0); 1197#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1198#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1420#L296 assume 1 == ~m_pc~0; 1421#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1408#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1430#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1494#L747 assume !(0 != activate_threads_~tmp~1); 1486#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1487#L315 assume !(1 == ~t1_pc~0); 1556#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 1557#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1585#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1597#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1598#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1150#L334 assume 1 == ~t2_pc~0; 1151#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1148#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1149#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1207#L763 assume !(0 != activate_threads_~tmp___1~0); 1191#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1192#L353 assume !(1 == ~t3_pc~0); 1287#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 1288#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1284#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1285#L771 assume !(0 != activate_threads_~tmp___2~0); 1509#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1501#L372 assume 1 == ~t4_pc~0; 1480#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1481#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1477#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1478#L779 assume !(0 != activate_threads_~tmp___3~0); 1608#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1241#L391 assume !(1 == ~t5_pc~0); 1242#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 1239#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1240#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1266#L787 assume !(0 != activate_threads_~tmp___4~0); 1267#L787-2 assume !(1 == ~M_E~0); 1268#L671-1 assume !(1 == ~T1_E~0); 1088#L676-1 assume !(1 == ~T2_E~0); 1089#L681-1 assume !(1 == ~T3_E~0); 1195#L686-1 assume !(1 == ~T4_E~0); 1196#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1379#L696-1 assume !(1 == ~E_M~0); 1380#L701-1 assume !(1 == ~E_1~0); 1318#L706-1 assume !(1 == ~E_2~0); 1319#L711-1 assume !(1 == ~E_3~0); 1510#L716-1 assume !(1 == ~E_4~0); 1269#L721-1 assume !(1 == ~E_5~0); 1270#L932-1 [2021-07-06 20:41:41,398 INFO L793 eck$LassoCheckResult]: Loop: 1270#L932-1 assume !false; 1534#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1257#L578 assume !false; 1169#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1170#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1175#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1176#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1274#L503 assume !(0 != eval_~tmp~0); 1490#L593 start_simulation_~kernel_st~0 := 2; 1188#L411-1 start_simulation_~kernel_st~0 := 3; 1189#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L603-4 assume !(0 == ~T1_E~0); 1372#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1373#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1309#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1310#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1363#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1260#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1261#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1098#L643-3 assume !(0 == ~E_3~0); 1099#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1203#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1204#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1527#L296-21 assume 1 == ~m_pc~0; 1521#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1414#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1415#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1416#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1417#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1529#L315-21 assume 1 == ~t1_pc~0; 1614#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1579#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1580#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1542#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1543#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1085#L334-21 assume 1 == ~t2_pc~0; 1086#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1092#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1140#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1145#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1114#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1115#L353-21 assume 1 == ~t3_pc~0; 1316#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1320#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1351#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1334#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1335#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1340#L372-21 assume 1 == ~t4_pc~0; 1399#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1400#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1392#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1393#L779-21 assume !(0 != activate_threads_~tmp___3~0); 1495#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1496#L391-21 assume 1 == ~t5_pc~0; 1570#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1225#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1226#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1566#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1604#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1528#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1093#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1094#L681-3 assume !(1 == ~T3_E~0); 1200#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1201#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1381#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1382#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1321#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1322#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1358#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1251#L721-3 assume !(1 == ~E_5~0); 1252#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1277#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1179#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1180#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1123#L951 assume !(0 == start_simulation_~tmp~3); 1124#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1127#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1181#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1182#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 1279#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1367#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 1511#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 1512#L964 assume !(0 != start_simulation_~tmp___0~1); 1270#L932-1 [2021-07-06 20:41:41,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,400 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-07-06 20:41:41,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,401 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562433235] [2021-07-06 20:41:41,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,402 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,465 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,466 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,467 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,467 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,471 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,471 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,472 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,473 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562433235] [2021-07-06 20:41:41,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562433235] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,473 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [622498149] [2021-07-06 20:41:41,474 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,475 INFO L82 PathProgramCache]: Analyzing trace with hash 464587162, now seen corresponding path program 1 times [2021-07-06 20:41:41,475 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,475 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17942941] [2021-07-06 20:41:41,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,475 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,528 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,530 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,531 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,533 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,537 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,537 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,538 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17942941] [2021-07-06 20:41:41,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17942941] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,539 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,539 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,539 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241843942] [2021-07-06 20:41:41,540 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,542 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,555 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2021-07-06 20:41:41,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2021-07-06 20:41:41,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2021-07-06 20:41:41,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-07-06 20:41:41,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-07-06 20:41:41,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2021-07-06 20:41:41,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,568 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-07-06 20:41:41,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2021-07-06 20:41:41,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-07-06 20:41:41,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5169172932330828) internal successors, (807), 531 states have internal predecessors, (807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2021-07-06 20:41:41,579 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-07-06 20:41:41,579 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-07-06 20:41:41,580 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-07-06 20:41:41,580 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2021-07-06 20:41:41,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,583 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,583 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,585 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,585 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,586 INFO L791 eck$LassoCheckResult]: Stem: 2589#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2493#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2439#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2254#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 2255#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2352#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2353#L428-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2256#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2257#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2448#L443-1 assume !(0 == ~M_E~0); 2449#L603-1 assume !(0 == ~T1_E~0); 2454#L608-1 assume !(0 == ~T2_E~0); 2455#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2377#L618-1 assume !(0 == ~T4_E~0); 2378#L623-1 assume !(0 == ~T5_E~0); 2432#L628-1 assume !(0 == ~E_M~0); 2324#L633-1 assume !(0 == ~E_1~0); 2325#L638-1 assume !(0 == ~E_2~0); 2161#L643-1 assume !(0 == ~E_3~0); 2162#L648-1 assume !(0 == ~E_4~0); 2268#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2269#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2491#L296 assume 1 == ~m_pc~0; 2492#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2479#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2501#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2565#L747 assume !(0 != activate_threads_~tmp~1); 2557#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2558#L315 assume !(1 == ~t1_pc~0); 2627#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 2628#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2656#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2668#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2669#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2221#L334 assume 1 == ~t2_pc~0; 2222#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2219#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2220#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2278#L763 assume !(0 != activate_threads_~tmp___1~0); 2262#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2263#L353 assume !(1 == ~t3_pc~0); 2358#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 2359#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2355#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2356#L771 assume !(0 != activate_threads_~tmp___2~0); 2580#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2572#L372 assume 1 == ~t4_pc~0; 2551#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2552#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2548#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2549#L779 assume !(0 != activate_threads_~tmp___3~0); 2679#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2314#L391 assume !(1 == ~t5_pc~0); 2315#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 2310#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2311#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2337#L787 assume !(0 != activate_threads_~tmp___4~0); 2338#L787-2 assume !(1 == ~M_E~0); 2339#L671-1 assume !(1 == ~T1_E~0); 2159#L676-1 assume !(1 == ~T2_E~0); 2160#L681-1 assume !(1 == ~T3_E~0); 2266#L686-1 assume !(1 == ~T4_E~0); 2267#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2450#L696-1 assume !(1 == ~E_M~0); 2451#L701-1 assume !(1 == ~E_1~0); 2389#L706-1 assume !(1 == ~E_2~0); 2390#L711-1 assume !(1 == ~E_3~0); 2581#L716-1 assume !(1 == ~E_4~0); 2340#L721-1 assume !(1 == ~E_5~0); 2341#L932-1 [2021-07-06 20:41:41,588 INFO L793 eck$LassoCheckResult]: Loop: 2341#L932-1 assume !false; 2605#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2328#L578 assume !false; 2240#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2241#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2246#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2247#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2345#L503 assume !(0 != eval_~tmp~0); 2561#L593 start_simulation_~kernel_st~0 := 2; 2259#L411-1 start_simulation_~kernel_st~0 := 3; 2260#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2676#L603-4 assume !(0 == ~T1_E~0); 2443#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2444#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2380#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2381#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2434#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2331#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2332#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2169#L643-3 assume !(0 == ~E_3~0); 2170#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2274#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2275#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2598#L296-21 assume 1 == ~m_pc~0; 2592#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2485#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2486#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2487#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2488#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2600#L315-21 assume 1 == ~t1_pc~0; 2685#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2650#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2651#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2613#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2614#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2156#L334-21 assume 1 == ~t2_pc~0; 2157#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2163#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2211#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2216#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2185#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2186#L353-21 assume 1 == ~t3_pc~0; 2387#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2391#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2422#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2405#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2406#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2411#L372-21 assume 1 == ~t4_pc~0; 2470#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2471#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2461#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2462#L779-21 assume !(0 != activate_threads_~tmp___3~0); 2566#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2567#L391-21 assume 1 == ~t5_pc~0; 2638#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2296#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2297#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2637#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2674#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2599#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2164#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2165#L681-3 assume !(1 == ~T3_E~0); 2271#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2272#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2452#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2453#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2392#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2393#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2429#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2321#L721-3 assume !(1 == ~E_5~0); 2322#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2348#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2250#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2251#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2194#L951 assume !(0 == start_simulation_~tmp~3); 2195#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2198#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2252#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2253#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 2350#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2438#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 2582#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 2583#L964 assume !(0 != start_simulation_~tmp___0~1); 2341#L932-1 [2021-07-06 20:41:41,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,588 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-07-06 20:41:41,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,589 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2066521949] [2021-07-06 20:41:41,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,589 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,633 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,633 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,634 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,634 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,646 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,646 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2066521949] [2021-07-06 20:41:41,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2066521949] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,648 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,648 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,648 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272071573] [2021-07-06 20:41:41,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,649 INFO L82 PathProgramCache]: Analyzing trace with hash 464587162, now seen corresponding path program 2 times [2021-07-06 20:41:41,649 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,649 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653523358] [2021-07-06 20:41:41,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,650 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,715 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,716 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,717 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,717 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,720 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,723 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,726 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,726 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653523358] [2021-07-06 20:41:41,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653523358] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,727 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491432990] [2021-07-06 20:41:41,728 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,729 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,729 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,730 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,730 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,740 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2021-07-06 20:41:41,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2021-07-06 20:41:41,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,747 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2021-07-06 20:41:41,747 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-07-06 20:41:41,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-07-06 20:41:41,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2021-07-06 20:41:41,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,749 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-07-06 20:41:41,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2021-07-06 20:41:41,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-07-06 20:41:41,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5150375939849625) internal successors, (806), 531 states have internal predecessors, (806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2021-07-06 20:41:41,757 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-07-06 20:41:41,760 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-07-06 20:41:41,760 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-07-06 20:41:41,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2021-07-06 20:41:41,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,764 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,764 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,765 INFO L791 eck$LassoCheckResult]: Stem: 3660#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3564#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3510#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3325#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 3326#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3423#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3424#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3327#L433-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3328#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3519#L443-1 assume !(0 == ~M_E~0); 3520#L603-1 assume !(0 == ~T1_E~0); 3525#L608-1 assume !(0 == ~T2_E~0); 3526#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3448#L618-1 assume !(0 == ~T4_E~0); 3449#L623-1 assume !(0 == ~T5_E~0); 3503#L628-1 assume !(0 == ~E_M~0); 3395#L633-1 assume !(0 == ~E_1~0); 3396#L638-1 assume !(0 == ~E_2~0); 3232#L643-1 assume !(0 == ~E_3~0); 3233#L648-1 assume !(0 == ~E_4~0); 3339#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3340#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3562#L296 assume 1 == ~m_pc~0; 3563#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3550#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3572#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3636#L747 assume !(0 != activate_threads_~tmp~1); 3628#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3629#L315 assume !(1 == ~t1_pc~0); 3698#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 3699#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3727#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3739#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3740#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3292#L334 assume 1 == ~t2_pc~0; 3293#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3290#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3291#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3349#L763 assume !(0 != activate_threads_~tmp___1~0); 3333#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3334#L353 assume !(1 == ~t3_pc~0); 3429#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 3430#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3426#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3427#L771 assume !(0 != activate_threads_~tmp___2~0); 3651#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3643#L372 assume 1 == ~t4_pc~0; 3622#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3623#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3619#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3620#L779 assume !(0 != activate_threads_~tmp___3~0); 3750#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3385#L391 assume !(1 == ~t5_pc~0); 3386#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 3381#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3382#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3408#L787 assume !(0 != activate_threads_~tmp___4~0); 3409#L787-2 assume !(1 == ~M_E~0); 3410#L671-1 assume !(1 == ~T1_E~0); 3230#L676-1 assume !(1 == ~T2_E~0); 3231#L681-1 assume !(1 == ~T3_E~0); 3337#L686-1 assume !(1 == ~T4_E~0); 3338#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3521#L696-1 assume !(1 == ~E_M~0); 3522#L701-1 assume !(1 == ~E_1~0); 3460#L706-1 assume !(1 == ~E_2~0); 3461#L711-1 assume !(1 == ~E_3~0); 3652#L716-1 assume !(1 == ~E_4~0); 3412#L721-1 assume !(1 == ~E_5~0); 3413#L932-1 [2021-07-06 20:41:41,765 INFO L793 eck$LassoCheckResult]: Loop: 3413#L932-1 assume !false; 3676#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3399#L578 assume !false; 3311#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3312#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3317#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3318#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3416#L503 assume !(0 != eval_~tmp~0); 3632#L593 start_simulation_~kernel_st~0 := 2; 3330#L411-1 start_simulation_~kernel_st~0 := 3; 3331#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3747#L603-4 assume !(0 == ~T1_E~0); 3514#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3515#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3451#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3452#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3505#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3402#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3403#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3240#L643-3 assume !(0 == ~E_3~0); 3241#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3345#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3346#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3669#L296-21 assume !(1 == ~m_pc~0); 3664#L296-23 is_master_triggered_~__retres1~0 := 0; 3556#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3557#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3558#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3559#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3671#L315-21 assume 1 == ~t1_pc~0; 3756#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3721#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3722#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3684#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3685#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3227#L334-21 assume 1 == ~t2_pc~0; 3228#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3234#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3282#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3287#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3256#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3257#L353-21 assume 1 == ~t3_pc~0; 3458#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3462#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3493#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3476#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3477#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3482#L372-21 assume 1 == ~t4_pc~0; 3536#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3537#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3532#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3533#L779-21 assume !(0 != activate_threads_~tmp___3~0); 3637#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3638#L391-21 assume 1 == ~t5_pc~0; 3709#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3367#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3368#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3708#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3746#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3670#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3235#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3236#L681-3 assume !(1 == ~T3_E~0); 3342#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3343#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3523#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3524#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3463#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3464#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3500#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3393#L721-3 assume !(1 == ~E_5~0); 3394#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3419#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3321#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3322#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3265#L951 assume !(0 == start_simulation_~tmp~3); 3266#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3269#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3323#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3324#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 3421#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3509#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 3653#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 3654#L964 assume !(0 != start_simulation_~tmp___0~1); 3413#L932-1 [2021-07-06 20:41:41,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,771 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-07-06 20:41:41,771 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,771 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [618938883] [2021-07-06 20:41:41,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,771 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,807 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,807 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,808 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,808 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,811 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,812 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,815 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [618938883] [2021-07-06 20:41:41,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [618938883] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,815 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,815 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473051953] [2021-07-06 20:41:41,816 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,816 INFO L82 PathProgramCache]: Analyzing trace with hash -1441897031, now seen corresponding path program 1 times [2021-07-06 20:41:41,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,817 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069096184] [2021-07-06 20:41:41,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,817 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,845 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,846 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,846 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,847 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,861 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,862 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,863 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2069096184] [2021-07-06 20:41:41,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2069096184] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,863 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,863 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,863 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82581700] [2021-07-06 20:41:41,864 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,864 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,864 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,864 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,865 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,875 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2021-07-06 20:41:41,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,875 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2021-07-06 20:41:41,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2021-07-06 20:41:41,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-07-06 20:41:41,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-07-06 20:41:41,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2021-07-06 20:41:41,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,883 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-07-06 20:41:41,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2021-07-06 20:41:41,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-07-06 20:41:41,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.513157894736842) internal successors, (805), 531 states have internal predecessors, (805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2021-07-06 20:41:41,891 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-07-06 20:41:41,891 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-07-06 20:41:41,892 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-07-06 20:41:41,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2021-07-06 20:41:41,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,895 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,896 INFO L791 eck$LassoCheckResult]: Stem: 4731#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4635#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4581#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4396#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 4397#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4494#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4495#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4398#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4399#L438-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4590#L443-1 assume !(0 == ~M_E~0); 4591#L603-1 assume !(0 == ~T1_E~0); 4596#L608-1 assume !(0 == ~T2_E~0); 4597#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4519#L618-1 assume !(0 == ~T4_E~0); 4520#L623-1 assume !(0 == ~T5_E~0); 4574#L628-1 assume !(0 == ~E_M~0); 4466#L633-1 assume !(0 == ~E_1~0); 4467#L638-1 assume !(0 == ~E_2~0); 4303#L643-1 assume !(0 == ~E_3~0); 4304#L648-1 assume !(0 == ~E_4~0); 4410#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4411#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4633#L296 assume 1 == ~m_pc~0; 4634#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4621#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4646#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4707#L747 assume !(0 != activate_threads_~tmp~1); 4699#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4700#L315 assume !(1 == ~t1_pc~0); 4769#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 4770#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4798#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4810#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4811#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4363#L334 assume 1 == ~t2_pc~0; 4364#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4361#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4362#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4420#L763 assume !(0 != activate_threads_~tmp___1~0); 4404#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4405#L353 assume !(1 == ~t3_pc~0); 4500#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 4501#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4497#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4498#L771 assume !(0 != activate_threads_~tmp___2~0); 4722#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4714#L372 assume 1 == ~t4_pc~0; 4693#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4694#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4690#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4691#L779 assume !(0 != activate_threads_~tmp___3~0); 4821#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4456#L391 assume !(1 == ~t5_pc~0); 4457#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 4452#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4453#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4479#L787 assume !(0 != activate_threads_~tmp___4~0); 4480#L787-2 assume !(1 == ~M_E~0); 4481#L671-1 assume !(1 == ~T1_E~0); 4301#L676-1 assume !(1 == ~T2_E~0); 4302#L681-1 assume !(1 == ~T3_E~0); 4408#L686-1 assume !(1 == ~T4_E~0); 4409#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4592#L696-1 assume !(1 == ~E_M~0); 4593#L701-1 assume !(1 == ~E_1~0); 4531#L706-1 assume !(1 == ~E_2~0); 4532#L711-1 assume !(1 == ~E_3~0); 4723#L716-1 assume !(1 == ~E_4~0); 4483#L721-1 assume !(1 == ~E_5~0); 4484#L932-1 [2021-07-06 20:41:41,896 INFO L793 eck$LassoCheckResult]: Loop: 4484#L932-1 assume !false; 4747#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4470#L578 assume !false; 4382#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4383#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4388#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4389#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4487#L503 assume !(0 != eval_~tmp~0); 4703#L593 start_simulation_~kernel_st~0 := 2; 4401#L411-1 start_simulation_~kernel_st~0 := 3; 4402#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4818#L603-4 assume !(0 == ~T1_E~0); 4585#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4586#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4522#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4523#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4576#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4473#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4474#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4311#L643-3 assume !(0 == ~E_3~0); 4312#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4416#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4417#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4740#L296-21 assume 1 == ~m_pc~0; 4734#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4627#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4628#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4629#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4630#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4742#L315-21 assume 1 == ~t1_pc~0; 4827#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4792#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4793#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4755#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4756#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4298#L334-21 assume 1 == ~t2_pc~0; 4299#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4305#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4353#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4357#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4327#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4328#L353-21 assume 1 == ~t3_pc~0; 4529#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4533#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4564#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4547#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4548#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4553#L372-21 assume !(1 == ~t4_pc~0); 4609#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 4608#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4603#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4604#L779-21 assume !(0 != activate_threads_~tmp___3~0); 4708#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4709#L391-21 assume 1 == ~t5_pc~0; 4780#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4438#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4439#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4779#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4817#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4741#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4306#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4307#L681-3 assume !(1 == ~T3_E~0); 4413#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4414#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4594#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4595#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4534#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4535#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4571#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4464#L721-3 assume !(1 == ~E_5~0); 4465#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4490#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4392#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4393#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4336#L951 assume !(0 == start_simulation_~tmp~3); 4337#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4340#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4394#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4395#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 4492#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4580#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 4724#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 4725#L964 assume !(0 != start_simulation_~tmp___0~1); 4484#L932-1 [2021-07-06 20:41:41,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,896 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-07-06 20:41:41,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,897 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621581752] [2021-07-06 20:41:41,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,897 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,912 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,912 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,913 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,913 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:41,916 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,916 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,917 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621581752] [2021-07-06 20:41:41,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621581752] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,917 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045285460] [2021-07-06 20:41:41,918 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:41,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,918 INFO L82 PathProgramCache]: Analyzing trace with hash -1300229447, now seen corresponding path program 1 times [2021-07-06 20:41:41,918 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,919 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574472977] [2021-07-06 20:41:41,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,919 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:41,937 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,938 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,938 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,939 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:41,942 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:41,942 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:41,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:41,943 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:41,943 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574472977] [2021-07-06 20:41:41,943 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574472977] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:41,943 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:41,943 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:41,943 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [798258218] [2021-07-06 20:41:41,944 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:41,944 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:41,944 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:41,944 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:41,945 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:41,954 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-07-06 20:41:41,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:41,955 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-07-06 20:41:41,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2021-07-06 20:41:41,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-07-06 20:41:41,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-07-06 20:41:41,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2021-07-06 20:41:41,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:41,976 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-07-06 20:41:41,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2021-07-06 20:41:41,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-07-06 20:41:41,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5112781954887218) internal successors, (804), 531 states have internal predecessors, (804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:41,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2021-07-06 20:41:41,984 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-07-06 20:41:41,985 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-07-06 20:41:41,985 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-07-06 20:41:41,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2021-07-06 20:41:41,987 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-07-06 20:41:41,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:41,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:41,988 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,988 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:41,989 INFO L791 eck$LassoCheckResult]: Stem: 5802#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5709#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5652#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5467#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 5468#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5565#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5566#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5470#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5471#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5661#L443-1 assume !(0 == ~M_E~0); 5662#L603-1 assume !(0 == ~T1_E~0); 5667#L608-1 assume !(0 == ~T2_E~0); 5668#L613-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5590#L618-1 assume !(0 == ~T4_E~0); 5591#L623-1 assume !(0 == ~T5_E~0); 5645#L628-1 assume !(0 == ~E_M~0); 5537#L633-1 assume !(0 == ~E_1~0); 5538#L638-1 assume !(0 == ~E_2~0); 5374#L643-1 assume !(0 == ~E_3~0); 5375#L648-1 assume !(0 == ~E_4~0); 5481#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5482#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5704#L296 assume 1 == ~m_pc~0; 5705#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5692#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5717#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5778#L747 assume !(0 != activate_threads_~tmp~1); 5770#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5771#L315 assume !(1 == ~t1_pc~0); 5840#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 5841#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5869#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5881#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5882#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5434#L334 assume 1 == ~t2_pc~0; 5435#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5432#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5433#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5491#L763 assume !(0 != activate_threads_~tmp___1~0); 5475#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5476#L353 assume !(1 == ~t3_pc~0); 5571#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 5572#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5568#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5569#L771 assume !(0 != activate_threads_~tmp___2~0); 5793#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5785#L372 assume 1 == ~t4_pc~0; 5764#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5765#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5761#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5762#L779 assume !(0 != activate_threads_~tmp___3~0); 5892#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5527#L391 assume !(1 == ~t5_pc~0); 5528#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 5523#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5524#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5550#L787 assume !(0 != activate_threads_~tmp___4~0); 5551#L787-2 assume !(1 == ~M_E~0); 5552#L671-1 assume !(1 == ~T1_E~0); 5372#L676-1 assume !(1 == ~T2_E~0); 5373#L681-1 assume !(1 == ~T3_E~0); 5479#L686-1 assume !(1 == ~T4_E~0); 5480#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5663#L696-1 assume !(1 == ~E_M~0); 5664#L701-1 assume !(1 == ~E_1~0); 5602#L706-1 assume !(1 == ~E_2~0); 5603#L711-1 assume !(1 == ~E_3~0); 5794#L716-1 assume !(1 == ~E_4~0); 5554#L721-1 assume !(1 == ~E_5~0); 5555#L932-1 [2021-07-06 20:41:41,989 INFO L793 eck$LassoCheckResult]: Loop: 5555#L932-1 assume !false; 5818#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5541#L578 assume !false; 5453#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5454#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5459#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5460#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5558#L503 assume !(0 != eval_~tmp~0); 5774#L593 start_simulation_~kernel_st~0 := 2; 5472#L411-1 start_simulation_~kernel_st~0 := 3; 5473#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5889#L603-4 assume !(0 == ~T1_E~0); 5656#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5657#L613-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5593#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5594#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5647#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5544#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5545#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5382#L643-3 assume !(0 == ~E_3~0); 5383#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5487#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5488#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5811#L296-21 assume 1 == ~m_pc~0; 5805#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5698#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5699#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5700#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5701#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5813#L315-21 assume 1 == ~t1_pc~0; 5898#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5863#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5864#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5824#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5825#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5369#L334-21 assume 1 == ~t2_pc~0; 5370#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5376#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5424#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5428#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5398#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5399#L353-21 assume 1 == ~t3_pc~0; 5600#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5604#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5635#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5618#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5619#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5624#L372-21 assume !(1 == ~t4_pc~0); 5680#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 5679#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5674#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5675#L779-21 assume !(0 != activate_threads_~tmp___3~0); 5779#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5780#L391-21 assume 1 == ~t5_pc~0; 5851#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5509#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5510#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5850#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5888#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5812#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5377#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5378#L681-3 assume !(1 == ~T3_E~0); 5484#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5485#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5665#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5666#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5605#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5606#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5642#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5535#L721-3 assume !(1 == ~E_5~0); 5536#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5561#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5463#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5464#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5407#L951 assume !(0 == start_simulation_~tmp~3); 5408#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5411#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5465#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5466#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 5563#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5651#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 5795#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 5796#L964 assume !(0 != start_simulation_~tmp___0~1); 5555#L932-1 [2021-07-06 20:41:41,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:41,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-07-06 20:41:41,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:41,990 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [458376113] [2021-07-06 20:41:41,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:41,990 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:41,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,009 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,010 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,013 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,014 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:42,017 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,018 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,018 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,019 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [458376113] [2021-07-06 20:41:42,019 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [458376113] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,019 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,019 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,019 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68604954] [2021-07-06 20:41:42,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1300229447, now seen corresponding path program 2 times [2021-07-06 20:41:42,020 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,020 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87361507] [2021-07-06 20:41:42,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,020 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,051 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,052 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,054 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,054 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:42,057 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,057 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,058 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,058 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87361507] [2021-07-06 20:41:42,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87361507] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,059 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,059 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,059 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677703572] [2021-07-06 20:41:42,059 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,061 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,061 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:42,061 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:42,062 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:42,153 INFO L93 Difference]: Finished difference Result 946 states and 1423 transitions. [2021-07-06 20:41:42,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:42,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 946 states and 1423 transitions. [2021-07-06 20:41:42,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 860 [2021-07-06 20:41:42,165 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 946 states to 946 states and 1423 transitions. [2021-07-06 20:41:42,165 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 946 [2021-07-06 20:41:42,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 946 [2021-07-06 20:41:42,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 946 states and 1423 transitions. [2021-07-06 20:41:42,167 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:42,167 INFO L681 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2021-07-06 20:41:42,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 946 states and 1423 transitions. [2021-07-06 20:41:42,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 946 to 946. [2021-07-06 20:41:42,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 946 states, 946 states have (on average 1.5042283298097252) internal successors, (1423), 945 states have internal predecessors, (1423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 946 states to 946 states and 1423 transitions. [2021-07-06 20:41:42,187 INFO L704 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2021-07-06 20:41:42,187 INFO L587 BuchiCegarLoop]: Abstraction has 946 states and 1423 transitions. [2021-07-06 20:41:42,187 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-07-06 20:41:42,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 946 states and 1423 transitions. [2021-07-06 20:41:42,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 860 [2021-07-06 20:41:42,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:42,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:42,192 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,192 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,193 INFO L791 eck$LassoCheckResult]: Stem: 7318#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7214#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7152#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6957#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 6958#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7062#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7063#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6960#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6961#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7162#L443-1 assume !(0 == ~M_E~0); 7163#L603-1 assume !(0 == ~T1_E~0); 7168#L608-1 assume !(0 == ~T2_E~0); 7169#L613-1 assume !(0 == ~T3_E~0); 7087#L618-1 assume !(0 == ~T4_E~0); 7088#L623-1 assume !(0 == ~T5_E~0); 7145#L628-1 assume !(0 == ~E_M~0); 7029#L633-1 assume !(0 == ~E_1~0); 7030#L638-1 assume !(0 == ~E_2~0); 6862#L643-1 assume !(0 == ~E_3~0); 6863#L648-1 assume !(0 == ~E_4~0); 6971#L653-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6972#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7209#L296 assume 1 == ~m_pc~0; 7210#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7199#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7222#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7286#L747 assume !(0 != activate_threads_~tmp~1); 7276#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7277#L315 assume !(1 == ~t1_pc~0); 7363#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 7364#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7394#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7407#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7408#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6923#L334 assume 1 == ~t2_pc~0; 6924#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6921#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6922#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6981#L763 assume !(0 != activate_threads_~tmp___1~0); 6965#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6966#L353 assume !(1 == ~t3_pc~0); 7068#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 7069#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7065#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7066#L771 assume !(0 != activate_threads_~tmp___2~0); 7309#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7298#L372 assume 1 == ~t4_pc~0; 7269#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7270#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7267#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7268#L779 assume !(0 != activate_threads_~tmp___3~0); 7425#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7018#L391 assume !(1 == ~t5_pc~0); 7019#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 7014#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7015#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7042#L787 assume !(0 != activate_threads_~tmp___4~0); 7043#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 7044#L671-1 assume !(1 == ~T1_E~0); 6860#L676-1 assume !(1 == ~T2_E~0); 6861#L681-1 assume !(1 == ~T3_E~0); 6969#L686-1 assume !(1 == ~T4_E~0); 6970#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7164#L696-1 assume !(1 == ~E_M~0); 7165#L701-1 assume !(1 == ~E_1~0); 7099#L706-1 assume !(1 == ~E_2~0); 7100#L711-1 assume !(1 == ~E_3~0); 7310#L716-1 assume !(1 == ~E_4~0); 7047#L721-1 assume !(1 == ~E_5~0); 7048#L932-1 [2021-07-06 20:41:42,193 INFO L793 eck$LassoCheckResult]: Loop: 7048#L932-1 assume !false; 7340#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7033#L578 assume !false; 6945#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6946#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6949#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6950#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7441#L503 assume !(0 != eval_~tmp~0); 7440#L593 start_simulation_~kernel_st~0 := 2; 7439#L411-1 start_simulation_~kernel_st~0 := 3; 7438#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7420#L603-4 assume !(0 == ~T1_E~0); 7157#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7158#L613-3 assume !(0 == ~T3_E~0); 7090#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7091#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7147#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7036#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7037#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6870#L643-3 assume !(0 == ~E_3~0); 6871#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6977#L653-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6978#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7331#L296-21 assume 1 == ~m_pc~0; 7321#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7203#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7204#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7205#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7206#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7335#L315-21 assume 1 == ~t1_pc~0; 7431#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7388#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7389#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7346#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7347#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6857#L334-21 assume 1 == ~t2_pc~0; 6858#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6864#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6913#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6918#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6886#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6887#L353-21 assume 1 == ~t3_pc~0; 7097#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7101#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7135#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7117#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7118#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7123#L372-21 assume 1 == ~t4_pc~0; 7185#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7186#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7181#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7182#L779-21 assume !(0 != activate_threads_~tmp___3~0); 7287#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7288#L391-21 assume 1 == ~t5_pc~0; 7379#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6999#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7000#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7375#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7414#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7333#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6865#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6866#L681-3 assume !(1 == ~T3_E~0); 6974#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6975#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7166#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7167#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7102#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7103#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7142#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7027#L721-3 assume !(1 == ~E_5~0); 7028#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7058#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6953#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6954#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6895#L951 assume !(0 == start_simulation_~tmp~3); 6896#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6899#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6955#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6956#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 7060#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7151#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 7311#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 7312#L964 assume !(0 != start_simulation_~tmp___0~1); 7048#L932-1 [2021-07-06 20:41:42,193 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,194 INFO L82 PathProgramCache]: Analyzing trace with hash -515799174, now seen corresponding path program 1 times [2021-07-06 20:41:42,194 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,194 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407751353] [2021-07-06 20:41:42,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,194 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,211 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,211 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,215 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,215 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:42,220 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,221 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407751353] [2021-07-06 20:41:42,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407751353] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,222 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,222 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,222 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1366317148] [2021-07-06 20:41:42,223 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,223 INFO L82 PathProgramCache]: Analyzing trace with hash -1921922344, now seen corresponding path program 1 times [2021-07-06 20:41:42,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,223 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1738789898] [2021-07-06 20:41:42,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,224 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,248 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,248 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,249 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,249 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:42,253 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,253 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,256 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1738789898] [2021-07-06 20:41:42,256 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1738789898] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,256 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,256 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,257 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294866801] [2021-07-06 20:41:42,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,257 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,257 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:42,258 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:42,258 INFO L87 Difference]: Start difference. First operand 946 states and 1423 transitions. cyclomatic complexity: 479 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:42,371 INFO L93 Difference]: Finished difference Result 1676 states and 2514 transitions. [2021-07-06 20:41:42,372 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:42,372 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1676 states and 2514 transitions. [2021-07-06 20:41:42,402 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1580 [2021-07-06 20:41:42,410 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1676 states to 1676 states and 2514 transitions. [2021-07-06 20:41:42,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1676 [2021-07-06 20:41:42,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1676 [2021-07-06 20:41:42,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1676 states and 2514 transitions. [2021-07-06 20:41:42,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:42,413 INFO L681 BuchiCegarLoop]: Abstraction has 1676 states and 2514 transitions. [2021-07-06 20:41:42,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1676 states and 2514 transitions. [2021-07-06 20:41:42,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1676 to 1674. [2021-07-06 20:41:42,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1674 states, 1674 states have (on average 1.5005973715651135) internal successors, (2512), 1673 states have internal predecessors, (2512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1674 states to 1674 states and 2512 transitions. [2021-07-06 20:41:42,439 INFO L704 BuchiCegarLoop]: Abstraction has 1674 states and 2512 transitions. [2021-07-06 20:41:42,439 INFO L587 BuchiCegarLoop]: Abstraction has 1674 states and 2512 transitions. [2021-07-06 20:41:42,439 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-07-06 20:41:42,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1674 states and 2512 transitions. [2021-07-06 20:41:42,447 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1580 [2021-07-06 20:41:42,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:42,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:42,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,449 INFO L791 eck$LassoCheckResult]: Stem: 9949#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9843#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9784#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9588#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 9589#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9695#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9696#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9591#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9592#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9793#L443-1 assume !(0 == ~M_E~0); 9794#L603-1 assume !(0 == ~T1_E~0); 9799#L608-1 assume !(0 == ~T2_E~0); 9800#L613-1 assume !(0 == ~T3_E~0); 9720#L618-1 assume !(0 == ~T4_E~0); 9721#L623-1 assume !(0 == ~T5_E~0); 9777#L628-1 assume !(0 == ~E_M~0); 9661#L633-1 assume !(0 == ~E_1~0); 9662#L638-1 assume !(0 == ~E_2~0); 9494#L643-1 assume !(0 == ~E_3~0); 9495#L648-1 assume !(0 == ~E_4~0); 9602#L653-1 assume !(0 == ~E_5~0); 9603#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9838#L296 assume 1 == ~m_pc~0; 9839#L297 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 9828#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9851#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9915#L747 assume !(0 != activate_threads_~tmp~1); 9904#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9905#L315 assume !(1 == ~t1_pc~0); 9990#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 9991#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10021#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10034#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10035#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9554#L334 assume 1 == ~t2_pc~0; 9555#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9552#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9553#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9612#L763 assume !(0 != activate_threads_~tmp___1~0); 9596#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9597#L353 assume !(1 == ~t3_pc~0); 9701#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 9702#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9698#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9699#L771 assume !(0 != activate_threads_~tmp___2~0); 9938#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9928#L372 assume 1 == ~t4_pc~0; 9898#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9899#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9896#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9897#L779 assume !(0 != activate_threads_~tmp___3~0); 10048#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9650#L391 assume !(1 == ~t5_pc~0); 9651#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 9646#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9647#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9674#L787 assume !(0 != activate_threads_~tmp___4~0); 9675#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 9676#L671-1 assume !(1 == ~T1_E~0); 10129#L676-1 assume !(1 == ~T2_E~0); 10128#L681-1 assume !(1 == ~T3_E~0); 10127#L686-1 assume !(1 == ~T4_E~0); 10126#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10106#L696-1 assume !(1 == ~E_M~0); 10104#L701-1 assume !(1 == ~E_1~0); 10103#L706-1 assume !(1 == ~E_2~0); 10036#L711-1 assume !(1 == ~E_3~0); 9939#L716-1 assume !(1 == ~E_4~0); 9940#L721-1 assume !(1 == ~E_5~0); 10081#L932-1 [2021-07-06 20:41:42,449 INFO L793 eck$LassoCheckResult]: Loop: 10081#L932-1 assume !false; 10076#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10075#L578 assume !false; 10074#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10068#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10067#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10066#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 10064#L503 assume !(0 != eval_~tmp~0); 10063#L593 start_simulation_~kernel_st~0 := 2; 10062#L411-1 start_simulation_~kernel_st~0 := 3; 10060#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10061#L603-4 assume !(0 == ~T1_E~0); 10583#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10580#L613-3 assume !(0 == ~T3_E~0); 10577#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10574#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10571#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10568#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10565#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10562#L643-3 assume !(0 == ~E_3~0); 10559#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10556#L653-3 assume !(0 == ~E_5~0); 10553#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10550#L296-21 assume 1 == ~m_pc~0; 10544#L297-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10541#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10538#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10535#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10532#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10530#L315-21 assume !(1 == ~t1_pc~0); 10524#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 10521#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10518#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10515#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10512#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10509#L334-21 assume 1 == ~t2_pc~0; 10503#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10500#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10497#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10494#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10491#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10489#L353-21 assume !(1 == ~t3_pc~0); 10483#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 10479#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10477#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10473#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10471#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10469#L372-21 assume !(1 == ~t4_pc~0); 10464#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 10460#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10457#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10455#L779-21 assume !(0 != activate_threads_~tmp___3~0); 10453#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10450#L391-21 assume 1 == ~t5_pc~0; 10444#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10441#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10438#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10435#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10432#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 10043#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10427#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10424#L681-3 assume !(1 == ~T3_E~0); 10423#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10421#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10419#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10417#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10415#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10412#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10408#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10405#L721-3 assume !(1 == ~E_5~0); 10403#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10400#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10394#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10392#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 10389#L951 assume !(0 == start_simulation_~tmp~3); 9944#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 10243#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10217#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 10215#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 10153#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10124#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 10099#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 10087#L964 assume !(0 != start_simulation_~tmp___0~1); 10081#L932-1 [2021-07-06 20:41:42,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,450 INFO L82 PathProgramCache]: Analyzing trace with hash -531317892, now seen corresponding path program 1 times [2021-07-06 20:41:42,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190185917] [2021-07-06 20:41:42,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,451 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,468 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,469 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,472 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,472 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,473 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,473 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190185917] [2021-07-06 20:41:42,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190185917] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,473 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:42,473 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [145812751] [2021-07-06 20:41:42,474 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,474 INFO L82 PathProgramCache]: Analyzing trace with hash -765212557, now seen corresponding path program 1 times [2021-07-06 20:41:42,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,474 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [123543943] [2021-07-06 20:41:42,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,475 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,502 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,503 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,503 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,504 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:42,507 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,508 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,508 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,508 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [123543943] [2021-07-06 20:41:42,510 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [123543943] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,510 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,511 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818826511] [2021-07-06 20:41:42,511 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:42,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:42,512 INFO L87 Difference]: Start difference. First operand 1674 states and 2512 transitions. cyclomatic complexity: 842 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:42,580 INFO L93 Difference]: Finished difference Result 3198 states and 4735 transitions. [2021-07-06 20:41:42,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:42,581 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3198 states and 4735 transitions. [2021-07-06 20:41:42,602 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3101 [2021-07-06 20:41:42,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3198 states to 3198 states and 4735 transitions. [2021-07-06 20:41:42,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3198 [2021-07-06 20:41:42,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3198 [2021-07-06 20:41:42,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3198 states and 4735 transitions. [2021-07-06 20:41:42,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:42,627 INFO L681 BuchiCegarLoop]: Abstraction has 3198 states and 4735 transitions. [2021-07-06 20:41:42,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3198 states and 4735 transitions. [2021-07-06 20:41:42,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3198 to 3038. [2021-07-06 20:41:42,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3038 states, 3038 states have (on average 1.4848584595128373) internal successors, (4511), 3037 states have internal predecessors, (4511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:42,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3038 states to 3038 states and 4511 transitions. [2021-07-06 20:41:42,704 INFO L704 BuchiCegarLoop]: Abstraction has 3038 states and 4511 transitions. [2021-07-06 20:41:42,704 INFO L587 BuchiCegarLoop]: Abstraction has 3038 states and 4511 transitions. [2021-07-06 20:41:42,704 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-07-06 20:41:42,704 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3038 states and 4511 transitions. [2021-07-06 20:41:42,718 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2941 [2021-07-06 20:41:42,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:42,718 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:42,719 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,719 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:42,720 INFO L791 eck$LassoCheckResult]: Stem: 14841#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 14725#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14669#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14468#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 14469#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14579#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14580#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14470#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14471#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14678#L443-1 assume !(0 == ~M_E~0); 14679#L603-1 assume !(0 == ~T1_E~0); 14685#L608-1 assume !(0 == ~T2_E~0); 14686#L613-1 assume !(0 == ~T3_E~0); 14603#L618-1 assume !(0 == ~T4_E~0); 14604#L623-1 assume !(0 == ~T5_E~0); 14662#L628-1 assume !(0 == ~E_M~0); 14544#L633-1 assume !(0 == ~E_1~0); 14545#L638-1 assume !(0 == ~E_2~0); 14373#L643-1 assume !(0 == ~E_3~0); 14374#L648-1 assume !(0 == ~E_4~0); 14482#L653-1 assume !(0 == ~E_5~0); 14483#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14722#L296 assume !(1 == ~m_pc~0); 14708#L296-2 is_master_triggered_~__retres1~0 := 0; 14709#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14733#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14801#L747 assume !(0 != activate_threads_~tmp~1); 14789#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14790#L315 assume !(1 == ~t1_pc~0); 14892#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 14893#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14922#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14934#L755 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14935#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14434#L334 assume 1 == ~t2_pc~0; 14435#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14432#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14433#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 14492#L763 assume !(0 != activate_threads_~tmp___1~0); 14476#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14477#L353 assume !(1 == ~t3_pc~0); 14586#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 14587#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14583#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 14584#L771 assume !(0 != activate_threads_~tmp___2~0); 14822#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14809#L372 assume 1 == ~t4_pc~0; 14783#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14784#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14780#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 14781#L779 assume !(0 != activate_threads_~tmp___3~0); 14952#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14529#L391 assume !(1 == ~t5_pc~0); 14530#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 14524#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14525#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14555#L787 assume !(0 != activate_threads_~tmp___4~0); 14556#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 14559#L671-1 assume !(1 == ~T1_E~0); 14371#L676-1 assume !(1 == ~T2_E~0); 14372#L681-1 assume !(1 == ~T3_E~0); 14791#L686-1 assume !(1 == ~T4_E~0); 16334#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16332#L696-1 assume !(1 == ~E_M~0); 16330#L701-1 assume !(1 == ~E_1~0); 16327#L706-1 assume !(1 == ~E_2~0); 14936#L711-1 assume !(1 == ~E_3~0); 14823#L716-1 assume !(1 == ~E_4~0); 14824#L721-1 assume !(1 == ~E_5~0); 16171#L932-1 [2021-07-06 20:41:42,720 INFO L793 eck$LassoCheckResult]: Loop: 16171#L932-1 assume !false; 15998#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 15997#L578 assume !false; 15996#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15979#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15977#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15975#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 15973#L503 assume !(0 != eval_~tmp~0); 15974#L593 start_simulation_~kernel_st~0 := 2; 16590#L411-1 start_simulation_~kernel_st~0 := 3; 16588#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16586#L603-4 assume !(0 == ~T1_E~0); 16584#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16582#L613-3 assume !(0 == ~T3_E~0); 16580#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16577#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16575#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16573#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16571#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16569#L643-3 assume !(0 == ~E_3~0); 16567#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16564#L653-3 assume !(0 == ~E_5~0); 16562#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16560#L296-21 assume !(1 == ~m_pc~0); 16558#L296-23 is_master_triggered_~__retres1~0 := 0; 16556#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16554#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16553#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16550#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16548#L315-21 assume !(1 == ~t1_pc~0); 16545#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 16543#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16541#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16539#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16536#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16534#L334-21 assume 1 == ~t2_pc~0; 16531#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16529#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16527#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16525#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16524#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16523#L353-21 assume !(1 == ~t3_pc~0); 16521#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 16519#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16517#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16515#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16513#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16511#L372-21 assume 1 == ~t4_pc~0; 16505#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16503#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16501#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16499#L779-21 assume !(0 != activate_threads_~tmp___3~0); 16497#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16495#L391-21 assume 1 == ~t5_pc~0; 16485#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16480#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16475#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16470#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16465#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 14948#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16454#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16448#L681-3 assume !(1 == ~T3_E~0); 16445#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16441#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16437#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16433#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16427#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16423#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16420#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16417#L721-3 assume !(1 == ~E_5~0); 16415#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16255#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16249#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16247#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 16245#L951 assume !(0 == start_simulation_~tmp~3); 14828#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16199#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16194#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16192#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 16190#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16188#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 16185#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 16174#L964 assume !(0 != start_simulation_~tmp___0~1); 16171#L932-1 [2021-07-06 20:41:42,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1870207229, now seen corresponding path program 1 times [2021-07-06 20:41:42,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,721 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913030446] [2021-07-06 20:41:42,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,721 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,742 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,743 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,743 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,744 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,747 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,747 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,751 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,751 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:42,756 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,757 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,757 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,757 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913030446] [2021-07-06 20:41:42,757 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913030446] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,758 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,758 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:42,758 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312309377] [2021-07-06 20:41:42,758 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:42,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:42,759 INFO L82 PathProgramCache]: Analyzing trace with hash -906880141, now seen corresponding path program 1 times [2021-07-06 20:41:42,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:42,759 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553319657] [2021-07-06 20:41:42,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:42,759 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:42,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:42,772 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,774 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,774 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,775 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:42,778 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:42,778 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:42,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:42,779 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:42,779 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553319657] [2021-07-06 20:41:42,779 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553319657] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:42,779 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:42,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:42,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160587838] [2021-07-06 20:41:42,780 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:42,780 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:42,780 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:42,780 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:42,780 INFO L87 Difference]: Start difference. First operand 3038 states and 4511 transitions. cyclomatic complexity: 1481 Second operand has 5 states, 5 states have (on average 13.8) internal successors, (69), 5 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:43,009 INFO L93 Difference]: Finished difference Result 8268 states and 12255 transitions. [2021-07-06 20:41:43,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-07-06 20:41:43,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8268 states and 12255 transitions. [2021-07-06 20:41:43,068 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8042 [2021-07-06 20:41:43,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8268 states to 8268 states and 12255 transitions. [2021-07-06 20:41:43,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8268 [2021-07-06 20:41:43,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8268 [2021-07-06 20:41:43,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8268 states and 12255 transitions. [2021-07-06 20:41:43,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:43,143 INFO L681 BuchiCegarLoop]: Abstraction has 8268 states and 12255 transitions. [2021-07-06 20:41:43,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8268 states and 12255 transitions. [2021-07-06 20:41:43,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8268 to 3191. [2021-07-06 20:41:43,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3191 states, 3191 states have (on average 1.461610780319649) internal successors, (4664), 3190 states have internal predecessors, (4664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3191 states to 3191 states and 4664 transitions. [2021-07-06 20:41:43,266 INFO L704 BuchiCegarLoop]: Abstraction has 3191 states and 4664 transitions. [2021-07-06 20:41:43,266 INFO L587 BuchiCegarLoop]: Abstraction has 3191 states and 4664 transitions. [2021-07-06 20:41:43,266 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-07-06 20:41:43,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3191 states and 4664 transitions. [2021-07-06 20:41:43,279 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3091 [2021-07-06 20:41:43,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:43,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:43,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,280 INFO L791 eck$LassoCheckResult]: Stem: 26162#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 26043#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 25988#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25787#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 25788#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25895#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25896#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25789#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25790#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25996#L443-1 assume !(0 == ~M_E~0); 25997#L603-1 assume !(0 == ~T1_E~0); 26003#L608-1 assume !(0 == ~T2_E~0); 26004#L613-1 assume !(0 == ~T3_E~0); 25919#L618-1 assume !(0 == ~T4_E~0); 25920#L623-1 assume !(0 == ~T5_E~0); 25981#L628-1 assume !(0 == ~E_M~0); 25862#L633-1 assume !(0 == ~E_1~0); 25863#L638-1 assume !(0 == ~E_2~0); 25692#L643-1 assume !(0 == ~E_3~0); 25693#L648-1 assume !(0 == ~E_4~0); 25801#L653-1 assume !(0 == ~E_5~0); 25802#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26040#L296 assume !(1 == ~m_pc~0); 26026#L296-2 is_master_triggered_~__retres1~0 := 0; 26027#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26051#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26121#L747 assume !(0 != activate_threads_~tmp~1); 26110#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26111#L315 assume !(1 == ~t1_pc~0); 26228#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 26229#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26266#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26282#L755 assume !(0 != activate_threads_~tmp___0~0); 26283#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25754#L334 assume 1 == ~t2_pc~0; 25755#L335 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25752#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25753#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 25811#L763 assume !(0 != activate_threads_~tmp___1~0); 25795#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25796#L353 assume !(1 == ~t3_pc~0); 25902#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 25903#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25899#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 25900#L771 assume !(0 != activate_threads_~tmp___2~0); 26145#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26132#L372 assume 1 == ~t4_pc~0; 26103#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26104#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26099#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26100#L779 assume !(0 != activate_threads_~tmp___3~0); 26300#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25848#L391 assume !(1 == ~t5_pc~0); 25849#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 25844#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 25845#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 25873#L787 assume !(0 != activate_threads_~tmp___4~0); 25874#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 25877#L671-1 assume !(1 == ~T1_E~0); 25690#L676-1 assume !(1 == ~T2_E~0); 25691#L681-1 assume !(1 == ~T3_E~0); 25799#L686-1 assume !(1 == ~T4_E~0); 25800#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26302#L696-1 assume !(1 == ~E_M~0); 26686#L701-1 assume !(1 == ~E_1~0); 26684#L706-1 assume !(1 == ~E_2~0); 26285#L711-1 assume !(1 == ~E_3~0); 26146#L716-1 assume !(1 == ~E_4~0); 26147#L721-1 assume !(1 == ~E_5~0); 26661#L932-1 [2021-07-06 20:41:43,281 INFO L793 eck$LassoCheckResult]: Loop: 26661#L932-1 assume !false; 26656#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 26655#L578 assume !false; 26654#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26648#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26647#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26646#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 26644#L503 assume !(0 != eval_~tmp~0); 26643#L593 start_simulation_~kernel_st~0 := 2; 26642#L411-1 start_simulation_~kernel_st~0 := 3; 26639#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 26640#L603-4 assume !(0 == ~T1_E~0); 27548#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27528#L613-3 assume !(0 == ~T3_E~0); 27335#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27331#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27328#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27323#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27040#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27038#L643-3 assume !(0 == ~E_3~0); 27037#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27036#L653-3 assume !(0 == ~E_5~0); 27035#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27034#L296-21 assume !(1 == ~m_pc~0); 27033#L296-23 is_master_triggered_~__retres1~0 := 0; 27032#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27031#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27030#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27029#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27028#L315-21 assume 1 == ~t1_pc~0; 27026#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27024#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27022#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27020#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27018#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27017#L334-21 assume 1 == ~t2_pc~0; 27015#L335-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 27014#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27013#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27011#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27006#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27004#L353-21 assume !(1 == ~t3_pc~0); 27001#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 27000#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26999#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 26998#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26997#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26996#L372-21 assume 1 == ~t4_pc~0; 26988#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26986#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26984#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26981#L779-21 assume !(0 != activate_threads_~tmp___3~0); 26977#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26976#L391-21 assume 1 == ~t5_pc~0; 26974#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26973#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26972#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26971#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 26967#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 26963#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26962#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26958#L681-3 assume !(1 == ~T3_E~0); 26956#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26953#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26951#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26949#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26947#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26942#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26940#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26936#L721-3 assume !(1 == ~E_5~0); 26899#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26851#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26841#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26792#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 26789#L951 assume !(0 == start_simulation_~tmp~3); 26787#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 26759#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 26754#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 26753#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 26750#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26711#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 26679#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 26667#L964 assume !(0 != start_simulation_~tmp___0~1); 26661#L932-1 [2021-07-06 20:41:43,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,282 INFO L82 PathProgramCache]: Analyzing trace with hash -1765228545, now seen corresponding path program 1 times [2021-07-06 20:41:43,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,282 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133380509] [2021-07-06 20:41:43,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,282 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,298 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,299 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,302 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,302 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:43,306 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,307 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,307 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133380509] [2021-07-06 20:41:43,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133380509] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,308 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:43,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951440760] [2021-07-06 20:41:43,308 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:43,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,309 INFO L82 PathProgramCache]: Analyzing trace with hash -1009681388, now seen corresponding path program 1 times [2021-07-06 20:41:43,309 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,309 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160050888] [2021-07-06 20:41:43,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,309 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,327 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,328 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,328 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,329 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:43,332 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,332 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,333 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160050888] [2021-07-06 20:41:43,333 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160050888] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,333 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,333 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:43,334 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [250350967] [2021-07-06 20:41:43,334 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:43,334 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:43,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:43,335 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:43,335 INFO L87 Difference]: Start difference. First operand 3191 states and 4664 transitions. cyclomatic complexity: 1481 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:43,496 INFO L93 Difference]: Finished difference Result 7490 states and 10816 transitions. [2021-07-06 20:41:43,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:43,496 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7490 states and 10816 transitions. [2021-07-06 20:41:43,570 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7187 [2021-07-06 20:41:43,603 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7490 states to 7490 states and 10816 transitions. [2021-07-06 20:41:43,603 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7490 [2021-07-06 20:41:43,609 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7490 [2021-07-06 20:41:43,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7490 states and 10816 transitions. [2021-07-06 20:41:43,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:43,618 INFO L681 BuchiCegarLoop]: Abstraction has 7490 states and 10816 transitions. [2021-07-06 20:41:43,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7490 states and 10816 transitions. [2021-07-06 20:41:43,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7490 to 5863. [2021-07-06 20:41:43,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5863 states, 5863 states have (on average 1.4535220876684292) internal successors, (8522), 5862 states have internal predecessors, (8522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:43,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5863 states to 5863 states and 8522 transitions. [2021-07-06 20:41:43,726 INFO L704 BuchiCegarLoop]: Abstraction has 5863 states and 8522 transitions. [2021-07-06 20:41:43,726 INFO L587 BuchiCegarLoop]: Abstraction has 5863 states and 8522 transitions. [2021-07-06 20:41:43,726 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-07-06 20:41:43,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5863 states and 8522 transitions. [2021-07-06 20:41:43,745 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5760 [2021-07-06 20:41:43,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:43,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:43,746 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,746 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:43,747 INFO L791 eck$LassoCheckResult]: Stem: 36859#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36749#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36687#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36471#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 36472#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36595#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36596#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36474#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36475#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36696#L443-1 assume !(0 == ~M_E~0); 36697#L603-1 assume !(0 == ~T1_E~0); 36702#L608-1 assume !(0 == ~T2_E~0); 36703#L613-1 assume !(0 == ~T3_E~0); 36620#L618-1 assume !(0 == ~T4_E~0); 36621#L623-1 assume !(0 == ~T5_E~0); 36680#L628-1 assume !(0 == ~E_M~0); 36544#L633-1 assume !(0 == ~E_1~0); 36545#L638-1 assume !(0 == ~E_2~0); 36382#L643-1 assume !(0 == ~E_3~0); 36383#L648-1 assume !(0 == ~E_4~0); 36485#L653-1 assume !(0 == ~E_5~0); 36486#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36746#L296 assume !(1 == ~m_pc~0); 36735#L296-2 is_master_triggered_~__retres1~0 := 0; 36736#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36760#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36822#L747 assume !(0 != activate_threads_~tmp~1); 36812#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36813#L315 assume !(1 == ~t1_pc~0); 36912#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 36913#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36943#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36958#L755 assume !(0 != activate_threads_~tmp___0~0); 36959#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36439#L334 assume !(1 == ~t2_pc~0); 36440#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 36437#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36438#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36495#L763 assume !(0 != activate_threads_~tmp___1~0); 36479#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36480#L353 assume !(1 == ~t3_pc~0); 36601#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 36602#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36598#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36599#L771 assume !(0 != activate_threads_~tmp___2~0); 36840#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36829#L372 assume 1 == ~t4_pc~0; 36806#L373 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36807#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36804#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36805#L779 assume !(0 != activate_threads_~tmp___3~0); 36973#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36532#L391 assume !(1 == ~t5_pc~0); 36533#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 36528#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36529#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 36557#L787 assume !(0 != activate_threads_~tmp___4~0); 36558#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 36559#L671-1 assume !(1 == ~T1_E~0); 36878#L676-1 assume !(1 == ~T2_E~0); 36816#L681-1 assume !(1 == ~T3_E~0); 36817#L686-1 assume !(1 == ~T4_E~0); 36975#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36976#L696-1 assume !(1 == ~E_M~0); 37003#L701-1 assume !(1 == ~E_1~0); 37004#L706-1 assume !(1 == ~E_2~0); 36960#L711-1 assume !(1 == ~E_3~0); 36961#L716-1 assume !(1 == ~E_4~0); 36561#L721-1 assume !(1 == ~E_5~0); 36562#L932-1 [2021-07-06 20:41:43,747 INFO L793 eck$LassoCheckResult]: Loop: 36562#L932-1 assume !false; 36888#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 36548#L578 assume !false; 36459#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36460#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36463#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36464#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 36588#L503 assume !(0 != eval_~tmp~0); 37002#L593 start_simulation_~kernel_st~0 := 2; 42101#L411-1 start_simulation_~kernel_st~0 := 3; 42099#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42096#L603-4 assume !(0 == ~T1_E~0); 42093#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42091#L613-3 assume !(0 == ~T3_E~0); 42089#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42087#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42085#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42084#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42080#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42078#L643-3 assume !(0 == ~E_3~0); 42076#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42074#L653-3 assume !(0 == ~E_5~0); 42071#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42069#L296-21 assume !(1 == ~m_pc~0); 42067#L296-23 is_master_triggered_~__retres1~0 := 0; 42066#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42064#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42062#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 42060#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42055#L315-21 assume !(1 == ~t1_pc~0); 42052#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 42050#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42048#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42046#L755-21 assume !(0 != activate_threads_~tmp___0~0); 42043#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42041#L334-21 assume !(1 == ~t2_pc~0); 38445#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 42037#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42035#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42033#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42032#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42031#L353-21 assume !(1 == ~t3_pc~0); 42029#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 42028#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42026#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36650#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36651#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36655#L372-21 assume 1 == ~t4_pc~0; 36721#L373-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36722#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36719#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36720#L779-21 assume !(0 != activate_threads_~tmp___3~0); 36823#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36824#L391-21 assume !(1 == ~t5_pc~0); 36928#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 36514#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36515#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 36923#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36966#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 36879#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36385#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36386#L681-3 assume !(1 == ~T3_E~0); 36488#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36489#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36700#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36701#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36635#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36636#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36677#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36542#L721-3 assume !(1 == ~E_5~0); 36543#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36591#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36467#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36468#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 36412#L951 assume !(0 == start_simulation_~tmp~3); 36413#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36416#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 36469#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36470#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 36593#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 36686#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 36843#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 36844#L964 assume !(0 != start_simulation_~tmp___0~1); 36562#L932-1 [2021-07-06 20:41:43,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,747 INFO L82 PathProgramCache]: Analyzing trace with hash -713779456, now seen corresponding path program 1 times [2021-07-06 20:41:43,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,748 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195390730] [2021-07-06 20:41:43,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,748 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,762 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,763 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,766 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,766 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:43,770 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,770 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,771 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,771 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195390730] [2021-07-06 20:41:43,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195390730] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,771 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:43,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613714258] [2021-07-06 20:41:43,772 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:43,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:43,772 INFO L82 PathProgramCache]: Analyzing trace with hash -12269905, now seen corresponding path program 1 times [2021-07-06 20:41:43,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:43,773 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022042933] [2021-07-06 20:41:43,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:43,773 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:43,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:43,786 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,786 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,787 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,787 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,790 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,790 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,794 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,794 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:43,798 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:43,799 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:43,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:43,799 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:43,799 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022042933] [2021-07-06 20:41:43,799 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022042933] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:43,799 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:43,800 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:43,800 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965515526] [2021-07-06 20:41:43,800 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:43,800 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:43,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:43,801 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:43,801 INFO L87 Difference]: Start difference. First operand 5863 states and 8522 transitions. cyclomatic complexity: 2667 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:44,040 INFO L93 Difference]: Finished difference Result 14043 states and 20152 transitions. [2021-07-06 20:41:44,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:44,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14043 states and 20152 transitions. [2021-07-06 20:41:44,101 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 13537 [2021-07-06 20:41:44,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14043 states to 14043 states and 20152 transitions. [2021-07-06 20:41:44,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14043 [2021-07-06 20:41:44,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14043 [2021-07-06 20:41:44,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14043 states and 20152 transitions. [2021-07-06 20:41:44,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:44,185 INFO L681 BuchiCegarLoop]: Abstraction has 14043 states and 20152 transitions. [2021-07-06 20:41:44,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14043 states and 20152 transitions. [2021-07-06 20:41:44,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14043 to 11154. [2021-07-06 20:41:44,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11154 states, 11154 states have (on average 1.443697328312713) internal successors, (16103), 11153 states have internal predecessors, (16103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11154 states to 11154 states and 16103 transitions. [2021-07-06 20:41:44,446 INFO L704 BuchiCegarLoop]: Abstraction has 11154 states and 16103 transitions. [2021-07-06 20:41:44,446 INFO L587 BuchiCegarLoop]: Abstraction has 11154 states and 16103 transitions. [2021-07-06 20:41:44,446 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-07-06 20:41:44,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11154 states and 16103 transitions. [2021-07-06 20:41:44,484 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11044 [2021-07-06 20:41:44,485 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:44,485 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:44,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,486 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,486 INFO L791 eck$LassoCheckResult]: Stem: 56788#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 56661#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56604#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56392#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 56393#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56512#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56513#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56394#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56395#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56612#L443-1 assume !(0 == ~M_E~0); 56613#L603-1 assume !(0 == ~T1_E~0); 56619#L608-1 assume !(0 == ~T2_E~0); 56620#L613-1 assume !(0 == ~T3_E~0); 56536#L618-1 assume !(0 == ~T4_E~0); 56537#L623-1 assume !(0 == ~T5_E~0); 56596#L628-1 assume !(0 == ~E_M~0); 56464#L633-1 assume !(0 == ~E_1~0); 56465#L638-1 assume !(0 == ~E_2~0); 56300#L643-1 assume !(0 == ~E_3~0); 56301#L648-1 assume !(0 == ~E_4~0); 56406#L653-1 assume !(0 == ~E_5~0); 56407#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56658#L296 assume !(1 == ~m_pc~0); 56644#L296-2 is_master_triggered_~__retres1~0 := 0; 56645#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56668#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56737#L747 assume !(0 != activate_threads_~tmp~1); 56722#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56723#L315 assume !(1 == ~t1_pc~0); 56847#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 56848#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 56880#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 56895#L755 assume !(0 != activate_threads_~tmp___0~0); 56896#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56360#L334 assume !(1 == ~t2_pc~0); 56361#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 56358#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56359#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 56416#L763 assume !(0 != activate_threads_~tmp___1~0); 56400#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56401#L353 assume !(1 == ~t3_pc~0); 56519#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 56520#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56516#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56517#L771 assume !(0 != activate_threads_~tmp___2~0); 56768#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56755#L372 assume !(1 == ~t4_pc~0); 56756#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 56761#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56716#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56717#L779 assume !(0 != activate_threads_~tmp___3~0); 56909#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56451#L391 assume !(1 == ~t5_pc~0); 56452#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 56447#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56448#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 56476#L787 assume !(0 != activate_threads_~tmp___4~0); 56477#L787-2 assume 1 == ~M_E~0;~M_E~0 := 2; 56480#L671-1 assume !(1 == ~T1_E~0); 61086#L676-1 assume !(1 == ~T2_E~0); 61084#L681-1 assume !(1 == ~T3_E~0); 61085#L686-1 assume !(1 == ~T4_E~0); 66897#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 66896#L696-1 assume !(1 == ~E_M~0); 66895#L701-1 assume !(1 == ~E_1~0); 66894#L706-1 assume !(1 == ~E_2~0); 66893#L711-1 assume !(1 == ~E_3~0); 66892#L716-1 assume !(1 == ~E_4~0); 56482#L721-1 assume !(1 == ~E_5~0); 56483#L932-1 [2021-07-06 20:41:44,487 INFO L793 eck$LassoCheckResult]: Loop: 56483#L932-1 assume !false; 56822#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 56468#L578 assume !false; 56378#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56379#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56384#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 56385#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 56502#L503 assume !(0 != eval_~tmp~0); 56932#L593 start_simulation_~kernel_st~0 := 2; 67260#L411-1 start_simulation_~kernel_st~0 := 3; 67259#L603-2 assume 0 == ~M_E~0;~M_E~0 := 1; 67257#L603-4 assume !(0 == ~T1_E~0); 67245#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67243#L613-3 assume !(0 == ~T3_E~0); 67171#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67011#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56598#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56472#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56473#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66773#L643-3 assume !(0 == ~E_3~0); 56733#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 56412#L653-3 assume !(0 == ~E_5~0); 56413#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56806#L296-21 assume !(1 == ~m_pc~0); 56805#L296-23 is_master_triggered_~__retres1~0 := 0; 56654#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56655#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 56656#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 56657#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56812#L315-21 assume 1 == ~t1_pc~0; 56923#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56924#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67305#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 67264#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56831#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56296#L334-21 assume !(1 == ~t2_pc~0); 56297#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 66864#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66862#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 66860#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 66859#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66857#L353-21 assume 1 == ~t3_pc~0; 66855#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56585#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56586#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 56567#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56568#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56572#L372-21 assume !(1 == ~t4_pc~0); 56727#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 56728#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56633#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 56634#L779-21 assume !(0 != activate_threads_~tmp___3~0); 56739#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56740#L391-21 assume 1 == ~t5_pc~0; 56864#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56434#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56435#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 56859#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 56904#L787-23 assume 1 == ~M_E~0;~M_E~0 := 2; 56809#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56304#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56305#L681-3 assume !(1 == ~T3_E~0); 56409#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56410#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56617#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56618#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56553#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56554#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56593#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56462#L721-3 assume !(1 == ~E_5~0); 56463#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 56509#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 56443#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67105#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 56331#L951 assume !(0 == start_simulation_~tmp~3); 56332#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 67252#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 67247#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 67246#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 56602#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56603#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 56818#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 66851#L964 assume !(0 != start_simulation_~tmp___0~1); 56483#L932-1 [2021-07-06 20:41:44,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,487 INFO L82 PathProgramCache]: Analyzing trace with hash 66201473, now seen corresponding path program 1 times [2021-07-06 20:41:44,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,487 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665792715] [2021-07-06 20:41:44,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,488 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,508 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,509 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:44,512 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,512 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,513 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,513 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665792715] [2021-07-06 20:41:44,513 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665792715] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,513 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,513 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:41:44,514 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1243259160] [2021-07-06 20:41:44,515 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:44,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,515 INFO L82 PathProgramCache]: Analyzing trace with hash 813851123, now seen corresponding path program 1 times [2021-07-06 20:41:44,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,515 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113623602] [2021-07-06 20:41:44,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,515 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:44,528 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,529 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,529 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,530 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:44,532 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:44,533 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:44,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:44,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:44,533 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113623602] [2021-07-06 20:41:44,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113623602] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:44,534 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:44,534 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:44,534 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415830360] [2021-07-06 20:41:44,534 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:44,534 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:44,535 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:44,535 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:44,536 INFO L87 Difference]: Start difference. First operand 11154 states and 16103 transitions. cyclomatic complexity: 4957 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:44,686 INFO L93 Difference]: Finished difference Result 13975 states and 20168 transitions. [2021-07-06 20:41:44,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:44,687 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13975 states and 20168 transitions. [2021-07-06 20:41:44,755 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13872 [2021-07-06 20:41:44,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13975 states to 13975 states and 20168 transitions. [2021-07-06 20:41:44,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13975 [2021-07-06 20:41:44,815 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13975 [2021-07-06 20:41:44,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13975 states and 20168 transitions. [2021-07-06 20:41:44,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:44,829 INFO L681 BuchiCegarLoop]: Abstraction has 13975 states and 20168 transitions. [2021-07-06 20:41:44,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13975 states and 20168 transitions. [2021-07-06 20:41:44,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13975 to 6095. [2021-07-06 20:41:44,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6095 states, 6095 states have (on average 1.4490566037735848) internal successors, (8832), 6094 states have internal predecessors, (8832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:44,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6095 states to 6095 states and 8832 transitions. [2021-07-06 20:41:44,953 INFO L704 BuchiCegarLoop]: Abstraction has 6095 states and 8832 transitions. [2021-07-06 20:41:44,953 INFO L587 BuchiCegarLoop]: Abstraction has 6095 states and 8832 transitions. [2021-07-06 20:41:44,953 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-07-06 20:41:44,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6095 states and 8832 transitions. [2021-07-06 20:41:44,972 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2021-07-06 20:41:44,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:44,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:44,975 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,975 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:44,976 INFO L791 eck$LassoCheckResult]: Stem: 81919#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 81801#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 81745#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81527#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 81528#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81649#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81650#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81529#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81530#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 81753#L443-1 assume !(0 == ~M_E~0); 81754#L603-1 assume !(0 == ~T1_E~0); 81760#L608-1 assume !(0 == ~T2_E~0); 81761#L613-1 assume !(0 == ~T3_E~0); 81674#L618-1 assume !(0 == ~T4_E~0); 81675#L623-1 assume !(0 == ~T5_E~0); 81738#L628-1 assume !(0 == ~E_M~0); 81599#L633-1 assume !(0 == ~E_1~0); 81600#L638-1 assume !(0 == ~E_2~0); 81436#L643-1 assume !(0 == ~E_3~0); 81437#L648-1 assume !(0 == ~E_4~0); 81543#L653-1 assume !(0 == ~E_5~0); 81544#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 81798#L296 assume !(1 == ~m_pc~0); 81784#L296-2 is_master_triggered_~__retres1~0 := 0; 81785#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 81809#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 81879#L747 assume !(0 != activate_threads_~tmp~1); 81863#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 81864#L315 assume !(1 == ~t1_pc~0); 81980#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 81981#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 82015#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 82029#L755 assume !(0 != activate_threads_~tmp___0~0); 82030#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 81495#L334 assume !(1 == ~t2_pc~0); 81496#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 81493#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 81494#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 81553#L763 assume !(0 != activate_threads_~tmp___1~0); 81537#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 81538#L353 assume !(1 == ~t3_pc~0); 81657#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 81658#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 81654#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 81655#L771 assume !(0 != activate_threads_~tmp___2~0); 81907#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81895#L372 assume !(1 == ~t4_pc~0); 81896#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 81901#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81857#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 81858#L779 assume !(0 != activate_threads_~tmp___3~0); 82049#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81587#L391 assume !(1 == ~t5_pc~0); 81588#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 81583#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81584#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 81610#L787 assume !(0 != activate_threads_~tmp___4~0); 81611#L787-2 assume !(1 == ~M_E~0); 81614#L671-1 assume !(1 == ~T1_E~0); 81434#L676-1 assume !(1 == ~T2_E~0); 81435#L681-1 assume !(1 == ~T3_E~0); 81541#L686-1 assume !(1 == ~T4_E~0); 81542#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 81756#L696-1 assume !(1 == ~E_M~0); 81757#L701-1 assume !(1 == ~E_1~0); 81690#L706-1 assume !(1 == ~E_2~0); 81691#L711-1 assume !(1 == ~E_3~0); 81908#L716-1 assume !(1 == ~E_4~0); 81615#L721-1 assume !(1 == ~E_5~0); 81616#L932-1 [2021-07-06 20:41:44,976 INFO L793 eck$LassoCheckResult]: Loop: 81616#L932-1 assume !false; 85976#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 85974#L578 assume !false; 85972#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 85959#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 85957#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 85955#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 85952#L503 assume !(0 != eval_~tmp~0); 85953#L593 start_simulation_~kernel_st~0 := 2; 87424#L411-1 start_simulation_~kernel_st~0 := 3; 87422#L603-2 assume !(0 == ~M_E~0); 87420#L603-4 assume !(0 == ~T1_E~0); 87418#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 87414#L613-3 assume !(0 == ~T3_E~0); 87412#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87410#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 87408#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87405#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87403#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87402#L643-3 assume !(0 == ~E_3~0); 87401#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87400#L653-3 assume !(0 == ~E_5~0); 87399#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87398#L296-21 assume !(1 == ~m_pc~0); 87397#L296-23 is_master_triggered_~__retres1~0 := 0; 87396#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87394#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 87393#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 87392#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87391#L315-21 assume !(1 == ~t1_pc~0); 87389#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 87387#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87385#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 87384#L755-21 assume !(0 != activate_threads_~tmp___0~0); 87382#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87381#L334-21 assume !(1 == ~t2_pc~0); 87008#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 87380#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87379#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 87378#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87377#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87376#L353-21 assume 1 == ~t3_pc~0; 87375#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 87373#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87372#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 87371#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 87370#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 81880#L372-21 assume !(1 == ~t4_pc~0); 81867#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 81868#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 81773#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 81774#L779-21 assume !(0 != activate_threads_~tmp___3~0); 81881#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81882#L391-21 assume 1 == ~t5_pc~0; 81997#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 81571#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 81572#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 82041#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 82042#L787-23 assume !(1 == ~M_E~0); 82044#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86987#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86986#L681-3 assume !(1 == ~T3_E~0); 86985#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86984#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86983#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 86982#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86980#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86978#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86976#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86974#L721-3 assume !(1 == ~E_5~0); 86971#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86966#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86847#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 85309#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 81467#L951 assume !(0 == start_simulation_~tmp~3); 81468#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86031#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86027#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86026#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 86025#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86024#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 86022#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 86020#L964 assume !(0 != start_simulation_~tmp___0~1); 81616#L932-1 [2021-07-06 20:41:44,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:44,977 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-07-06 20:41:44,977 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:44,977 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543854484] [2021-07-06 20:41:44,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:44,977 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:44,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,003 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,004 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,007 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,008 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:45,011 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,012 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,012 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,013 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543854484] [2021-07-06 20:41:45,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543854484] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,013 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,013 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,013 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847725889] [2021-07-06 20:41:45,014 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:45,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,014 INFO L82 PathProgramCache]: Analyzing trace with hash -1334921836, now seen corresponding path program 1 times [2021-07-06 20:41:45,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,014 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813581762] [2021-07-06 20:41:45,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,015 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,027 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,028 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,029 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,029 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:45,032 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,032 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,033 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,033 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813581762] [2021-07-06 20:41:45,033 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813581762] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,033 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,034 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,034 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1039842929] [2021-07-06 20:41:45,034 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:45,034 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:45,035 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:45,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:45,035 INFO L87 Difference]: Start difference. First operand 6095 states and 8832 transitions. cyclomatic complexity: 2739 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:45,121 INFO L93 Difference]: Finished difference Result 9787 states and 14111 transitions. [2021-07-06 20:41:45,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:45,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9787 states and 14111 transitions. [2021-07-06 20:41:45,167 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9640 [2021-07-06 20:41:45,199 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9787 states to 9787 states and 14111 transitions. [2021-07-06 20:41:45,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9787 [2021-07-06 20:41:45,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9787 [2021-07-06 20:41:45,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9787 states and 14111 transitions. [2021-07-06 20:41:45,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:45,218 INFO L681 BuchiCegarLoop]: Abstraction has 9787 states and 14111 transitions. [2021-07-06 20:41:45,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9787 states and 14111 transitions. [2021-07-06 20:41:45,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9787 to 7037. [2021-07-06 20:41:45,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7037 states, 7037 states have (on average 1.4453602387380986) internal successors, (10171), 7036 states have internal predecessors, (10171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7037 states to 7037 states and 10171 transitions. [2021-07-06 20:41:45,416 INFO L704 BuchiCegarLoop]: Abstraction has 7037 states and 10171 transitions. [2021-07-06 20:41:45,416 INFO L587 BuchiCegarLoop]: Abstraction has 7037 states and 10171 transitions. [2021-07-06 20:41:45,416 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-07-06 20:41:45,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7037 states and 10171 transitions. [2021-07-06 20:41:45,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6900 [2021-07-06 20:41:45,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:45,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:45,437 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,437 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,438 INFO L791 eck$LassoCheckResult]: Stem: 97803#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 97686#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 97628#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97416#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 97417#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97538#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97539#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97418#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97419#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97637#L443-1 assume !(0 == ~M_E~0); 97638#L603-1 assume !(0 == ~T1_E~0); 97644#L608-1 assume !(0 == ~T2_E~0); 97645#L613-1 assume !(0 == ~T3_E~0); 97562#L618-1 assume !(0 == ~T4_E~0); 97563#L623-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97898#L628-1 assume !(0 == ~E_M~0); 97999#L633-1 assume !(0 == ~E_1~0); 97998#L638-1 assume !(0 == ~E_2~0); 97997#L643-1 assume !(0 == ~E_3~0); 97996#L648-1 assume !(0 == ~E_4~0); 97995#L653-1 assume !(0 == ~E_5~0); 97994#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97993#L296 assume !(1 == ~m_pc~0); 97992#L296-2 is_master_triggered_~__retres1~0 := 0; 97991#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97990#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 97989#L747 assume !(0 != activate_threads_~tmp~1); 97988#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97890#L315 assume !(1 == ~t1_pc~0); 97859#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 97860#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 97889#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 97904#L755 assume !(0 != activate_threads_~tmp___0~0); 97905#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97385#L334 assume !(1 == ~t2_pc~0); 97386#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 97383#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97384#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 97441#L763 assume !(0 != activate_threads_~tmp___1~0); 97425#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97426#L353 assume !(1 == ~t3_pc~0); 97545#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 97546#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97542#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 97543#L771 assume !(0 != activate_threads_~tmp___2~0); 97785#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97774#L372 assume !(1 == ~t4_pc~0); 97775#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 97779#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97741#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97742#L779 assume !(0 != activate_threads_~tmp___3~0); 97919#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 97475#L391 assume !(1 == ~t5_pc~0); 97476#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 97471#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97472#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 97499#L787 assume !(0 != activate_threads_~tmp___4~0); 97500#L787-2 assume !(1 == ~M_E~0); 97503#L671-1 assume !(1 == ~T1_E~0); 97326#L676-1 assume !(1 == ~T2_E~0); 97327#L681-1 assume !(1 == ~T3_E~0); 97948#L686-1 assume !(1 == ~T4_E~0); 97947#L691-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97640#L696-1 assume !(1 == ~E_M~0); 97641#L701-1 assume !(1 == ~E_1~0); 97577#L706-1 assume !(1 == ~E_2~0); 97578#L711-1 assume !(1 == ~E_3~0); 97786#L716-1 assume !(1 == ~E_4~0); 97504#L721-1 assume !(1 == ~E_5~0); 97505#L932-1 [2021-07-06 20:41:45,438 INFO L793 eck$LassoCheckResult]: Loop: 97505#L932-1 assume !false; 103885#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 97629#L578 assume !false; 103884#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 103878#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 103877#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 103876#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 103873#L503 assume !(0 != eval_~tmp~0); 103874#L593 start_simulation_~kernel_st~0 := 2; 104342#L411-1 start_simulation_~kernel_st~0 := 3; 104341#L603-2 assume !(0 == ~M_E~0); 104339#L603-4 assume !(0 == ~T1_E~0); 104284#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 97943#L613-3 assume !(0 == ~T3_E~0); 97566#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97567#L623-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97902#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 104283#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 104282#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 104281#L643-3 assume !(0 == ~E_3~0); 104280#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 104279#L653-3 assume !(0 == ~E_5~0); 104278#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104277#L296-21 assume !(1 == ~m_pc~0); 104276#L296-23 is_master_triggered_~__retres1~0 := 0; 104275#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 104274#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 104273#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 104272#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 104271#L315-21 assume 1 == ~t1_pc~0; 104269#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 104267#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 104265#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 104263#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 104262#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104261#L334-21 assume !(1 == ~t2_pc~0); 101864#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 104260#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104259#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 104258#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 104257#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104256#L353-21 assume 1 == ~t3_pc~0; 104255#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 104253#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104252#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 104251#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 104250#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 104249#L372-21 assume !(1 == ~t4_pc~0); 103721#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 104248#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104247#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 104246#L779-21 assume !(0 != activate_threads_~tmp___3~0); 104245#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 104244#L391-21 assume !(1 == ~t5_pc~0); 104243#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 104241#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 104240#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 104239#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 104238#L787-23 assume !(1 == ~M_E~0); 101367#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 104237#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104236#L681-3 assume !(1 == ~T3_E~0); 104235#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 104234#L691-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 97642#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97643#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103934#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103933#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 103932#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 103931#L721-3 assume !(1 == ~E_5~0); 97817#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 97535#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 97412#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 97413#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 97358#L951 assume !(0 == start_simulation_~tmp~3); 97359#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 103904#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 103899#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 103897#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 103894#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 103892#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 103890#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 103888#L964 assume !(0 != start_simulation_~tmp___0~1); 97505#L932-1 [2021-07-06 20:41:45,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,439 INFO L82 PathProgramCache]: Analyzing trace with hash -1062418499, now seen corresponding path program 1 times [2021-07-06 20:41:45,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,439 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119411439] [2021-07-06 20:41:45,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,439 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,465 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,465 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,468 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,469 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:45,472 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,472 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,473 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,473 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119411439] [2021-07-06 20:41:45,473 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119411439] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,473 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,473 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,474 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732368812] [2021-07-06 20:41:45,474 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:45,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1013787050, now seen corresponding path program 1 times [2021-07-06 20:41:45,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,475 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935248558] [2021-07-06 20:41:45,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,475 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,489 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,490 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,491 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,491 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,494 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,494 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,498 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,499 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:45,507 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,507 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,508 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,508 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935248558] [2021-07-06 20:41:45,508 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935248558] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,508 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:45,509 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1905015580] [2021-07-06 20:41:45,509 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:45,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:45,510 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:41:45,510 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:41:45,511 INFO L87 Difference]: Start difference. First operand 7037 states and 10171 transitions. cyclomatic complexity: 3136 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:45,578 INFO L93 Difference]: Finished difference Result 8839 states and 12702 transitions. [2021-07-06 20:41:45,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:41:45,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8839 states and 12702 transitions. [2021-07-06 20:41:45,615 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8752 [2021-07-06 20:41:45,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8839 states to 8839 states and 12702 transitions. [2021-07-06 20:41:45,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8839 [2021-07-06 20:41:45,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8839 [2021-07-06 20:41:45,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8839 states and 12702 transitions. [2021-07-06 20:41:45,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:45,664 INFO L681 BuchiCegarLoop]: Abstraction has 8839 states and 12702 transitions. [2021-07-06 20:41:45,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8839 states and 12702 transitions. [2021-07-06 20:41:45,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8839 to 6095. [2021-07-06 20:41:45,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6095 states, 6095 states have (on average 1.4408531583264972) internal successors, (8782), 6094 states have internal predecessors, (8782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6095 states to 6095 states and 8782 transitions. [2021-07-06 20:41:45,747 INFO L704 BuchiCegarLoop]: Abstraction has 6095 states and 8782 transitions. [2021-07-06 20:41:45,747 INFO L587 BuchiCegarLoop]: Abstraction has 6095 states and 8782 transitions. [2021-07-06 20:41:45,747 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-07-06 20:41:45,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6095 states and 8782 transitions. [2021-07-06 20:41:45,764 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6012 [2021-07-06 20:41:45,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:45,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:45,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:45,766 INFO L791 eck$LassoCheckResult]: Stem: 113701#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 113582#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 113521#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 113307#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 113308#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 113428#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 113429#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 113309#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 113310#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 113530#L443-1 assume !(0 == ~M_E~0); 113531#L603-1 assume !(0 == ~T1_E~0); 113537#L608-1 assume !(0 == ~T2_E~0); 113538#L613-1 assume !(0 == ~T3_E~0); 113452#L618-1 assume !(0 == ~T4_E~0); 113453#L623-1 assume !(0 == ~T5_E~0); 113512#L628-1 assume !(0 == ~E_M~0); 113378#L633-1 assume !(0 == ~E_1~0); 113379#L638-1 assume !(0 == ~E_2~0); 113216#L643-1 assume !(0 == ~E_3~0); 113217#L648-1 assume !(0 == ~E_4~0); 113322#L653-1 assume !(0 == ~E_5~0); 113323#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 113579#L296 assume !(1 == ~m_pc~0); 113565#L296-2 is_master_triggered_~__retres1~0 := 0; 113566#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 113589#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 113658#L747 assume !(0 != activate_threads_~tmp~1); 113644#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 113645#L315 assume !(1 == ~t1_pc~0); 113755#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 113756#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 113788#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 113800#L755 assume !(0 != activate_threads_~tmp___0~0); 113801#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 113276#L334 assume !(1 == ~t2_pc~0); 113277#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 113274#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 113275#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 113332#L763 assume !(0 != activate_threads_~tmp___1~0); 113316#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 113317#L353 assume !(1 == ~t3_pc~0); 113435#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 113436#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 113432#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 113433#L771 assume !(0 != activate_threads_~tmp___2~0); 113685#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 113671#L372 assume !(1 == ~t4_pc~0); 113672#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 113677#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113638#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 113639#L779 assume !(0 != activate_threads_~tmp___3~0); 113815#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 113366#L391 assume !(1 == ~t5_pc~0); 113367#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 113362#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 113363#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 113391#L787 assume !(0 != activate_threads_~tmp___4~0); 113392#L787-2 assume !(1 == ~M_E~0); 113395#L671-1 assume !(1 == ~T1_E~0); 113214#L676-1 assume !(1 == ~T2_E~0); 113215#L681-1 assume !(1 == ~T3_E~0); 113320#L686-1 assume !(1 == ~T4_E~0); 113321#L691-1 assume !(1 == ~T5_E~0); 113533#L696-1 assume !(1 == ~E_M~0); 113534#L701-1 assume !(1 == ~E_1~0); 113468#L706-1 assume !(1 == ~E_2~0); 113469#L711-1 assume !(1 == ~E_3~0); 113686#L716-1 assume !(1 == ~E_4~0); 113396#L721-1 assume !(1 == ~E_5~0); 113397#L932-1 [2021-07-06 20:41:45,766 INFO L793 eck$LassoCheckResult]: Loop: 113397#L932-1 assume !false; 117721#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 117720#L578 assume !false; 117718#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 117700#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117698#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117697#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 117695#L503 assume !(0 != eval_~tmp~0); 117696#L593 start_simulation_~kernel_st~0 := 2; 119304#L411-1 start_simulation_~kernel_st~0 := 3; 119303#L603-2 assume !(0 == ~M_E~0); 119302#L603-4 assume !(0 == ~T1_E~0); 119301#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 113838#L613-3 assume !(0 == ~T3_E~0); 113457#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 113458#L623-3 assume !(0 == ~T5_E~0); 113514#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 113515#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119225#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119224#L643-3 assume !(0 == ~E_3~0); 119223#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119222#L653-3 assume !(0 == ~E_5~0); 119221#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119220#L296-21 assume !(1 == ~m_pc~0); 113717#L296-23 is_master_triggered_~__retres1~0 := 0; 113575#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 113576#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 113577#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 113578#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 113722#L315-21 assume 1 == ~t1_pc~0; 113828#L316-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 113829#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119268#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 119267#L755-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 113739#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 113212#L334-21 assume !(1 == ~t2_pc~0); 113213#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 119269#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 113404#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 113271#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 113239#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 113240#L353-21 assume !(1 == ~t3_pc~0); 113467#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 113470#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 113501#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 113485#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 113486#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 113490#L372-21 assume !(1 == ~t4_pc~0); 113648#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 113649#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 113554#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 113555#L779-21 assume !(0 != activate_threads_~tmp___3~0); 113659#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 113660#L391-21 assume 1 == ~t5_pc~0; 113771#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 113350#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 113351#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 113766#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 113810#L787-23 assume !(1 == ~M_E~0); 113720#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 113220#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 113221#L681-3 assume !(1 == ~T3_E~0); 113325#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 113326#L691-3 assume !(1 == ~T5_E~0); 113535#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 113536#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 113471#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113472#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 113509#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113376#L721-3 assume !(1 == ~E_5~0); 113377#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 113425#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 113303#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 113304#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 113423#L951 assume !(0 == start_simulation_~tmp~3); 116055#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 117772#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117767#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117765#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 117763#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 117760#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 117758#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 117756#L964 assume !(0 != start_simulation_~tmp___0~1); 113397#L932-1 [2021-07-06 20:41:45,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,767 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-07-06 20:41:45,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478176876] [2021-07-06 20:41:45,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,767 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:45,782 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:45,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:45,797 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:45,834 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:45,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:45,835 INFO L82 PathProgramCache]: Analyzing trace with hash 1319101778, now seen corresponding path program 1 times [2021-07-06 20:41:45,835 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:45,835 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644309558] [2021-07-06 20:41:45,835 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:45,836 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:45,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:45,847 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,847 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,848 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,849 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:41:45,851 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:45,852 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:45,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:45,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:45,852 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644309558] [2021-07-06 20:41:45,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644309558] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:45,853 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:45,853 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:45,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [570281403] [2021-07-06 20:41:45,853 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:45,853 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:45,854 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:45,854 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:45,854 INFO L87 Difference]: Start difference. First operand 6095 states and 8782 transitions. cyclomatic complexity: 2689 Second operand has 3 states, 3 states have (on average 27.666666666666668) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:45,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:45,953 INFO L93 Difference]: Finished difference Result 11054 states and 15823 transitions. [2021-07-06 20:41:45,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:45,954 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11054 states and 15823 transitions. [2021-07-06 20:41:46,082 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10948 [2021-07-06 20:41:46,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11054 states to 11054 states and 15823 transitions. [2021-07-06 20:41:46,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11054 [2021-07-06 20:41:46,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11054 [2021-07-06 20:41:46,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11054 states and 15823 transitions. [2021-07-06 20:41:46,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:46,134 INFO L681 BuchiCegarLoop]: Abstraction has 11054 states and 15823 transitions. [2021-07-06 20:41:46,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11054 states and 15823 transitions. [2021-07-06 20:41:46,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11054 to 11046. [2021-07-06 20:41:46,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11046 states, 11046 states have (on average 1.4317399963787796) internal successors, (15815), 11045 states have internal predecessors, (15815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11046 states to 11046 states and 15815 transitions. [2021-07-06 20:41:46,270 INFO L704 BuchiCegarLoop]: Abstraction has 11046 states and 15815 transitions. [2021-07-06 20:41:46,270 INFO L587 BuchiCegarLoop]: Abstraction has 11046 states and 15815 transitions. [2021-07-06 20:41:46,270 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-07-06 20:41:46,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11046 states and 15815 transitions. [2021-07-06 20:41:46,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10940 [2021-07-06 20:41:46,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:46,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:46,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,309 INFO L791 eck$LassoCheckResult]: Stem: 130869#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 130745#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 130689#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 130461#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 130462#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130589#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130590#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 130463#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130464#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 130697#L443-1 assume !(0 == ~M_E~0); 130698#L603-1 assume !(0 == ~T1_E~0); 130704#L608-1 assume !(0 == ~T2_E~0); 130705#L613-1 assume !(0 == ~T3_E~0); 130613#L618-1 assume !(0 == ~T4_E~0); 130614#L623-1 assume !(0 == ~T5_E~0); 130680#L628-1 assume !(0 == ~E_M~0); 130536#L633-1 assume !(0 == ~E_1~0); 130537#L638-1 assume !(0 == ~E_2~0); 130371#L643-1 assume !(0 == ~E_3~0); 130372#L648-1 assume !(0 == ~E_4~0); 130476#L653-1 assume !(0 == ~E_5~0); 130477#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 130742#L296 assume !(1 == ~m_pc~0); 130728#L296-2 is_master_triggered_~__retres1~0 := 0; 130729#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 130753#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 130825#L747 assume !(0 != activate_threads_~tmp~1); 130809#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 130810#L315 assume !(1 == ~t1_pc~0); 130915#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 130916#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130949#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 130967#L755 assume !(0 != activate_threads_~tmp___0~0); 130968#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 130430#L334 assume !(1 == ~t2_pc~0); 130431#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 130428#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 130429#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 130487#L763 assume !(0 != activate_threads_~tmp___1~0); 130470#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 130471#L353 assume !(1 == ~t3_pc~0); 130596#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 130597#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 130593#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 130594#L771 assume !(0 != activate_threads_~tmp___2~0); 130857#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 130844#L372 assume !(1 == ~t4_pc~0); 130845#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 130850#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 130801#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 130802#L779 assume !(0 != activate_threads_~tmp___3~0); 130990#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 130523#L391 assume !(1 == ~t5_pc~0); 130524#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 130519#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 130520#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 130940#L787 assume !(0 != activate_threads_~tmp___4~0); 133693#L787-2 assume !(1 == ~M_E~0); 133690#L671-1 assume !(1 == ~T1_E~0); 133688#L676-1 assume !(1 == ~T2_E~0); 133686#L681-1 assume !(1 == ~T3_E~0); 133684#L686-1 assume !(1 == ~T4_E~0); 133682#L691-1 assume !(1 == ~T5_E~0); 133680#L696-1 assume !(1 == ~E_M~0); 133679#L701-1 assume !(1 == ~E_1~0); 133677#L706-1 assume !(1 == ~E_2~0); 133675#L711-1 assume !(1 == ~E_3~0); 133673#L716-1 assume !(1 == ~E_4~0); 133671#L721-1 assume !(1 == ~E_5~0); 130554#L932-1 [2021-07-06 20:41:46,309 INFO L793 eck$LassoCheckResult]: Loop: 130554#L932-1 assume !false; 133648#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 133645#L578 assume !false; 133643#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133489#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133487#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133485#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 133482#L503 assume !(0 != eval_~tmp~0); 133483#L593 start_simulation_~kernel_st~0 := 2; 134638#L411-1 start_simulation_~kernel_st~0 := 3; 134616#L603-2 assume !(0 == ~M_E~0); 134611#L603-4 assume !(0 == ~T1_E~0); 134606#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134600#L613-3 assume !(0 == ~T3_E~0); 134592#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134581#L623-3 assume !(0 == ~T5_E~0); 134580#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134579#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 134577#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134576#L643-3 assume !(0 == ~E_3~0); 134575#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 134574#L653-3 assume !(0 == ~E_5~0); 134572#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134570#L296-21 assume !(1 == ~m_pc~0); 134568#L296-23 is_master_triggered_~__retres1~0 := 0; 134566#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134564#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134562#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 134558#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134556#L315-21 assume !(1 == ~t1_pc~0); 134554#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 134593#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134582#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 134539#L755-21 assume !(0 != activate_threads_~tmp___0~0); 134289#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 133937#L334-21 assume !(1 == ~t2_pc~0); 133935#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 133934#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 133932#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 133930#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 133928#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 133926#L353-21 assume !(1 == ~t3_pc~0); 133922#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 133920#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 133918#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 133916#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 133914#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 133913#L372-21 assume !(1 == ~t4_pc~0); 132479#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 133912#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 133910#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 133908#L779-21 assume !(0 != activate_threads_~tmp___3~0); 133906#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 133904#L391-21 assume 1 == ~t5_pc~0; 133903#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 133826#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 133824#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 133821#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 133819#L787-23 assume !(1 == ~M_E~0); 133815#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 133814#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 133812#L681-3 assume !(1 == ~T3_E~0); 133810#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133808#L691-3 assume !(1 == ~T5_E~0); 133806#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133804#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133801#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 133799#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 133797#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 133795#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 133792#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133788#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133782#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133780#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 133743#L951 assume !(0 == start_simulation_~tmp~3); 133742#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133727#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 133723#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 133722#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 133721#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 133720#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 133719#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 133670#L964 assume !(0 != start_simulation_~tmp___0~1); 130554#L932-1 [2021-07-06 20:41:46,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,309 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-07-06 20:41:46,310 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,310 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58492628] [2021-07-06 20:41:46,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,310 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,317 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:46,323 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:46,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:46,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,337 INFO L82 PathProgramCache]: Analyzing trace with hash 1951940017, now seen corresponding path program 1 times [2021-07-06 20:41:46,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,338 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558094854] [2021-07-06 20:41:46,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,338 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:46,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:46,348 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,348 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,349 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,349 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,352 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,352 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,356 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,356 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:46,361 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:46,362 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:46,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:46,362 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:46,362 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558094854] [2021-07-06 20:41:46,363 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1558094854] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:46,363 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:46,363 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:46,363 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184080804] [2021-07-06 20:41:46,363 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:46,363 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:46,364 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:46,364 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:46,364 INFO L87 Difference]: Start difference. First operand 11046 states and 15815 transitions. cyclomatic complexity: 4771 Second operand has 5 states, 5 states have (on average 16.6) internal successors, (83), 5 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:46,511 INFO L93 Difference]: Finished difference Result 19730 states and 27947 transitions. [2021-07-06 20:41:46,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-07-06 20:41:46,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19730 states and 27947 transitions. [2021-07-06 20:41:46,603 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 19608 [2021-07-06 20:41:46,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19730 states to 19730 states and 27947 transitions. [2021-07-06 20:41:46,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19730 [2021-07-06 20:41:46,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19730 [2021-07-06 20:41:46,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19730 states and 27947 transitions. [2021-07-06 20:41:46,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:46,817 INFO L681 BuchiCegarLoop]: Abstraction has 19730 states and 27947 transitions. [2021-07-06 20:41:46,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19730 states and 27947 transitions. [2021-07-06 20:41:46,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19730 to 11142. [2021-07-06 20:41:46,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11142 states, 11142 states have (on average 1.4280201041105727) internal successors, (15911), 11141 states have internal predecessors, (15911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:46,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11142 states to 11142 states and 15911 transitions. [2021-07-06 20:41:46,962 INFO L704 BuchiCegarLoop]: Abstraction has 11142 states and 15911 transitions. [2021-07-06 20:41:46,962 INFO L587 BuchiCegarLoop]: Abstraction has 11142 states and 15911 transitions. [2021-07-06 20:41:46,962 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-07-06 20:41:46,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11142 states and 15911 transitions. [2021-07-06 20:41:46,994 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11036 [2021-07-06 20:41:46,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:46,995 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:46,997 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,997 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:46,997 INFO L791 eck$LassoCheckResult]: Stem: 161656#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 161528#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 161471#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 161252#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 161253#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161379#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161380#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161254#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161255#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 161480#L443-1 assume !(0 == ~M_E~0); 161481#L603-1 assume !(0 == ~T1_E~0); 161487#L608-1 assume !(0 == ~T2_E~0); 161488#L613-1 assume !(0 == ~T3_E~0); 161404#L618-1 assume !(0 == ~T4_E~0); 161405#L623-1 assume !(0 == ~T5_E~0); 161464#L628-1 assume !(0 == ~E_M~0); 161325#L633-1 assume !(0 == ~E_1~0); 161326#L638-1 assume !(0 == ~E_2~0); 161163#L643-1 assume !(0 == ~E_3~0); 161164#L648-1 assume !(0 == ~E_4~0); 161266#L653-1 assume !(0 == ~E_5~0); 161267#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161525#L296 assume !(1 == ~m_pc~0); 161511#L296-2 is_master_triggered_~__retres1~0 := 0; 161512#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 161535#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 161606#L747 assume !(0 != activate_threads_~tmp~1); 161588#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 161589#L315 assume !(1 == ~t1_pc~0); 161713#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 161714#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 161745#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 161760#L755 assume !(0 != activate_threads_~tmp___0~0); 161761#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 161221#L334 assume !(1 == ~t2_pc~0); 161222#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 161219#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 161220#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 161276#L763 assume !(0 != activate_threads_~tmp___1~0); 161260#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 161261#L353 assume !(1 == ~t3_pc~0); 161387#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 161388#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161384#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 161385#L771 assume !(0 != activate_threads_~tmp___2~0); 161638#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 161624#L372 assume !(1 == ~t4_pc~0); 161625#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 161630#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161582#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 161583#L779 assume !(0 != activate_threads_~tmp___3~0); 161783#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 161311#L391 assume !(1 == ~t5_pc~0); 161312#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 161318#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161739#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 161740#L787 assume !(0 != activate_threads_~tmp___4~0); 161341#L787-2 assume !(1 == ~M_E~0); 161342#L671-1 assume !(1 == ~T1_E~0); 161161#L676-1 assume !(1 == ~T2_E~0); 161162#L681-1 assume !(1 == ~T3_E~0); 161264#L686-1 assume !(1 == ~T4_E~0); 161265#L691-1 assume !(1 == ~T5_E~0); 161483#L696-1 assume !(1 == ~E_M~0); 161484#L701-1 assume !(1 == ~E_1~0); 161420#L706-1 assume !(1 == ~E_2~0); 161421#L711-1 assume !(1 == ~E_3~0); 161639#L716-1 assume !(1 == ~E_4~0); 161640#L721-1 assume !(1 == ~E_5~0); 161344#L932-1 [2021-07-06 20:41:46,998 INFO L793 eck$LassoCheckResult]: Loop: 161344#L932-1 assume !false; 161688#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 161329#L578 assume !false; 161330#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 171814#L456 assume !(0 == ~m_st~0); 171815#L460 assume !(0 == ~t1_st~0); 171818#L464 assume !(0 == ~t2_st~0); 171820#L468 assume !(0 == ~t3_st~0); 171816#L472 assume !(0 == ~t4_st~0); 171817#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 171819#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 168431#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 168432#L503 assume !(0 != eval_~tmp~0); 171798#L593 start_simulation_~kernel_st~0 := 2; 171796#L411-1 start_simulation_~kernel_st~0 := 3; 171794#L603-2 assume !(0 == ~M_E~0); 171792#L603-4 assume !(0 == ~T1_E~0); 171790#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 161811#L613-3 assume !(0 == ~T3_E~0); 161408#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 161409#L623-3 assume !(0 == ~T5_E~0); 161466#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 161333#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 161334#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 161171#L643-3 assume !(0 == ~E_3~0); 161172#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 161602#L653-3 assume !(0 == ~E_5~0); 161787#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 161788#L296-21 assume !(1 == ~m_pc~0); 171779#L296-23 is_master_triggered_~__retres1~0 := 0; 171777#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 171775#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 171773#L747-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 171771#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 171769#L315-21 assume !(1 == ~t1_pc~0); 171766#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 171762#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 171758#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 171754#L755-21 assume !(0 != activate_threads_~tmp___0~0); 171751#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 171749#L334-21 assume !(1 == ~t2_pc~0); 170164#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 171747#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 171745#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 171743#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 171741#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 171739#L353-21 assume !(1 == ~t3_pc~0); 171735#L353-23 is_transmit3_triggered_~__retres1~3 := 0; 171733#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 171731#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 171729#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 171727#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 171725#L372-21 assume !(1 == ~t4_pc~0); 170905#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 171723#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 171721#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 171719#L779-21 assume !(0 != activate_threads_~tmp___3~0); 171717#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 171606#L391-21 assume 1 == ~t5_pc~0; 171607#L392-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 161294#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161295#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 171713#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 171712#L787-23 assume !(1 == ~M_E~0); 161675#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 161676#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 161599#L681-3 assume !(1 == ~T3_E~0); 161600#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 171711#L691-3 assume !(1 == ~T5_E~0); 171710#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 161818#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 161819#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 171709#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 171708#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 161323#L721-3 assume 1 == ~E_5~0;~E_5~0 := 2; 161324#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161376#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161248#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161249#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 161194#L951 assume !(0 == start_simulation_~tmp~3); 161195#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 161381#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 161250#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 161251#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 161378#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 161470#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 161641#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 161642#L964 assume !(0 != start_simulation_~tmp___0~1); 161344#L932-1 [2021-07-06 20:41:46,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:46,998 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-07-06 20:41:46,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:46,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049910947] [2021-07-06 20:41:46,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:46,999 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,005 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,011 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,023 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:47,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:47,024 INFO L82 PathProgramCache]: Analyzing trace with hash 1274155466, now seen corresponding path program 1 times [2021-07-06 20:41:47,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:47,024 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786705689] [2021-07-06 20:41:47,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:47,024 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:47,039 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,040 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,044 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,045 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 7 [2021-07-06 20:41:47,050 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,051 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 7 [2021-07-06 20:41:47,060 INFO L142 QuantifierPusher]: treesize reduction 9, result has 50.0 percent of original size [2021-07-06 20:41:47,061 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 9 [2021-07-06 20:41:47,073 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,073 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:47,074 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:47,074 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786705689] [2021-07-06 20:41:47,074 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786705689] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:47,074 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:47,074 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:41:47,075 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1280068856] [2021-07-06 20:41:47,075 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:47,075 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:47,075 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:41:47,075 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:41:47,076 INFO L87 Difference]: Start difference. First operand 11142 states and 15911 transitions. cyclomatic complexity: 4771 Second operand has 5 states, 5 states have (on average 17.6) internal successors, (88), 5 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:47,291 INFO L93 Difference]: Finished difference Result 22274 states and 31618 transitions. [2021-07-06 20:41:47,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-07-06 20:41:47,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22274 states and 31618 transitions. [2021-07-06 20:41:47,478 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22168 [2021-07-06 20:41:47,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22274 states to 22274 states and 31618 transitions. [2021-07-06 20:41:47,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22274 [2021-07-06 20:41:47,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22274 [2021-07-06 20:41:47,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22274 states and 31618 transitions. [2021-07-06 20:41:47,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:47,588 INFO L681 BuchiCegarLoop]: Abstraction has 22274 states and 31618 transitions. [2021-07-06 20:41:47,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22274 states and 31618 transitions. [2021-07-06 20:41:47,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22274 to 11430. [2021-07-06 20:41:47,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11430 states, 11430 states have (on average 1.4101487314085739) internal successors, (16118), 11429 states have internal predecessors, (16118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11430 states to 11430 states and 16118 transitions. [2021-07-06 20:41:47,778 INFO L704 BuchiCegarLoop]: Abstraction has 11430 states and 16118 transitions. [2021-07-06 20:41:47,778 INFO L587 BuchiCegarLoop]: Abstraction has 11430 states and 16118 transitions. [2021-07-06 20:41:47,778 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-07-06 20:41:47,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11430 states and 16118 transitions. [2021-07-06 20:41:47,814 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 11324 [2021-07-06 20:41:47,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:47,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:47,816 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:47,816 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:47,817 INFO L791 eck$LassoCheckResult]: Stem: 195088#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 194957#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 194897#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 194683#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 194684#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194806#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194807#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194685#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194686#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 194908#L443-1 assume !(0 == ~M_E~0); 194909#L603-1 assume !(0 == ~T1_E~0); 194915#L608-1 assume !(0 == ~T2_E~0); 194916#L613-1 assume !(0 == ~T3_E~0); 194830#L618-1 assume !(0 == ~T4_E~0); 194831#L623-1 assume !(0 == ~T5_E~0); 194890#L628-1 assume !(0 == ~E_M~0); 194756#L633-1 assume !(0 == ~E_1~0); 194757#L638-1 assume !(0 == ~E_2~0); 194592#L643-1 assume !(0 == ~E_3~0); 194593#L648-1 assume !(0 == ~E_4~0); 194697#L653-1 assume !(0 == ~E_5~0); 194698#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 194954#L296 assume !(1 == ~m_pc~0); 194940#L296-2 is_master_triggered_~__retres1~0 := 0; 194941#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 194964#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 195039#L747 assume !(0 != activate_threads_~tmp~1); 195023#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 195024#L315 assume !(1 == ~t1_pc~0); 195161#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 195162#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 195189#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 195204#L755 assume !(0 != activate_threads_~tmp___0~0); 195205#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 194651#L334 assume !(1 == ~t2_pc~0); 194652#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 194649#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 194650#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 194707#L763 assume !(0 != activate_threads_~tmp___1~0); 194691#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 194692#L353 assume !(1 == ~t3_pc~0); 194813#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 194814#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 194810#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 194811#L771 assume !(0 != activate_threads_~tmp___2~0); 195067#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 195054#L372 assume !(1 == ~t4_pc~0); 195055#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 195060#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 195016#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 195017#L779 assume !(0 != activate_threads_~tmp___3~0); 195223#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 194742#L391 assume !(1 == ~t5_pc~0); 194743#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 194749#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 199019#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 199018#L787 assume !(0 != activate_threads_~tmp___4~0); 199017#L787-2 assume !(1 == ~M_E~0); 195115#L671-1 assume !(1 == ~T1_E~0); 194590#L676-1 assume !(1 == ~T2_E~0); 194591#L681-1 assume !(1 == ~T3_E~0); 199013#L686-1 assume !(1 == ~T4_E~0); 199011#L691-1 assume !(1 == ~T5_E~0); 194911#L696-1 assume !(1 == ~E_M~0); 194912#L701-1 assume !(1 == ~E_1~0); 195254#L706-1 assume !(1 == ~E_2~0); 198985#L711-1 assume !(1 == ~E_3~0); 198983#L716-1 assume !(1 == ~E_4~0); 198981#L721-1 assume !(1 == ~E_5~0); 194773#L932-1 [2021-07-06 20:41:47,817 INFO L793 eck$LassoCheckResult]: Loop: 194773#L932-1 assume !false; 198924#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 198922#L578 assume !false; 198920#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 198812#L456 assume !(0 == ~m_st~0); 198813#L460 assume !(0 == ~t1_st~0); 198816#L464 assume !(0 == ~t2_st~0); 198818#L468 assume !(0 == ~t3_st~0); 198814#L472 assume !(0 == ~t4_st~0); 198815#L476 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 198817#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 198346#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 198347#L503 assume !(0 != eval_~tmp~0); 200239#L593 start_simulation_~kernel_st~0 := 2; 200235#L411-1 start_simulation_~kernel_st~0 := 3; 200231#L603-2 assume !(0 == ~M_E~0); 200187#L603-4 assume !(0 == ~T1_E~0); 200181#L608-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 200177#L613-3 assume !(0 == ~T3_E~0); 200174#L618-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 200169#L623-3 assume !(0 == ~T5_E~0); 200164#L628-3 assume 0 == ~E_M~0;~E_M~0 := 1; 200159#L633-3 assume 0 == ~E_1~0;~E_1~0 := 1; 200155#L638-3 assume 0 == ~E_2~0;~E_2~0 := 1; 200150#L643-3 assume !(0 == ~E_3~0); 200145#L648-3 assume 0 == ~E_4~0;~E_4~0 := 1; 200141#L653-3 assume !(0 == ~E_5~0); 200136#L658-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 200132#L296-21 assume !(1 == ~m_pc~0); 200128#L296-23 is_master_triggered_~__retres1~0 := 0; 200124#L307-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 200119#L308-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 200113#L747-21 assume !(0 != activate_threads_~tmp~1); 200107#L747-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 200104#L315-21 assume !(1 == ~t1_pc~0); 200103#L315-23 is_transmit1_triggered_~__retres1~1 := 0; 200102#L326-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 200101#L327-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 200099#L755-21 assume !(0 != activate_threads_~tmp___0~0); 200093#L755-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 199480#L334-21 assume !(1 == ~t2_pc~0); 199478#L334-23 is_transmit2_triggered_~__retres1~2 := 0; 199477#L345-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 199475#L346-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 199473#L763-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 199471#L763-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 199469#L353-21 assume 1 == ~t3_pc~0; 199467#L354-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 199463#L364-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 199461#L365-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 199459#L771-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 199457#L771-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 199455#L372-21 assume !(1 == ~t4_pc~0); 198758#L372-23 is_transmit4_triggered_~__retres1~4 := 0; 199453#L383-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 199451#L384-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 199449#L779-21 assume !(0 != activate_threads_~tmp___3~0); 199447#L779-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 199445#L391-21 assume !(1 == ~t5_pc~0); 199442#L391-23 is_transmit5_triggered_~__retres1~5 := 0; 199439#L402-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 199437#L403-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 199435#L787-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 199433#L787-23 assume !(1 == ~M_E~0); 199397#L671-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 199431#L676-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 199429#L681-3 assume !(1 == ~T3_E~0); 199427#L686-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199425#L691-3 assume !(1 == ~T5_E~0); 199423#L696-3 assume 1 == ~E_M~0;~E_M~0 := 2; 199421#L701-3 assume 1 == ~E_1~0;~E_1~0 := 2; 199419#L706-3 assume 1 == ~E_2~0;~E_2~0 := 2; 199417#L711-3 assume 1 == ~E_3~0;~E_3~0 := 2; 199415#L716-3 assume 1 == ~E_4~0;~E_4~0 := 2; 199412#L721-3 assume !(1 == ~E_5~0); 199411#L726-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 199369#L456-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 199364#L488-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 199363#L489-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 199251#L951 assume !(0 == start_simulation_~tmp~3); 199249#L951-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 199141#L456-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 199064#L488-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 199032#L489-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 199022#L906 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 199021#L913 stop_simulation_#res := stop_simulation_~__retres2~0; 199020#L914 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 198980#L964 assume !(0 != start_simulation_~tmp___0~1); 194773#L932-1 [2021-07-06 20:41:47,817 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:47,818 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 4 times [2021-07-06 20:41:47,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:47,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543042051] [2021-07-06 20:41:47,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:47,818 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,826 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:47,832 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:47,845 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:47,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:47,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1892884154, now seen corresponding path program 1 times [2021-07-06 20:41:47,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:47,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323789268] [2021-07-06 20:41:47,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:47,846 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:47,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:47,861 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,862 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,862 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,862 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:41:47,865 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:47,866 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:47,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:47,867 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:47,867 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323789268] [2021-07-06 20:41:47,867 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323789268] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:47,867 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:47,867 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:47,867 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337850171] [2021-07-06 20:41:47,868 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:41:47,868 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:47,868 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:47,868 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:47,868 INFO L87 Difference]: Start difference. First operand 11430 states and 16118 transitions. cyclomatic complexity: 4690 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:47,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:47,951 INFO L93 Difference]: Finished difference Result 18361 states and 25589 transitions. [2021-07-06 20:41:47,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:47,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18361 states and 25589 transitions. [2021-07-06 20:41:48,024 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 18261 [2021-07-06 20:41:48,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18361 states to 18361 states and 25589 transitions. [2021-07-06 20:41:48,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18361 [2021-07-06 20:41:48,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18361 [2021-07-06 20:41:48,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18361 states and 25589 transitions. [2021-07-06 20:41:48,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:48,100 INFO L681 BuchiCegarLoop]: Abstraction has 18361 states and 25589 transitions. [2021-07-06 20:41:48,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18361 states and 25589 transitions. [2021-07-06 20:41:48,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18361 to 17753. [2021-07-06 20:41:48,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17753 states, 17753 states have (on average 1.395876753224807) internal successors, (24781), 17752 states have internal predecessors, (24781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:48,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17753 states to 17753 states and 24781 transitions. [2021-07-06 20:41:48,430 INFO L704 BuchiCegarLoop]: Abstraction has 17753 states and 24781 transitions. [2021-07-06 20:41:48,431 INFO L587 BuchiCegarLoop]: Abstraction has 17753 states and 24781 transitions. [2021-07-06 20:41:48,431 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-07-06 20:41:48,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17753 states and 24781 transitions. [2021-07-06 20:41:48,488 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 17653 [2021-07-06 20:41:48,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:48,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:48,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:48,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:48,490 INFO L791 eck$LassoCheckResult]: Stem: 224900#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 224765#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 224704#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 224480#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 224481#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 224609#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224610#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 224482#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 224483#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224715#L443-1 assume !(0 == ~M_E~0); 224716#L603-1 assume !(0 == ~T1_E~0); 224722#L608-1 assume !(0 == ~T2_E~0); 224723#L613-1 assume !(0 == ~T3_E~0); 224634#L618-1 assume !(0 == ~T4_E~0); 224635#L623-1 assume !(0 == ~T5_E~0); 224697#L628-1 assume !(0 == ~E_M~0); 224558#L633-1 assume !(0 == ~E_1~0); 224559#L638-1 assume !(0 == ~E_2~0); 224389#L643-1 assume !(0 == ~E_3~0); 224390#L648-1 assume !(0 == ~E_4~0); 224494#L653-1 assume !(0 == ~E_5~0); 224495#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 224762#L296 assume !(1 == ~m_pc~0); 224747#L296-2 is_master_triggered_~__retres1~0 := 0; 224748#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 224773#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 224844#L747 assume !(0 != activate_threads_~tmp~1); 224830#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 224831#L315 assume !(1 == ~t1_pc~0); 224959#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 224960#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 224994#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 225011#L755 assume !(0 != activate_threads_~tmp___0~0); 225012#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 224448#L334 assume !(1 == ~t2_pc~0); 224449#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 224446#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 224447#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 224504#L763 assume !(0 != activate_threads_~tmp___1~0); 224488#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 224489#L353 assume !(1 == ~t3_pc~0); 224617#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 224618#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224614#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 224615#L771 assume !(0 != activate_threads_~tmp___2~0); 224880#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 224862#L372 assume !(1 == ~t4_pc~0); 224863#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 224868#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 224823#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 224824#L779 assume !(0 != activate_threads_~tmp___3~0); 225042#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 224543#L391 assume !(1 == ~t5_pc~0); 224544#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 224550#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 224983#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 224984#L787 assume !(0 != activate_threads_~tmp___4~0); 224576#L787-2 assume !(1 == ~M_E~0); 224577#L671-1 assume !(1 == ~T1_E~0); 224387#L676-1 assume !(1 == ~T2_E~0); 224388#L681-1 assume !(1 == ~T3_E~0); 224492#L686-1 assume !(1 == ~T4_E~0); 224493#L691-1 assume !(1 == ~T5_E~0); 224718#L696-1 assume !(1 == ~E_M~0); 224719#L701-1 assume !(1 == ~E_1~0); 224649#L706-1 assume !(1 == ~E_2~0); 224650#L711-1 assume !(1 == ~E_3~0); 224881#L716-1 assume !(1 == ~E_4~0); 224882#L721-1 assume !(1 == ~E_5~0); 224579#L932-1 assume !false; 231567#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 231564#L578 [2021-07-06 20:41:48,490 INFO L793 eck$LassoCheckResult]: Loop: 231564#L578 assume !false; 231562#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 231561#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 231560#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 231559#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 231176#L503 assume 0 != eval_~tmp~0; 231177#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 231437#L511 assume !(0 != eval_~tmp_ndt_1~0); 231179#L508 assume !(0 == ~t1_st~0); 231170#L522 assume !(0 == ~t2_st~0); 230473#L536 assume !(0 == ~t3_st~0); 230468#L550 assume !(0 == ~t4_st~0); 230467#L564 assume !(0 == ~t5_st~0); 231564#L578 [2021-07-06 20:41:48,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-07-06 20:41:48,491 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,491 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417865088] [2021-07-06 20:41:48,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,491 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,502 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,509 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,527 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:48,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,528 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 1 times [2021-07-06 20:41:48,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,528 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020567108] [2021-07-06 20:41:48,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,529 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,531 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:48,534 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:48,536 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:48,537 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:48,537 INFO L82 PathProgramCache]: Analyzing trace with hash -1605223329, now seen corresponding path program 1 times [2021-07-06 20:41:48,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:48,537 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827204252] [2021-07-06 20:41:48,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:48,537 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:48,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:48,554 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,554 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:48,555 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,555 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:48,561 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,562 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:48,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:48,562 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:48,563 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827204252] [2021-07-06 20:41:48,563 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827204252] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:48,563 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:48,563 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:48,563 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022052307] [2021-07-06 20:41:48,609 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:48,613 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 39 [2021-07-06 20:41:48,656 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:48,657 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:48,657 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:48,657 INFO L87 Difference]: Start difference. First operand 17753 states and 24781 transitions. cyclomatic complexity: 7031 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:48,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:48,773 INFO L93 Difference]: Finished difference Result 32773 states and 45524 transitions. [2021-07-06 20:41:48,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:48,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32773 states and 45524 transitions. [2021-07-06 20:41:48,937 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 32578 [2021-07-06 20:41:49,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32773 states to 32773 states and 45524 transitions. [2021-07-06 20:41:49,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32773 [2021-07-06 20:41:49,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32773 [2021-07-06 20:41:49,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32773 states and 45524 transitions. [2021-07-06 20:41:49,288 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:49,289 INFO L681 BuchiCegarLoop]: Abstraction has 32773 states and 45524 transitions. [2021-07-06 20:41:49,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32773 states and 45524 transitions. [2021-07-06 20:41:49,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32773 to 31093. [2021-07-06 20:41:49,586 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31093 states, 31093 states have (on average 1.3929823432927024) internal successors, (43312), 31092 states have internal predecessors, (43312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:49,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31093 states to 31093 states and 43312 transitions. [2021-07-06 20:41:49,648 INFO L704 BuchiCegarLoop]: Abstraction has 31093 states and 43312 transitions. [2021-07-06 20:41:49,648 INFO L587 BuchiCegarLoop]: Abstraction has 31093 states and 43312 transitions. [2021-07-06 20:41:49,648 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-07-06 20:41:49,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31093 states and 43312 transitions. [2021-07-06 20:41:49,751 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30898 [2021-07-06 20:41:49,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:49,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:49,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:49,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:49,752 INFO L791 eck$LassoCheckResult]: Stem: 275425#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 275297#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 275238#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 275013#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 275014#L418-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 275442#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 289763#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 289762#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 289761#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 289760#L443-1 assume !(0 == ~M_E~0); 289759#L603-1 assume !(0 == ~T1_E~0); 289758#L608-1 assume !(0 == ~T2_E~0); 289757#L613-1 assume !(0 == ~T3_E~0); 289756#L618-1 assume !(0 == ~T4_E~0); 289755#L623-1 assume !(0 == ~T5_E~0); 289754#L628-1 assume !(0 == ~E_M~0); 289753#L633-1 assume !(0 == ~E_1~0); 289752#L638-1 assume !(0 == ~E_2~0); 289751#L643-1 assume !(0 == ~E_3~0); 289750#L648-1 assume !(0 == ~E_4~0); 289749#L653-1 assume !(0 == ~E_5~0); 289748#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 289747#L296 assume !(1 == ~m_pc~0); 289746#L296-2 is_master_triggered_~__retres1~0 := 0; 289745#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 289744#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 289743#L747 assume !(0 != activate_threads_~tmp~1); 289742#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 289741#L315 assume !(1 == ~t1_pc~0); 289740#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 289765#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 289764#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 289735#L755 assume !(0 != activate_threads_~tmp___0~0); 289734#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 289733#L334 assume !(1 == ~t2_pc~0); 289732#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 289731#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 289730#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 289729#L763 assume !(0 != activate_threads_~tmp___1~0); 289728#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 289727#L353 assume !(1 == ~t3_pc~0); 289725#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 289724#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 289723#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 289722#L771 assume !(0 != activate_threads_~tmp___2~0); 289721#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 289720#L372 assume !(1 == ~t4_pc~0); 289719#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 289718#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 289717#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 289715#L779 assume !(0 != activate_threads_~tmp___3~0); 289713#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 289668#L391 assume !(1 == ~t5_pc~0); 289665#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 289664#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 289663#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 289660#L787 assume !(0 != activate_threads_~tmp___4~0); 289659#L787-2 assume !(1 == ~M_E~0); 289658#L671-1 assume !(1 == ~T1_E~0); 289657#L676-1 assume !(1 == ~T2_E~0); 289656#L681-1 assume !(1 == ~T3_E~0); 289654#L686-1 assume !(1 == ~T4_E~0); 289652#L691-1 assume !(1 == ~T5_E~0); 289650#L696-1 assume !(1 == ~E_M~0); 289648#L701-1 assume !(1 == ~E_1~0); 289646#L706-1 assume !(1 == ~E_2~0); 289644#L711-1 assume !(1 == ~E_3~0); 289642#L716-1 assume !(1 == ~E_4~0); 289640#L721-1 assume !(1 == ~E_5~0); 275112#L932-1 assume !false; 289600#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 289599#L578 [2021-07-06 20:41:49,752 INFO L793 eck$LassoCheckResult]: Loop: 289599#L578 assume !false; 289598#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 289593#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 289591#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 289590#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 289589#L503 assume 0 != eval_~tmp~0; 289586#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 289439#L511 assume !(0 != eval_~tmp_ndt_1~0); 289440#L508 assume !(0 == ~t1_st~0); 289777#L522 assume !(0 == ~t2_st~0); 289773#L536 assume !(0 == ~t3_st~0); 289768#L550 assume !(0 == ~t4_st~0); 289604#L564 assume !(0 == ~t5_st~0); 289599#L578 [2021-07-06 20:41:49,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:49,753 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-07-06 20:41:49,753 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:49,753 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894597262] [2021-07-06 20:41:49,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:49,753 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:49,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:49,766 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,766 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:49,768 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,769 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:49,771 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,772 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:49,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:49,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:49,773 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894597262] [2021-07-06 20:41:49,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894597262] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:49,773 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:49,773 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:49,773 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124233966] [2021-07-06 20:41:49,773 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:41:49,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:49,774 INFO L82 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 2 times [2021-07-06 20:41:49,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:49,774 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [708699349] [2021-07-06 20:41:49,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:49,774 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:49,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:49,777 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:49,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:49,778 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:49,781 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:49,974 WARN L205 SmtUtils]: Spent 192.00 ms on a formula simplification. DAG size of input: 32 DAG size of output: 30 [2021-07-06 20:41:49,976 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:49,977 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 39 [2021-07-06 20:41:49,996 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:49,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:49,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:49,997 INFO L87 Difference]: Start difference. First operand 31093 states and 43312 transitions. cyclomatic complexity: 12222 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:50,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:50,082 INFO L93 Difference]: Finished difference Result 31006 states and 43185 transitions. [2021-07-06 20:41:50,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:50,083 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31006 states and 43185 transitions. [2021-07-06 20:41:50,191 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30898 [2021-07-06 20:41:50,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31006 states to 31006 states and 43185 transitions. [2021-07-06 20:41:50,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31006 [2021-07-06 20:41:50,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31006 [2021-07-06 20:41:50,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31006 states and 43185 transitions. [2021-07-06 20:41:50,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:50,293 INFO L681 BuchiCegarLoop]: Abstraction has 31006 states and 43185 transitions. [2021-07-06 20:41:50,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31006 states and 43185 transitions. [2021-07-06 20:41:50,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31006 to 31006. [2021-07-06 20:41:50,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31006 states, 31006 states have (on average 1.3927949429142747) internal successors, (43185), 31005 states have internal predecessors, (43185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:50,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31006 states to 31006 states and 43185 transitions. [2021-07-06 20:41:50,778 INFO L704 BuchiCegarLoop]: Abstraction has 31006 states and 43185 transitions. [2021-07-06 20:41:50,778 INFO L587 BuchiCegarLoop]: Abstraction has 31006 states and 43185 transitions. [2021-07-06 20:41:50,778 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-07-06 20:41:50,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31006 states and 43185 transitions. [2021-07-06 20:41:50,862 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30898 [2021-07-06 20:41:50,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:50,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:50,863 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:50,863 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:50,864 INFO L791 eck$LassoCheckResult]: Stem: 337518#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 337396#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 337337#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 337116#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 337117#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 337246#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 337247#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 337119#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 337120#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 337346#L443-1 assume !(0 == ~M_E~0); 337347#L603-1 assume !(0 == ~T1_E~0); 337353#L608-1 assume !(0 == ~T2_E~0); 337354#L613-1 assume !(0 == ~T3_E~0); 337270#L618-1 assume !(0 == ~T4_E~0); 337271#L623-1 assume !(0 == ~T5_E~0); 337329#L628-1 assume !(0 == ~E_M~0); 337191#L633-1 assume !(0 == ~E_1~0); 337192#L638-1 assume !(0 == ~E_2~0); 337028#L643-1 assume !(0 == ~E_3~0); 337029#L648-1 assume !(0 == ~E_4~0); 337130#L653-1 assume !(0 == ~E_5~0); 337131#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 337389#L296 assume !(1 == ~m_pc~0); 337377#L296-2 is_master_triggered_~__retres1~0 := 0; 337378#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 337404#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 337468#L747 assume !(0 != activate_threads_~tmp~1); 337453#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 337454#L315 assume !(1 == ~t1_pc~0); 337578#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 337579#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 337609#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 337622#L755 assume !(0 != activate_threads_~tmp___0~0); 337623#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 337084#L334 assume !(1 == ~t2_pc~0); 337085#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 337082#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 337083#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 337140#L763 assume !(0 != activate_threads_~tmp___1~0); 337124#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 337125#L353 assume !(1 == ~t3_pc~0); 337253#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 337254#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 337250#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 337251#L771 assume !(0 != activate_threads_~tmp___2~0); 337496#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 337483#L372 assume !(1 == ~t4_pc~0); 337484#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 337488#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 337448#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 337449#L779 assume !(0 != activate_threads_~tmp___3~0); 337645#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 337179#L391 assume !(1 == ~t5_pc~0); 337180#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 337184#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 355157#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 337203#L787 assume !(0 != activate_threads_~tmp___4~0); 337204#L787-2 assume !(1 == ~M_E~0); 337535#L671-1 assume !(1 == ~T1_E~0); 337536#L676-1 assume !(1 == ~T2_E~0); 337457#L681-1 assume !(1 == ~T3_E~0); 337458#L686-1 assume !(1 == ~T4_E~0); 337647#L691-1 assume !(1 == ~T5_E~0); 337648#L696-1 assume !(1 == ~E_M~0); 355096#L701-1 assume !(1 == ~E_1~0); 355094#L706-1 assume !(1 == ~E_2~0); 355092#L711-1 assume !(1 == ~E_3~0); 355090#L716-1 assume !(1 == ~E_4~0); 355089#L721-1 assume !(1 == ~E_5~0); 337211#L932-1 assume !false; 355059#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 355057#L578 [2021-07-06 20:41:50,864 INFO L793 eck$LassoCheckResult]: Loop: 355057#L578 assume !false; 355056#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 355054#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 355041#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 355036#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 355029#L503 assume 0 != eval_~tmp~0; 355021#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 355016#L511 assume !(0 != eval_~tmp_ndt_1~0); 353688#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 353685#L525 assume !(0 != eval_~tmp_ndt_2~0); 353683#L522 assume !(0 == ~t2_st~0); 353679#L536 assume !(0 == ~t3_st~0); 353675#L550 assume !(0 == ~t4_st~0); 353672#L564 assume !(0 == ~t5_st~0); 355057#L578 [2021-07-06 20:41:50,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:50,864 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-07-06 20:41:50,865 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:50,865 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323419830] [2021-07-06 20:41:50,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:50,865 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:50,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:50,878 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:50,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:50,885 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:50,901 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:50,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:50,902 INFO L82 PathProgramCache]: Analyzing trace with hash -11527191, now seen corresponding path program 1 times [2021-07-06 20:41:50,902 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:50,902 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351585357] [2021-07-06 20:41:50,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:50,903 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:50,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:50,905 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:50,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:50,907 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:50,908 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:50,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:50,909 INFO L82 PathProgramCache]: Analyzing trace with hash 888960747, now seen corresponding path program 1 times [2021-07-06 20:41:50,909 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:50,909 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252914783] [2021-07-06 20:41:50,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:50,909 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:50,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:50,926 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:50,927 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:50,927 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:50,927 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:50,931 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:50,931 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:50,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:50,932 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:50,932 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252914783] [2021-07-06 20:41:50,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252914783] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:50,932 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:50,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:50,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [255548213] [2021-07-06 20:41:50,982 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:50,983 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 44 [2021-07-06 20:41:51,009 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:51,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:51,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:51,010 INFO L87 Difference]: Start difference. First operand 31006 states and 43185 transitions. cyclomatic complexity: 12182 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:51,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:51,381 INFO L93 Difference]: Finished difference Result 58072 states and 80623 transitions. [2021-07-06 20:41:51,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:51,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58072 states and 80623 transitions. [2021-07-06 20:41:51,599 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 57948 [2021-07-06 20:41:51,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58072 states to 58072 states and 80623 transitions. [2021-07-06 20:41:51,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58072 [2021-07-06 20:41:51,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58072 [2021-07-06 20:41:51,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58072 states and 80623 transitions. [2021-07-06 20:41:51,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:51,779 INFO L681 BuchiCegarLoop]: Abstraction has 58072 states and 80623 transitions. [2021-07-06 20:41:51,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58072 states and 80623 transitions. [2021-07-06 20:41:52,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58072 to 56756. [2021-07-06 20:41:52,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56756 states, 56756 states have (on average 1.3899323419550356) internal successors, (78887), 56755 states have internal predecessors, (78887), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:52,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56756 states to 56756 states and 78887 transitions. [2021-07-06 20:41:52,612 INFO L704 BuchiCegarLoop]: Abstraction has 56756 states and 78887 transitions. [2021-07-06 20:41:52,612 INFO L587 BuchiCegarLoop]: Abstraction has 56756 states and 78887 transitions. [2021-07-06 20:41:52,612 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-07-06 20:41:52,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56756 states and 78887 transitions. [2021-07-06 20:41:52,764 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 56632 [2021-07-06 20:41:52,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:52,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:52,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:52,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:52,766 INFO L791 eck$LassoCheckResult]: Stem: 426626#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 426498#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 426429#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 426207#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 426208#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 426336#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 426337#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 426210#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 426211#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 426442#L443-1 assume !(0 == ~M_E~0); 426443#L603-1 assume !(0 == ~T1_E~0); 426448#L608-1 assume !(0 == ~T2_E~0); 426449#L613-1 assume !(0 == ~T3_E~0); 426362#L618-1 assume !(0 == ~T4_E~0); 426363#L623-1 assume !(0 == ~T5_E~0); 426420#L628-1 assume !(0 == ~E_M~0); 426286#L633-1 assume !(0 == ~E_1~0); 426287#L638-1 assume !(0 == ~E_2~0); 426114#L643-1 assume !(0 == ~E_3~0); 426115#L648-1 assume !(0 == ~E_4~0); 426221#L653-1 assume !(0 == ~E_5~0); 426222#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 426491#L296 assume !(1 == ~m_pc~0); 426478#L296-2 is_master_triggered_~__retres1~0 := 0; 426479#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 426506#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 426572#L747 assume !(0 != activate_threads_~tmp~1); 426558#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 426559#L315 assume !(1 == ~t1_pc~0); 426688#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 426689#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 426725#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 426743#L755 assume !(0 != activate_threads_~tmp___0~0); 426744#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 426175#L334 assume !(1 == ~t2_pc~0); 426176#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 426173#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 426174#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 426232#L763 assume !(0 != activate_threads_~tmp___1~0); 426215#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 426216#L353 assume !(1 == ~t3_pc~0); 426343#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 426344#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 426340#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 426341#L771 assume !(0 != activate_threads_~tmp___2~0); 426608#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 426590#L372 assume !(1 == ~t4_pc~0); 426591#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 426596#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 426552#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 426553#L779 assume !(0 != activate_threads_~tmp___3~0); 426770#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 426273#L391 assume !(1 == ~t5_pc~0); 426274#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 426269#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 426270#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 426300#L787 assume !(0 != activate_threads_~tmp___4~0); 426301#L787-2 assume !(1 == ~M_E~0); 426302#L671-1 assume !(1 == ~T1_E~0); 426112#L676-1 assume !(1 == ~T2_E~0); 426113#L681-1 assume !(1 == ~T3_E~0); 426219#L686-1 assume !(1 == ~T4_E~0); 426220#L691-1 assume !(1 == ~T5_E~0); 426444#L696-1 assume !(1 == ~E_M~0); 426445#L701-1 assume !(1 == ~E_1~0); 445236#L706-1 assume !(1 == ~E_2~0); 445234#L711-1 assume !(1 == ~E_3~0); 426609#L716-1 assume !(1 == ~E_4~0); 426610#L721-1 assume !(1 == ~E_5~0); 426305#L932-1 assume !false; 437868#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 437869#L578 [2021-07-06 20:41:52,766 INFO L793 eck$LassoCheckResult]: Loop: 437869#L578 assume !false; 440549#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 440547#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 440546#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 440545#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 440544#L503 assume 0 != eval_~tmp~0; 440542#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 440543#L511 assume !(0 != eval_~tmp_ndt_1~0); 440564#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 440563#L525 assume !(0 != eval_~tmp_ndt_2~0); 440562#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 430841#L539 assume !(0 != eval_~tmp_ndt_3~0); 440560#L536 assume !(0 == ~t3_st~0); 440556#L550 assume !(0 == ~t4_st~0); 440553#L564 assume !(0 == ~t5_st~0); 437869#L578 [2021-07-06 20:41:52,766 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:52,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-07-06 20:41:52,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:52,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562651209] [2021-07-06 20:41:52,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:52,767 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:52,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:52,773 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:52,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:52,779 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:52,790 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:52,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:52,790 INFO L82 PathProgramCache]: Analyzing trace with hash -524557124, now seen corresponding path program 1 times [2021-07-06 20:41:52,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:52,791 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697262344] [2021-07-06 20:41:52,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:52,791 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:52,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:52,793 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:52,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:52,795 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:52,796 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:52,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:52,797 INFO L82 PathProgramCache]: Analyzing trace with hash 1620765178, now seen corresponding path program 1 times [2021-07-06 20:41:52,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:52,797 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667605684] [2021-07-06 20:41:52,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:52,797 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:52,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:52,811 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:52,812 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:52,812 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:52,813 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:52,815 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:52,816 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:52,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:52,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:52,816 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667605684] [2021-07-06 20:41:52,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667605684] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:52,817 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:52,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:52,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172891964] [2021-07-06 20:41:52,871 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:52,872 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 49 [2021-07-06 20:41:52,911 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:52,912 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:52,912 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:52,912 INFO L87 Difference]: Start difference. First operand 56756 states and 78887 transitions. cyclomatic complexity: 22134 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:53,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:53,359 INFO L93 Difference]: Finished difference Result 102252 states and 141947 transitions. [2021-07-06 20:41:53,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:53,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102252 states and 141947 transitions. [2021-07-06 20:41:53,784 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 102096 [2021-07-06 20:41:54,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102252 states to 102252 states and 141947 transitions. [2021-07-06 20:41:54,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102252 [2021-07-06 20:41:54,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102252 [2021-07-06 20:41:54,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102252 states and 141947 transitions. [2021-07-06 20:41:54,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:54,146 INFO L681 BuchiCegarLoop]: Abstraction has 102252 states and 141947 transitions. [2021-07-06 20:41:54,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102252 states and 141947 transitions. [2021-07-06 20:41:55,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102252 to 98556. [2021-07-06 20:41:55,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98556 states, 98556 states have (on average 1.392538252364138) internal successors, (137243), 98555 states have internal predecessors, (137243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:55,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98556 states to 98556 states and 137243 transitions. [2021-07-06 20:41:55,607 INFO L704 BuchiCegarLoop]: Abstraction has 98556 states and 137243 transitions. [2021-07-06 20:41:55,607 INFO L587 BuchiCegarLoop]: Abstraction has 98556 states and 137243 transitions. [2021-07-06 20:41:55,607 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-07-06 20:41:55,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98556 states and 137243 transitions. [2021-07-06 20:41:55,910 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 98400 [2021-07-06 20:41:55,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:41:55,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:41:55,911 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:55,911 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:41:55,911 INFO L791 eck$LassoCheckResult]: Stem: 585660#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 585524#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 585454#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 585226#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 585227#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 585355#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 585356#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 585229#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 585230#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 585468#L443-1 assume !(0 == ~M_E~0); 585469#L603-1 assume !(0 == ~T1_E~0); 585474#L608-1 assume !(0 == ~T2_E~0); 585475#L613-1 assume !(0 == ~T3_E~0); 585381#L618-1 assume !(0 == ~T4_E~0); 585382#L623-1 assume !(0 == ~T5_E~0); 585445#L628-1 assume !(0 == ~E_M~0); 585301#L633-1 assume !(0 == ~E_1~0); 585302#L638-1 assume !(0 == ~E_2~0); 585130#L643-1 assume !(0 == ~E_3~0); 585131#L648-1 assume !(0 == ~E_4~0); 585241#L653-1 assume !(0 == ~E_5~0); 585242#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 585518#L296 assume !(1 == ~m_pc~0); 585506#L296-2 is_master_triggered_~__retres1~0 := 0; 585507#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 585532#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 585606#L747 assume !(0 != activate_threads_~tmp~1); 585588#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 585589#L315 assume !(1 == ~t1_pc~0); 585728#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 585729#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 585765#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 585781#L755 assume !(0 != activate_threads_~tmp___0~0); 585782#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 585191#L334 assume !(1 == ~t2_pc~0); 585192#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 585189#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 585190#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 585252#L763 assume !(0 != activate_threads_~tmp___1~0); 585235#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 585236#L353 assume !(1 == ~t3_pc~0); 585362#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 585363#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 585359#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 585360#L771 assume !(0 != activate_threads_~tmp___2~0); 585640#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 585625#L372 assume !(1 == ~t4_pc~0); 585626#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 585631#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 585582#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 585583#L779 assume !(0 != activate_threads_~tmp___3~0); 585813#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 585288#L391 assume !(1 == ~t5_pc~0); 585289#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 585294#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 585758#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 585759#L787 assume !(0 != activate_threads_~tmp___4~0); 585317#L787-2 assume !(1 == ~M_E~0); 585318#L671-1 assume !(1 == ~T1_E~0); 585128#L676-1 assume !(1 == ~T2_E~0); 585129#L681-1 assume !(1 == ~T3_E~0); 585592#L686-1 assume !(1 == ~T4_E~0); 620186#L691-1 assume !(1 == ~T5_E~0); 585470#L696-1 assume !(1 == ~E_M~0); 585471#L701-1 assume !(1 == ~E_1~0); 585396#L706-1 assume !(1 == ~E_2~0); 585397#L711-1 assume !(1 == ~E_3~0); 585641#L716-1 assume !(1 == ~E_4~0); 585642#L721-1 assume !(1 == ~E_5~0); 585322#L932-1 assume !false; 620124#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 615972#L578 [2021-07-06 20:41:55,912 INFO L793 eck$LassoCheckResult]: Loop: 615972#L578 assume !false; 620114#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 620107#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 620099#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 620093#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 620087#L503 assume 0 != eval_~tmp~0; 620080#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 620075#L511 assume !(0 != eval_~tmp_ndt_1~0); 606421#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 606418#L525 assume !(0 != eval_~tmp_ndt_2~0); 606416#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 606415#L539 assume !(0 != eval_~tmp_ndt_3~0); 606412#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 606219#L553 assume !(0 != eval_~tmp_ndt_4~0); 606410#L550 assume !(0 == ~t4_st~0); 608483#L564 assume !(0 == ~t5_st~0); 615972#L578 [2021-07-06 20:41:55,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:55,912 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-07-06 20:41:55,912 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:55,912 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779547387] [2021-07-06 20:41:55,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:55,913 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:55,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:55,919 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:55,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:55,925 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:55,936 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:55,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:55,937 INFO L82 PathProgramCache]: Analyzing trace with hash 913205966, now seen corresponding path program 1 times [2021-07-06 20:41:55,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:55,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2067151950] [2021-07-06 20:41:55,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:55,938 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:55,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:55,940 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:55,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:41:55,942 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:41:55,943 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:41:55,943 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:41:55,944 INFO L82 PathProgramCache]: Analyzing trace with hash -1301279408, now seen corresponding path program 1 times [2021-07-06 20:41:55,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:41:55,944 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125392563] [2021-07-06 20:41:55,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:41:55,944 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:41:55,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:41:55,960 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:55,961 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:55,961 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:55,962 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:41:55,964 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:55,965 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:41:55,965 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:41:55,965 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:41:55,965 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2125392563] [2021-07-06 20:41:55,966 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2125392563] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:41:55,966 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:41:55,966 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:41:55,966 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944873354] [2021-07-06 20:41:56,035 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:41:56,038 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 54 [2021-07-06 20:41:56,073 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:41:56,074 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:41:56,074 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:41:56,074 INFO L87 Difference]: Start difference. First operand 98556 states and 137243 transitions. cyclomatic complexity: 38690 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:41:56,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:41:56,912 INFO L93 Difference]: Finished difference Result 185300 states and 257483 transitions. [2021-07-06 20:41:56,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:41:56,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 185300 states and 257483 transitions. [2021-07-06 20:41:58,011 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 185080 [2021-07-06 20:41:58,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 185300 states to 185300 states and 257483 transitions. [2021-07-06 20:41:58,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185300 [2021-07-06 20:41:58,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185300 [2021-07-06 20:41:58,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 185300 states and 257483 transitions. [2021-07-06 20:41:58,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:41:58,546 INFO L681 BuchiCegarLoop]: Abstraction has 185300 states and 257483 transitions. [2021-07-06 20:41:58,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185300 states and 257483 transitions. [2021-07-06 20:42:00,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185300 to 184180. [2021-07-06 20:42:00,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184180 states, 184180 states have (on average 1.3906993158866325) internal successors, (256139), 184179 states have internal predecessors, (256139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:00,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184180 states to 184180 states and 256139 transitions. [2021-07-06 20:42:00,825 INFO L704 BuchiCegarLoop]: Abstraction has 184180 states and 256139 transitions. [2021-07-06 20:42:00,825 INFO L587 BuchiCegarLoop]: Abstraction has 184180 states and 256139 transitions. [2021-07-06 20:42:00,825 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-07-06 20:42:00,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184180 states and 256139 transitions. [2021-07-06 20:42:01,379 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 183960 [2021-07-06 20:42:01,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:42:01,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:42:01,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:01,380 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:01,380 INFO L791 eck$LassoCheckResult]: Stem: 869533#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 869394#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 869319#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 869090#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 869091#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 869214#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 869215#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 869094#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 869095#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 869334#L443-1 assume !(0 == ~M_E~0); 869335#L603-1 assume !(0 == ~T1_E~0); 869340#L608-1 assume !(0 == ~T2_E~0); 869341#L613-1 assume !(0 == ~T3_E~0); 869240#L618-1 assume !(0 == ~T4_E~0); 869241#L623-1 assume !(0 == ~T5_E~0); 869311#L628-1 assume !(0 == ~E_M~0); 869168#L633-1 assume !(0 == ~E_1~0); 869169#L638-1 assume !(0 == ~E_2~0); 868994#L643-1 assume !(0 == ~E_3~0); 868995#L648-1 assume !(0 == ~E_4~0); 869106#L653-1 assume !(0 == ~E_5~0); 869107#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 869386#L296 assume !(1 == ~m_pc~0); 869376#L296-2 is_master_triggered_~__retres1~0 := 0; 869377#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 869402#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 869473#L747 assume !(0 != activate_threads_~tmp~1); 869458#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 869459#L315 assume !(1 == ~t1_pc~0); 869599#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 869600#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 869637#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 869653#L755 assume !(0 != activate_threads_~tmp___0~0); 869654#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 869057#L334 assume !(1 == ~t2_pc~0); 869058#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 869055#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 869056#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 869117#L763 assume !(0 != activate_threads_~tmp___1~0); 869100#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 869101#L353 assume !(1 == ~t3_pc~0); 869221#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 869222#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 869218#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 869219#L771 assume !(0 != activate_threads_~tmp___2~0); 869514#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 869494#L372 assume !(1 == ~t4_pc~0); 869495#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 869501#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 869453#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 869454#L779 assume !(0 != activate_threads_~tmp___3~0); 869679#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 869155#L391 assume !(1 == ~t5_pc~0); 869156#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 869161#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 869631#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 869632#L787 assume !(0 != activate_threads_~tmp___4~0); 869184#L787-2 assume !(1 == ~M_E~0); 869185#L671-1 assume !(1 == ~T1_E~0); 868992#L676-1 assume !(1 == ~T2_E~0); 868993#L681-1 assume !(1 == ~T3_E~0); 928580#L686-1 assume !(1 == ~T4_E~0); 928579#L691-1 assume !(1 == ~T5_E~0); 928577#L696-1 assume !(1 == ~E_M~0); 928575#L701-1 assume !(1 == ~E_1~0); 928573#L706-1 assume !(1 == ~E_2~0); 928572#L711-1 assume !(1 == ~E_3~0); 928566#L716-1 assume !(1 == ~E_4~0); 928564#L721-1 assume !(1 == ~E_5~0); 869188#L932-1 assume !false; 928545#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 928543#L578 [2021-07-06 20:42:01,380 INFO L793 eck$LassoCheckResult]: Loop: 928543#L578 assume !false; 928541#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 928538#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 928536#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 928533#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 928531#L503 assume 0 != eval_~tmp~0; 928528#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 928529#L511 assume !(0 != eval_~tmp_ndt_1~0); 928519#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 928516#L525 assume !(0 != eval_~tmp_ndt_2~0); 928515#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 928512#L539 assume !(0 != eval_~tmp_ndt_3~0); 928510#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 928457#L553 assume !(0 != eval_~tmp_ndt_4~0); 881492#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 881487#L567 assume !(0 != eval_~tmp_ndt_5~0); 881488#L564 assume !(0 == ~t5_st~0); 928543#L578 [2021-07-06 20:42:01,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:01,381 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-07-06 20:42:01,381 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:01,381 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698796636] [2021-07-06 20:42:01,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:01,381 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:01,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:01,387 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:01,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:01,392 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:01,403 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:01,404 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:01,404 INFO L82 PathProgramCache]: Analyzing trace with hash -1755558441, now seen corresponding path program 1 times [2021-07-06 20:42:01,404 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:01,404 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192518948] [2021-07-06 20:42:01,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:01,404 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:01,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:01,407 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:01,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:01,408 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:01,410 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:01,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:01,410 INFO L82 PathProgramCache]: Analyzing trace with hash -1685128299, now seen corresponding path program 1 times [2021-07-06 20:42:01,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:01,410 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296203144] [2021-07-06 20:42:01,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:01,411 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:01,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:42:01,425 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:01,425 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:42:01,426 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:01,426 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:42:01,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:42:01,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:42:01,429 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296203144] [2021-07-06 20:42:01,429 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296203144] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:42:01,429 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:42:01,429 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:42:01,429 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423492022] [2021-07-06 20:42:01,487 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:01,489 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 59 [2021-07-06 20:42:01,522 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:42:01,523 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:42:01,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:42:01,523 INFO L87 Difference]: Start difference. First operand 184180 states and 256139 transitions. cyclomatic complexity: 71962 Second operand has 3 states, 2 states have (on average 44.0) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:02,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:42:02,928 INFO L93 Difference]: Finished difference Result 313788 states and 437331 transitions. [2021-07-06 20:42:02,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:42:02,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 313788 states and 437331 transitions. [2021-07-06 20:42:05,016 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 313440 [2021-07-06 20:42:05,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 313788 states to 313788 states and 437331 transitions. [2021-07-06 20:42:05,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 313788 [2021-07-06 20:42:05,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 313788 [2021-07-06 20:42:05,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 313788 states and 437331 transitions. [2021-07-06 20:42:06,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:42:06,551 INFO L681 BuchiCegarLoop]: Abstraction has 313788 states and 437331 transitions. [2021-07-06 20:42:06,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313788 states and 437331 transitions. [2021-07-06 20:42:09,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313788 to 311100. [2021-07-06 20:42:09,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311100 states, 311100 states have (on average 1.3971166827386692) internal successors, (434643), 311099 states have internal predecessors, (434643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:42:09,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311100 states to 311100 states and 434643 transitions. [2021-07-06 20:42:09,933 INFO L704 BuchiCegarLoop]: Abstraction has 311100 states and 434643 transitions. [2021-07-06 20:42:09,933 INFO L587 BuchiCegarLoop]: Abstraction has 311100 states and 434643 transitions. [2021-07-06 20:42:09,933 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-07-06 20:42:09,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311100 states and 434643 transitions. [2021-07-06 20:42:11,590 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 310752 [2021-07-06 20:42:11,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:42:11,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:42:11,591 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:11,591 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:42:11,591 INFO L791 eck$LassoCheckResult]: Stem: 1367495#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1367357#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1367294#L895 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1367066#L411 assume 1 == ~m_i~0;~m_st~0 := 0; 1367067#L418-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1367195#L423-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1367196#L428-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1367068#L433-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1367069#L438-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1367305#L443-1 assume !(0 == ~M_E~0); 1367306#L603-1 assume !(0 == ~T1_E~0); 1367313#L608-1 assume !(0 == ~T2_E~0); 1367314#L613-1 assume !(0 == ~T3_E~0); 1367220#L618-1 assume !(0 == ~T4_E~0); 1367221#L623-1 assume !(0 == ~T5_E~0); 1367285#L628-1 assume !(0 == ~E_M~0); 1367143#L633-1 assume !(0 == ~E_1~0); 1367144#L638-1 assume !(0 == ~E_2~0); 1366970#L643-1 assume !(0 == ~E_3~0); 1366971#L648-1 assume !(0 == ~E_4~0); 1367080#L653-1 assume !(0 == ~E_5~0); 1367081#L658-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1367354#L296 assume !(1 == ~m_pc~0); 1367339#L296-2 is_master_triggered_~__retres1~0 := 0; 1367340#L307 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1367365#L308 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1367440#L747 assume !(0 != activate_threads_~tmp~1); 1367425#L747-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1367426#L315 assume !(1 == ~t1_pc~0); 1367566#L315-2 is_transmit1_triggered_~__retres1~1 := 0; 1367567#L326 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1367605#L327 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1367625#L755 assume !(0 != activate_threads_~tmp___0~0); 1367626#L755-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1367033#L334 assume !(1 == ~t2_pc~0); 1367034#L334-2 is_transmit2_triggered_~__retres1~2 := 0; 1367031#L345 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1367032#L346 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1367091#L763 assume !(0 != activate_threads_~tmp___1~0); 1367074#L763-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1367075#L353 assume !(1 == ~t3_pc~0); 1367203#L353-2 is_transmit3_triggered_~__retres1~3 := 0; 1367204#L364 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1367200#L365 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1367201#L771 assume !(0 != activate_threads_~tmp___2~0); 1367480#L771-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1367463#L372 assume !(1 == ~t4_pc~0); 1367464#L372-2 is_transmit4_triggered_~__retres1~4 := 0; 1367470#L383 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1367419#L384 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1367420#L779 assume !(0 != activate_threads_~tmp___3~0); 1367666#L779-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1367128#L391 assume !(1 == ~t5_pc~0); 1367129#L391-2 is_transmit5_triggered_~__retres1~5 := 0; 1367124#L402 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1367125#L403 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1367156#L787 assume !(0 != activate_threads_~tmp___4~0); 1367157#L787-2 assume !(1 == ~M_E~0); 1367160#L671-1 assume !(1 == ~T1_E~0); 1367516#L676-1 assume !(1 == ~T2_E~0); 1442692#L681-1 assume !(1 == ~T3_E~0); 1367078#L686-1 assume !(1 == ~T4_E~0); 1367079#L691-1 assume !(1 == ~T5_E~0); 1367668#L696-1 assume !(1 == ~E_M~0); 1442687#L701-1 assume !(1 == ~E_1~0); 1442685#L706-1 assume !(1 == ~E_2~0); 1442682#L711-1 assume !(1 == ~E_3~0); 1442680#L716-1 assume !(1 == ~E_4~0); 1442678#L721-1 assume !(1 == ~E_5~0); 1367162#L932-1 assume !false; 1442666#L933 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1442662#L578 [2021-07-06 20:42:11,592 INFO L793 eck$LassoCheckResult]: Loop: 1442662#L578 assume !false; 1442663#L499 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1442655#L456 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1442656#L488 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1442650#L489 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1442651#L503 assume 0 != eval_~tmp~0; 1442642#L503-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1442643#L511 assume !(0 != eval_~tmp_ndt_1~0); 1435571#L508 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1435568#L525 assume !(0 != eval_~tmp_ndt_2~0); 1435566#L522 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 1435059#L539 assume !(0 != eval_~tmp_ndt_3~0); 1435561#L536 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 1432542#L553 assume !(0 != eval_~tmp_ndt_4~0); 1435560#L550 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 1452517#L567 assume !(0 != eval_~tmp_ndt_5~0); 1442671#L564 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet15;havoc eval_#t~nondet15; 1442672#L581 assume !(0 != eval_~tmp_ndt_6~0); 1442662#L578 [2021-07-06 20:42:11,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:11,592 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-07-06 20:42:11,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:11,592 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709220138] [2021-07-06 20:42:11,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:11,592 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:11,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,599 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,603 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,615 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:11,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:11,616 INFO L82 PathProgramCache]: Analyzing trace with hash 1412259251, now seen corresponding path program 1 times [2021-07-06 20:42:11,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:11,616 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013088000] [2021-07-06 20:42:11,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:11,617 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:11,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,620 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,621 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,622 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:11,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:42:11,623 INFO L82 PathProgramCache]: Analyzing trace with hash -699373643, now seen corresponding path program 1 times [2021-07-06 20:42:11,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:42:11,623 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [385416926] [2021-07-06 20:42:11,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:42:11,623 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:42:11,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,629 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:42:11,634 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:42:11,652 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:42:11,725 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:11,726 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 64 [2021-07-06 20:42:12,703 WARN L205 SmtUtils]: Spent 927.00 ms on a formula simplification. DAG size of input: 251 DAG size of output: 179 [2021-07-06 20:42:12,719 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:42:12,747 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 257 [2021-07-06 20:42:13,027 WARN L205 SmtUtils]: Spent 278.00 ms on a formula simplification that was a NOOP. DAG size: 153 [2021-07-06 20:42:13,076 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.07 08:42:13 BoogieIcfgContainer [2021-07-06 20:42:13,077 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-07-06 20:42:13,077 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-07-06 20:42:13,077 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-07-06 20:42:13,077 INFO L275 PluginConnector]: Witness Printer initialized [2021-07-06 20:42:13,078 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:41:40" (3/4) ... [2021-07-06 20:42:13,080 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-07-06 20:42:13,139 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-07-06 20:42:13,140 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-07-06 20:42:13,141 INFO L168 Benchmark]: Toolchain (without parser) took 34121.74 ms. Allocated memory was 48.2 MB in the beginning and 14.2 GB in the end (delta: 14.2 GB). Free memory was 23.7 MB in the beginning and 10.2 GB in the end (delta: -10.2 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,141 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 48.2 MB. Free memory was 30.9 MB in the beginning and 30.8 MB in the end (delta: 32.8 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-07-06 20:42:13,141 INFO L168 Benchmark]: CACSL2BoogieTranslator took 347.82 ms. Allocated memory was 48.2 MB in the beginning and 58.7 MB in the end (delta: 10.5 MB). Free memory was 23.5 MB in the beginning and 38.4 MB in the end (delta: -14.9 MB). Peak memory consumption was 3.6 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,142 INFO L168 Benchmark]: Boogie Procedure Inliner took 87.16 ms. Allocated memory is still 58.7 MB. Free memory was 38.3 MB in the beginning and 33.2 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,142 INFO L168 Benchmark]: Boogie Preprocessor took 69.93 ms. Allocated memory is still 58.7 MB. Free memory was 33.2 MB in the beginning and 28.6 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,143 INFO L168 Benchmark]: RCFGBuilder took 1254.32 ms. Allocated memory was 58.7 MB in the beginning and 71.3 MB in the end (delta: 12.6 MB). Free memory was 28.4 MB in the beginning and 45.6 MB in the end (delta: -17.1 MB). Peak memory consumption was 19.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,143 INFO L168 Benchmark]: BuchiAutomizer took 32291.82 ms. Allocated memory was 71.3 MB in the beginning and 14.2 GB in the end (delta: 14.1 GB). Free memory was 45.6 MB in the beginning and 10.2 GB in the end (delta: -10.2 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,143 INFO L168 Benchmark]: Witness Printer took 63.06 ms. Allocated memory is still 14.2 GB. Free memory was 10.2 GB in the beginning and 10.2 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:42:13,144 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 48.2 MB. Free memory was 30.9 MB in the beginning and 30.8 MB in the end (delta: 32.8 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 347.82 ms. Allocated memory was 48.2 MB in the beginning and 58.7 MB in the end (delta: 10.5 MB). Free memory was 23.5 MB in the beginning and 38.4 MB in the end (delta: -14.9 MB). Peak memory consumption was 3.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 87.16 ms. Allocated memory is still 58.7 MB. Free memory was 38.3 MB in the beginning and 33.2 MB in the end (delta: 5.0 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 69.93 ms. Allocated memory is still 58.7 MB. Free memory was 33.2 MB in the beginning and 28.6 MB in the end (delta: 4.6 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1254.32 ms. Allocated memory was 58.7 MB in the beginning and 71.3 MB in the end (delta: 12.6 MB). Free memory was 28.4 MB in the beginning and 45.6 MB in the end (delta: -17.1 MB). Peak memory consumption was 19.2 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 32291.82 ms. Allocated memory was 71.3 MB in the beginning and 14.2 GB in the end (delta: 14.1 GB). Free memory was 45.6 MB in the beginning and 10.2 GB in the end (delta: -10.2 GB). Peak memory consumption was 4.0 GB. Max. memory is 16.1 GB. * Witness Printer took 63.06 ms. Allocated memory is still 14.2 GB. Free memory was 10.2 GB in the beginning and 10.2 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 311100 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 32.2s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 3.9s. Construction of modules took 0.9s. Büchi inclusion checks took 4.1s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 10702.5ms AutomataMinimizationTime, 24 MinimizatonAttempts, 53677 StatesRemovedByMinimization, 17 NontrivialMinimizations. Non-live state removal took 7.2s Buchi closure took 0.5s. Biggest automaton had 311100 states and ocurred in iteration 24. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 22195 SDtfs, 26987 SDslu, 21099 SDs, 0 SdLazy, 790 SolverSat, 330 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 985.2ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc5 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 498]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=16844} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=16844, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d75f5fc=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67acd1d6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35e2bba4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@601eadc8=0, NULL=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d08b7d0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@9ffb8c6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b776610=0, tmp=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7be8d941=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@597594af=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3229d6d1=0, NULL=16845, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d3f1227=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5042ffff=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@64a2169b=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d3be525=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37f7bfdb=0, T1_E=2, NULL=16846, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=16847, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 498]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L977] int __retres1 ; [L888] m_i = 1 [L889] t1_i = 1 [L890] t2_i = 1 [L891] t3_i = 1 [L892] t4_i = 1 [L893] t5_i = 1 [L918] int kernel_st ; [L919] int tmp ; [L920] int tmp___0 ; [L924] kernel_st = 0 [L418] COND TRUE m_i == 1 [L419] m_st = 0 [L423] COND TRUE t1_i == 1 [L424] t1_st = 0 [L428] COND TRUE t2_i == 1 [L429] t2_st = 0 [L433] COND TRUE t3_i == 1 [L434] t3_st = 0 [L438] COND TRUE t4_i == 1 [L439] t4_st = 0 [L443] COND TRUE t5_i == 1 [L444] t5_st = 0 [L603] COND FALSE !(M_E == 0) [L608] COND FALSE !(T1_E == 0) [L613] COND FALSE !(T2_E == 0) [L618] COND FALSE !(T3_E == 0) [L623] COND FALSE !(T4_E == 0) [L628] COND FALSE !(T5_E == 0) [L633] COND FALSE !(E_M == 0) [L638] COND FALSE !(E_1 == 0) [L643] COND FALSE !(E_2 == 0) [L648] COND FALSE !(E_3 == 0) [L653] COND FALSE !(E_4 == 0) [L658] COND FALSE !(E_5 == 0) [L736] int tmp ; [L737] int tmp___0 ; [L738] int tmp___1 ; [L739] int tmp___2 ; [L740] int tmp___3 ; [L741] int tmp___4 ; [L293] int __retres1 ; [L296] COND FALSE !(m_pc == 1) [L306] __retres1 = 0 [L308] return (__retres1); [L745] tmp = is_master_triggered() [L747] COND FALSE !(\read(tmp)) [L312] int __retres1 ; [L315] COND FALSE !(t1_pc == 1) [L325] __retres1 = 0 [L327] return (__retres1); [L753] tmp___0 = is_transmit1_triggered() [L755] COND FALSE !(\read(tmp___0)) [L331] int __retres1 ; [L334] COND FALSE !(t2_pc == 1) [L344] __retres1 = 0 [L346] return (__retres1); [L761] tmp___1 = is_transmit2_triggered() [L763] COND FALSE !(\read(tmp___1)) [L350] int __retres1 ; [L353] COND FALSE !(t3_pc == 1) [L363] __retres1 = 0 [L365] return (__retres1); [L769] tmp___2 = is_transmit3_triggered() [L771] COND FALSE !(\read(tmp___2)) [L369] int __retres1 ; [L372] COND FALSE !(t4_pc == 1) [L382] __retres1 = 0 [L384] return (__retres1); [L777] tmp___3 = is_transmit4_triggered() [L779] COND FALSE !(\read(tmp___3)) [L388] int __retres1 ; [L391] COND FALSE !(t5_pc == 1) [L401] __retres1 = 0 [L403] return (__retres1); [L785] tmp___4 = is_transmit5_triggered() [L787] COND FALSE !(\read(tmp___4)) [L671] COND FALSE !(M_E == 1) [L676] COND FALSE !(T1_E == 1) [L681] COND FALSE !(T2_E == 1) [L686] COND FALSE !(T3_E == 1) [L691] COND FALSE !(T4_E == 1) [L696] COND FALSE !(T5_E == 1) [L701] COND FALSE !(E_M == 1) [L706] COND FALSE !(E_1 == 1) [L711] COND FALSE !(E_2 == 1) [L716] COND FALSE !(E_3 == 1) [L721] COND FALSE !(E_4 == 1) [L726] COND FALSE !(E_5 == 1) [L932] COND TRUE 1 [L935] kernel_st = 1 [L494] int tmp ; Loop: [L498] COND TRUE 1 [L453] int __retres1 ; [L456] COND TRUE m_st == 0 [L457] __retres1 = 1 [L489] return (__retres1); [L501] tmp = exists_runnable_thread() [L503] COND TRUE \read(tmp) [L508] COND TRUE m_st == 0 [L509] int tmp_ndt_1; [L510] tmp_ndt_1 = __VERIFIER_nondet_int() [L511] COND FALSE !(\read(tmp_ndt_1)) [L522] COND TRUE t1_st == 0 [L523] int tmp_ndt_2; [L524] tmp_ndt_2 = __VERIFIER_nondet_int() [L525] COND FALSE !(\read(tmp_ndt_2)) [L536] COND TRUE t2_st == 0 [L537] int tmp_ndt_3; [L538] tmp_ndt_3 = __VERIFIER_nondet_int() [L539] COND FALSE !(\read(tmp_ndt_3)) [L550] COND TRUE t3_st == 0 [L551] int tmp_ndt_4; [L552] tmp_ndt_4 = __VERIFIER_nondet_int() [L553] COND FALSE !(\read(tmp_ndt_4)) [L564] COND TRUE t4_st == 0 [L565] int tmp_ndt_5; [L566] tmp_ndt_5 = __VERIFIER_nondet_int() [L567] COND FALSE !(\read(tmp_ndt_5)) [L578] COND TRUE t5_st == 0 [L579] int tmp_ndt_6; [L580] tmp_ndt_6 = __VERIFIER_nondet_int() [L581] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-07-06 20:42:13,202 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...