./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.04.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 8d31f386 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.04.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3723db60962369c4b10118802934116c8cea6114 .......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-wip.dd.multireach-323-8d31f38 [2021-07-06 20:43:31,801 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-07-06 20:43:31,804 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-07-06 20:43:31,843 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-07-06 20:43:31,843 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-07-06 20:43:31,847 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-07-06 20:43:31,848 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-07-06 20:43:31,853 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-07-06 20:43:31,855 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-07-06 20:43:31,859 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-07-06 20:43:31,860 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-07-06 20:43:31,861 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-07-06 20:43:31,862 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-07-06 20:43:31,864 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-07-06 20:43:31,865 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-07-06 20:43:31,866 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-07-06 20:43:31,869 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-07-06 20:43:31,870 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-07-06 20:43:31,872 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-07-06 20:43:31,879 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-07-06 20:43:31,880 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-07-06 20:43:31,881 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-07-06 20:43:31,882 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-07-06 20:43:31,883 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-07-06 20:43:31,889 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-07-06 20:43:31,889 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-07-06 20:43:31,890 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-07-06 20:43:31,891 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-07-06 20:43:31,891 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-07-06 20:43:31,892 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-07-06 20:43:31,892 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-07-06 20:43:31,893 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-07-06 20:43:31,894 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-07-06 20:43:31,895 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-07-06 20:43:31,896 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-07-06 20:43:31,896 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-07-06 20:43:31,897 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-07-06 20:43:31,897 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-07-06 20:43:31,897 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-07-06 20:43:31,898 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-07-06 20:43:31,899 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-07-06 20:43:31,903 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-07-06 20:43:31,944 INFO L113 SettingsManager]: Loading preferences was successful [2021-07-06 20:43:31,945 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-07-06 20:43:31,947 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-07-06 20:43:31,947 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-07-06 20:43:31,947 INFO L138 SettingsManager]: * Use SBE=true [2021-07-06 20:43:31,947 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-07-06 20:43:31,948 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-07-06 20:43:31,948 INFO L138 SettingsManager]: * Use old map elimination=false [2021-07-06 20:43:31,948 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-07-06 20:43:31,949 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-07-06 20:43:31,949 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-07-06 20:43:31,950 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-07-06 20:43:31,950 INFO L138 SettingsManager]: * sizeof long=4 [2021-07-06 20:43:31,950 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-07-06 20:43:31,950 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-07-06 20:43:31,950 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-07-06 20:43:31,951 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-07-06 20:43:31,951 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-07-06 20:43:31,951 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-07-06 20:43:31,951 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-07-06 20:43:31,951 INFO L138 SettingsManager]: * sizeof long double=12 [2021-07-06 20:43:31,952 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-07-06 20:43:31,952 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-07-06 20:43:31,952 INFO L138 SettingsManager]: * Use constant arrays=true [2021-07-06 20:43:31,952 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-07-06 20:43:31,952 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-07-06 20:43:31,953 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-07-06 20:43:31,953 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-07-06 20:43:31,953 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-07-06 20:43:31,953 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-07-06 20:43:31,954 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-07-06 20:43:31,954 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3723db60962369c4b10118802934116c8cea6114 [2021-07-06 20:43:32,229 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-07-06 20:43:32,253 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-07-06 20:43:32,256 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-07-06 20:43:32,257 INFO L271 PluginConnector]: Initializing CDTParser... [2021-07-06 20:43:32,257 INFO L275 PluginConnector]: CDTParser initialized [2021-07-06 20:43:32,258 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-07-06 20:43:32,329 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00c4cc6b7/0ab400e1b2ff46c893acb19802a87a61/FLAGc15fc4f90 [2021-07-06 20:43:32,739 INFO L306 CDTParser]: Found 1 translation units. [2021-07-06 20:43:32,740 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c [2021-07-06 20:43:32,749 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00c4cc6b7/0ab400e1b2ff46c893acb19802a87a61/FLAGc15fc4f90 [2021-07-06 20:43:32,766 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00c4cc6b7/0ab400e1b2ff46c893acb19802a87a61 [2021-07-06 20:43:32,768 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-07-06 20:43:32,770 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-07-06 20:43:32,774 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-07-06 20:43:32,775 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-07-06 20:43:32,777 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-07-06 20:43:32,778 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:43:32" (1/1) ... [2021-07-06 20:43:32,779 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@345f890c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:32, skipping insertion in model container [2021-07-06 20:43:32,779 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.07 08:43:32" (1/1) ... [2021-07-06 20:43:32,785 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-07-06 20:43:32,830 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-07-06 20:43:32,966 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] [2021-07-06 20:43:33,041 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:43:33,055 INFO L203 MainTranslator]: Completed pre-run [2021-07-06 20:43:33,070 WARN L224 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.04.cil.c[401,414] [2021-07-06 20:43:33,099 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-07-06 20:43:33,136 INFO L208 MainTranslator]: Completed translation [2021-07-06 20:43:33,137 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33 WrapperNode [2021-07-06 20:43:33,137 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-07-06 20:43:33,138 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-07-06 20:43:33,139 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-07-06 20:43:33,139 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-07-06 20:43:33,144 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,168 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,213 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-07-06 20:43:33,214 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-07-06 20:43:33,214 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-07-06 20:43:33,215 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-07-06 20:43:33,221 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,222 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,225 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,225 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,235 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,245 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,249 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,254 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-07-06 20:43:33,265 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-07-06 20:43:33,266 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-07-06 20:43:33,266 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-07-06 20:43:33,267 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (1/1) ... [2021-07-06 20:43:33,272 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-07-06 20:43:33,279 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-07-06 20:43:33,294 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-07-06 20:43:33,323 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-07-06 20:43:33,344 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-07-06 20:43:33,345 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-07-06 20:43:33,345 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-07-06 20:43:33,345 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-07-06 20:43:34,197 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-07-06 20:43:34,197 INFO L299 CfgBuilder]: Removed 148 assume(true) statements. [2021-07-06 20:43:34,199 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:43:34 BoogieIcfgContainer [2021-07-06 20:43:34,199 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-07-06 20:43:34,200 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-07-06 20:43:34,200 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-07-06 20:43:34,202 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-07-06 20:43:34,203 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:43:34,203 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.07 08:43:32" (1/3) ... [2021-07-06 20:43:34,204 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8f53d0b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:43:34, skipping insertion in model container [2021-07-06 20:43:34,204 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:43:34,204 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.07 08:43:33" (2/3) ... [2021-07-06 20:43:34,205 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8f53d0b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.07 08:43:34, skipping insertion in model container [2021-07-06 20:43:34,205 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-07-06 20:43:34,205 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:43:34" (3/3) ... [2021-07-06 20:43:34,206 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.04.cil.c [2021-07-06 20:43:34,245 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-07-06 20:43:34,246 INFO L360 BuchiCegarLoop]: Hoare is false [2021-07-06 20:43:34,246 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-07-06 20:43:34,246 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-07-06 20:43:34,246 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-07-06 20:43:34,246 INFO L364 BuchiCegarLoop]: Difference is false [2021-07-06 20:43:34,246 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-07-06 20:43:34,247 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-07-06 20:43:34,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2021-07-06 20:43:34,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:34,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:34,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,315 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,316 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-07-06 20:43:34,320 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,333 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 308 [2021-07-06 20:43:34,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:34,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:34,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,349 INFO L791 eck$LassoCheckResult]: Stem: 150#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 23#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 39#L731true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 247#L326true assume !(1 == ~m_i~0);~m_st~0 := 2; 318#L333-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 343#L338-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 199#L343-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 250#L348-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 295#L353-1true assume !(0 == ~M_E~0); 54#L494-1true assume !(0 == ~T1_E~0); 98#L499-1true assume !(0 == ~T2_E~0); 306#L504-1true assume !(0 == ~T3_E~0); 322#L509-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 362#L514-1true assume !(0 == ~E_1~0); 217#L519-1true assume !(0 == ~E_2~0); 269#L524-1true assume !(0 == ~E_3~0); 303#L529-1true assume !(0 == ~E_4~0); 148#L534-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15#L230true assume !(1 == ~m_pc~0); 48#L230-2true is_master_triggered_~__retres1~0 := 0; 17#L241true is_master_triggered_#res := is_master_triggered_~__retres1~0; 146#L242true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 231#L607true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 213#L607-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 255#L249true assume 1 == ~t1_pc~0; 324#L250true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 256#L260true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 325#L261true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 75#L615true assume !(0 != activate_threads_~tmp___0~0); 78#L615-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 100#L268true assume !(1 == ~t2_pc~0); 93#L268-2true is_transmit2_triggered_~__retres1~2 := 0; 103#L279true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 192#L280true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 285#L623true assume !(0 != activate_threads_~tmp___1~0); 260#L623-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 298#L287true assume 1 == ~t3_pc~0; 210#L288true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 299#L298true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211#L299true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 114#L631true assume !(0 != activate_threads_~tmp___2~0); 117#L631-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 122#L306true assume !(1 == ~t4_pc~0); 126#L306-2true is_transmit4_triggered_~__retres1~4 := 0; 121#L317true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24#L318true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 131#L639true assume !(0 != activate_threads_~tmp___3~0); 300#L639-2true assume !(1 == ~M_E~0); 358#L547-1true assume !(1 == ~T1_E~0); 215#L552-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 265#L557-1true assume !(1 == ~T3_E~0); 302#L562-1true assume !(1 == ~T4_E~0); 147#L567-1true assume !(1 == ~E_1~0); 176#L572-1true assume !(1 == ~E_2~0); 20#L577-1true assume !(1 == ~E_3~0); 79#L582-1true assume !(1 == ~E_4~0); 320#L768-1true [2021-07-06 20:43:34,353 INFO L793 eck$LassoCheckResult]: Loop: 320#L768-1true assume !false; 88#L769true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 272#L469true assume !true; 161#L484true start_simulation_~kernel_st~0 := 2; 253#L326-1true start_simulation_~kernel_st~0 := 3; 60#L494-2true assume !(0 == ~M_E~0); 65#L494-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 107#L499-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 309#L504-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 323#L509-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 371#L514-3true assume 0 == ~E_1~0;~E_1~0 := 1; 194#L519-3true assume 0 == ~E_2~0;~E_2~0 := 1; 235#L524-3true assume 0 == ~E_3~0;~E_3~0 := 1; 290#L529-3true assume !(0 == ~E_4~0); 135#L534-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 189#L230-15true assume !(1 == ~m_pc~0); 182#L230-17true is_master_triggered_~__retres1~0 := 0; 33#L241-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 157#L242-5true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 375#L607-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 352#L607-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 207#L249-15true assume 1 == ~t1_pc~0; 332#L250-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 234#L260-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 334#L261-5true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12#L615-15true assume !(0 != activate_threads_~tmp___0~0); 18#L615-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19#L268-15true assume 1 == ~t2_pc~0; 169#L269-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 63#L279-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 170#L280-5true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 229#L623-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 209#L623-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 226#L287-15true assume 1 == ~t3_pc~0; 355#L288-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 258#L298-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 356#L299-5true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 73#L631-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 76#L631-17true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85#L306-15true assume 1 == ~t4_pc~0; 9#L307-5true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 111#L317-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5#L318-5true activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 282#L639-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 259#L639-17true assume 1 == ~M_E~0;~M_E~0 := 2; 368#L547-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 221#L552-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 276#L557-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 305#L562-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 134#L567-3true assume 1 == ~E_1~0;~E_1~0 := 2; 162#L572-3true assume !(1 == ~E_2~0); 184#L577-3true assume 1 == ~E_3~0;~E_3~0 := 2; 51#L582-3true assume 1 == ~E_4~0;~E_4~0 := 2; 96#L587-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 317#L366-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 335#L393-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 119#L394-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 151#L787true assume !(0 == start_simulation_~tmp~3); 152#L787-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 319#L366-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 340#L393-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 120#L394-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 38#L742true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 130#L749true stop_simulation_#res := stop_simulation_~__retres2~0; 224#L750true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 203#L800true assume !(0 != start_simulation_~tmp___0~1); 320#L768-1true [2021-07-06 20:43:34,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,358 INFO L82 PathProgramCache]: Analyzing trace with hash 1688618289, now seen corresponding path program 1 times [2021-07-06 20:43:34,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,364 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702464546] [2021-07-06 20:43:34,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,365 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,523 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,525 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,526 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,526 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:34,535 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,536 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,538 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,538 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702464546] [2021-07-06 20:43:34,539 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702464546] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,539 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:34,541 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812538341] [2021-07-06 20:43:34,545 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:34,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,547 INFO L82 PathProgramCache]: Analyzing trace with hash -1850523906, now seen corresponding path program 1 times [2021-07-06 20:43:34,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,548 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554507123] [2021-07-06 20:43:34,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,549 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,584 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,585 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,587 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,587 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,589 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554507123] [2021-07-06 20:43:34,589 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554507123] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,589 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:43:34,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547170182] [2021-07-06 20:43:34,591 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:34,592 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:34,604 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:34,605 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:34,607 INFO L87 Difference]: Start difference. First operand has 373 states, 372 states have (on average 1.564516129032258) internal successors, (582), 372 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:34,639 INFO L93 Difference]: Finished difference Result 373 states and 564 transitions. [2021-07-06 20:43:34,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:34,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 373 states and 564 transitions. [2021-07-06 20:43:34,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:34,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 373 states to 368 states and 559 transitions. [2021-07-06 20:43:34,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-07-06 20:43:34,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-07-06 20:43:34,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 559 transitions. [2021-07-06 20:43:34,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:34,663 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-07-06 20:43:34,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 559 transitions. [2021-07-06 20:43:34,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-07-06 20:43:34,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.5190217391304348) internal successors, (559), 367 states have internal predecessors, (559), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 559 transitions. [2021-07-06 20:43:34,712 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-07-06 20:43:34,713 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 559 transitions. [2021-07-06 20:43:34,713 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-07-06 20:43:34,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 559 transitions. [2021-07-06 20:43:34,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:34,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:34,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:34,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,717 INFO L791 eck$LassoCheckResult]: Stem: 966#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 798#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 799#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 837#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1071#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1114#L338-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1003#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1004#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1072#L353-1 assume !(0 == ~M_E~0); 863#L494-1 assume !(0 == ~T1_E~0); 864#L499-1 assume !(0 == ~T2_E~0); 917#L504-1 assume !(0 == ~T3_E~0); 1109#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1117#L514-1 assume !(0 == ~E_1~0); 1035#L519-1 assume !(0 == ~E_2~0); 1036#L524-1 assume !(0 == ~E_3~0); 1091#L529-1 assume !(0 == ~E_4~0); 963#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 785#L230 assume !(1 == ~m_pc~0); 786#L230-2 is_master_triggered_~__retres1~0 := 0; 788#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 789#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 960#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1028#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1029#L249 assume 1 == ~t1_pc~0; 1076#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1067#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1077#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 890#L615 assume !(0 != activate_threads_~tmp___0~0); 891#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 895#L268 assume !(1 == ~t2_pc~0); 911#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 912#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 920#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 992#L623 assume !(0 != activate_threads_~tmp___1~0); 1083#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1084#L287 assume 1 == ~t3_pc~0; 1021#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1022#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1026#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 932#L631 assume !(0 != activate_threads_~tmp___2~0); 933#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 934#L306 assume !(1 == ~t4_pc~0); 805#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 806#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 802#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 803#L639 assume !(0 != activate_threads_~tmp___3~0); 944#L639-2 assume !(1 == ~M_E~0); 1107#L547-1 assume !(1 == ~T1_E~0); 1030#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1031#L557-1 assume !(1 == ~T3_E~0); 1088#L562-1 assume !(1 == ~T4_E~0); 961#L567-1 assume !(1 == ~E_1~0); 962#L572-1 assume !(1 == ~E_2~0); 792#L577-1 assume !(1 == ~E_3~0); 793#L582-1 assume !(1 == ~E_4~0); 896#L768-1 [2021-07-06 20:43:34,718 INFO L793 eck$LassoCheckResult]: Loop: 896#L768-1 assume !false; 907#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 859#L469 assume !false; 1092#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1113#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 929#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1111#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1104#L408 assume !(0 != eval_~tmp~0); 980#L484 start_simulation_~kernel_st~0 := 2; 981#L326-1 start_simulation_~kernel_st~0 := 3; 873#L494-2 assume !(0 == ~M_E~0); 874#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 880#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 926#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1110#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1118#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 993#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 994#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1056#L529-3 assume !(0 == ~E_4~0); 947#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 948#L230-15 assume 1 == ~m_pc~0; 972#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 821#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 822#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 974#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1119#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1015#L249-15 assume !(1 == ~t1_pc~0); 1016#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 1053#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1054#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 776#L615-15 assume !(0 != activate_threads_~tmp___0~0); 777#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 790#L268-15 assume 1 == ~t2_pc~0; 791#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 779#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 877#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 985#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1019#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1020#L287-15 assume !(1 == ~t3_pc~0); 1045#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 1075#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1078#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 887#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 888#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 892#L306-15 assume !(1 == ~t4_pc~0); 768#L306-17 is_transmit4_triggered_~__retres1~4 := 0; 767#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 759#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 760#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1079#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1080#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1039#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1040#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1093#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 945#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 946#L572-3 assume !(1 == ~E_2~0); 982#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 854#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 855#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 914#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 899#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 935#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 936#L787 assume !(0 == start_simulation_~tmp~3); 965#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 967#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 904#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 937#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 831#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 832#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 941#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1006#L800 assume !(0 != start_simulation_~tmp___0~1); 896#L768-1 [2021-07-06 20:43:34,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,718 INFO L82 PathProgramCache]: Analyzing trace with hash 1244717615, now seen corresponding path program 1 times [2021-07-06 20:43:34,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,719 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480227354] [2021-07-06 20:43:34,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,719 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,748 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,749 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,750 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,750 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:34,753 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,754 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,755 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,755 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480227354] [2021-07-06 20:43:34,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480227354] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,755 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:34,756 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045532910] [2021-07-06 20:43:34,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:34,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,757 INFO L82 PathProgramCache]: Analyzing trace with hash 726656802, now seen corresponding path program 1 times [2021-07-06 20:43:34,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783097927] [2021-07-06 20:43:34,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,757 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,800 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,801 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,802 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,802 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:34,805 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,806 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,806 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,807 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783097927] [2021-07-06 20:43:34,807 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783097927] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,807 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:34,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337117760] [2021-07-06 20:43:34,808 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:34,808 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:34,808 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:34,809 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:34,809 INFO L87 Difference]: Start difference. First operand 368 states and 559 transitions. cyclomatic complexity: 192 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:34,824 INFO L93 Difference]: Finished difference Result 368 states and 558 transitions. [2021-07-06 20:43:34,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:34,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 558 transitions. [2021-07-06 20:43:34,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:34,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 558 transitions. [2021-07-06 20:43:34,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-07-06 20:43:34,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-07-06 20:43:34,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 558 transitions. [2021-07-06 20:43:34,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:34,833 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-07-06 20:43:34,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 558 transitions. [2021-07-06 20:43:34,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-07-06 20:43:34,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.516304347826087) internal successors, (558), 367 states have internal predecessors, (558), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 558 transitions. [2021-07-06 20:43:34,843 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-07-06 20:43:34,843 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 558 transitions. [2021-07-06 20:43:34,843 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-07-06 20:43:34,843 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 558 transitions. [2021-07-06 20:43:34,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:34,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:34,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:34,846 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,846 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:34,847 INFO L791 eck$LassoCheckResult]: Stem: 1708#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1541#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1542#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1576#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 1813#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1857#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1745#L343-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1746#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1815#L353-1 assume !(0 == ~M_E~0); 1603#L494-1 assume !(0 == ~T1_E~0); 1604#L499-1 assume !(0 == ~T2_E~0); 1659#L504-1 assume !(0 == ~T3_E~0); 1852#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1860#L514-1 assume !(0 == ~E_1~0); 1776#L519-1 assume !(0 == ~E_2~0); 1777#L524-1 assume !(0 == ~E_3~0); 1832#L529-1 assume !(0 == ~E_4~0); 1706#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1525#L230 assume !(1 == ~m_pc~0); 1526#L230-2 is_master_triggered_~__retres1~0 := 0; 1531#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1532#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1703#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1770#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1771#L249 assume 1 == ~t1_pc~0; 1819#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1810#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1820#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1633#L615 assume !(0 != activate_threads_~tmp___0~0); 1634#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1637#L268 assume !(1 == ~t2_pc~0); 1654#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 1655#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1663#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1735#L623 assume !(0 != activate_threads_~tmp___1~0); 1824#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1825#L287 assume 1 == ~t3_pc~0; 1764#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1765#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1767#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1675#L631 assume !(0 != activate_threads_~tmp___2~0); 1676#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1677#L306 assume !(1 == ~t4_pc~0); 1548#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 1549#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1543#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1544#L639 assume !(0 != activate_threads_~tmp___3~0); 1685#L639-2 assume !(1 == ~M_E~0); 1850#L547-1 assume !(1 == ~T1_E~0); 1773#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1774#L557-1 assume !(1 == ~T3_E~0); 1829#L562-1 assume !(1 == ~T4_E~0); 1704#L567-1 assume !(1 == ~E_1~0); 1705#L572-1 assume !(1 == ~E_2~0); 1535#L577-1 assume !(1 == ~E_3~0); 1536#L582-1 assume !(1 == ~E_4~0); 1638#L768-1 [2021-07-06 20:43:34,847 INFO L793 eck$LassoCheckResult]: Loop: 1638#L768-1 assume !false; 1650#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1602#L469 assume !false; 1835#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1856#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1672#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1854#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1847#L408 assume !(0 != eval_~tmp~0); 1723#L484 start_simulation_~kernel_st~0 := 2; 1724#L326-1 start_simulation_~kernel_st~0 := 3; 1614#L494-2 assume !(0 == ~M_E~0); 1615#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1622#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1669#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1853#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1861#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1736#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1737#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1799#L529-3 assume !(0 == ~E_4~0); 1690#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1691#L230-15 assume 1 == ~m_pc~0; 1715#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1564#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1565#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1717#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1862#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1758#L249-15 assume 1 == ~t1_pc~0; 1760#L250-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1797#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1798#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1519#L615-15 assume !(0 != activate_threads_~tmp___0~0); 1520#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1533#L268-15 assume !(1 == ~t2_pc~0); 1521#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 1522#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1620#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1728#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1762#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1763#L287-15 assume !(1 == ~t3_pc~0); 1788#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 1818#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1821#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1630#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1631#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1635#L306-15 assume 1 == ~t4_pc~0; 1512#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1513#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1502#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1503#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1822#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1823#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1782#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1783#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1838#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1688#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1689#L572-3 assume !(1 == ~E_2~0); 1725#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1597#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1598#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1657#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1642#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1678#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1679#L787 assume !(0 == start_simulation_~tmp~3); 1709#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1710#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1647#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1680#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1574#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1575#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 1684#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1750#L800 assume !(0 != start_simulation_~tmp___0~1); 1638#L768-1 [2021-07-06 20:43:34,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1021663571, now seen corresponding path program 1 times [2021-07-06 20:43:34,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930637148] [2021-07-06 20:43:34,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,849 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,874 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,874 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,875 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,875 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:34,881 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,881 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,882 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,882 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930637148] [2021-07-06 20:43:34,882 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930637148] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,883 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,883 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:34,883 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655265074] [2021-07-06 20:43:34,883 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:34,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:34,884 INFO L82 PathProgramCache]: Analyzing trace with hash -1979243551, now seen corresponding path program 1 times [2021-07-06 20:43:34,884 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:34,884 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996462695] [2021-07-06 20:43:34,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:34,885 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:34,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:34,964 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,964 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,965 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,966 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:34,970 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:34,970 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:34,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:34,974 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:34,975 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996462695] [2021-07-06 20:43:34,975 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996462695] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:34,975 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:34,975 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:34,975 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935245248] [2021-07-06 20:43:34,976 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:34,976 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:34,976 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:34,977 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:34,977 INFO L87 Difference]: Start difference. First operand 368 states and 558 transitions. cyclomatic complexity: 191 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:34,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:34,995 INFO L93 Difference]: Finished difference Result 368 states and 557 transitions. [2021-07-06 20:43:34,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:34,997 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 557 transitions. [2021-07-06 20:43:34,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 557 transitions. [2021-07-06 20:43:35,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-07-06 20:43:35,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-07-06 20:43:35,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 557 transitions. [2021-07-06 20:43:35,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,002 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-07-06 20:43:35,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 557 transitions. [2021-07-06 20:43:35,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-07-06 20:43:35,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.513586956521739) internal successors, (557), 367 states have internal predecessors, (557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 557 transitions. [2021-07-06 20:43:35,009 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-07-06 20:43:35,009 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 557 transitions. [2021-07-06 20:43:35,010 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-07-06 20:43:35,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 557 transitions. [2021-07-06 20:43:35,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:35,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:35,013 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,013 INFO L791 eck$LassoCheckResult]: Stem: 2452#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2284#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2285#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2323#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 2557#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2600#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2488#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2489#L348-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2558#L353-1 assume !(0 == ~M_E~0); 2349#L494-1 assume !(0 == ~T1_E~0); 2350#L499-1 assume !(0 == ~T2_E~0); 2403#L504-1 assume !(0 == ~T3_E~0); 2595#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2603#L514-1 assume !(0 == ~E_1~0); 2519#L519-1 assume !(0 == ~E_2~0); 2520#L524-1 assume !(0 == ~E_3~0); 2577#L529-1 assume !(0 == ~E_4~0); 2449#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2271#L230 assume !(1 == ~m_pc~0); 2272#L230-2 is_master_triggered_~__retres1~0 := 0; 2274#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2275#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2446#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2514#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2515#L249 assume 1 == ~t1_pc~0; 2562#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2553#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2563#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2376#L615 assume !(0 != activate_threads_~tmp___0~0); 2377#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2381#L268 assume !(1 == ~t2_pc~0); 2397#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 2398#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2406#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2478#L623 assume !(0 != activate_threads_~tmp___1~0); 2569#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2570#L287 assume 1 == ~t3_pc~0; 2507#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2508#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2510#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2418#L631 assume !(0 != activate_threads_~tmp___2~0); 2419#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2420#L306 assume !(1 == ~t4_pc~0); 2291#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 2292#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2288#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2289#L639 assume !(0 != activate_threads_~tmp___3~0); 2430#L639-2 assume !(1 == ~M_E~0); 2593#L547-1 assume !(1 == ~T1_E~0); 2516#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2517#L557-1 assume !(1 == ~T3_E~0); 2574#L562-1 assume !(1 == ~T4_E~0); 2447#L567-1 assume !(1 == ~E_1~0); 2448#L572-1 assume !(1 == ~E_2~0); 2278#L577-1 assume !(1 == ~E_3~0); 2279#L582-1 assume !(1 == ~E_4~0); 2382#L768-1 [2021-07-06 20:43:35,014 INFO L793 eck$LassoCheckResult]: Loop: 2382#L768-1 assume !false; 2393#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2345#L469 assume !false; 2578#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2599#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2415#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2597#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2590#L408 assume !(0 != eval_~tmp~0); 2466#L484 start_simulation_~kernel_st~0 := 2; 2467#L326-1 start_simulation_~kernel_st~0 := 3; 2359#L494-2 assume !(0 == ~M_E~0); 2360#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2366#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2412#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2596#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2604#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2479#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2480#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2543#L529-3 assume !(0 == ~E_4~0); 2433#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2434#L230-15 assume 1 == ~m_pc~0; 2458#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2307#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2308#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2460#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2605#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2501#L249-15 assume !(1 == ~t1_pc~0); 2502#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 2539#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2540#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2262#L615-15 assume !(0 != activate_threads_~tmp___0~0); 2263#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2276#L268-15 assume 1 == ~t2_pc~0; 2277#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2265#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2361#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2471#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2505#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2506#L287-15 assume !(1 == ~t3_pc~0); 2531#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 2561#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2564#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2373#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2374#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2378#L306-15 assume 1 == ~t4_pc~0; 2252#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2253#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2245#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2246#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2565#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2566#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2524#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2525#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2579#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2431#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2432#L572-3 assume !(1 == ~E_2~0); 2468#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2340#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2341#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2400#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2385#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2421#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2422#L787 assume !(0 == start_simulation_~tmp~3); 2451#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2453#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2390#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2423#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 2315#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2316#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 2427#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2491#L800 assume !(0 != start_simulation_~tmp___0~1); 2382#L768-1 [2021-07-06 20:43:35,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,014 INFO L82 PathProgramCache]: Analyzing trace with hash -540583313, now seen corresponding path program 1 times [2021-07-06 20:43:35,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,015 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51430063] [2021-07-06 20:43:35,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,015 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,034 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,035 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,035 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,036 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,039 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,039 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,040 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,040 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51430063] [2021-07-06 20:43:35,040 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51430063] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,040 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,040 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56983981] [2021-07-06 20:43:35,041 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:35,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,041 INFO L82 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 1 times [2021-07-06 20:43:35,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,042 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692492023] [2021-07-06 20:43:35,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,042 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,088 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,089 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,090 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,090 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:35,093 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,094 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692492023] [2021-07-06 20:43:35,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692492023] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969072714] [2021-07-06 20:43:35,095 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:35,096 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:35,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:35,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:35,096 INFO L87 Difference]: Start difference. First operand 368 states and 557 transitions. cyclomatic complexity: 190 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:35,111 INFO L93 Difference]: Finished difference Result 368 states and 556 transitions. [2021-07-06 20:43:35,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:35,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 556 transitions. [2021-07-06 20:43:35,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 556 transitions. [2021-07-06 20:43:35,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-07-06 20:43:35,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-07-06 20:43:35,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 556 transitions. [2021-07-06 20:43:35,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,117 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-07-06 20:43:35,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 556 transitions. [2021-07-06 20:43:35,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-07-06 20:43:35,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.5108695652173914) internal successors, (556), 367 states have internal predecessors, (556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 556 transitions. [2021-07-06 20:43:35,124 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-07-06 20:43:35,124 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 556 transitions. [2021-07-06 20:43:35,124 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-07-06 20:43:35,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 556 transitions. [2021-07-06 20:43:35,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:35,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:35,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,130 INFO L791 eck$LassoCheckResult]: Stem: 3194#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3027#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3028#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3062#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 3299#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3343#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3231#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3232#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3301#L353-1 assume !(0 == ~M_E~0); 3089#L494-1 assume !(0 == ~T1_E~0); 3090#L499-1 assume !(0 == ~T2_E~0); 3145#L504-1 assume !(0 == ~T3_E~0); 3338#L509-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3346#L514-1 assume !(0 == ~E_1~0); 3262#L519-1 assume !(0 == ~E_2~0); 3263#L524-1 assume !(0 == ~E_3~0); 3318#L529-1 assume !(0 == ~E_4~0); 3192#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3011#L230 assume !(1 == ~m_pc~0); 3012#L230-2 is_master_triggered_~__retres1~0 := 0; 3017#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3018#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3189#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3256#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3257#L249 assume 1 == ~t1_pc~0; 3305#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3296#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3306#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3119#L615 assume !(0 != activate_threads_~tmp___0~0); 3120#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3123#L268 assume !(1 == ~t2_pc~0); 3140#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3141#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3149#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3221#L623 assume !(0 != activate_threads_~tmp___1~0); 3310#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3311#L287 assume 1 == ~t3_pc~0; 3250#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3251#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3253#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3161#L631 assume !(0 != activate_threads_~tmp___2~0); 3162#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3163#L306 assume !(1 == ~t4_pc~0); 3034#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3035#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3029#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3030#L639 assume !(0 != activate_threads_~tmp___3~0); 3171#L639-2 assume !(1 == ~M_E~0); 3336#L547-1 assume !(1 == ~T1_E~0); 3259#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3260#L557-1 assume !(1 == ~T3_E~0); 3315#L562-1 assume !(1 == ~T4_E~0); 3190#L567-1 assume !(1 == ~E_1~0); 3191#L572-1 assume !(1 == ~E_2~0); 3021#L577-1 assume !(1 == ~E_3~0); 3022#L582-1 assume !(1 == ~E_4~0); 3124#L768-1 [2021-07-06 20:43:35,132 INFO L793 eck$LassoCheckResult]: Loop: 3124#L768-1 assume !false; 3136#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3088#L469 assume !false; 3321#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3342#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3158#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3340#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3333#L408 assume !(0 != eval_~tmp~0); 3209#L484 start_simulation_~kernel_st~0 := 2; 3210#L326-1 start_simulation_~kernel_st~0 := 3; 3100#L494-2 assume !(0 == ~M_E~0); 3101#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3108#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3155#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3339#L509-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3347#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3222#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3223#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3285#L529-3 assume !(0 == ~E_4~0); 3176#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3177#L230-15 assume 1 == ~m_pc~0; 3201#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3050#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3051#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3203#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3348#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3244#L249-15 assume !(1 == ~t1_pc~0); 3245#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 3283#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3284#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3005#L615-15 assume !(0 != activate_threads_~tmp___0~0); 3006#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3019#L268-15 assume 1 == ~t2_pc~0; 3020#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3008#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3106#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3214#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3248#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3249#L287-15 assume !(1 == ~t3_pc~0); 3274#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 3304#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3307#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3116#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3117#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3121#L306-15 assume 1 == ~t4_pc~0; 2998#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2999#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2988#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2989#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3308#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 3309#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3268#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3269#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3324#L562-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3174#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3175#L572-3 assume !(1 == ~E_2~0); 3211#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3083#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3084#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3143#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3128#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3164#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3165#L787 assume !(0 == start_simulation_~tmp~3); 3195#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3196#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3133#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3166#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3060#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3061#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 3170#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3236#L800 assume !(0 != start_simulation_~tmp___0~1); 3124#L768-1 [2021-07-06 20:43:35,133 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,133 INFO L82 PathProgramCache]: Analyzing trace with hash -525064595, now seen corresponding path program 1 times [2021-07-06 20:43:35,133 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,133 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575380864] [2021-07-06 20:43:35,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,134 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,196 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,197 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,200 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,200 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,201 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,201 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575380864] [2021-07-06 20:43:35,201 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575380864] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,202 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,202 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:43:35,202 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264972675] [2021-07-06 20:43:35,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:35,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,204 INFO L82 PathProgramCache]: Analyzing trace with hash -1895792863, now seen corresponding path program 2 times [2021-07-06 20:43:35,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,205 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439781362] [2021-07-06 20:43:35,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,205 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,232 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,233 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,233 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,234 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:35,237 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,237 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,238 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,238 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439781362] [2021-07-06 20:43:35,238 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439781362] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,239 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,239 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,239 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523997203] [2021-07-06 20:43:35,239 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:35,240 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:35,240 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:35,240 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:35,240 INFO L87 Difference]: Start difference. First operand 368 states and 556 transitions. cyclomatic complexity: 189 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:35,276 INFO L93 Difference]: Finished difference Result 368 states and 551 transitions. [2021-07-06 20:43:35,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:35,277 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 368 states and 551 transitions. [2021-07-06 20:43:35,279 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 368 states to 368 states and 551 transitions. [2021-07-06 20:43:35,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 368 [2021-07-06 20:43:35,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 368 [2021-07-06 20:43:35,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 551 transitions. [2021-07-06 20:43:35,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,282 INFO L681 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-07-06 20:43:35,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 551 transitions. [2021-07-06 20:43:35,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 368. [2021-07-06 20:43:35,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 368 states, 368 states have (on average 1.497282608695652) internal successors, (551), 367 states have internal predecessors, (551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 551 transitions. [2021-07-06 20:43:35,288 INFO L704 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-07-06 20:43:35,288 INFO L587 BuchiCegarLoop]: Abstraction has 368 states and 551 transitions. [2021-07-06 20:43:35,289 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-07-06 20:43:35,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 368 states and 551 transitions. [2021-07-06 20:43:35,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 307 [2021-07-06 20:43:35,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:35,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:35,291 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,291 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,292 INFO L791 eck$LassoCheckResult]: Stem: 3938#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3770#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3771#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3808#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 4043#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4086#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3974#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3975#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4044#L353-1 assume !(0 == ~M_E~0); 3832#L494-1 assume !(0 == ~T1_E~0); 3833#L499-1 assume !(0 == ~T2_E~0); 3889#L504-1 assume !(0 == ~T3_E~0); 4081#L509-1 assume !(0 == ~T4_E~0); 4089#L514-1 assume !(0 == ~E_1~0); 4005#L519-1 assume !(0 == ~E_2~0); 4006#L524-1 assume !(0 == ~E_3~0); 4063#L529-1 assume !(0 == ~E_4~0); 3935#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3757#L230 assume !(1 == ~m_pc~0); 3758#L230-2 is_master_triggered_~__retres1~0 := 0; 3760#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3761#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3932#L607 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4000#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4001#L249 assume 1 == ~t1_pc~0; 4048#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4039#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4049#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3862#L615 assume !(0 != activate_threads_~tmp___0~0); 3863#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3867#L268 assume !(1 == ~t2_pc~0); 3883#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 3884#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3892#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3964#L623 assume !(0 != activate_threads_~tmp___1~0); 4055#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4056#L287 assume 1 == ~t3_pc~0; 3993#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3994#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3996#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3904#L631 assume !(0 != activate_threads_~tmp___2~0); 3905#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3906#L306 assume !(1 == ~t4_pc~0); 3777#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 3778#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3772#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3773#L639 assume !(0 != activate_threads_~tmp___3~0); 3916#L639-2 assume !(1 == ~M_E~0); 4079#L547-1 assume !(1 == ~T1_E~0); 4002#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4003#L557-1 assume !(1 == ~T3_E~0); 4059#L562-1 assume !(1 == ~T4_E~0); 3933#L567-1 assume !(1 == ~E_1~0); 3934#L572-1 assume !(1 == ~E_2~0); 3764#L577-1 assume !(1 == ~E_3~0); 3765#L582-1 assume !(1 == ~E_4~0); 3868#L768-1 [2021-07-06 20:43:35,292 INFO L793 eck$LassoCheckResult]: Loop: 3868#L768-1 assume !false; 3879#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3831#L469 assume !false; 4064#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4085#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3901#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4083#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4076#L408 assume !(0 != eval_~tmp~0); 3952#L484 start_simulation_~kernel_st~0 := 2; 3953#L326-1 start_simulation_~kernel_st~0 := 3; 3843#L494-2 assume !(0 == ~M_E~0); 3844#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3851#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3898#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4082#L509-3 assume !(0 == ~T4_E~0); 4090#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3965#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3966#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4028#L529-3 assume !(0 == ~E_4~0); 3919#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3920#L230-15 assume 1 == ~m_pc~0; 3944#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3793#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3794#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3946#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4091#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3988#L249-15 assume !(1 == ~t1_pc~0); 3989#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 4026#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4027#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3752#L615-15 assume !(0 != activate_threads_~tmp___0~0); 3753#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3762#L268-15 assume 1 == ~t2_pc~0; 3763#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3749#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3847#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3957#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3991#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3992#L287-15 assume !(1 == ~t3_pc~0); 4016#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 4047#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4050#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3859#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3860#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3864#L306-15 assume 1 == ~t4_pc~0; 3738#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3739#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3729#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3730#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4051#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4052#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4010#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4011#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4065#L562-3 assume !(1 == ~T4_E~0); 3917#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3918#L572-3 assume !(1 == ~E_2~0); 3954#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3826#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3827#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3886#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3871#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3907#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3908#L787 assume !(0 == start_simulation_~tmp~3); 3937#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3939#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3876#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3909#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3801#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3802#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 3913#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3977#L800 assume !(0 != start_simulation_~tmp___0~1); 3868#L768-1 [2021-07-06 20:43:35,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,293 INFO L82 PathProgramCache]: Analyzing trace with hash 1720514859, now seen corresponding path program 1 times [2021-07-06 20:43:35,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,293 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177433170] [2021-07-06 20:43:35,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,293 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,314 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,314 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,315 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,315 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,318 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,319 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,323 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,324 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,329 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,329 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,330 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,330 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177433170] [2021-07-06 20:43:35,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177433170] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,330 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,330 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:43:35,331 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003713165] [2021-07-06 20:43:35,331 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:35,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,332 INFO L82 PathProgramCache]: Analyzing trace with hash 1665946977, now seen corresponding path program 1 times [2021-07-06 20:43:35,332 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,332 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826948688] [2021-07-06 20:43:35,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,332 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,348 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,349 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,350 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,350 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:35,353 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,353 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,354 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,354 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826948688] [2021-07-06 20:43:35,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826948688] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,355 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164613069] [2021-07-06 20:43:35,355 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:35,355 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:35,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:43:35,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:43:35,356 INFO L87 Difference]: Start difference. First operand 368 states and 551 transitions. cyclomatic complexity: 184 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:35,513 INFO L93 Difference]: Finished difference Result 1005 states and 1494 transitions. [2021-07-06 20:43:35,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-07-06 20:43:35,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1005 states and 1494 transitions. [2021-07-06 20:43:35,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 867 [2021-07-06 20:43:35,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1005 states to 1005 states and 1494 transitions. [2021-07-06 20:43:35,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1005 [2021-07-06 20:43:35,527 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1005 [2021-07-06 20:43:35,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1005 states and 1494 transitions. [2021-07-06 20:43:35,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,528 INFO L681 BuchiCegarLoop]: Abstraction has 1005 states and 1494 transitions. [2021-07-06 20:43:35,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1005 states and 1494 transitions. [2021-07-06 20:43:35,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1005 to 389. [2021-07-06 20:43:35,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 389 states have (on average 1.4704370179948587) internal successors, (572), 388 states have internal predecessors, (572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 572 transitions. [2021-07-06 20:43:35,538 INFO L704 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2021-07-06 20:43:35,538 INFO L587 BuchiCegarLoop]: Abstraction has 389 states and 572 transitions. [2021-07-06 20:43:35,538 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-07-06 20:43:35,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 389 states and 572 transitions. [2021-07-06 20:43:35,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 325 [2021-07-06 20:43:35,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:35,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:35,541 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,541 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,542 INFO L791 eck$LassoCheckResult]: Stem: 5330#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5156#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5157#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5191#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 5446#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5490#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5375#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5376#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5448#L353-1 assume !(0 == ~M_E~0); 5218#L494-1 assume !(0 == ~T1_E~0); 5219#L499-1 assume !(0 == ~T2_E~0); 5274#L504-1 assume !(0 == ~T3_E~0); 5485#L509-1 assume !(0 == ~T4_E~0); 5493#L514-1 assume !(0 == ~E_1~0); 5408#L519-1 assume !(0 == ~E_2~0); 5409#L524-1 assume !(0 == ~E_3~0); 5465#L529-1 assume !(0 == ~E_4~0); 5328#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5140#L230 assume !(1 == ~m_pc~0); 5141#L230-2 is_master_triggered_~__retres1~0 := 0; 5146#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5147#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5426#L607 assume !(0 != activate_threads_~tmp~1); 5401#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5402#L249 assume 1 == ~t1_pc~0; 5452#L250 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5443#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5453#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5248#L615 assume !(0 != activate_threads_~tmp___0~0); 5249#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5252#L268 assume !(1 == ~t2_pc~0); 5269#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 5270#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5278#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5364#L623 assume !(0 != activate_threads_~tmp___1~0); 5457#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5458#L287 assume 1 == ~t3_pc~0; 5395#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5396#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5398#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5290#L631 assume !(0 != activate_threads_~tmp___2~0); 5291#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5292#L306 assume !(1 == ~t4_pc~0); 5163#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 5164#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5158#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5159#L639 assume !(0 != activate_threads_~tmp___3~0); 5300#L639-2 assume !(1 == ~M_E~0); 5483#L547-1 assume !(1 == ~T1_E~0); 5404#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5405#L557-1 assume !(1 == ~T3_E~0); 5462#L562-1 assume !(1 == ~T4_E~0); 5326#L567-1 assume !(1 == ~E_1~0); 5327#L572-1 assume !(1 == ~E_2~0); 5150#L577-1 assume !(1 == ~E_3~0); 5151#L582-1 assume !(1 == ~E_4~0); 5253#L768-1 [2021-07-06 20:43:35,542 INFO L793 eck$LassoCheckResult]: Loop: 5253#L768-1 assume !false; 5265#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5217#L469 assume !false; 5468#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5489#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5287#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5487#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 5480#L408 assume !(0 != eval_~tmp~0); 5352#L484 start_simulation_~kernel_st~0 := 2; 5353#L326-1 start_simulation_~kernel_st~0 := 3; 5229#L494-2 assume !(0 == ~M_E~0); 5230#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5237#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5284#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5486#L509-3 assume !(0 == ~T4_E~0); 5494#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5365#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5366#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5432#L529-3 assume !(0 == ~E_4~0); 5305#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5306#L230-15 assume 1 == ~m_pc~0; 5339#L231-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5340#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5342#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5343#L607-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5495#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5389#L249-15 assume !(1 == ~t1_pc~0); 5390#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 5430#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5431#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5134#L615-15 assume !(0 != activate_threads_~tmp___0~0); 5135#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5148#L268-15 assume !(1 == ~t2_pc~0); 5136#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 5137#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5235#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5357#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5393#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5394#L287-15 assume !(1 == ~t3_pc~0); 5420#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 5451#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5454#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5245#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5246#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5250#L306-15 assume 1 == ~t4_pc~0; 5127#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5128#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5117#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5118#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5455#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 5456#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5414#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5415#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5471#L562-3 assume !(1 == ~T4_E~0); 5303#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5304#L572-3 assume !(1 == ~E_2~0); 5354#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5212#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5213#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5272#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5257#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5293#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5294#L787 assume !(0 == start_simulation_~tmp~3); 5331#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5332#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5262#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5295#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 5189#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5190#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 5299#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5381#L800 assume !(0 != start_simulation_~tmp___0~1); 5253#L768-1 [2021-07-06 20:43:35,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,543 INFO L82 PathProgramCache]: Analyzing trace with hash -523468439, now seen corresponding path program 1 times [2021-07-06 20:43:35,543 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,543 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390794838] [2021-07-06 20:43:35,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,543 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,559 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,560 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,563 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,564 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:43:35,568 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,568 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,569 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,569 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390794838] [2021-07-06 20:43:35,569 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390794838] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,569 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,570 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884023249] [2021-07-06 20:43:35,570 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:35,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,571 INFO L82 PathProgramCache]: Analyzing trace with hash 709018594, now seen corresponding path program 1 times [2021-07-06 20:43:35,571 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,571 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707655464] [2021-07-06 20:43:35,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,572 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,587 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,587 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,588 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,589 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:35,592 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,592 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,593 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,593 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707655464] [2021-07-06 20:43:35,593 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707655464] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,593 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752323405] [2021-07-06 20:43:35,594 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:35,594 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:35,595 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:43:35,595 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:43:35,595 INFO L87 Difference]: Start difference. First operand 389 states and 572 transitions. cyclomatic complexity: 184 Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:35,725 INFO L93 Difference]: Finished difference Result 952 states and 1374 transitions. [2021-07-06 20:43:35,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:43:35,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1374 transitions. [2021-07-06 20:43:35,731 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 850 [2021-07-06 20:43:35,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1374 transitions. [2021-07-06 20:43:35,736 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2021-07-06 20:43:35,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2021-07-06 20:43:35,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1374 transitions. [2021-07-06 20:43:35,738 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,738 INFO L681 BuchiCegarLoop]: Abstraction has 952 states and 1374 transitions. [2021-07-06 20:43:35,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1374 transitions. [2021-07-06 20:43:35,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 886. [2021-07-06 20:43:35,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 886 states, 886 states have (on average 1.4525959367945824) internal successors, (1287), 885 states have internal predecessors, (1287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 886 states to 886 states and 1287 transitions. [2021-07-06 20:43:35,768 INFO L704 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2021-07-06 20:43:35,768 INFO L587 BuchiCegarLoop]: Abstraction has 886 states and 1287 transitions. [2021-07-06 20:43:35,768 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-07-06 20:43:35,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 886 states and 1287 transitions. [2021-07-06 20:43:35,772 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 822 [2021-07-06 20:43:35,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:35,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:35,773 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,773 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:35,773 INFO L791 eck$LassoCheckResult]: Stem: 6684#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 6506#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6507#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6541#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 6806#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6857#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6734#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6735#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6807#L353-1 assume !(0 == ~M_E~0); 6568#L494-1 assume !(0 == ~T1_E~0); 6569#L499-1 assume !(0 == ~T2_E~0); 6626#L504-1 assume !(0 == ~T3_E~0); 6852#L509-1 assume !(0 == ~T4_E~0); 6860#L514-1 assume !(0 == ~E_1~0); 6765#L519-1 assume !(0 == ~E_2~0); 6766#L524-1 assume !(0 == ~E_3~0); 6826#L529-1 assume !(0 == ~E_4~0); 6681#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6494#L230 assume !(1 == ~m_pc~0); 6495#L230-2 is_master_triggered_~__retres1~0 := 0; 6496#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6497#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6678#L607 assume !(0 != activate_threads_~tmp~1); 6759#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6760#L249 assume !(1 == ~t1_pc~0); 6801#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 6802#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6811#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6596#L615 assume !(0 != activate_threads_~tmp___0~0); 6597#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6603#L268 assume !(1 == ~t2_pc~0); 6619#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 6620#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6630#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6724#L623 assume !(0 != activate_threads_~tmp___1~0); 6817#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6818#L287 assume 1 == ~t3_pc~0; 6752#L288 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6753#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6755#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6642#L631 assume !(0 != activate_threads_~tmp___2~0); 6643#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6644#L306 assume !(1 == ~t4_pc~0); 6513#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 6514#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6508#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6509#L639 assume !(0 != activate_threads_~tmp___3~0); 6655#L639-2 assume !(1 == ~M_E~0); 6850#L547-1 assume !(1 == ~T1_E~0); 6761#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6762#L557-1 assume !(1 == ~T3_E~0); 6822#L562-1 assume !(1 == ~T4_E~0); 6679#L567-1 assume !(1 == ~E_1~0); 6680#L572-1 assume !(1 == ~E_2~0); 6500#L577-1 assume !(1 == ~E_3~0); 6501#L582-1 assume !(1 == ~E_4~0); 6604#L768-1 [2021-07-06 20:43:35,773 INFO L793 eck$LassoCheckResult]: Loop: 6604#L768-1 assume !false; 7217#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 6829#L469 assume !false; 6830#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 6856#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 6639#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 6854#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6845#L408 assume !(0 != eval_~tmp~0); 6703#L484 start_simulation_~kernel_st~0 := 2; 6704#L326-1 start_simulation_~kernel_st~0 := 3; 6577#L494-2 assume !(0 == ~M_E~0); 6578#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6585#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6636#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6853#L509-3 assume !(0 == ~T4_E~0); 6861#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6725#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6726#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6792#L529-3 assume !(0 == ~E_4~0); 6661#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6662#L230-15 assume !(1 == ~m_pc~0); 6720#L230-17 is_master_triggered_~__retres1~0 := 0; 6528#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6529#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6695#L607-15 assume !(0 != activate_threads_~tmp~1); 6879#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6747#L249-15 assume !(1 == ~t1_pc~0); 6748#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 6790#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6791#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6487#L615-15 assume !(0 != activate_threads_~tmp___0~0); 6488#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6498#L268-15 assume 1 == ~t2_pc~0; 6499#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6490#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6581#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6710#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6787#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6777#L287-15 assume !(1 == ~t3_pc~0); 6778#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 6810#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7289#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7287#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7285#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7283#L306-15 assume 1 == ~t4_pc~0; 7281#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7280#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7279#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7278#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7277#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 7276#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7275#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7274#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7273#L562-3 assume !(1 == ~T4_E~0); 7272#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7271#L572-3 assume !(1 == ~E_2~0); 7270#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7269#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7268#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7265#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7262#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7261#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7259#L787 assume !(0 == start_simulation_~tmp~3); 7260#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7255#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7252#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7251#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 7250#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 7249#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 7248#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7247#L800 assume !(0 != start_simulation_~tmp___0~1); 6604#L768-1 [2021-07-06 20:43:35,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,774 INFO L82 PathProgramCache]: Analyzing trace with hash 395506184, now seen corresponding path program 1 times [2021-07-06 20:43:35,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,775 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216111569] [2021-07-06 20:43:35,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,775 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,789 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,790 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:35,793 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,793 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:43:35,797 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,798 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,798 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,798 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216111569] [2021-07-06 20:43:35,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216111569] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,799 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,799 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,799 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988812411] [2021-07-06 20:43:35,799 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:35,799 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:35,800 INFO L82 PathProgramCache]: Analyzing trace with hash -787982620, now seen corresponding path program 1 times [2021-07-06 20:43:35,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:35,800 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222579003] [2021-07-06 20:43:35,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:35,800 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:35,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:35,813 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,814 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,815 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,815 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:35,818 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:35,819 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:35,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:35,819 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:35,819 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222579003] [2021-07-06 20:43:35,819 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222579003] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:35,820 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:35,820 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:35,820 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025167036] [2021-07-06 20:43:35,820 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:35,820 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:35,821 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-07-06 20:43:35,821 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-07-06 20:43:35,821 INFO L87 Difference]: Start difference. First operand 886 states and 1287 transitions. cyclomatic complexity: 403 Second operand has 4 states, 4 states have (on average 14.0) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:35,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:35,959 INFO L93 Difference]: Finished difference Result 2293 states and 3293 transitions. [2021-07-06 20:43:35,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-07-06 20:43:35,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2293 states and 3293 transitions. [2021-07-06 20:43:35,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2131 [2021-07-06 20:43:35,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2293 states to 2293 states and 3293 transitions. [2021-07-06 20:43:35,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2293 [2021-07-06 20:43:35,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2293 [2021-07-06 20:43:35,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2293 states and 3293 transitions. [2021-07-06 20:43:35,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:35,992 INFO L681 BuchiCegarLoop]: Abstraction has 2293 states and 3293 transitions. [2021-07-06 20:43:35,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2293 states and 3293 transitions. [2021-07-06 20:43:36,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2293 to 2162. [2021-07-06 20:43:36,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.446345975948196) internal successors, (3127), 2161 states have internal predecessors, (3127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3127 transitions. [2021-07-06 20:43:36,044 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2021-07-06 20:43:36,044 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3127 transitions. [2021-07-06 20:43:36,044 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-07-06 20:43:36,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3127 transitions. [2021-07-06 20:43:36,054 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-07-06 20:43:36,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:36,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:36,055 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,055 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,055 INFO L791 eck$LassoCheckResult]: Stem: 9881#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 9697#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 9698#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9733#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 10010#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10069#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9943#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9944#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10011#L353-1 assume !(0 == ~M_E~0); 9761#L494-1 assume !(0 == ~T1_E~0); 9762#L499-1 assume !(0 == ~T2_E~0); 9822#L504-1 assume !(0 == ~T3_E~0); 10060#L509-1 assume !(0 == ~T4_E~0); 10074#L514-1 assume !(0 == ~E_1~0); 9971#L519-1 assume !(0 == ~E_2~0); 9972#L524-1 assume !(0 == ~E_3~0); 10035#L529-1 assume !(0 == ~E_4~0); 9877#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9683#L230 assume !(1 == ~m_pc~0); 9684#L230-2 is_master_triggered_~__retres1~0 := 0; 9685#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9686#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9874#L607 assume !(0 != activate_threads_~tmp~1); 9964#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9965#L249 assume !(1 == ~t1_pc~0); 10006#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 10007#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10016#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9791#L615 assume !(0 != activate_threads_~tmp___0~0); 9792#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9796#L268 assume !(1 == ~t2_pc~0); 9815#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 9816#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9828#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9932#L623 assume !(0 != activate_threads_~tmp___1~0); 10025#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10026#L287 assume !(1 == ~t3_pc~0); 10031#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 10032#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9960#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9838#L631 assume !(0 != activate_threads_~tmp___2~0); 9839#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9840#L306 assume !(1 == ~t4_pc~0); 9706#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 9707#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9701#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9702#L639 assume !(0 != activate_threads_~tmp___3~0); 9852#L639-2 assume !(1 == ~M_E~0); 10058#L547-1 assume !(1 == ~T1_E~0); 9966#L552-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9967#L557-1 assume !(1 == ~T3_E~0); 10030#L562-1 assume !(1 == ~T4_E~0); 9875#L567-1 assume !(1 == ~E_1~0); 9876#L572-1 assume !(1 == ~E_2~0); 9691#L577-1 assume !(1 == ~E_3~0); 9692#L582-1 assume !(1 == ~E_4~0); 9797#L768-1 [2021-07-06 20:43:36,056 INFO L793 eck$LassoCheckResult]: Loop: 9797#L768-1 assume !false; 11711#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11710#L469 assume !false; 11709#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11708#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11163#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11164#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11155#L408 assume !(0 != eval_~tmp~0); 11157#L484 start_simulation_~kernel_st~0 := 2; 10015#L326-1 start_simulation_~kernel_st~0 := 3; 9769#L494-2 assume !(0 == ~M_E~0); 9770#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9778#L499-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9831#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10062#L509-3 assume !(0 == ~T4_E~0); 10075#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9933#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9934#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9996#L529-3 assume !(0 == ~E_4~0); 9856#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9857#L230-15 assume !(1 == ~m_pc~0); 9928#L230-17 is_master_triggered_~__retres1~0 := 0; 9718#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9719#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9893#L607-15 assume !(0 != activate_threads_~tmp~1); 10099#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9956#L249-15 assume !(1 == ~t1_pc~0); 9957#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 9994#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9995#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9674#L615-15 assume !(0 != activate_threads_~tmp___0~0); 9675#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9687#L268-15 assume 1 == ~t2_pc~0; 9911#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9677#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9773#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9914#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9958#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9959#L287-15 assume !(1 == ~t3_pc~0); 9982#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 10014#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10019#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9788#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9789#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9793#L306-15 assume 1 == ~t4_pc~0; 9667#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9668#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9655#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9656#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10020#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 10021#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9975#L552-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9976#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10040#L562-3 assume !(1 == ~T4_E~0); 9853#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9854#L572-3 assume !(1 == ~E_2~0); 9925#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9926#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9818#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 9819#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11726#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11725#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11724#L787 assume !(0 == start_simulation_~tmp~3); 11723#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 10068#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 9808#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 9843#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 9726#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 9727#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 9849#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9946#L800 assume !(0 != start_simulation_~tmp___0~1); 9797#L768-1 [2021-07-06 20:43:36,056 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,056 INFO L82 PathProgramCache]: Analyzing trace with hash 1056839975, now seen corresponding path program 1 times [2021-07-06 20:43:36,057 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,057 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081419502] [2021-07-06 20:43:36,057 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,057 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,088 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,088 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,093 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,093 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081419502] [2021-07-06 20:43:36,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081419502] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:43:36,095 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702704935] [2021-07-06 20:43:36,097 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:36,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,097 INFO L82 PathProgramCache]: Analyzing trace with hash -787982620, now seen corresponding path program 2 times [2021-07-06 20:43:36,097 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503684697] [2021-07-06 20:43:36,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,098 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,112 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,113 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,116 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,117 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:36,121 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,121 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,122 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503684697] [2021-07-06 20:43:36,122 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503684697] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,122 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,122 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:36,124 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887102899] [2021-07-06 20:43:36,125 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:36,125 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:36,125 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:36,128 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:36,128 INFO L87 Difference]: Start difference. First operand 2162 states and 3127 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:36,152 INFO L93 Difference]: Finished difference Result 2162 states and 3098 transitions. [2021-07-06 20:43:36,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:36,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3098 transitions. [2021-07-06 20:43:36,166 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-07-06 20:43:36,179 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3098 transitions. [2021-07-06 20:43:36,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2021-07-06 20:43:36,181 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2021-07-06 20:43:36,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3098 transitions. [2021-07-06 20:43:36,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:36,185 INFO L681 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-07-06 20:43:36,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3098 transitions. [2021-07-06 20:43:36,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2021-07-06 20:43:36,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.432932469935245) internal successors, (3098), 2161 states have internal predecessors, (3098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,220 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3098 transitions. [2021-07-06 20:43:36,220 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-07-06 20:43:36,220 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3098 transitions. [2021-07-06 20:43:36,220 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-07-06 20:43:36,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3098 transitions. [2021-07-06 20:43:36,234 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-07-06 20:43:36,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:36,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:36,238 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,238 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,238 INFO L791 eck$LassoCheckResult]: Stem: 14203#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 14027#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14028#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14066#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 14324#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14380#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14258#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14259#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14325#L353-1 assume !(0 == ~M_E~0); 14093#L494-1 assume !(0 == ~T1_E~0); 14094#L499-1 assume !(0 == ~T2_E~0); 14149#L504-1 assume !(0 == ~T3_E~0); 14374#L509-1 assume !(0 == ~T4_E~0); 14384#L514-1 assume !(0 == ~E_1~0); 14286#L519-1 assume !(0 == ~E_2~0); 14287#L524-1 assume !(0 == ~E_3~0); 14349#L529-1 assume !(0 == ~E_4~0); 14200#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14014#L230 assume !(1 == ~m_pc~0); 14015#L230-2 is_master_triggered_~__retres1~0 := 0; 14016#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14017#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14197#L607 assume !(0 != activate_threads_~tmp~1); 14280#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14281#L249 assume !(1 == ~t1_pc~0); 14320#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 14321#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14329#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14119#L615 assume !(0 != activate_threads_~tmp___0~0); 14120#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14125#L268 assume !(1 == ~t2_pc~0); 14143#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 14144#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14155#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14247#L623 assume !(0 != activate_threads_~tmp___1~0); 14338#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14339#L287 assume !(1 == ~t3_pc~0); 14345#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 14346#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14278#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14166#L631 assume !(0 != activate_threads_~tmp___2~0); 14167#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14168#L306 assume !(1 == ~t4_pc~0); 14037#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 14038#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14031#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 14032#L639 assume !(0 != activate_threads_~tmp___3~0); 14180#L639-2 assume !(1 == ~M_E~0); 14372#L547-1 assume !(1 == ~T1_E~0); 14282#L552-1 assume !(1 == ~T2_E~0); 14283#L557-1 assume !(1 == ~T3_E~0); 14344#L562-1 assume !(1 == ~T4_E~0); 14198#L567-1 assume !(1 == ~E_1~0); 14199#L572-1 assume !(1 == ~E_2~0); 14021#L577-1 assume !(1 == ~E_3~0); 14022#L582-1 assume !(1 == ~E_4~0); 14126#L768-1 [2021-07-06 20:43:36,238 INFO L793 eck$LassoCheckResult]: Loop: 14126#L768-1 assume !false; 15653#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15648#L469 assume !false; 15643#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15613#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15607#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15605#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15602#L408 assume !(0 != eval_~tmp~0); 15603#L484 start_simulation_~kernel_st~0 := 2; 16104#L326-1 start_simulation_~kernel_st~0 := 3; 16103#L494-2 assume !(0 == ~M_E~0); 16102#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14158#L499-3 assume !(0 == ~T2_E~0); 14159#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16099#L509-3 assume !(0 == ~T4_E~0); 16098#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16097#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16096#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16095#L529-3 assume !(0 == ~E_4~0); 16094#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16092#L230-15 assume !(1 == ~m_pc~0); 16090#L230-17 is_master_triggered_~__retres1~0 := 0; 16089#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16088#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16087#L607-15 assume !(0 != activate_threads_~tmp~1); 16086#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16085#L249-15 assume !(1 == ~t1_pc~0); 16084#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 16083#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16081#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16079#L615-15 assume !(0 != activate_threads_~tmp___0~0); 16039#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16038#L268-15 assume 1 == ~t2_pc~0; 16006#L269-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16004#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16002#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16000#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15998#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15996#L287-15 assume !(1 == ~t3_pc~0); 15994#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 15992#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15990#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15988#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15982#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15943#L306-15 assume 1 == ~t4_pc~0; 15939#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15937#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15935#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15933#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15931#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 15929#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15927#L552-3 assume !(1 == ~T2_E~0); 15925#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15923#L562-3 assume !(1 == ~T4_E~0); 15921#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15918#L572-3 assume !(1 == ~E_2~0); 15897#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15885#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15880#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15874#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15830#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15821#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 15815#L787 assume !(0 == start_simulation_~tmp~3); 15811#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15792#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15786#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15782#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 15779#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 15773#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 15767#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15762#L800 assume !(0 != start_simulation_~tmp___0~1); 14126#L768-1 [2021-07-06 20:43:36,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 1 times [2021-07-06 20:43:36,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,240 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583249323] [2021-07-06 20:43:36,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,241 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:36,252 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:36,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:36,260 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:36,297 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:36,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,298 INFO L82 PathProgramCache]: Analyzing trace with hash -1044931292, now seen corresponding path program 1 times [2021-07-06 20:43:36,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,300 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408787782] [2021-07-06 20:43:36,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,301 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,337 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,337 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,338 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,338 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 5 [2021-07-06 20:43:36,341 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,342 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,342 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408787782] [2021-07-06 20:43:36,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408787782] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,343 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,343 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:36,343 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743635875] [2021-07-06 20:43:36,343 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:36,344 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:36,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:36,344 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:36,344 INFO L87 Difference]: Start difference. First operand 2162 states and 3098 transitions. cyclomatic complexity: 940 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:36,419 INFO L93 Difference]: Finished difference Result 3793 states and 5373 transitions. [2021-07-06 20:43:36,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:36,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3793 states and 5373 transitions. [2021-07-06 20:43:36,442 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3664 [2021-07-06 20:43:36,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3793 states to 3793 states and 5373 transitions. [2021-07-06 20:43:36,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3793 [2021-07-06 20:43:36,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3793 [2021-07-06 20:43:36,466 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3793 states and 5373 transitions. [2021-07-06 20:43:36,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:36,472 INFO L681 BuchiCegarLoop]: Abstraction has 3793 states and 5373 transitions. [2021-07-06 20:43:36,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3793 states and 5373 transitions. [2021-07-06 20:43:36,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3793 to 3790. [2021-07-06 20:43:36,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3790 states, 3790 states have (on average 1.4168865435356202) internal successors, (5370), 3789 states have internal predecessors, (5370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3790 states to 3790 states and 5370 transitions. [2021-07-06 20:43:36,534 INFO L704 BuchiCegarLoop]: Abstraction has 3790 states and 5370 transitions. [2021-07-06 20:43:36,534 INFO L587 BuchiCegarLoop]: Abstraction has 3790 states and 5370 transitions. [2021-07-06 20:43:36,534 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-07-06 20:43:36,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3790 states and 5370 transitions. [2021-07-06 20:43:36,554 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3661 [2021-07-06 20:43:36,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:36,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:36,555 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,555 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,556 INFO L791 eck$LassoCheckResult]: Stem: 20171#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 19987#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 19988#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20024#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 20299#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20370#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20233#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20234#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20300#L353-1 assume !(0 == ~M_E~0); 20052#L494-1 assume !(0 == ~T1_E~0); 20053#L499-1 assume !(0 == ~T2_E~0); 20109#L504-1 assume !(0 == ~T3_E~0); 20360#L509-1 assume !(0 == ~T4_E~0); 20374#L514-1 assume !(0 == ~E_1~0); 20261#L519-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20262#L524-1 assume !(0 == ~E_3~0); 20358#L529-1 assume !(0 == ~E_4~0); 20359#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19975#L230 assume !(1 == ~m_pc~0); 19976#L230-2 is_master_triggered_~__retres1~0 := 0; 20464#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20162#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20163#L607 assume !(0 != activate_threads_~tmp~1); 20255#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20256#L249 assume !(1 == ~t1_pc~0); 20294#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 20295#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20304#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20078#L615 assume !(0 != activate_threads_~tmp___0~0); 20079#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20458#L268 assume !(1 == ~t2_pc~0); 20457#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 20222#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20456#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20342#L623 assume !(0 != activate_threads_~tmp___1~0); 20343#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20352#L287 assume !(1 == ~t3_pc~0); 20353#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 20354#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20253#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20125#L631 assume !(0 != activate_threads_~tmp___2~0); 20126#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20127#L306 assume !(1 == ~t4_pc~0); 19996#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 19997#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20132#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20433#L639 assume !(0 != activate_threads_~tmp___3~0); 20355#L639-2 assume !(1 == ~M_E~0); 20356#L547-1 assume !(1 == ~T1_E~0); 20428#L552-1 assume !(1 == ~T2_E~0); 20319#L557-1 assume !(1 == ~T3_E~0); 20320#L562-1 assume !(1 == ~T4_E~0); 20164#L567-1 assume !(1 == ~E_1~0); 20165#L572-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19981#L577-1 assume !(1 == ~E_3~0); 19982#L582-1 assume !(1 == ~E_4~0); 20086#L768-1 [2021-07-06 20:43:36,556 INFO L793 eck$LassoCheckResult]: Loop: 20086#L768-1 assume !false; 23393#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 23391#L469 assume !false; 23389#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 23386#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 23086#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 23087#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 23079#L408 assume !(0 != eval_~tmp~0); 23081#L484 start_simulation_~kernel_st~0 := 2; 23734#L326-1 start_simulation_~kernel_st~0 := 3; 23733#L494-2 assume !(0 == ~M_E~0); 23732#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23731#L499-3 assume !(0 == ~T2_E~0); 23730#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23729#L509-3 assume !(0 == ~T4_E~0); 23728#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23727#L519-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20225#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20283#L529-3 assume !(0 == ~E_4~0); 20145#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20146#L230-15 assume !(1 == ~m_pc~0); 20214#L230-17 is_master_triggered_~__retres1~0 := 0; 20008#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20009#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20183#L607-15 assume !(0 != activate_threads_~tmp~1); 23719#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23718#L249-15 assume !(1 == ~t1_pc~0); 20410#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 20281#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20282#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19966#L615-15 assume !(0 != activate_threads_~tmp___0~0); 19967#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19979#L268-15 assume !(1 == ~t2_pc~0); 19968#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 19969#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20063#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20202#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20249#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20250#L287-15 assume !(1 == ~t3_pc~0); 20272#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 20303#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20307#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20075#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20076#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20080#L306-15 assume 1 == ~t4_pc~0; 19956#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 19957#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19949#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19950#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20308#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 20309#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20267#L552-3 assume !(1 == ~T2_E~0); 20268#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20332#L562-3 assume !(1 == ~T4_E~0); 20143#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20144#L572-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20193#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20041#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20042#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20106#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20089#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20128#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 20129#L787 assume !(0 == start_simulation_~tmp~3); 23427#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20369#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20094#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20130#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 20131#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 23409#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 23406#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 23405#L800 assume !(0 != start_simulation_~tmp___0~1); 20086#L768-1 [2021-07-06 20:43:36,557 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,557 INFO L82 PathProgramCache]: Analyzing trace with hash -1711268375, now seen corresponding path program 1 times [2021-07-06 20:43:36,557 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,557 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564005529] [2021-07-06 20:43:36,557 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,557 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,573 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,574 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,577 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,578 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,579 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,579 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564005529] [2021-07-06 20:43:36,579 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564005529] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,579 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,579 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:43:36,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684647548] [2021-07-06 20:43:36,580 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:36,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,581 INFO L82 PathProgramCache]: Analyzing trace with hash -980791321, now seen corresponding path program 1 times [2021-07-06 20:43:36,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,582 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27425787] [2021-07-06 20:43:36,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,582 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,596 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,596 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,597 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,598 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,602 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,602 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,610 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,611 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,616 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,616 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,618 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,619 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27425787] [2021-07-06 20:43:36,619 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27425787] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,619 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,619 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:43:36,619 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085902859] [2021-07-06 20:43:36,620 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:36,620 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:36,620 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:36,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:36,621 INFO L87 Difference]: Start difference. First operand 3790 states and 5370 transitions. cyclomatic complexity: 1584 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 2 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:36,660 INFO L93 Difference]: Finished difference Result 2162 states and 3031 transitions. [2021-07-06 20:43:36,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:36,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2162 states and 3031 transitions. [2021-07-06 20:43:36,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-07-06 20:43:36,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2162 states to 2162 states and 3031 transitions. [2021-07-06 20:43:36,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2162 [2021-07-06 20:43:36,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2162 [2021-07-06 20:43:36,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2162 states and 3031 transitions. [2021-07-06 20:43:36,683 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:36,683 INFO L681 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-07-06 20:43:36,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2162 states and 3031 transitions. [2021-07-06 20:43:36,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2162 to 2162. [2021-07-06 20:43:36,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2162 states, 2162 states have (on average 1.4019426456984274) internal successors, (3031), 2161 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2162 states to 2162 states and 3031 transitions. [2021-07-06 20:43:36,713 INFO L704 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-07-06 20:43:36,713 INFO L587 BuchiCegarLoop]: Abstraction has 2162 states and 3031 transitions. [2021-07-06 20:43:36,713 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-07-06 20:43:36,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2162 states and 3031 transitions. [2021-07-06 20:43:36,718 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2089 [2021-07-06 20:43:36,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:36,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:36,719 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,719 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,720 INFO L791 eck$LassoCheckResult]: Stem: 26121#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 25948#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 25949#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 25984#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 26230#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26281#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26169#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26170#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26231#L353-1 assume !(0 == ~M_E~0); 26010#L494-1 assume !(0 == ~T1_E~0); 26011#L499-1 assume !(0 == ~T2_E~0); 26065#L504-1 assume !(0 == ~T3_E~0); 26275#L509-1 assume !(0 == ~T4_E~0); 26285#L514-1 assume !(0 == ~E_1~0); 26198#L519-1 assume !(0 == ~E_2~0); 26199#L524-1 assume !(0 == ~E_3~0); 26255#L529-1 assume !(0 == ~E_4~0); 26117#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25936#L230 assume !(1 == ~m_pc~0); 25937#L230-2 is_master_triggered_~__retres1~0 := 0; 25938#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25939#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26114#L607 assume !(0 != activate_threads_~tmp~1); 26191#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26192#L249 assume !(1 == ~t1_pc~0); 26226#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 26227#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26235#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26038#L615 assume !(0 != activate_threads_~tmp___0~0); 26039#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26043#L268 assume !(1 == ~t2_pc~0); 26059#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 26060#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26071#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26159#L623 assume !(0 != activate_threads_~tmp___1~0); 26244#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26245#L287 assume !(1 == ~t3_pc~0); 26250#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 26251#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26187#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26081#L631 assume !(0 != activate_threads_~tmp___2~0); 26082#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26083#L306 assume !(1 == ~t4_pc~0); 25957#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 25958#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25952#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 25953#L639 assume !(0 != activate_threads_~tmp___3~0); 26094#L639-2 assume !(1 == ~M_E~0); 26273#L547-1 assume !(1 == ~T1_E~0); 26193#L552-1 assume !(1 == ~T2_E~0); 26194#L557-1 assume !(1 == ~T3_E~0); 26248#L562-1 assume !(1 == ~T4_E~0); 26115#L567-1 assume !(1 == ~E_1~0); 26116#L572-1 assume !(1 == ~E_2~0); 25942#L577-1 assume !(1 == ~E_3~0); 25943#L582-1 assume !(1 == ~E_4~0); 26044#L768-1 [2021-07-06 20:43:36,720 INFO L793 eck$LassoCheckResult]: Loop: 26044#L768-1 assume !false; 26055#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 26006#L469 assume !false; 26256#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 26279#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 26077#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 26277#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 26269#L408 assume !(0 != eval_~tmp~0); 26271#L484 start_simulation_~kernel_st~0 := 2; 28050#L326-1 start_simulation_~kernel_st~0 := 3; 28049#L494-2 assume !(0 == ~M_E~0); 28048#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28047#L499-3 assume !(0 == ~T2_E~0); 28046#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28044#L509-3 assume !(0 == ~T4_E~0); 28042#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28040#L519-3 assume !(0 == ~E_2~0); 28038#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27818#L529-3 assume !(0 == ~E_4~0); 27816#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27815#L230-15 assume !(1 == ~m_pc~0); 27814#L230-17 is_master_triggered_~__retres1~0 := 0; 27813#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27812#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27811#L607-15 assume !(0 != activate_threads_~tmp~1); 27810#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27809#L249-15 assume !(1 == ~t1_pc~0); 27808#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 27806#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27804#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 27802#L615-15 assume !(0 != activate_threads_~tmp___0~0); 27800#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27798#L268-15 assume !(1 == ~t2_pc~0); 27795#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 27793#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27791#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27789#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27787#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27785#L287-15 assume !(1 == ~t3_pc~0); 27783#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 27780#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27778#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27776#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27774#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27772#L306-15 assume 1 == ~t4_pc~0; 27769#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27767#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27765#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27763#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27761#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 27759#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27757#L552-3 assume !(1 == ~T2_E~0); 27755#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27752#L562-3 assume !(1 == ~T4_E~0); 27750#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27748#L572-3 assume !(1 == ~E_2~0); 27746#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27744#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27742#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27735#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27731#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27729#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 27727#L787 assume !(0 == start_simulation_~tmp~3); 27725#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27721#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27717#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27714#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 27712#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 27710#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 27708#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 27707#L800 assume !(0 != start_simulation_~tmp___0~1); 26044#L768-1 [2021-07-06 20:43:36,720 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,721 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 2 times [2021-07-06 20:43:36,721 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,721 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685591870] [2021-07-06 20:43:36,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,723 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:36,735 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:36,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:36,742 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:36,760 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:36,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,761 INFO L82 PathProgramCache]: Analyzing trace with hash -615074265, now seen corresponding path program 1 times [2021-07-06 20:43:36,761 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,761 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889401502] [2021-07-06 20:43:36,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,761 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:36,774 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,777 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,777 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,778 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,781 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,782 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,785 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,786 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:36,790 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:36,791 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:36,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:36,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:36,791 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889401502] [2021-07-06 20:43:36,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889401502] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:36,791 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:36,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-07-06 20:43:36,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537161299] [2021-07-06 20:43:36,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:36,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:36,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-07-06 20:43:36,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-07-06 20:43:36,794 INFO L87 Difference]: Start difference. First operand 2162 states and 3031 transitions. cyclomatic complexity: 873 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:36,904 INFO L93 Difference]: Finished difference Result 3731 states and 5155 transitions. [2021-07-06 20:43:36,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-07-06 20:43:36,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3731 states and 5155 transitions. [2021-07-06 20:43:36,920 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3643 [2021-07-06 20:43:36,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3731 states to 3731 states and 5155 transitions. [2021-07-06 20:43:36,935 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3731 [2021-07-06 20:43:36,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3731 [2021-07-06 20:43:36,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3731 states and 5155 transitions. [2021-07-06 20:43:36,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:36,941 INFO L681 BuchiCegarLoop]: Abstraction has 3731 states and 5155 transitions. [2021-07-06 20:43:36,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3731 states and 5155 transitions. [2021-07-06 20:43:36,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3731 to 2189. [2021-07-06 20:43:36,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2189 states, 2189 states have (on average 1.3969849246231156) internal successors, (3058), 2188 states have internal predecessors, (3058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:36,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2189 states to 2189 states and 3058 transitions. [2021-07-06 20:43:36,980 INFO L704 BuchiCegarLoop]: Abstraction has 2189 states and 3058 transitions. [2021-07-06 20:43:36,980 INFO L587 BuchiCegarLoop]: Abstraction has 2189 states and 3058 transitions. [2021-07-06 20:43:36,980 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-07-06 20:43:36,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2189 states and 3058 transitions. [2021-07-06 20:43:36,986 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2116 [2021-07-06 20:43:36,986 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:36,986 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:36,987 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,987 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:36,987 INFO L791 eck$LassoCheckResult]: Stem: 32032#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 31857#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31858#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 31890#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 32144#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32198#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32082#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32083#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32146#L353-1 assume !(0 == ~M_E~0); 31916#L494-1 assume !(0 == ~T1_E~0); 31917#L499-1 assume !(0 == ~T2_E~0); 31974#L504-1 assume !(0 == ~T3_E~0); 32192#L509-1 assume !(0 == ~T4_E~0); 32203#L514-1 assume !(0 == ~E_1~0); 32110#L519-1 assume !(0 == ~E_2~0); 32111#L524-1 assume !(0 == ~E_3~0); 32168#L529-1 assume !(0 == ~E_4~0); 32030#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31842#L230 assume !(1 == ~m_pc~0); 31843#L230-2 is_master_triggered_~__retres1~0 := 0; 31847#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31848#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32027#L607 assume !(0 != activate_threads_~tmp~1); 32104#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32105#L249 assume !(1 == ~t1_pc~0); 32140#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 32141#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32150#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31947#L615 assume !(0 != activate_threads_~tmp___0~0); 31948#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31951#L268 assume !(1 == ~t2_pc~0); 31968#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 31969#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31978#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32073#L623 assume !(0 != activate_threads_~tmp___1~0); 32156#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32157#L287 assume !(1 == ~t3_pc~0); 32166#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 32167#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32101#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31990#L631 assume !(0 != activate_threads_~tmp___2~0); 31991#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31993#L306 assume !(1 == ~t4_pc~0); 31864#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 31865#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31859#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31860#L639 assume !(0 != activate_threads_~tmp___3~0); 32004#L639-2 assume !(1 == ~M_E~0); 32190#L547-1 assume !(1 == ~T1_E~0); 32107#L552-1 assume !(1 == ~T2_E~0); 32108#L557-1 assume !(1 == ~T3_E~0); 32163#L562-1 assume !(1 == ~T4_E~0); 32028#L567-1 assume !(1 == ~E_1~0); 32029#L572-1 assume !(1 == ~E_2~0); 31851#L577-1 assume !(1 == ~E_3~0); 31852#L582-1 assume !(1 == ~E_4~0); 31952#L768-1 [2021-07-06 20:43:36,987 INFO L793 eck$LassoCheckResult]: Loop: 31952#L768-1 assume !false; 33904#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 33848#L469 assume !false; 32205#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 32196#L366 assume !(0 == ~m_st~0); 32137#L370 assume !(0 == ~t1_st~0); 32060#L374 assume !(0 == ~t2_st~0); 31985#L378 assume !(0 == ~t3_st~0); 31986#L382 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 32208#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33408#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 33409#L408 assume !(0 != eval_~tmp~0); 32054#L484 start_simulation_~kernel_st~0 := 2; 32055#L326-1 start_simulation_~kernel_st~0 := 3; 31927#L494-2 assume !(0 == ~M_E~0); 31928#L494-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31935#L499-3 assume !(0 == ~T2_E~0); 31984#L504-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32193#L509-3 assume !(0 == ~T4_E~0); 32204#L514-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32074#L519-3 assume !(0 == ~E_2~0); 32075#L524-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32131#L529-3 assume !(0 == ~E_4~0); 32009#L534-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32010#L230-15 assume !(1 == ~m_pc~0); 32069#L230-17 is_master_triggered_~__retres1~0 := 0; 31878#L241-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31879#L242-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32046#L607-15 assume !(0 != activate_threads_~tmp~1); 32226#L607-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32096#L249-15 assume !(1 == ~t1_pc~0); 32097#L249-17 is_transmit1_triggered_~__retres1~1 := 0; 32129#L260-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32130#L261-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31836#L615-15 assume !(0 != activate_threads_~tmp___0~0); 31837#L615-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31849#L268-15 assume !(1 == ~t2_pc~0); 31838#L268-17 is_transmit2_triggered_~__retres1~2 := 0; 31839#L279-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31931#L280-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32062#L623-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32099#L623-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32100#L287-15 assume !(1 == ~t3_pc~0); 32121#L287-17 is_transmit3_triggered_~__retres1~3 := 0; 32149#L298-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32153#L299-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31944#L631-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31945#L631-17 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31949#L306-15 assume 1 == ~t4_pc~0; 31829#L307-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 31830#L317-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31819#L318-5 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 31820#L639-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32154#L639-17 assume 1 == ~M_E~0;~M_E~0 := 2; 32155#L547-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32115#L552-3 assume !(1 == ~T2_E~0); 32116#L557-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32175#L562-3 assume !(1 == ~T4_E~0); 32007#L567-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32008#L572-3 assume !(1 == ~E_2~0); 32056#L577-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31910#L582-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31911#L587-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 32197#L366-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31956#L393-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 31994#L394-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 31995#L787 assume !(0 == start_simulation_~tmp~3); 33915#L787-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 32199#L366-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 31961#L393-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 32216#L394-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 33909#L742 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 32002#L749 stop_simulation_#res := stop_simulation_~__retres2~0; 32003#L750 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 33908#L800 assume !(0 != start_simulation_~tmp___0~1); 31952#L768-1 [2021-07-06 20:43:36,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:36,988 INFO L82 PathProgramCache]: Analyzing trace with hash -1463119959, now seen corresponding path program 3 times [2021-07-06 20:43:36,988 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:36,988 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1721866857] [2021-07-06 20:43:36,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:36,989 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:36,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:36,997 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,003 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,017 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:37,018 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,018 INFO L82 PathProgramCache]: Analyzing trace with hash 370582195, now seen corresponding path program 1 times [2021-07-06 20:43:37,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,018 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067416627] [2021-07-06 20:43:37,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,019 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:37,035 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,035 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,036 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,036 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 4 [2021-07-06 20:43:37,039 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,039 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:37,040 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:37,040 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067416627] [2021-07-06 20:43:37,040 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067416627] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:37,040 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:37,040 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:37,040 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [928394444] [2021-07-06 20:43:37,041 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-07-06 20:43:37,041 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:37,041 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:37,042 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:37,042 INFO L87 Difference]: Start difference. First operand 2189 states and 3058 transitions. cyclomatic complexity: 873 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:37,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:37,088 INFO L93 Difference]: Finished difference Result 3483 states and 4792 transitions. [2021-07-06 20:43:37,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:37,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3483 states and 4792 transitions. [2021-07-06 20:43:37,101 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3408 [2021-07-06 20:43:37,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3483 states to 3483 states and 4792 transitions. [2021-07-06 20:43:37,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3483 [2021-07-06 20:43:37,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3483 [2021-07-06 20:43:37,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3483 states and 4792 transitions. [2021-07-06 20:43:37,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:37,126 INFO L681 BuchiCegarLoop]: Abstraction has 3483 states and 4792 transitions. [2021-07-06 20:43:37,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3483 states and 4792 transitions. [2021-07-06 20:43:37,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3483 to 3363. [2021-07-06 20:43:37,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3363 states, 3363 states have (on average 1.3785310734463276) internal successors, (4636), 3362 states have internal predecessors, (4636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:37,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3363 states to 3363 states and 4636 transitions. [2021-07-06 20:43:37,210 INFO L704 BuchiCegarLoop]: Abstraction has 3363 states and 4636 transitions. [2021-07-06 20:43:37,211 INFO L587 BuchiCegarLoop]: Abstraction has 3363 states and 4636 transitions. [2021-07-06 20:43:37,211 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-07-06 20:43:37,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3363 states and 4636 transitions. [2021-07-06 20:43:37,221 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3288 [2021-07-06 20:43:37,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:37,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:37,222 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:37,222 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:37,222 INFO L791 eck$LassoCheckResult]: Stem: 37708#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 37536#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37537#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37570#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 37820#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37876#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37756#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37757#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37821#L353-1 assume !(0 == ~M_E~0); 37596#L494-1 assume !(0 == ~T1_E~0); 37597#L499-1 assume !(0 == ~T2_E~0); 37653#L504-1 assume !(0 == ~T3_E~0); 37867#L509-1 assume !(0 == ~T4_E~0); 37880#L514-1 assume !(0 == ~E_1~0); 37786#L519-1 assume !(0 == ~E_2~0); 37787#L524-1 assume !(0 == ~E_3~0); 37842#L529-1 assume !(0 == ~E_4~0); 37706#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37520#L230 assume !(1 == ~m_pc~0); 37521#L230-2 is_master_triggered_~__retres1~0 := 0; 37525#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37526#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 37703#L607 assume !(0 != activate_threads_~tmp~1); 37779#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37780#L249 assume !(1 == ~t1_pc~0); 37816#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 37817#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37825#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 37627#L615 assume !(0 != activate_threads_~tmp___0~0); 37628#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37631#L268 assume !(1 == ~t2_pc~0); 37648#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 37649#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37657#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37747#L623 assume !(0 != activate_threads_~tmp___1~0); 37831#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37832#L287 assume !(1 == ~t3_pc~0); 37840#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 37841#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37776#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37669#L631 assume !(0 != activate_threads_~tmp___2~0); 37670#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37671#L306 assume !(1 == ~t4_pc~0); 37543#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 37544#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37538#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37539#L639 assume !(0 != activate_threads_~tmp___3~0); 37681#L639-2 assume !(1 == ~M_E~0); 37865#L547-1 assume !(1 == ~T1_E~0); 37782#L552-1 assume !(1 == ~T2_E~0); 37783#L557-1 assume !(1 == ~T3_E~0); 37837#L562-1 assume !(1 == ~T4_E~0); 37704#L567-1 assume !(1 == ~E_1~0); 37705#L572-1 assume !(1 == ~E_2~0); 37530#L577-1 assume !(1 == ~E_3~0); 37531#L582-1 assume !(1 == ~E_4~0); 37632#L768-1 assume !false; 39236#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 39234#L469 [2021-07-06 20:43:37,223 INFO L793 eck$LassoCheckResult]: Loop: 39234#L469 assume !false; 39224#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 39225#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 39215#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 39216#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 39208#L408 assume 0 != eval_~tmp~0; 39204#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 39203#L416 assume !(0 != eval_~tmp_ndt_1~0); 39202#L413 assume !(0 == ~t1_st~0); 39200#L427 assume !(0 == ~t2_st~0); 39198#L441 assume !(0 == ~t3_st~0); 39237#L455 assume !(0 == ~t4_st~0); 39234#L469 [2021-07-06 20:43:37,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,223 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 1 times [2021-07-06 20:43:37,223 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,223 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004710228] [2021-07-06 20:43:37,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,224 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,232 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,246 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,255 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:37,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,256 INFO L82 PathProgramCache]: Analyzing trace with hash 590384517, now seen corresponding path program 1 times [2021-07-06 20:43:37,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,256 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501829307] [2021-07-06 20:43:37,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,257 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,262 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,263 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,265 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:37,265 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,265 INFO L82 PathProgramCache]: Analyzing trace with hash 162355663, now seen corresponding path program 1 times [2021-07-06 20:43:37,265 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756575282] [2021-07-06 20:43:37,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,266 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:37,320 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,320 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,321 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,321 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:37,324 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,325 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:37,326 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:37,326 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756575282] [2021-07-06 20:43:37,326 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756575282] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:37,327 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:37,327 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:37,327 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468613875] [2021-07-06 20:43:37,373 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,377 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 35 [2021-07-06 20:43:37,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:37,421 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:37,422 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:37,422 INFO L87 Difference]: Start difference. First operand 3363 states and 4636 transitions. cyclomatic complexity: 1280 Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:37,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:37,476 INFO L93 Difference]: Finished difference Result 6225 states and 8480 transitions. [2021-07-06 20:43:37,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:37,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6225 states and 8480 transitions. [2021-07-06 20:43:37,503 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5817 [2021-07-06 20:43:37,525 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6225 states to 6225 states and 8480 transitions. [2021-07-06 20:43:37,525 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6225 [2021-07-06 20:43:37,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6225 [2021-07-06 20:43:37,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6225 states and 8480 transitions. [2021-07-06 20:43:37,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:37,537 INFO L681 BuchiCegarLoop]: Abstraction has 6225 states and 8480 transitions. [2021-07-06 20:43:37,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6225 states and 8480 transitions. [2021-07-06 20:43:37,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6225 to 6085. [2021-07-06 20:43:37,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6085 states, 6085 states have (on average 1.3640098603122432) internal successors, (8300), 6084 states have internal predecessors, (8300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:37,678 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6085 states to 6085 states and 8300 transitions. [2021-07-06 20:43:37,678 INFO L704 BuchiCegarLoop]: Abstraction has 6085 states and 8300 transitions. [2021-07-06 20:43:37,678 INFO L587 BuchiCegarLoop]: Abstraction has 6085 states and 8300 transitions. [2021-07-06 20:43:37,679 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-07-06 20:43:37,679 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6085 states and 8300 transitions. [2021-07-06 20:43:37,699 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 5677 [2021-07-06 20:43:37,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:37,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:37,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:37,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:37,701 INFO L791 eck$LassoCheckResult]: Stem: 47333#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 47133#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 47134#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 47168#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 47455#L333-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 47534#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 47387#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47388#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47511#L353-1 assume !(0 == ~M_E~0); 47512#L494-1 assume !(0 == ~T1_E~0); 47263#L499-1 assume !(0 == ~T2_E~0); 47264#L504-1 assume !(0 == ~T3_E~0); 47539#L509-1 assume !(0 == ~T4_E~0); 47540#L514-1 assume !(0 == ~E_1~0); 47416#L519-1 assume !(0 == ~E_2~0); 47417#L524-1 assume !(0 == ~E_3~0); 47522#L529-1 assume !(0 == ~E_4~0); 47523#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47117#L230 assume !(1 == ~m_pc~0); 47118#L230-2 is_master_triggered_~__retres1~0 := 0; 47122#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47123#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 47434#L607 assume !(0 != activate_threads_~tmp~1); 47435#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47463#L249 assume !(1 == ~t1_pc~0); 47464#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 47465#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47466#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 47233#L615 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 47234#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47238#L268 assume !(1 == ~t2_pc~0); 47257#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 47258#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47377#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 47378#L623 assume !(0 != activate_threads_~tmp___1~0); 47471#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47472#L287 assume !(1 == ~t3_pc~0); 47483#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 47484#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47406#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 47407#L631 assume !(0 != activate_threads_~tmp___2~0); 47287#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 47288#L306 assume !(1 == ~t4_pc~0); 47141#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 47142#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47135#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 47136#L639 assume !(0 != activate_threads_~tmp___3~0); 47517#L639-2 assume !(1 == ~M_E~0); 47518#L547-1 assume !(1 == ~T1_E~0); 47413#L552-1 assume !(1 == ~T2_E~0); 47414#L557-1 assume !(1 == ~T3_E~0); 47520#L562-1 assume !(1 == ~T4_E~0); 47521#L567-1 assume !(1 == ~E_1~0); 47367#L572-1 assume !(1 == ~E_2~0); 47368#L577-1 assume !(1 == ~E_3~0); 47239#L582-1 assume !(1 == ~E_4~0); 47240#L768-1 assume !false; 51970#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 51969#L469 [2021-07-06 20:43:37,701 INFO L793 eck$LassoCheckResult]: Loop: 51969#L469 assume !false; 51968#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51966#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51965#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51964#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 51963#L408 assume 0 != eval_~tmp~0; 51962#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 51659#L416 assume !(0 != eval_~tmp_ndt_1~0); 51244#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 47506#L430 assume !(0 != eval_~tmp_ndt_2~0); 47507#L427 assume !(0 == ~t2_st~0); 51976#L441 assume !(0 == ~t3_st~0); 51973#L455 assume !(0 == ~t4_st~0); 51969#L469 [2021-07-06 20:43:37,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,702 INFO L82 PathProgramCache]: Analyzing trace with hash -750579381, now seen corresponding path program 1 times [2021-07-06 20:43:37,702 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,702 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807437185] [2021-07-06 20:43:37,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,702 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:37,718 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,719 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,719 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,720 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:37,723 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,723 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:37,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:37,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:37,724 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807437185] [2021-07-06 20:43:37,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807437185] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:37,724 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:37,724 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:37,724 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1931118719] [2021-07-06 20:43:37,725 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-07-06 20:43:37,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:37,725 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 1 times [2021-07-06 20:43:37,725 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:37,726 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1830925330] [2021-07-06 20:43:37,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:37,726 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:37,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,729 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:37,730 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:37,732 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:37,784 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:37,786 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 40 [2021-07-06 20:43:37,811 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:37,812 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:37,812 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:37,812 INFO L87 Difference]: Start difference. First operand 6085 states and 8300 transitions. cyclomatic complexity: 2226 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:37,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:37,834 INFO L93 Difference]: Finished difference Result 4976 states and 6801 transitions. [2021-07-06 20:43:37,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:37,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4976 states and 6801 transitions. [2021-07-06 20:43:37,855 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2021-07-06 20:43:37,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4976 states to 4976 states and 6801 transitions. [2021-07-06 20:43:37,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4976 [2021-07-06 20:43:37,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4976 [2021-07-06 20:43:37,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4976 states and 6801 transitions. [2021-07-06 20:43:37,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:37,892 INFO L681 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-07-06 20:43:37,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4976 states and 6801 transitions. [2021-07-06 20:43:38,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4976 to 4976. [2021-07-06 20:43:38,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4976 states, 4976 states have (on average 1.3667604501607717) internal successors, (6801), 4975 states have internal predecessors, (6801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:38,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4976 states to 4976 states and 6801 transitions. [2021-07-06 20:43:38,039 INFO L704 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-07-06 20:43:38,039 INFO L587 BuchiCegarLoop]: Abstraction has 4976 states and 6801 transitions. [2021-07-06 20:43:38,039 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-07-06 20:43:38,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4976 states and 6801 transitions. [2021-07-06 20:43:38,058 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 4891 [2021-07-06 20:43:38,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:38,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:38,059 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:38,059 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:38,060 INFO L791 eck$LassoCheckResult]: Stem: 58373#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 58200#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 58201#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58234#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 58492#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58552#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58426#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58427#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58493#L353-1 assume !(0 == ~M_E~0); 58262#L494-1 assume !(0 == ~T1_E~0); 58263#L499-1 assume !(0 == ~T2_E~0); 58319#L504-1 assume !(0 == ~T3_E~0); 58542#L509-1 assume !(0 == ~T4_E~0); 58556#L514-1 assume !(0 == ~E_1~0); 58454#L519-1 assume !(0 == ~E_2~0); 58455#L524-1 assume !(0 == ~E_3~0); 58515#L529-1 assume !(0 == ~E_4~0); 58371#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58187#L230 assume !(1 == ~m_pc~0); 58188#L230-2 is_master_triggered_~__retres1~0 := 0; 58189#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58190#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58368#L607 assume !(0 != activate_threads_~tmp~1); 58449#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58450#L249 assume !(1 == ~t1_pc~0); 58485#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 58486#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58498#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58292#L615 assume !(0 != activate_threads_~tmp___0~0); 58293#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58297#L268 assume !(1 == ~t2_pc~0); 58314#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 58315#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58323#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58417#L623 assume !(0 != activate_threads_~tmp___1~0); 58505#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58506#L287 assume !(1 == ~t3_pc~0); 58513#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 58514#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58445#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58335#L631 assume !(0 != activate_threads_~tmp___2~0); 58336#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58337#L306 assume !(1 == ~t4_pc~0); 58207#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 58208#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58204#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58205#L639 assume !(0 != activate_threads_~tmp___3~0); 58349#L639-2 assume !(1 == ~M_E~0); 58540#L547-1 assume !(1 == ~T1_E~0); 58451#L552-1 assume !(1 == ~T2_E~0); 58452#L557-1 assume !(1 == ~T3_E~0); 58510#L562-1 assume !(1 == ~T4_E~0); 58369#L567-1 assume !(1 == ~E_1~0); 58370#L572-1 assume !(1 == ~E_2~0); 58194#L577-1 assume !(1 == ~E_3~0); 58195#L582-1 assume !(1 == ~E_4~0); 58298#L768-1 assume !false; 62492#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 62490#L469 [2021-07-06 20:43:38,060 INFO L793 eck$LassoCheckResult]: Loop: 62490#L469 assume !false; 62488#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 62485#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 62482#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 62480#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 62478#L408 assume 0 != eval_~tmp~0; 62475#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 62474#L416 assume !(0 != eval_~tmp_ndt_1~0); 62473#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 62472#L430 assume !(0 != eval_~tmp_ndt_2~0); 62466#L427 assume !(0 == ~t2_st~0); 62462#L441 assume !(0 == ~t3_st~0); 62460#L455 assume !(0 == ~t4_st~0); 62490#L469 [2021-07-06 20:43:38,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,060 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 2 times [2021-07-06 20:43:38,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,061 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1310630669] [2021-07-06 20:43:38,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,061 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,068 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,076 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,089 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:38,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,090 INFO L82 PathProgramCache]: Analyzing trace with hash 976788691, now seen corresponding path program 2 times [2021-07-06 20:43:38,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851145636] [2021-07-06 20:43:38,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,090 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,099 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,101 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:38,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,105 INFO L82 PathProgramCache]: Analyzing trace with hash 592796105, now seen corresponding path program 1 times [2021-07-06 20:43:38,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,105 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743829187] [2021-07-06 20:43:38,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,105 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:38,120 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,121 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:38,122 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,122 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:38,125 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,126 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:38,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:38,126 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:38,126 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743829187] [2021-07-06 20:43:38,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743829187] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:38,128 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:38,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:38,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1525404954] [2021-07-06 20:43:38,178 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,180 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 40 [2021-07-06 20:43:38,244 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:38,244 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:38,245 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:38,245 INFO L87 Difference]: Start difference. First operand 4976 states and 6801 transitions. cyclomatic complexity: 1832 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:38,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:38,309 INFO L93 Difference]: Finished difference Result 8779 states and 11960 transitions. [2021-07-06 20:43:38,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:38,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8779 states and 11960 transitions. [2021-07-06 20:43:38,348 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8669 [2021-07-06 20:43:38,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8779 states to 8779 states and 11960 transitions. [2021-07-06 20:43:38,372 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8779 [2021-07-06 20:43:38,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8779 [2021-07-06 20:43:38,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8779 states and 11960 transitions. [2021-07-06 20:43:38,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:38,389 INFO L681 BuchiCegarLoop]: Abstraction has 8779 states and 11960 transitions. [2021-07-06 20:43:38,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8779 states and 11960 transitions. [2021-07-06 20:43:38,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8779 to 8289. [2021-07-06 20:43:38,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8289 states, 8289 states have (on average 1.3668717577512366) internal successors, (11330), 8288 states have internal predecessors, (11330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:38,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8289 states to 8289 states and 11330 transitions. [2021-07-06 20:43:38,567 INFO L704 BuchiCegarLoop]: Abstraction has 8289 states and 11330 transitions. [2021-07-06 20:43:38,567 INFO L587 BuchiCegarLoop]: Abstraction has 8289 states and 11330 transitions. [2021-07-06 20:43:38,567 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-07-06 20:43:38,567 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8289 states and 11330 transitions. [2021-07-06 20:43:38,590 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 8179 [2021-07-06 20:43:38,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:38,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:38,591 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:38,591 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:38,591 INFO L791 eck$LassoCheckResult]: Stem: 72144#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 71963#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 71964#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 72000#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 72267#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72334#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72195#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 72196#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 72268#L353-1 assume !(0 == ~M_E~0); 72029#L494-1 assume !(0 == ~T1_E~0); 72030#L499-1 assume !(0 == ~T2_E~0); 72088#L504-1 assume !(0 == ~T3_E~0); 72324#L509-1 assume !(0 == ~T4_E~0); 72338#L514-1 assume !(0 == ~E_1~0); 72224#L519-1 assume !(0 == ~E_2~0); 72225#L524-1 assume !(0 == ~E_3~0); 72295#L529-1 assume !(0 == ~E_4~0); 72140#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71950#L230 assume !(1 == ~m_pc~0); 71951#L230-2 is_master_triggered_~__retres1~0 := 0; 71952#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71953#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72137#L607 assume !(0 != activate_threads_~tmp~1); 72218#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 72219#L249 assume !(1 == ~t1_pc~0); 72260#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 72261#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 72276#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 72056#L615 assume !(0 != activate_threads_~tmp___0~0); 72057#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 72062#L268 assume !(1 == ~t2_pc~0); 72081#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 72082#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 72094#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 72184#L623 assume !(0 != activate_threads_~tmp___1~0); 72283#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72284#L287 assume !(1 == ~t3_pc~0); 72290#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 72291#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 72213#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 72105#L631 assume !(0 != activate_threads_~tmp___2~0); 72106#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 72107#L306 assume !(1 == ~t4_pc~0); 71973#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 71974#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71967#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 71968#L639 assume !(0 != activate_threads_~tmp___3~0); 72119#L639-2 assume !(1 == ~M_E~0); 72322#L547-1 assume !(1 == ~T1_E~0); 72220#L552-1 assume !(1 == ~T2_E~0); 72221#L557-1 assume !(1 == ~T3_E~0); 72288#L562-1 assume !(1 == ~T4_E~0); 72138#L567-1 assume !(1 == ~E_1~0); 72139#L572-1 assume !(1 == ~E_2~0); 71957#L577-1 assume !(1 == ~E_3~0); 71958#L582-1 assume !(1 == ~E_4~0); 72063#L768-1 assume !false; 73303#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 73304#L469 [2021-07-06 20:43:38,591 INFO L793 eck$LassoCheckResult]: Loop: 73304#L469 assume !false; 73297#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 73298#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 73290#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 73291#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 73284#L408 assume 0 != eval_~tmp~0; 73285#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 78684#L416 assume !(0 != eval_~tmp_ndt_1~0); 78683#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 78682#L430 assume !(0 != eval_~tmp_ndt_2~0); 73801#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 73802#L444 assume !(0 != eval_~tmp_ndt_3~0); 78674#L441 assume !(0 == ~t3_st~0); 73307#L455 assume !(0 == ~t4_st~0); 73304#L469 [2021-07-06 20:43:38,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,592 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 3 times [2021-07-06 20:43:38,592 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,592 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257256380] [2021-07-06 20:43:38,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,593 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,601 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,613 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,622 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:38,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,622 INFO L82 PathProgramCache]: Analyzing trace with hash 210997043, now seen corresponding path program 1 times [2021-07-06 20:43:38,623 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,623 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [392823275] [2021-07-06 20:43:38,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,624 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,627 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:38,629 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:38,632 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:38,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:38,633 INFO L82 PathProgramCache]: Analyzing trace with hash 1192128765, now seen corresponding path program 1 times [2021-07-06 20:43:38,633 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:38,633 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787094141] [2021-07-06 20:43:38,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:38,633 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:38,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:38,655 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,656 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:38,657 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,659 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:38,663 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,663 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:38,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:38,664 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:38,664 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787094141] [2021-07-06 20:43:38,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787094141] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:38,665 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:38,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-07-06 20:43:38,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814479862] [2021-07-06 20:43:38,724 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:38,730 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 45 [2021-07-06 20:43:38,760 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:38,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:38,761 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:38,761 INFO L87 Difference]: Start difference. First operand 8289 states and 11330 transitions. cyclomatic complexity: 3048 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:38,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:38,870 INFO L93 Difference]: Finished difference Result 12888 states and 17587 transitions. [2021-07-06 20:43:38,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:38,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12888 states and 17587 transitions. [2021-07-06 20:43:38,935 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12758 [2021-07-06 20:43:38,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12888 states to 12888 states and 17587 transitions. [2021-07-06 20:43:38,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12888 [2021-07-06 20:43:38,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12888 [2021-07-06 20:43:38,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12888 states and 17587 transitions. [2021-07-06 20:43:39,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:39,009 INFO L681 BuchiCegarLoop]: Abstraction has 12888 states and 17587 transitions. [2021-07-06 20:43:39,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12888 states and 17587 transitions. [2021-07-06 20:43:39,263 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12888 to 12688. [2021-07-06 20:43:39,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12688 states, 12688 states have (on average 1.3656210592686002) internal successors, (17327), 12687 states have internal predecessors, (17327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:39,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12688 states to 12688 states and 17327 transitions. [2021-07-06 20:43:39,311 INFO L704 BuchiCegarLoop]: Abstraction has 12688 states and 17327 transitions. [2021-07-06 20:43:39,311 INFO L587 BuchiCegarLoop]: Abstraction has 12688 states and 17327 transitions. [2021-07-06 20:43:39,311 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-07-06 20:43:39,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12688 states and 17327 transitions. [2021-07-06 20:43:39,360 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 12558 [2021-07-06 20:43:39,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:39,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:39,361 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:39,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:39,361 INFO L791 eck$LassoCheckResult]: Stem: 93332#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 93147#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 93148#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 93182#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 93462#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93530#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93390#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93391#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93466#L353-1 assume !(0 == ~M_E~0); 93210#L494-1 assume !(0 == ~T1_E~0); 93211#L499-1 assume !(0 == ~T2_E~0); 93273#L504-1 assume !(0 == ~T3_E~0); 93520#L509-1 assume !(0 == ~T4_E~0); 93536#L514-1 assume !(0 == ~E_1~0); 93418#L519-1 assume !(0 == ~E_2~0); 93419#L524-1 assume !(0 == ~E_3~0); 93492#L529-1 assume !(0 == ~E_4~0); 93329#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93132#L230 assume !(1 == ~m_pc~0); 93133#L230-2 is_master_triggered_~__retres1~0 := 0; 93137#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93138#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 93326#L607 assume !(0 != activate_threads_~tmp~1); 93412#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 93413#L249 assume !(1 == ~t1_pc~0); 93457#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 93458#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93474#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 93245#L615 assume !(0 != activate_threads_~tmp___0~0); 93246#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93250#L268 assume !(1 == ~t2_pc~0); 93268#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 93269#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93278#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 93379#L623 assume !(0 != activate_threads_~tmp___1~0); 93480#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93481#L287 assume !(1 == ~t3_pc~0); 93490#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 93491#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 93409#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 93293#L631 assume !(0 != activate_threads_~tmp___2~0); 93294#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 93295#L306 assume !(1 == ~t4_pc~0); 93154#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 93155#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 93149#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 93150#L639 assume !(0 != activate_threads_~tmp___3~0); 93305#L639-2 assume !(1 == ~M_E~0); 93517#L547-1 assume !(1 == ~T1_E~0); 93415#L552-1 assume !(1 == ~T2_E~0); 93416#L557-1 assume !(1 == ~T3_E~0); 93486#L562-1 assume !(1 == ~T4_E~0); 93327#L567-1 assume !(1 == ~E_1~0); 93328#L572-1 assume !(1 == ~E_2~0); 93141#L577-1 assume !(1 == ~E_3~0); 93142#L582-1 assume !(1 == ~E_4~0); 93251#L768-1 assume !false; 100952#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 100948#L469 [2021-07-06 20:43:39,361 INFO L793 eck$LassoCheckResult]: Loop: 100948#L469 assume !false; 100946#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 100943#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 100941#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 100939#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 100937#L408 assume 0 != eval_~tmp~0; 100934#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 100931#L416 assume !(0 != eval_~tmp_ndt_1~0); 100929#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 99583#L430 assume !(0 != eval_~tmp_ndt_2~0); 99584#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 99833#L444 assume !(0 != eval_~tmp_ndt_3~0); 100963#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 101796#L458 assume !(0 != eval_~tmp_ndt_4~0); 100953#L455 assume !(0 == ~t4_st~0); 100948#L469 [2021-07-06 20:43:39,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:39,362 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 4 times [2021-07-06 20:43:39,362 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:39,362 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042282838] [2021-07-06 20:43:39,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:39,363 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:39,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:39,369 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:39,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:39,375 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:39,383 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:39,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:39,384 INFO L82 PathProgramCache]: Analyzing trace with hash -2049172699, now seen corresponding path program 1 times [2021-07-06 20:43:39,384 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:39,385 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647804868] [2021-07-06 20:43:39,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:39,385 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:39,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:39,388 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:39,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:39,389 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:39,391 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:39,391 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:39,391 INFO L82 PathProgramCache]: Analyzing trace with hash -1698860389, now seen corresponding path program 1 times [2021-07-06 20:43:39,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:39,392 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665728292] [2021-07-06 20:43:39,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:39,392 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:39,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-07-06 20:43:39,409 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:39,409 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 1 [2021-07-06 20:43:39,410 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:39,410 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 3 [2021-07-06 20:43:39,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-07-06 20:43:39,462 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-07-06 20:43:39,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665728292] [2021-07-06 20:43:39,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665728292] provided 1 perfect and 0 imperfect interpolant sequences [2021-07-06 20:43:39,463 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-07-06 20:43:39,463 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-07-06 20:43:39,463 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802710140] [2021-07-06 20:43:39,531 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:39,532 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 50 [2021-07-06 20:43:39,566 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-07-06 20:43:39,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-07-06 20:43:39,567 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-07-06 20:43:39,567 INFO L87 Difference]: Start difference. First operand 12688 states and 17327 transitions. cyclomatic complexity: 4646 Second operand has 3 states, 2 states have (on average 36.5) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:39,675 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-07-06 20:43:39,676 INFO L93 Difference]: Finished difference Result 23888 states and 32491 transitions. [2021-07-06 20:43:39,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-07-06 20:43:39,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23888 states and 32491 transitions. [2021-07-06 20:43:39,822 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2021-07-06 20:43:39,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23888 states to 23888 states and 32491 transitions. [2021-07-06 20:43:39,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23888 [2021-07-06 20:43:39,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23888 [2021-07-06 20:43:39,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23888 states and 32491 transitions. [2021-07-06 20:43:40,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-07-06 20:43:40,002 INFO L681 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-07-06 20:43:40,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23888 states and 32491 transitions. [2021-07-06 20:43:40,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23888 to 23888. [2021-07-06 20:43:40,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23888 states, 23888 states have (on average 1.3601389819156062) internal successors, (32491), 23887 states have internal predecessors, (32491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-07-06 20:43:40,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23888 states to 23888 states and 32491 transitions. [2021-07-06 20:43:40,409 INFO L704 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-07-06 20:43:40,409 INFO L587 BuchiCegarLoop]: Abstraction has 23888 states and 32491 transitions. [2021-07-06 20:43:40,409 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-07-06 20:43:40,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23888 states and 32491 transitions. [2021-07-06 20:43:40,490 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 23688 [2021-07-06 20:43:40,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-07-06 20:43:40,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-07-06 20:43:40,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:40,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-07-06 20:43:40,492 INFO L791 eck$LassoCheckResult]: Stem: 129909#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 129732#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 129733#L731 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 129765#L326 assume 1 == ~m_i~0;~m_st~0 := 0; 130034#L333-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130110#L338-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129963#L343-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129964#L348-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 130037#L353-1 assume !(0 == ~M_E~0); 129792#L494-1 assume !(0 == ~T1_E~0); 129793#L499-1 assume !(0 == ~T2_E~0); 129852#L504-1 assume !(0 == ~T3_E~0); 130097#L509-1 assume !(0 == ~T4_E~0); 130113#L514-1 assume !(0 == ~E_1~0); 129991#L519-1 assume !(0 == ~E_2~0); 129992#L524-1 assume !(0 == ~E_3~0); 130061#L529-1 assume !(0 == ~E_4~0); 129906#L534-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129716#L230 assume !(1 == ~m_pc~0); 129717#L230-2 is_master_triggered_~__retres1~0 := 0; 129721#L241 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129722#L242 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 129903#L607 assume !(0 != activate_threads_~tmp~1); 129985#L607-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129986#L249 assume !(1 == ~t1_pc~0); 130029#L249-2 is_transmit1_triggered_~__retres1~1 := 0; 130030#L260 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130042#L261 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 129826#L615 assume !(0 != activate_threads_~tmp___0~0); 129827#L615-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 129830#L268 assume !(1 == ~t2_pc~0); 129847#L268-2 is_transmit2_triggered_~__retres1~2 := 0; 129848#L279 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129857#L280 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129953#L623 assume !(0 != activate_threads_~tmp___1~0); 130048#L623-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 130049#L287 assume !(1 == ~t3_pc~0); 130059#L287-2 is_transmit3_triggered_~__retres1~3 := 0; 130060#L298 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129982#L299 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129870#L631 assume !(0 != activate_threads_~tmp___2~0); 129871#L631-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 129872#L306 assume !(1 == ~t4_pc~0); 129739#L306-2 is_transmit4_triggered_~__retres1~4 := 0; 129740#L317 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129734#L318 activate_threads_#t~ret17 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 129735#L639 assume !(0 != activate_threads_~tmp___3~0); 129882#L639-2 assume !(1 == ~M_E~0); 130094#L547-1 assume !(1 == ~T1_E~0); 129988#L552-1 assume !(1 == ~T2_E~0); 129989#L557-1 assume !(1 == ~T3_E~0); 130055#L562-1 assume !(1 == ~T4_E~0); 129904#L567-1 assume !(1 == ~E_1~0); 129905#L572-1 assume !(1 == ~E_2~0); 129726#L577-1 assume !(1 == ~E_3~0); 129727#L582-1 assume !(1 == ~E_4~0); 129831#L768-1 assume !false; 146184#L769 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 146123#L469 [2021-07-06 20:43:40,492 INFO L793 eck$LassoCheckResult]: Loop: 146123#L469 assume !false; 146180#L404 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 146176#L366 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 146173#L393 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 146170#L394 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 146166#L408 assume 0 != eval_~tmp~0; 146160#L408-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 146155#L416 assume !(0 != eval_~tmp_ndt_1~0); 146151#L413 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 146145#L430 assume !(0 != eval_~tmp_ndt_2~0); 146140#L427 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 146121#L444 assume !(0 != eval_~tmp_ndt_3~0); 146135#L441 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 143561#L458 assume !(0 != eval_~tmp_ndt_4~0); 143562#L455 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 146110#L472 assume !(0 != eval_~tmp_ndt_5~0); 146123#L469 [2021-07-06 20:43:40,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:40,493 INFO L82 PathProgramCache]: Analyzing trace with hash -1603966133, now seen corresponding path program 5 times [2021-07-06 20:43:40,493 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:40,493 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109784400] [2021-07-06 20:43:40,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:40,494 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:40,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,502 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,509 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,518 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:40,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:40,518 INFO L82 PathProgramCache]: Analyzing trace with hash 900155617, now seen corresponding path program 1 times [2021-07-06 20:43:40,518 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:40,519 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1463937308] [2021-07-06 20:43:40,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:40,519 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:40,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,526 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,528 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,529 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:40,530 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-07-06 20:43:40,530 INFO L82 PathProgramCache]: Analyzing trace with hash -1125064661, now seen corresponding path program 1 times [2021-07-06 20:43:40,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-07-06 20:43:40,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1244123017] [2021-07-06 20:43:40,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-07-06 20:43:40,531 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-07-06 20:43:40,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,539 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-07-06 20:43:40,545 INFO L224 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-07-06 20:43:40,556 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-07-06 20:43:40,637 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:40,639 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 55 [2021-07-06 20:43:41,719 WARN L205 SmtUtils]: Spent 1.04 s on a formula simplification. DAG size of input: 210 DAG size of output: 153 [2021-07-06 20:43:41,747 INFO L142 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size [2021-07-06 20:43:41,777 INFO L147 QuantifierPusher]: treesize reduction 0, result has 100.0 percent of original size 224 [2021-07-06 20:43:42,007 WARN L205 SmtUtils]: Spent 226.00 ms on a formula simplification that was a NOOP. DAG size: 131 [2021-07-06 20:43:42,064 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.07 08:43:42 BoogieIcfgContainer [2021-07-06 20:43:42,064 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-07-06 20:43:42,065 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-07-06 20:43:42,065 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-07-06 20:43:42,065 INFO L275 PluginConnector]: Witness Printer initialized [2021-07-06 20:43:42,065 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.07 08:43:34" (3/4) ... [2021-07-06 20:43:42,068 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-07-06 20:43:42,122 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-07-06 20:43:42,122 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-07-06 20:43:42,123 INFO L168 Benchmark]: Toolchain (without parser) took 9353.00 ms. Allocated memory was 54.5 MB in the beginning and 2.9 GB in the end (delta: 2.9 GB). Free memory was 31.3 MB in the beginning and 2.6 GB in the end (delta: -2.6 GB). Peak memory consumption was 336.4 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,123 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 54.5 MB. Free memory was 35.8 MB in the beginning and 35.8 MB in the end (delta: 38.2 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-07-06 20:43:42,124 INFO L168 Benchmark]: CACSL2BoogieTranslator took 362.85 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 31.1 MB in the beginning and 47.3 MB in the end (delta: -16.2 MB). Peak memory consumption was 7.7 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,124 INFO L168 Benchmark]: Boogie Procedure Inliner took 75.40 ms. Allocated memory is still 67.1 MB. Free memory was 47.1 MB in the beginning and 43.2 MB in the end (delta: 3.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,124 INFO L168 Benchmark]: Boogie Preprocessor took 49.99 ms. Allocated memory is still 67.1 MB. Free memory was 43.2 MB in the beginning and 39.8 MB in the end (delta: 3.4 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,124 INFO L168 Benchmark]: RCFGBuilder took 934.12 ms. Allocated memory was 67.1 MB in the beginning and 90.2 MB in the end (delta: 23.1 MB). Free memory was 39.6 MB in the beginning and 44.5 MB in the end (delta: -4.9 MB). Peak memory consumption was 21.7 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,125 INFO L168 Benchmark]: BuchiAutomizer took 7864.31 ms. Allocated memory was 90.2 MB in the beginning and 2.9 GB in the end (delta: 2.9 GB). Free memory was 44.5 MB in the beginning and 2.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 386.0 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,125 INFO L168 Benchmark]: Witness Printer took 57.81 ms. Allocated memory is still 2.9 GB. Free memory was 2.6 GB in the beginning and 2.6 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-07-06 20:43:42,126 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 54.5 MB. Free memory was 35.8 MB in the beginning and 35.8 MB in the end (delta: 38.2 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 362.85 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 31.1 MB in the beginning and 47.3 MB in the end (delta: -16.2 MB). Peak memory consumption was 7.7 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 75.40 ms. Allocated memory is still 67.1 MB. Free memory was 47.1 MB in the beginning and 43.2 MB in the end (delta: 3.9 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 49.99 ms. Allocated memory is still 67.1 MB. Free memory was 43.2 MB in the beginning and 39.8 MB in the end (delta: 3.4 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 934.12 ms. Allocated memory was 67.1 MB in the beginning and 90.2 MB in the end (delta: 23.1 MB). Free memory was 39.6 MB in the beginning and 44.5 MB in the end (delta: -4.9 MB). Peak memory consumption was 21.7 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 7864.31 ms. Allocated memory was 90.2 MB in the beginning and 2.9 GB in the end (delta: 2.9 GB). Free memory was 44.5 MB in the beginning and 2.6 GB in the end (delta: -2.5 GB). Peak memory consumption was 386.0 MB. Max. memory is 16.1 GB. * Witness Printer took 57.81 ms. Allocated memory is still 2.9 GB. Free memory was 2.6 GB in the beginning and 2.6 GB in the end (delta: 4.1 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 23888 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.7s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 3.5s. Construction of modules took 0.4s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1582.0ms AutomataMinimizationTime, 18 MinimizatonAttempts, 3308 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.7s Buchi closure took 0.0s. Biggest automaton had 23888 states and ocurred in iteration 18. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 10632 SDtfs, 11500 SDslu, 8611 SDs, 0 SdLazy, 423 SolverSat, 222 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 485.5ms Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc4 concLT0 SILN1 SILU0 SILI10 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 403]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=28660} State at position 1 is {__retres1=0, NULL=0, t3_st=0, NULL=28660, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@356cc2ca=0, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2b96279e=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e99d4cd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7574c2bb=0, NULL=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2b138114=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39214c19=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@17d3839d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7d8a6b82=0, NULL=28661, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4264b792=0, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=28663, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=28662, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@25a64ad9=0, t1_st=0, tmp_ndt_5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e98bdd8=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, t1_i=1, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5ca349d9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@390f4bc9=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 403]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L17] int m_pc = 0; [L18] int t1_pc = 0; [L19] int t2_pc = 0; [L20] int t3_pc = 0; [L21] int t4_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int M_E = 2; [L33] int T1_E = 2; [L34] int T2_E = 2; [L35] int T3_E = 2; [L36] int T4_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L813] int __retres1 ; [L725] m_i = 1 [L726] t1_i = 1 [L727] t2_i = 1 [L728] t3_i = 1 [L729] t4_i = 1 [L754] int kernel_st ; [L755] int tmp ; [L756] int tmp___0 ; [L760] kernel_st = 0 [L333] COND TRUE m_i == 1 [L334] m_st = 0 [L338] COND TRUE t1_i == 1 [L339] t1_st = 0 [L343] COND TRUE t2_i == 1 [L344] t2_st = 0 [L348] COND TRUE t3_i == 1 [L349] t3_st = 0 [L353] COND TRUE t4_i == 1 [L354] t4_st = 0 [L494] COND FALSE !(M_E == 0) [L499] COND FALSE !(T1_E == 0) [L504] COND FALSE !(T2_E == 0) [L509] COND FALSE !(T3_E == 0) [L514] COND FALSE !(T4_E == 0) [L519] COND FALSE !(E_1 == 0) [L524] COND FALSE !(E_2 == 0) [L529] COND FALSE !(E_3 == 0) [L534] COND FALSE !(E_4 == 0) [L597] int tmp ; [L598] int tmp___0 ; [L599] int tmp___1 ; [L600] int tmp___2 ; [L601] int tmp___3 ; [L227] int __retres1 ; [L230] COND FALSE !(m_pc == 1) [L240] __retres1 = 0 [L242] return (__retres1); [L605] tmp = is_master_triggered() [L607] COND FALSE !(\read(tmp)) [L246] int __retres1 ; [L249] COND FALSE !(t1_pc == 1) [L259] __retres1 = 0 [L261] return (__retres1); [L613] tmp___0 = is_transmit1_triggered() [L615] COND FALSE !(\read(tmp___0)) [L265] int __retres1 ; [L268] COND FALSE !(t2_pc == 1) [L278] __retres1 = 0 [L280] return (__retres1); [L621] tmp___1 = is_transmit2_triggered() [L623] COND FALSE !(\read(tmp___1)) [L284] int __retres1 ; [L287] COND FALSE !(t3_pc == 1) [L297] __retres1 = 0 [L299] return (__retres1); [L629] tmp___2 = is_transmit3_triggered() [L631] COND FALSE !(\read(tmp___2)) [L303] int __retres1 ; [L306] COND FALSE !(t4_pc == 1) [L316] __retres1 = 0 [L318] return (__retres1); [L637] tmp___3 = is_transmit4_triggered() [L639] COND FALSE !(\read(tmp___3)) [L547] COND FALSE !(M_E == 1) [L552] COND FALSE !(T1_E == 1) [L557] COND FALSE !(T2_E == 1) [L562] COND FALSE !(T3_E == 1) [L567] COND FALSE !(T4_E == 1) [L572] COND FALSE !(E_1 == 1) [L577] COND FALSE !(E_2 == 1) [L582] COND FALSE !(E_3 == 1) [L587] COND FALSE !(E_4 == 1) [L768] COND TRUE 1 [L771] kernel_st = 1 [L399] int tmp ; Loop: [L403] COND TRUE 1 [L363] int __retres1 ; [L366] COND TRUE m_st == 0 [L367] __retres1 = 1 [L394] return (__retres1); [L406] tmp = exists_runnable_thread() [L408] COND TRUE \read(tmp) [L413] COND TRUE m_st == 0 [L414] int tmp_ndt_1; [L415] tmp_ndt_1 = __VERIFIER_nondet_int() [L416] COND FALSE !(\read(tmp_ndt_1)) [L427] COND TRUE t1_st == 0 [L428] int tmp_ndt_2; [L429] tmp_ndt_2 = __VERIFIER_nondet_int() [L430] COND FALSE !(\read(tmp_ndt_2)) [L441] COND TRUE t2_st == 0 [L442] int tmp_ndt_3; [L443] tmp_ndt_3 = __VERIFIER_nondet_int() [L444] COND FALSE !(\read(tmp_ndt_3)) [L455] COND TRUE t3_st == 0 [L456] int tmp_ndt_4; [L457] tmp_ndt_4 = __VERIFIER_nondet_int() [L458] COND FALSE !(\read(tmp_ndt_4)) [L469] COND TRUE t4_st == 0 [L470] int tmp_ndt_5; [L471] tmp_ndt_5 = __VERIFIER_nondet_int() [L472] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-07-06 20:43:42,165 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...