./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 20ed64ec Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 37c2f037dea88b70ca73720b5945796ac3b5419f ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-20ed64e [2021-08-27 16:30:30,202 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-08-27 16:30:30,204 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-08-27 16:30:30,234 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-08-27 16:30:30,234 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-08-27 16:30:30,237 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-08-27 16:30:30,237 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-08-27 16:30:30,241 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-08-27 16:30:30,243 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-08-27 16:30:30,246 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-08-27 16:30:30,246 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-08-27 16:30:30,249 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-08-27 16:30:30,249 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-08-27 16:30:30,251 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-08-27 16:30:30,252 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-08-27 16:30:30,254 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-08-27 16:30:30,255 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-08-27 16:30:30,255 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-08-27 16:30:30,257 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-08-27 16:30:30,261 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-08-27 16:30:30,262 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-08-27 16:30:30,262 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-08-27 16:30:30,264 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-08-27 16:30:30,265 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-08-27 16:30:30,267 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-08-27 16:30:30,267 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-08-27 16:30:30,267 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-08-27 16:30:30,268 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-08-27 16:30:30,273 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-08-27 16:30:30,274 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-08-27 16:30:30,274 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-08-27 16:30:30,275 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-08-27 16:30:30,276 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-08-27 16:30:30,276 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-08-27 16:30:30,277 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-08-27 16:30:30,277 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-08-27 16:30:30,278 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-08-27 16:30:30,278 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-08-27 16:30:30,278 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-08-27 16:30:30,280 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-08-27 16:30:30,280 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-08-27 16:30:30,281 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-08-27 16:30:30,306 INFO L113 SettingsManager]: Loading preferences was successful [2021-08-27 16:30:30,306 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-08-27 16:30:30,307 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-08-27 16:30:30,307 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-08-27 16:30:30,309 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-08-27 16:30:30,309 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-08-27 16:30:30,309 INFO L138 SettingsManager]: * Use SBE=true [2021-08-27 16:30:30,309 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-08-27 16:30:30,309 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-08-27 16:30:30,309 INFO L138 SettingsManager]: * Use old map elimination=false [2021-08-27 16:30:30,310 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-08-27 16:30:30,310 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-08-27 16:30:30,310 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-08-27 16:30:30,310 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * sizeof long=4 [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-08-27 16:30:30,311 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * sizeof long double=12 [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * Use constant arrays=true [2021-08-27 16:30:30,312 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-08-27 16:30:30,313 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-08-27 16:30:30,313 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-08-27 16:30:30,313 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-08-27 16:30:30,313 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-08-27 16:30:30,313 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-08-27 16:30:30,314 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-08-27 16:30:30,314 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 37c2f037dea88b70ca73720b5945796ac3b5419f [2021-08-27 16:30:30,571 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-08-27 16:30:30,585 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-08-27 16:30:30,587 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-08-27 16:30:30,587 INFO L271 PluginConnector]: Initializing CDTParser... [2021-08-27 16:30:30,588 INFO L275 PluginConnector]: CDTParser initialized [2021-08-27 16:30:30,588 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-08-27 16:30:30,637 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f679b79d/9cb9f248df104fec95b753ef55b552a1/FLAG93472daf8 [2021-08-27 16:30:31,017 INFO L306 CDTParser]: Found 1 translation units. [2021-08-27 16:30:31,017 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2021-08-27 16:30:31,023 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f679b79d/9cb9f248df104fec95b753ef55b552a1/FLAG93472daf8 [2021-08-27 16:30:31,033 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0f679b79d/9cb9f248df104fec95b753ef55b552a1 [2021-08-27 16:30:31,035 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-08-27 16:30:31,036 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-08-27 16:30:31,038 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-08-27 16:30:31,038 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-08-27 16:30:31,040 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-08-27 16:30:31,041 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,041 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6a0efcbb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31, skipping insertion in model container [2021-08-27 16:30:31,042 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,046 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-08-27 16:30:31,080 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-08-27 16:30:31,180 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[366,379] [2021-08-27 16:30:31,245 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-27 16:30:31,282 INFO L203 MainTranslator]: Completed pre-run [2021-08-27 16:30:31,293 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-2.c[366,379] [2021-08-27 16:30:31,338 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-27 16:30:31,350 INFO L208 MainTranslator]: Completed translation [2021-08-27 16:30:31,352 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31 WrapperNode [2021-08-27 16:30:31,352 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-08-27 16:30:31,353 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-08-27 16:30:31,353 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-08-27 16:30:31,353 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-08-27 16:30:31,358 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,373 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,404 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-08-27 16:30:31,405 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-08-27 16:30:31,405 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-08-27 16:30:31,405 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-08-27 16:30:31,411 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,411 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,414 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,414 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,422 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,448 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,449 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,452 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-08-27 16:30:31,453 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-08-27 16:30:31,453 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-08-27 16:30:31,453 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-08-27 16:30:31,454 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,465 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-08-27 16:30:31,469 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-08-27 16:30:31,477 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-08-27 16:30:31,481 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-08-27 16:30:31,505 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-08-27 16:30:31,505 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-08-27 16:30:31,505 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-08-27 16:30:31,505 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-08-27 16:30:32,296 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-08-27 16:30:32,297 INFO L299 CfgBuilder]: Removed 163 assume(true) statements. [2021-08-27 16:30:32,298 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:32 BoogieIcfgContainer [2021-08-27 16:30:32,298 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-08-27 16:30:32,299 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-08-27 16:30:32,299 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-08-27 16:30:32,301 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-08-27 16:30:32,301 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:32,302 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.08 04:30:31" (1/3) ... [2021-08-27 16:30:32,302 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2d376035 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.08 04:30:32, skipping insertion in model container [2021-08-27 16:30:32,302 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:32,302 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31" (2/3) ... [2021-08-27 16:30:32,303 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2d376035 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.08 04:30:32, skipping insertion in model container [2021-08-27 16:30:32,303 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:32,303 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:32" (3/3) ... [2021-08-27 16:30:32,304 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2021-08-27 16:30:32,326 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-08-27 16:30:32,326 INFO L360 BuchiCegarLoop]: Hoare is false [2021-08-27 16:30:32,326 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-08-27 16:30:32,326 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-08-27 16:30:32,327 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-08-27 16:30:32,327 INFO L364 BuchiCegarLoop]: Difference is false [2021-08-27 16:30:32,327 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-08-27 16:30:32,327 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-08-27 16:30:32,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 419 states, 418 states have (on average 1.5598086124401913) internal successors, (652), 418 states have internal predecessors, (652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 352 [2021-08-27 16:30:32,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,368 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,368 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-08-27 16:30:32,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 419 states, 418 states have (on average 1.5598086124401913) internal successors, (652), 418 states have internal predecessors, (652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 352 [2021-08-27 16:30:32,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,377 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,377 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,382 INFO L791 eck$LassoCheckResult]: Stem: 417#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 351#L-1true havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 355#L770true havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 81#L350true assume !(1 == ~m_i~0);~m_st~0 := 2; 286#L357-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 124#L362-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 184#L367-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 320#L372-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 325#L377-1true assume !(0 == ~M_E~0); 128#L518-1true assume !(0 == ~T1_E~0); 375#L523-1true assume !(0 == ~T2_E~0); 238#L528-1true assume !(0 == ~T3_E~0); 388#L533-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 146#L538-1true assume !(0 == ~E_M~0); 72#L543-1true assume !(0 == ~E_1~0); 403#L548-1true assume !(0 == ~E_2~0); 387#L553-1true assume !(0 == ~E_3~0); 290#L558-1true assume !(0 == ~E_4~0); 321#L563-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 241#L254true assume 1 == ~m_pc~0; 220#L255true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 251#L265true is_master_triggered_#res := is_master_triggered_~__retres1~0; 215#L266true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134#L641true assume !(0 != activate_threads_~tmp~1); 187#L641-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 366#L273true assume !(1 == ~t1_pc~0); 404#L273-2true is_transmit1_triggered_~__retres1~1 := 0; 46#L284true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 195#L285true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 365#L649true assume !(0 != activate_threads_~tmp___0~0); 419#L649-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70#L292true assume 1 == ~t2_pc~0; 203#L293true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 206#L303true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 395#L304true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 103#L657true assume !(0 != activate_threads_~tmp___1~0); 346#L657-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 236#L311true assume !(1 == ~t3_pc~0); 273#L311-2true is_transmit3_triggered_~__retres1~3 := 0; 171#L322true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4#L323true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 174#L665true assume !(0 != activate_threads_~tmp___2~0); 28#L665-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 239#L330true assume 1 == ~t4_pc~0; 114#L331true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 71#L341true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22#L342true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 125#L673true assume !(0 != activate_threads_~tmp___3~0); 19#L673-2true assume !(1 == ~M_E~0); 117#L576-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 130#L581-1true assume !(1 == ~T2_E~0); 327#L586-1true assume !(1 == ~T3_E~0); 197#L591-1true assume !(1 == ~T4_E~0); 172#L596-1true assume !(1 == ~E_M~0); 227#L601-1true assume !(1 == ~E_1~0); 211#L606-1true assume !(1 == ~E_2~0); 391#L611-1true assume !(1 == ~E_3~0); 269#L616-1true assume 1 == ~E_4~0;~E_4~0 := 2; 142#L807-1true [2021-08-27 16:30:32,383 INFO L793 eck$LassoCheckResult]: Loop: 142#L807-1true assume !false; 283#L808true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 324#L493true assume !true; 20#L508true start_simulation_~kernel_st~0 := 2; 362#L350-1true start_simulation_~kernel_st~0 := 3; 294#L518-2true assume 0 == ~M_E~0;~M_E~0 := 1; 376#L518-4true assume !(0 == ~T1_E~0); 232#L523-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 264#L528-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 390#L533-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 3#L538-3true assume 0 == ~E_M~0;~E_M~0 := 1; 95#L543-3true assume 0 == ~E_1~0;~E_1~0 := 1; 32#L548-3true assume 0 == ~E_2~0;~E_2~0 := 1; 254#L553-3true assume 0 == ~E_3~0;~E_3~0 := 1; 345#L558-3true assume !(0 == ~E_4~0); 406#L563-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 338#L254-18true assume 1 == ~m_pc~0; 109#L255-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 210#L265-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 116#L266-6true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 157#L641-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 58#L641-20true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 148#L273-18true assume 1 == ~t1_pc~0; 64#L274-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 127#L284-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 333#L285-6true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 360#L649-18true assume !(0 != activate_threads_~tmp___0~0); 16#L649-20true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96#L292-18true assume !(1 == ~t2_pc~0); 59#L292-20true is_transmit2_triggered_~__retres1~2 := 0; 6#L303-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 173#L304-6true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 398#L657-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 248#L657-20true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 383#L311-18true assume !(1 == ~t3_pc~0); 357#L311-20true is_transmit3_triggered_~__retres1~3 := 0; 11#L322-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78#L323-6true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 225#L665-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 287#L665-20true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 266#L330-18true assume 1 == ~t4_pc~0; 106#L331-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 168#L341-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 121#L342-6true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 208#L673-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 188#L673-20true assume 1 == ~M_E~0;~M_E~0 := 2; 155#L576-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 161#L581-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 354#L586-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 182#L591-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 86#L596-3true assume 1 == ~E_M~0;~E_M~0 := 2; 192#L601-3true assume !(1 == ~E_1~0); 315#L606-3true assume 1 == ~E_2~0;~E_2~0 := 2; 217#L611-3true assume 1 == ~E_3~0;~E_3~0 := 2; 222#L616-3true assume 1 == ~E_4~0;~E_4~0 := 2; 33#L621-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 183#L390-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 416#L417-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 319#L418-1true start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 237#L826true assume !(0 == start_simulation_~tmp~3); 37#L826-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 204#L390-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 159#L417-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 322#L418-2true stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 76#L781true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 104#L788true stop_simulation_#res := stop_simulation_~__retres2~0; 253#L789true start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 226#L839true assume !(0 != start_simulation_~tmp___0~1); 142#L807-1true [2021-08-27 16:30:32,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,386 INFO L82 PathProgramCache]: Analyzing trace with hash -2002818045, now seen corresponding path program 1 times [2021-08-27 16:30:32,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,391 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054999059] [2021-08-27 16:30:32,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,392 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,488 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054999059] [2021-08-27 16:30:32,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054999059] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,489 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,490 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820067004] [2021-08-27 16:30:32,493 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:32,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,494 INFO L82 PathProgramCache]: Analyzing trace with hash 1157176394, now seen corresponding path program 1 times [2021-08-27 16:30:32,494 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,494 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291142952] [2021-08-27 16:30:32,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,494 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291142952] [2021-08-27 16:30:32,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291142952] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,509 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:32,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9003672] [2021-08-27 16:30:32,511 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:32,511 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:32,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:32,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:32,536 INFO L87 Difference]: Start difference. First operand has 419 states, 418 states have (on average 1.5598086124401913) internal successors, (652), 418 states have internal predecessors, (652), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:32,564 INFO L93 Difference]: Finished difference Result 419 states and 635 transitions. [2021-08-27 16:30:32,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:32,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 635 transitions. [2021-08-27 16:30:32,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 413 states and 629 transitions. [2021-08-27 16:30:32,578 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-08-27 16:30:32,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-08-27 16:30:32,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 629 transitions. [2021-08-27 16:30:32,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:32,582 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2021-08-27 16:30:32,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 629 transitions. [2021-08-27 16:30:32,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-08-27 16:30:32,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.523002421307506) internal successors, (629), 412 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 629 transitions. [2021-08-27 16:30:32,612 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2021-08-27 16:30:32,612 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 629 transitions. [2021-08-27 16:30:32,612 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-08-27 16:30:32,612 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 629 transitions. [2021-08-27 16:30:32,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,616 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,616 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,616 INFO L791 eck$LassoCheckResult]: Stem: 1259#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1249#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1250#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1002#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 1003#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1066#L362-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1067#L367-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1137#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1234#L377-1 assume !(0 == ~M_E~0); 1070#L518-1 assume !(0 == ~T1_E~0); 1071#L523-1 assume !(0 == ~T2_E~0); 1190#L528-1 assume !(0 == ~T3_E~0); 1191#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1095#L538-1 assume !(0 == ~E_M~0); 987#L543-1 assume !(0 == ~E_1~0); 988#L548-1 assume !(0 == ~E_2~0); 1256#L553-1 assume !(0 == ~E_3~0); 1217#L558-1 assume !(0 == ~E_4~0); 1218#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1192#L254 assume 1 == ~m_pc~0; 1177#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 879#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1170#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1076#L641 assume !(0 != activate_threads_~tmp~1); 1077#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1140#L273 assume !(1 == ~t1_pc~0); 981#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 935#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 936#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1150#L649 assume !(0 != activate_threads_~tmp___0~0); 1251#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 983#L292 assume 1 == ~t2_pc~0; 984#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1080#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1161#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1037#L657 assume !(0 != activate_threads_~tmp___1~0); 1038#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1188#L311 assume !(1 == ~t3_pc~0); 1033#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 1032#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 849#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 850#L665 assume !(0 != activate_threads_~tmp___2~0); 899#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 900#L330 assume 1 == ~t4_pc~0; 1053#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 986#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 887#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 888#L673 assume !(0 != activate_threads_~tmp___3~0); 880#L673-2 assume !(1 == ~M_E~0); 881#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1057#L581-1 assume !(1 == ~T2_E~0); 1072#L586-1 assume !(1 == ~T3_E~0); 1152#L591-1 assume !(1 == ~T4_E~0); 1124#L596-1 assume !(1 == ~E_M~0); 1125#L601-1 assume !(1 == ~E_1~0); 1164#L606-1 assume !(1 == ~E_2~0); 1165#L611-1 assume !(1 == ~E_3~0); 1211#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1089#L807-1 [2021-08-27 16:30:32,617 INFO L793 eck$LassoCheckResult]: Loop: 1089#L807-1 assume !false; 1090#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1112#L493 assume !false; 1236#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1128#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 901#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 866#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 867#L432 assume !(0 != eval_~tmp~0); 882#L508 start_simulation_~kernel_st~0 := 2; 883#L350-1 start_simulation_~kernel_st~0 := 3; 1222#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1223#L518-4 assume !(0 == ~T1_E~0); 1185#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1186#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1206#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 847#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 848#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 906#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 907#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1203#L558-3 assume !(0 == ~E_4~0); 1245#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1242#L254-18 assume !(1 == ~m_pc~0); 929#L254-20 is_master_triggered_~__retres1~0 := 0; 930#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1055#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1056#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 962#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 963#L273-18 assume 1 == ~t1_pc~0; 972#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 973#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1069#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1239#L649-18 assume !(0 != activate_threads_~tmp___0~0); 874#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 875#L292-18 assume 1 == ~t2_pc~0; 1026#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 854#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 855#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1126#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1200#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1201#L311-18 assume 1 == ~t3_pc~0; 939#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 864#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 865#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 999#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1180#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1207#L330-18 assume 1 == ~t4_pc~0; 1041#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1042#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1062#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1063#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1141#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1105#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1106#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1111#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1135#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1011#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1012#L601-3 assume !(1 == ~E_1~0); 1147#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1173#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1174#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 908#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 909#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1024#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1233#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1189#L826 assume !(0 == start_simulation_~tmp~3); 915#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 916#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1107#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1108#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 996#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 997#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 1039#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1181#L839 assume !(0 != start_simulation_~tmp___0~1); 1089#L807-1 [2021-08-27 16:30:32,617 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,617 INFO L82 PathProgramCache]: Analyzing trace with hash 905363841, now seen corresponding path program 1 times [2021-08-27 16:30:32,617 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,618 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466810587] [2021-08-27 16:30:32,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,618 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466810587] [2021-08-27 16:30:32,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466810587] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,647 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662957779] [2021-08-27 16:30:32,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:32,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,648 INFO L82 PathProgramCache]: Analyzing trace with hash -1890230681, now seen corresponding path program 1 times [2021-08-27 16:30:32,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,649 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638203271] [2021-08-27 16:30:32,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,649 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,701 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,702 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638203271] [2021-08-27 16:30:32,702 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638203271] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,702 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,703 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,703 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213936475] [2021-08-27 16:30:32,703 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:32,704 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:32,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:32,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:32,706 INFO L87 Difference]: Start difference. First operand 413 states and 629 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:32,721 INFO L93 Difference]: Finished difference Result 413 states and 628 transitions. [2021-08-27 16:30:32,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:32,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 628 transitions. [2021-08-27 16:30:32,725 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,728 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 628 transitions. [2021-08-27 16:30:32,728 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-08-27 16:30:32,729 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-08-27 16:30:32,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 628 transitions. [2021-08-27 16:30:32,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:32,734 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2021-08-27 16:30:32,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 628 transitions. [2021-08-27 16:30:32,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-08-27 16:30:32,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.5205811138014529) internal successors, (628), 412 states have internal predecessors, (628), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 628 transitions. [2021-08-27 16:30:32,744 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2021-08-27 16:30:32,744 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 628 transitions. [2021-08-27 16:30:32,744 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-08-27 16:30:32,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 628 transitions. [2021-08-27 16:30:32,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,758 INFO L791 eck$LassoCheckResult]: Stem: 2092#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2082#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2083#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1835#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 1836#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1899#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1900#L367-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1970#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2067#L377-1 assume !(0 == ~M_E~0); 1903#L518-1 assume !(0 == ~T1_E~0); 1904#L523-1 assume !(0 == ~T2_E~0); 2023#L528-1 assume !(0 == ~T3_E~0); 2024#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1928#L538-1 assume !(0 == ~E_M~0); 1820#L543-1 assume !(0 == ~E_1~0); 1821#L548-1 assume !(0 == ~E_2~0); 2089#L553-1 assume !(0 == ~E_3~0); 2050#L558-1 assume !(0 == ~E_4~0); 2051#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2025#L254 assume 1 == ~m_pc~0; 2010#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1712#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2003#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1909#L641 assume !(0 != activate_threads_~tmp~1); 1910#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1973#L273 assume !(1 == ~t1_pc~0); 1814#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 1768#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1769#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1983#L649 assume !(0 != activate_threads_~tmp___0~0); 2084#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1816#L292 assume 1 == ~t2_pc~0; 1817#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1913#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1994#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1870#L657 assume !(0 != activate_threads_~tmp___1~0); 1871#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2021#L311 assume !(1 == ~t3_pc~0); 1866#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 1865#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1682#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1683#L665 assume !(0 != activate_threads_~tmp___2~0); 1732#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1733#L330 assume 1 == ~t4_pc~0; 1886#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1819#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1720#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1721#L673 assume !(0 != activate_threads_~tmp___3~0); 1713#L673-2 assume !(1 == ~M_E~0); 1714#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1890#L581-1 assume !(1 == ~T2_E~0); 1905#L586-1 assume !(1 == ~T3_E~0); 1985#L591-1 assume !(1 == ~T4_E~0); 1957#L596-1 assume !(1 == ~E_M~0); 1958#L601-1 assume !(1 == ~E_1~0); 1997#L606-1 assume !(1 == ~E_2~0); 1998#L611-1 assume !(1 == ~E_3~0); 2044#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1922#L807-1 [2021-08-27 16:30:32,759 INFO L793 eck$LassoCheckResult]: Loop: 1922#L807-1 assume !false; 1923#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1945#L493 assume !false; 2069#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1961#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1734#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1699#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1700#L432 assume !(0 != eval_~tmp~0); 1715#L508 start_simulation_~kernel_st~0 := 2; 1716#L350-1 start_simulation_~kernel_st~0 := 3; 2055#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2056#L518-4 assume !(0 == ~T1_E~0); 2018#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2019#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2039#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1680#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1681#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1739#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1740#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2036#L558-3 assume !(0 == ~E_4~0); 2078#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2075#L254-18 assume !(1 == ~m_pc~0); 1762#L254-20 is_master_triggered_~__retres1~0 := 0; 1763#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1888#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1889#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1795#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1796#L273-18 assume 1 == ~t1_pc~0; 1805#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1806#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1902#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2072#L649-18 assume !(0 != activate_threads_~tmp___0~0); 1707#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1708#L292-18 assume 1 == ~t2_pc~0; 1859#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1687#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1688#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1959#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2033#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2034#L311-18 assume 1 == ~t3_pc~0; 1772#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1697#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1698#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1832#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2013#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2040#L330-18 assume 1 == ~t4_pc~0; 1874#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1875#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1895#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1896#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1974#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 1938#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1939#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1944#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1968#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1844#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1845#L601-3 assume !(1 == ~E_1~0); 1980#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2006#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2007#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1741#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1742#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1857#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2066#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2022#L826 assume !(0 == start_simulation_~tmp~3); 1748#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1749#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1940#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1941#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 1829#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1830#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 1872#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2014#L839 assume !(0 != start_simulation_~tmp___0~1); 1922#L807-1 [2021-08-27 16:30:32,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,759 INFO L82 PathProgramCache]: Analyzing trace with hash 461463167, now seen corresponding path program 1 times [2021-08-27 16:30:32,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [606781443] [2021-08-27 16:30:32,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,760 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,784 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,784 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [606781443] [2021-08-27 16:30:32,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [606781443] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,784 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79385016] [2021-08-27 16:30:32,785 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:32,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,785 INFO L82 PathProgramCache]: Analyzing trace with hash -1890230681, now seen corresponding path program 2 times [2021-08-27 16:30:32,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,786 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658622831] [2021-08-27 16:30:32,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,786 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,815 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,815 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658622831] [2021-08-27 16:30:32,816 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658622831] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,816 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,816 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [303220043] [2021-08-27 16:30:32,816 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:32,816 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:32,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:32,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:32,817 INFO L87 Difference]: Start difference. First operand 413 states and 628 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:32,824 INFO L93 Difference]: Finished difference Result 413 states and 627 transitions. [2021-08-27 16:30:32,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:32,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 627 transitions. [2021-08-27 16:30:32,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 627 transitions. [2021-08-27 16:30:32,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-08-27 16:30:32,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-08-27 16:30:32,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 627 transitions. [2021-08-27 16:30:32,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:32,829 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2021-08-27 16:30:32,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 627 transitions. [2021-08-27 16:30:32,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-08-27 16:30:32,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.5181598062953996) internal successors, (627), 412 states have internal predecessors, (627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 627 transitions. [2021-08-27 16:30:32,837 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2021-08-27 16:30:32,837 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 627 transitions. [2021-08-27 16:30:32,837 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-08-27 16:30:32,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 627 transitions. [2021-08-27 16:30:32,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,840 INFO L791 eck$LassoCheckResult]: Stem: 2925#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2915#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2916#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2668#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 2669#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2732#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2733#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2803#L372-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2900#L377-1 assume !(0 == ~M_E~0); 2736#L518-1 assume !(0 == ~T1_E~0); 2737#L523-1 assume !(0 == ~T2_E~0); 2856#L528-1 assume !(0 == ~T3_E~0); 2857#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2761#L538-1 assume !(0 == ~E_M~0); 2653#L543-1 assume !(0 == ~E_1~0); 2654#L548-1 assume !(0 == ~E_2~0); 2922#L553-1 assume !(0 == ~E_3~0); 2883#L558-1 assume !(0 == ~E_4~0); 2884#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2858#L254 assume 1 == ~m_pc~0; 2843#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2545#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2836#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2742#L641 assume !(0 != activate_threads_~tmp~1); 2743#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2806#L273 assume !(1 == ~t1_pc~0); 2647#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 2601#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2602#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2816#L649 assume !(0 != activate_threads_~tmp___0~0); 2917#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2649#L292 assume 1 == ~t2_pc~0; 2650#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2746#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2827#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2703#L657 assume !(0 != activate_threads_~tmp___1~0); 2704#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2854#L311 assume !(1 == ~t3_pc~0); 2699#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 2698#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2515#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2516#L665 assume !(0 != activate_threads_~tmp___2~0); 2565#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2566#L330 assume 1 == ~t4_pc~0; 2719#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2652#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2553#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2554#L673 assume !(0 != activate_threads_~tmp___3~0); 2546#L673-2 assume !(1 == ~M_E~0); 2547#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2723#L581-1 assume !(1 == ~T2_E~0); 2738#L586-1 assume !(1 == ~T3_E~0); 2818#L591-1 assume !(1 == ~T4_E~0); 2790#L596-1 assume !(1 == ~E_M~0); 2791#L601-1 assume !(1 == ~E_1~0); 2830#L606-1 assume !(1 == ~E_2~0); 2831#L611-1 assume !(1 == ~E_3~0); 2877#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2755#L807-1 [2021-08-27 16:30:32,840 INFO L793 eck$LassoCheckResult]: Loop: 2755#L807-1 assume !false; 2756#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2778#L493 assume !false; 2902#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2794#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2567#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2532#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2533#L432 assume !(0 != eval_~tmp~0); 2548#L508 start_simulation_~kernel_st~0 := 2; 2549#L350-1 start_simulation_~kernel_st~0 := 3; 2888#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2889#L518-4 assume !(0 == ~T1_E~0); 2851#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2852#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2872#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2513#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2514#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2572#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2573#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2869#L558-3 assume !(0 == ~E_4~0); 2911#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2908#L254-18 assume !(1 == ~m_pc~0); 2595#L254-20 is_master_triggered_~__retres1~0 := 0; 2596#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2721#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2722#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2628#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2629#L273-18 assume !(1 == ~t1_pc~0); 2640#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 2639#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2735#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2905#L649-18 assume !(0 != activate_threads_~tmp___0~0); 2540#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2541#L292-18 assume 1 == ~t2_pc~0; 2692#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2520#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2521#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2792#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2866#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2867#L311-18 assume 1 == ~t3_pc~0; 2605#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2530#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2531#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2665#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2846#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2873#L330-18 assume 1 == ~t4_pc~0; 2707#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2708#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2728#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2729#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2807#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 2771#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2772#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2777#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2801#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2677#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2678#L601-3 assume !(1 == ~E_1~0); 2813#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2839#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2840#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2574#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2575#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2690#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2899#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2855#L826 assume !(0 == start_simulation_~tmp~3); 2581#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2582#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2773#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2774#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 2662#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2663#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 2705#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2847#L839 assume !(0 != start_simulation_~tmp___0~1); 2755#L807-1 [2021-08-27 16:30:32,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1076876863, now seen corresponding path program 1 times [2021-08-27 16:30:32,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [916311836] [2021-08-27 16:30:32,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,841 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,860 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,861 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [916311836] [2021-08-27 16:30:32,861 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [916311836] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,861 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,861 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,861 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636348889] [2021-08-27 16:30:32,861 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:32,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1096731846, now seen corresponding path program 1 times [2021-08-27 16:30:32,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,862 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390848460] [2021-08-27 16:30:32,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,863 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,904 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,904 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [390848460] [2021-08-27 16:30:32,904 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [390848460] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,905 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,905 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,905 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560433111] [2021-08-27 16:30:32,905 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:32,905 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:32,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:32,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:32,906 INFO L87 Difference]: Start difference. First operand 413 states and 627 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:32,913 INFO L93 Difference]: Finished difference Result 413 states and 626 transitions. [2021-08-27 16:30:32,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:32,914 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 626 transitions. [2021-08-27 16:30:32,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 626 transitions. [2021-08-27 16:30:32,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-08-27 16:30:32,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-08-27 16:30:32,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 626 transitions. [2021-08-27 16:30:32,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:32,919 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2021-08-27 16:30:32,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 626 transitions. [2021-08-27 16:30:32,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-08-27 16:30:32,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.5157384987893463) internal successors, (626), 412 states have internal predecessors, (626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:32,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 626 transitions. [2021-08-27 16:30:32,925 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2021-08-27 16:30:32,925 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 626 transitions. [2021-08-27 16:30:32,926 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-08-27 16:30:32,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 626 transitions. [2021-08-27 16:30:32,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:32,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:32,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:32,928 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,928 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:32,929 INFO L791 eck$LassoCheckResult]: Stem: 3758#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3748#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3749#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3501#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 3502#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3565#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3566#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3637#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3733#L377-1 assume !(0 == ~M_E~0); 3569#L518-1 assume !(0 == ~T1_E~0); 3570#L523-1 assume !(0 == ~T2_E~0); 3689#L528-1 assume !(0 == ~T3_E~0); 3690#L533-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3594#L538-1 assume !(0 == ~E_M~0); 3486#L543-1 assume !(0 == ~E_1~0); 3487#L548-1 assume !(0 == ~E_2~0); 3755#L553-1 assume !(0 == ~E_3~0); 3716#L558-1 assume !(0 == ~E_4~0); 3717#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3691#L254 assume 1 == ~m_pc~0; 3676#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3378#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3669#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3575#L641 assume !(0 != activate_threads_~tmp~1); 3576#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3639#L273 assume !(1 == ~t1_pc~0); 3481#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 3434#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3435#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3649#L649 assume !(0 != activate_threads_~tmp___0~0); 3750#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3482#L292 assume 1 == ~t2_pc~0; 3483#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3579#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3660#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3537#L657 assume !(0 != activate_threads_~tmp___1~0); 3538#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3688#L311 assume !(1 == ~t3_pc~0); 3532#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 3531#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3348#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3349#L665 assume !(0 != activate_threads_~tmp___2~0); 3398#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3399#L330 assume 1 == ~t4_pc~0; 3552#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3485#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3386#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3387#L673 assume !(0 != activate_threads_~tmp___3~0); 3379#L673-2 assume !(1 == ~M_E~0); 3380#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3556#L581-1 assume !(1 == ~T2_E~0); 3571#L586-1 assume !(1 == ~T3_E~0); 3651#L591-1 assume !(1 == ~T4_E~0); 3623#L596-1 assume !(1 == ~E_M~0); 3624#L601-1 assume !(1 == ~E_1~0); 3663#L606-1 assume !(1 == ~E_2~0); 3664#L611-1 assume !(1 == ~E_3~0); 3712#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3588#L807-1 [2021-08-27 16:30:32,929 INFO L793 eck$LassoCheckResult]: Loop: 3588#L807-1 assume !false; 3589#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3612#L493 assume !false; 3735#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3627#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3400#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3365#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3366#L432 assume !(0 != eval_~tmp~0); 3381#L508 start_simulation_~kernel_st~0 := 2; 3382#L350-1 start_simulation_~kernel_st~0 := 3; 3721#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3722#L518-4 assume !(0 == ~T1_E~0); 3684#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3685#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3706#L533-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3346#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3347#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3405#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3406#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3702#L558-3 assume !(0 == ~E_4~0); 3744#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3741#L254-18 assume !(1 == ~m_pc~0); 3428#L254-20 is_master_triggered_~__retres1~0 := 0; 3429#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3554#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3555#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3461#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3462#L273-18 assume 1 == ~t1_pc~0; 3469#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3470#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3568#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3738#L649-18 assume !(0 != activate_threads_~tmp___0~0); 3373#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3374#L292-18 assume 1 == ~t2_pc~0; 3525#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3353#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3354#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3625#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3699#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3700#L311-18 assume 1 == ~t3_pc~0; 3438#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3363#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3364#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3498#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3679#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3705#L330-18 assume 1 == ~t4_pc~0; 3540#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3541#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3560#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3561#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3640#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 3604#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3605#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3610#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3634#L591-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3510#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3511#L601-3 assume !(1 == ~E_1~0); 3644#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3672#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3673#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3407#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3408#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3523#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3732#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 3687#L826 assume !(0 == start_simulation_~tmp~3); 3414#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3415#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3606#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3607#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 3495#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3496#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 3536#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3680#L839 assume !(0 != start_simulation_~tmp___0~1); 3588#L807-1 [2021-08-27 16:30:32,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,929 INFO L82 PathProgramCache]: Analyzing trace with hash 951709247, now seen corresponding path program 1 times [2021-08-27 16:30:32,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,930 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289936239] [2021-08-27 16:30:32,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,930 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,952 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,952 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289936239] [2021-08-27 16:30:32,952 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289936239] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,952 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:32,953 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682025032] [2021-08-27 16:30:32,953 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:32,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:32,953 INFO L82 PathProgramCache]: Analyzing trace with hash -1890230681, now seen corresponding path program 3 times [2021-08-27 16:30:32,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:32,954 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052980486] [2021-08-27 16:30:32,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:32,954 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:32,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:32,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:32,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:32,986 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052980486] [2021-08-27 16:30:32,986 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052980486] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:32,986 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:32,986 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:32,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278247366] [2021-08-27 16:30:32,987 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:32,987 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:32,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:32,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:32,987 INFO L87 Difference]: Start difference. First operand 413 states and 626 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,001 INFO L93 Difference]: Finished difference Result 413 states and 621 transitions. [2021-08-27 16:30:33,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 621 transitions. [2021-08-27 16:30:33,005 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:33,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 621 transitions. [2021-08-27 16:30:33,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2021-08-27 16:30:33,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2021-08-27 16:30:33,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 621 transitions. [2021-08-27 16:30:33,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,009 INFO L681 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2021-08-27 16:30:33,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 621 transitions. [2021-08-27 16:30:33,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 413. [2021-08-27 16:30:33,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 413 states, 413 states have (on average 1.5036319612590798) internal successors, (621), 412 states have internal predecessors, (621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413 states to 413 states and 621 transitions. [2021-08-27 16:30:33,014 INFO L704 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2021-08-27 16:30:33,015 INFO L587 BuchiCegarLoop]: Abstraction has 413 states and 621 transitions. [2021-08-27 16:30:33,015 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-08-27 16:30:33,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413 states and 621 transitions. [2021-08-27 16:30:33,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 350 [2021-08-27 16:30:33,017 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,017 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,019 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,019 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,019 INFO L791 eck$LassoCheckResult]: Stem: 4591#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4581#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4582#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4334#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 4335#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4398#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4399#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4469#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4566#L377-1 assume !(0 == ~M_E~0); 4402#L518-1 assume !(0 == ~T1_E~0); 4403#L523-1 assume !(0 == ~T2_E~0); 4522#L528-1 assume !(0 == ~T3_E~0); 4523#L533-1 assume !(0 == ~T4_E~0); 4427#L538-1 assume !(0 == ~E_M~0); 4319#L543-1 assume !(0 == ~E_1~0); 4320#L548-1 assume !(0 == ~E_2~0); 4588#L553-1 assume !(0 == ~E_3~0); 4549#L558-1 assume !(0 == ~E_4~0); 4550#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4524#L254 assume 1 == ~m_pc~0; 4509#L255 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4211#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4502#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4408#L641 assume !(0 != activate_threads_~tmp~1); 4409#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4472#L273 assume !(1 == ~t1_pc~0); 4313#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 4267#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4268#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4482#L649 assume !(0 != activate_threads_~tmp___0~0); 4583#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4315#L292 assume 1 == ~t2_pc~0; 4316#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4412#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4493#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4370#L657 assume !(0 != activate_threads_~tmp___1~0); 4371#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4521#L311 assume !(1 == ~t3_pc~0); 4365#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 4364#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4181#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4182#L665 assume !(0 != activate_threads_~tmp___2~0); 4231#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4232#L330 assume 1 == ~t4_pc~0; 4385#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4318#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4219#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4220#L673 assume !(0 != activate_threads_~tmp___3~0); 4212#L673-2 assume !(1 == ~M_E~0); 4213#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4389#L581-1 assume !(1 == ~T2_E~0); 4404#L586-1 assume !(1 == ~T3_E~0); 4484#L591-1 assume !(1 == ~T4_E~0); 4456#L596-1 assume !(1 == ~E_M~0); 4457#L601-1 assume !(1 == ~E_1~0); 4496#L606-1 assume !(1 == ~E_2~0); 4497#L611-1 assume !(1 == ~E_3~0); 4543#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4421#L807-1 [2021-08-27 16:30:33,020 INFO L793 eck$LassoCheckResult]: Loop: 4421#L807-1 assume !false; 4422#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4444#L493 assume !false; 4568#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4460#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4233#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4198#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4199#L432 assume !(0 != eval_~tmp~0); 4214#L508 start_simulation_~kernel_st~0 := 2; 4215#L350-1 start_simulation_~kernel_st~0 := 3; 4554#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4555#L518-4 assume !(0 == ~T1_E~0); 4517#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4518#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4539#L533-3 assume !(0 == ~T4_E~0); 4179#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4180#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4238#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4239#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4535#L558-3 assume !(0 == ~E_4~0); 4577#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4574#L254-18 assume !(1 == ~m_pc~0); 4261#L254-20 is_master_triggered_~__retres1~0 := 0; 4262#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4387#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4388#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4294#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4295#L273-18 assume 1 == ~t1_pc~0; 4304#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4305#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4401#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4571#L649-18 assume !(0 != activate_threads_~tmp___0~0); 4206#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4207#L292-18 assume 1 == ~t2_pc~0; 4358#L293-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4186#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4187#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4458#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4532#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4533#L311-18 assume 1 == ~t3_pc~0; 4273#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4196#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4197#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4331#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4513#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4538#L330-18 assume 1 == ~t4_pc~0; 4372#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4373#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4393#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4394#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4473#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 4435#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4436#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4443#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4467#L591-3 assume !(1 == ~T4_E~0); 4343#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4344#L601-3 assume !(1 == ~E_1~0); 4477#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4505#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4506#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4240#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4241#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4356#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4565#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4520#L826 assume !(0 == start_simulation_~tmp~3); 4247#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4248#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4439#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4440#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 4328#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4329#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 4369#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4512#L839 assume !(0 != start_simulation_~tmp___0~1); 4421#L807-1 [2021-08-27 16:30:33,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1414985347, now seen corresponding path program 1 times [2021-08-27 16:30:33,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,021 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979796511] [2021-08-27 16:30:33,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,022 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,067 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979796511] [2021-08-27 16:30:33,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979796511] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,068 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:33,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1746955638] [2021-08-27 16:30:33,069 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,069 INFO L82 PathProgramCache]: Analyzing trace with hash 1276492651, now seen corresponding path program 1 times [2021-08-27 16:30:33,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,070 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173887869] [2021-08-27 16:30:33,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,071 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,111 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173887869] [2021-08-27 16:30:33,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173887869] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,112 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,112 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332446006] [2021-08-27 16:30:33,113 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,113 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,115 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,115 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,116 INFO L87 Difference]: Start difference. First operand 413 states and 621 transitions. cyclomatic complexity: 209 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,159 INFO L93 Difference]: Finished difference Result 748 states and 1108 transitions. [2021-08-27 16:30:33,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,159 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 748 states and 1108 transitions. [2021-08-27 16:30:33,163 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 685 [2021-08-27 16:30:33,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 748 states to 748 states and 1108 transitions. [2021-08-27 16:30:33,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 748 [2021-08-27 16:30:33,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 748 [2021-08-27 16:30:33,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 748 states and 1108 transitions. [2021-08-27 16:30:33,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,174 INFO L681 BuchiCegarLoop]: Abstraction has 748 states and 1108 transitions. [2021-08-27 16:30:33,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 748 states and 1108 transitions. [2021-08-27 16:30:33,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 748 to 715. [2021-08-27 16:30:33,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 715 states, 715 states have (on average 1.4853146853146852) internal successors, (1062), 714 states have internal predecessors, (1062), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 715 states to 715 states and 1062 transitions. [2021-08-27 16:30:33,183 INFO L704 BuchiCegarLoop]: Abstraction has 715 states and 1062 transitions. [2021-08-27 16:30:33,183 INFO L587 BuchiCegarLoop]: Abstraction has 715 states and 1062 transitions. [2021-08-27 16:30:33,183 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-08-27 16:30:33,183 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 715 states and 1062 transitions. [2021-08-27 16:30:33,185 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2021-08-27 16:30:33,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,186 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,186 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,186 INFO L791 eck$LassoCheckResult]: Stem: 5782#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5765#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5766#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5502#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 5503#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5573#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5574#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5643#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5747#L377-1 assume !(0 == ~M_E~0); 5577#L518-1 assume !(0 == ~T1_E~0); 5578#L523-1 assume !(0 == ~T2_E~0); 5698#L528-1 assume !(0 == ~T3_E~0); 5699#L533-1 assume !(0 == ~T4_E~0); 5602#L538-1 assume !(0 == ~E_M~0); 5486#L543-1 assume !(0 == ~E_1~0); 5487#L548-1 assume !(0 == ~E_2~0); 5774#L553-1 assume !(0 == ~E_3~0); 5726#L558-1 assume !(0 == ~E_4~0); 5727#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5700#L254 assume !(1 == ~m_pc~0); 5378#L254-2 is_master_triggered_~__retres1~0 := 0; 5379#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5677#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5583#L641 assume !(0 != activate_threads_~tmp~1); 5584#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5645#L273 assume !(1 == ~t1_pc~0); 5481#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 5435#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5436#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5657#L649 assume !(0 != activate_threads_~tmp___0~0); 5768#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5482#L292 assume 1 == ~t2_pc~0; 5483#L293 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5587#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5668#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5541#L657 assume !(0 != activate_threads_~tmp___1~0); 5542#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5697#L311 assume !(1 == ~t3_pc~0); 5535#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 5534#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5349#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5350#L665 assume !(0 != activate_threads_~tmp___2~0); 5399#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5400#L330 assume 1 == ~t4_pc~0; 5560#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5485#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5387#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5388#L673 assume !(0 != activate_threads_~tmp___3~0); 5380#L673-2 assume !(1 == ~M_E~0); 5381#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5564#L581-1 assume !(1 == ~T2_E~0); 5579#L586-1 assume !(1 == ~T3_E~0); 5659#L591-1 assume !(1 == ~T4_E~0); 5630#L596-1 assume !(1 == ~E_M~0); 5631#L601-1 assume !(1 == ~E_1~0); 5671#L606-1 assume !(1 == ~E_2~0); 5672#L611-1 assume !(1 == ~E_3~0); 5722#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5596#L807-1 [2021-08-27 16:30:33,187 INFO L793 eck$LassoCheckResult]: Loop: 5596#L807-1 assume !false; 5597#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5620#L493 assume !false; 5750#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5634#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5401#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5366#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5367#L432 assume !(0 != eval_~tmp~0); 5382#L508 start_simulation_~kernel_st~0 := 2; 5383#L350-1 start_simulation_~kernel_st~0 := 3; 5731#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5732#L518-4 assume !(0 == ~T1_E~0); 5693#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5694#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5715#L533-3 assume !(0 == ~T4_E~0); 5347#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5348#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5406#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5407#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5711#L558-3 assume !(0 == ~E_4~0); 5760#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5756#L254-18 assume !(1 == ~m_pc~0); 5429#L254-20 is_master_triggered_~__retres1~0 := 0; 5430#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5562#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5563#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5461#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5462#L273-18 assume 1 == ~t1_pc~0; 5469#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5470#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5576#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5753#L649-18 assume !(0 != activate_threads_~tmp___0~0); 5374#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5375#L292-18 assume !(1 == ~t2_pc~0); 5463#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 5354#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5355#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5632#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5707#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5708#L311-18 assume 1 == ~t3_pc~0; 5441#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5364#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5365#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5498#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5689#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5714#L330-18 assume 1 == ~t4_pc~0; 5543#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5544#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5568#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5569#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5646#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 5611#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5612#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5618#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5640#L591-3 assume !(1 == ~T4_E~0); 5511#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5512#L601-3 assume !(1 == ~E_1~0); 5650#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5680#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5681#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5410#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5411#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5527#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5746#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 5696#L826 assume !(0 == start_simulation_~tmp~3); 5415#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5416#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5614#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5615#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 5748#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5539#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 5540#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5688#L839 assume !(0 != start_simulation_~tmp___0~1); 5596#L807-1 [2021-08-27 16:30:33,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,187 INFO L82 PathProgramCache]: Analyzing trace with hash 1923053566, now seen corresponding path program 1 times [2021-08-27 16:30:33,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1062290121] [2021-08-27 16:30:33,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,188 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,209 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,210 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1062290121] [2021-08-27 16:30:33,210 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1062290121] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,210 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,210 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891711669] [2021-08-27 16:30:33,210 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,211 INFO L82 PathProgramCache]: Analyzing trace with hash 1676483850, now seen corresponding path program 1 times [2021-08-27 16:30:33,211 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,211 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30925583] [2021-08-27 16:30:33,211 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,211 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30925583] [2021-08-27 16:30:33,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30925583] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,227 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,227 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,227 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987171153] [2021-08-27 16:30:33,228 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,228 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-27 16:30:33,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-27 16:30:33,228 INFO L87 Difference]: Start difference. First operand 715 states and 1062 transitions. cyclomatic complexity: 349 Second operand has 4 states, 4 states have (on average 14.5) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,342 INFO L93 Difference]: Finished difference Result 1618 states and 2368 transitions. [2021-08-27 16:30:33,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-27 16:30:33,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1618 states and 2368 transitions. [2021-08-27 16:30:33,348 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1515 [2021-08-27 16:30:33,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1618 states to 1618 states and 2368 transitions. [2021-08-27 16:30:33,354 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1618 [2021-08-27 16:30:33,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1618 [2021-08-27 16:30:33,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1618 states and 2368 transitions. [2021-08-27 16:30:33,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,356 INFO L681 BuchiCegarLoop]: Abstraction has 1618 states and 2368 transitions. [2021-08-27 16:30:33,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1618 states and 2368 transitions. [2021-08-27 16:30:33,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1618 to 1281. [2021-08-27 16:30:33,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1281 states, 1281 states have (on average 1.4746291959406714) internal successors, (1889), 1280 states have internal predecessors, (1889), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1281 states to 1281 states and 1889 transitions. [2021-08-27 16:30:33,370 INFO L704 BuchiCegarLoop]: Abstraction has 1281 states and 1889 transitions. [2021-08-27 16:30:33,370 INFO L587 BuchiCegarLoop]: Abstraction has 1281 states and 1889 transitions. [2021-08-27 16:30:33,370 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-08-27 16:30:33,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1281 states and 1889 transitions. [2021-08-27 16:30:33,374 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1218 [2021-08-27 16:30:33,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,378 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,378 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,379 INFO L791 eck$LassoCheckResult]: Stem: 8138#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8121#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8122#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7842#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 7843#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7909#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7910#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7978#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8103#L377-1 assume !(0 == ~M_E~0); 7913#L518-1 assume !(0 == ~T1_E~0); 7914#L523-1 assume !(0 == ~T2_E~0); 8035#L528-1 assume !(0 == ~T3_E~0); 8036#L533-1 assume !(0 == ~T4_E~0); 7938#L538-1 assume !(0 == ~E_M~0); 7827#L543-1 assume !(0 == ~E_1~0); 7828#L548-1 assume !(0 == ~E_2~0); 8130#L553-1 assume !(0 == ~E_3~0); 8078#L558-1 assume !(0 == ~E_4~0); 8079#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8039#L254 assume !(1 == ~m_pc~0); 7721#L254-2 is_master_triggered_~__retres1~0 := 0; 7722#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8015#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7919#L641 assume !(0 != activate_threads_~tmp~1); 7920#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7981#L273 assume !(1 == ~t1_pc~0); 7822#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 7778#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7779#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7993#L649 assume !(0 != activate_threads_~tmp___0~0); 8123#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7824#L292 assume !(1 == ~t2_pc~0); 7825#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 7923#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8004#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7878#L657 assume !(0 != activate_threads_~tmp___1~0); 7879#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8033#L311 assume !(1 == ~t3_pc~0); 7874#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 7873#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7692#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7693#L665 assume !(0 != activate_threads_~tmp___2~0); 7742#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7743#L330 assume 1 == ~t4_pc~0; 7895#L331 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7826#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7730#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7731#L673 assume !(0 != activate_threads_~tmp___3~0); 7723#L673-2 assume !(1 == ~M_E~0); 7724#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7899#L581-1 assume !(1 == ~T2_E~0); 7915#L586-1 assume !(1 == ~T3_E~0); 7995#L591-1 assume !(1 == ~T4_E~0); 7966#L596-1 assume !(1 == ~E_M~0); 7967#L601-1 assume !(1 == ~E_1~0); 8009#L606-1 assume !(1 == ~E_2~0); 8010#L611-1 assume !(1 == ~E_3~0); 8066#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7932#L807-1 [2021-08-27 16:30:33,379 INFO L793 eck$LassoCheckResult]: Loop: 7932#L807-1 assume !false; 7933#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7955#L493 assume !false; 8105#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7970#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7744#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7709#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7710#L432 assume !(0 != eval_~tmp~0); 8129#L508 start_simulation_~kernel_st~0 := 2; 8923#L350-1 start_simulation_~kernel_st~0 := 3; 8921#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8919#L518-4 assume !(0 == ~T1_E~0); 8918#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8917#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8916#L533-3 assume !(0 == ~T4_E~0); 8915#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8914#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8913#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8912#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8911#L558-3 assume !(0 == ~E_4~0); 8910#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8909#L254-18 assume !(1 == ~m_pc~0); 8908#L254-20 is_master_triggered_~__retres1~0 := 0; 8907#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8906#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8905#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8904#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8903#L273-18 assume 1 == ~t1_pc~0; 8901#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8900#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8899#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8898#L649-18 assume !(0 != activate_threads_~tmp___0~0); 8897#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7867#L292-18 assume !(1 == ~t2_pc~0); 7806#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 7697#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7698#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7968#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8047#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8048#L311-18 assume 1 == ~t3_pc~0; 7782#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7707#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7708#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7839#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8026#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8061#L330-18 assume 1 == ~t4_pc~0; 7882#L331-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7883#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7904#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7905#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7982#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 7949#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7950#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7954#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7976#L591-3 assume !(1 == ~T4_E~0); 7851#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7852#L601-3 assume !(1 == ~E_1~0); 7988#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8018#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8019#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7751#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7752#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7865#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 8102#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 8034#L826 assume !(0 == start_simulation_~tmp~3); 7758#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7759#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7951#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7952#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 7836#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7837#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 7880#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 8027#L839 assume !(0 != start_simulation_~tmp___0~1); 7932#L807-1 [2021-08-27 16:30:33,379 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,380 INFO L82 PathProgramCache]: Analyzing trace with hash 250535935, now seen corresponding path program 1 times [2021-08-27 16:30:33,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920829208] [2021-08-27 16:30:33,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,381 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,398 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920829208] [2021-08-27 16:30:33,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920829208] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,399 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,399 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:33,399 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [644462882] [2021-08-27 16:30:33,399 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,399 INFO L82 PathProgramCache]: Analyzing trace with hash 1676483850, now seen corresponding path program 2 times [2021-08-27 16:30:33,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,400 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1166902490] [2021-08-27 16:30:33,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,400 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,424 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1166902490] [2021-08-27 16:30:33,428 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1166902490] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,428 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,428 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,428 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403295574] [2021-08-27 16:30:33,429 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,429 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,429 INFO L87 Difference]: Start difference. First operand 1281 states and 1889 transitions. cyclomatic complexity: 610 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,474 INFO L93 Difference]: Finished difference Result 2340 states and 3428 transitions. [2021-08-27 16:30:33,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,474 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2340 states and 3428 transitions. [2021-08-27 16:30:33,488 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2268 [2021-08-27 16:30:33,497 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2340 states to 2340 states and 3428 transitions. [2021-08-27 16:30:33,497 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2340 [2021-08-27 16:30:33,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2340 [2021-08-27 16:30:33,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2340 states and 3428 transitions. [2021-08-27 16:30:33,523 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,523 INFO L681 BuchiCegarLoop]: Abstraction has 2340 states and 3428 transitions. [2021-08-27 16:30:33,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2340 states and 3428 transitions. [2021-08-27 16:30:33,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2340 to 2332. [2021-08-27 16:30:33,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2332 states, 2332 states have (on average 1.4665523156089193) internal successors, (3420), 2331 states have internal predecessors, (3420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2332 states to 2332 states and 3420 transitions. [2021-08-27 16:30:33,546 INFO L704 BuchiCegarLoop]: Abstraction has 2332 states and 3420 transitions. [2021-08-27 16:30:33,546 INFO L587 BuchiCegarLoop]: Abstraction has 2332 states and 3420 transitions. [2021-08-27 16:30:33,546 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-08-27 16:30:33,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2332 states and 3420 transitions. [2021-08-27 16:30:33,554 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2021-08-27 16:30:33,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,555 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,555 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,555 INFO L791 eck$LassoCheckResult]: Stem: 11785#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 11761#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 11762#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11471#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 11472#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11538#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11539#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11616#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11742#L377-1 assume !(0 == ~M_E~0); 11542#L518-1 assume !(0 == ~T1_E~0); 11543#L523-1 assume !(0 == ~T2_E~0); 11677#L528-1 assume !(0 == ~T3_E~0); 11678#L533-1 assume !(0 == ~T4_E~0); 11568#L538-1 assume !(0 == ~E_M~0); 11455#L543-1 assume !(0 == ~E_1~0); 11456#L548-1 assume !(0 == ~E_2~0); 11778#L553-1 assume !(0 == ~E_3~0); 11715#L558-1 assume !(0 == ~E_4~0); 11716#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11679#L254 assume !(1 == ~m_pc~0); 11349#L254-2 is_master_triggered_~__retres1~0 := 0; 11350#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11654#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11549#L641 assume !(0 != activate_threads_~tmp~1); 11550#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11619#L273 assume !(1 == ~t1_pc~0); 11450#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 11406#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11407#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11629#L649 assume !(0 != activate_threads_~tmp___0~0); 11768#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11452#L292 assume !(1 == ~t2_pc~0); 11453#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 11553#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11641#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11508#L657 assume !(0 != activate_threads_~tmp___1~0); 11509#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11674#L311 assume !(1 == ~t3_pc~0); 11504#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 11503#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11320#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11321#L665 assume !(0 != activate_threads_~tmp___2~0); 11370#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11371#L330 assume !(1 == ~t4_pc~0); 11653#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 11454#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11358#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11359#L673 assume !(0 != activate_threads_~tmp___3~0); 11351#L673-2 assume !(1 == ~M_E~0); 11352#L576-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11527#L581-1 assume !(1 == ~T2_E~0); 11544#L586-1 assume !(1 == ~T3_E~0); 11631#L591-1 assume !(1 == ~T4_E~0); 11601#L596-1 assume !(1 == ~E_M~0); 11602#L601-1 assume !(1 == ~E_1~0); 11646#L606-1 assume !(1 == ~E_2~0); 11647#L611-1 assume !(1 == ~E_3~0); 11704#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11562#L807-1 [2021-08-27 16:30:33,555 INFO L793 eck$LassoCheckResult]: Loop: 11562#L807-1 assume !false; 11563#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11592#L493 assume !false; 11744#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11605#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11372#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11337#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 11338#L432 assume !(0 != eval_~tmp~0); 11777#L508 start_simulation_~kernel_st~0 := 2; 13621#L350-1 start_simulation_~kernel_st~0 := 3; 13620#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13619#L518-4 assume !(0 == ~T1_E~0); 13618#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13617#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13615#L533-3 assume !(0 == ~T4_E~0); 13613#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13611#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13607#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13606#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13605#L558-3 assume !(0 == ~E_4~0); 13601#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13599#L254-18 assume !(1 == ~m_pc~0); 13596#L254-20 is_master_triggered_~__retres1~0 := 0; 13593#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13591#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13590#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13589#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13586#L273-18 assume 1 == ~t1_pc~0; 13581#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13580#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13578#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13576#L649-18 assume !(0 != activate_threads_~tmp___0~0); 13571#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11495#L292-18 assume !(1 == ~t2_pc~0); 11434#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 11325#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11326#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11603#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11687#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11688#L311-18 assume 1 == ~t3_pc~0; 11410#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11335#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11336#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11468#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11666#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11700#L330-18 assume !(1 == ~t4_pc~0); 11692#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 11597#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11532#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11533#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11620#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 11579#L576-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11580#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11585#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11614#L591-3 assume !(1 == ~T4_E~0); 11479#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11480#L601-3 assume !(1 == ~E_1~0); 11626#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11657#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11658#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11379#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11380#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11493#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11741#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 11675#L826 assume !(0 == start_simulation_~tmp~3); 11386#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11387#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11581#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11582#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 11464#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11465#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 11510#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 11667#L839 assume !(0 != start_simulation_~tmp___0~1); 11562#L807-1 [2021-08-27 16:30:33,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,556 INFO L82 PathProgramCache]: Analyzing trace with hash -819887744, now seen corresponding path program 1 times [2021-08-27 16:30:33,556 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,556 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975496836] [2021-08-27 16:30:33,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,556 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,574 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,574 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975496836] [2021-08-27 16:30:33,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975496836] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,574 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:33,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420678414] [2021-08-27 16:30:33,575 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,575 INFO L82 PathProgramCache]: Analyzing trace with hash 1368044841, now seen corresponding path program 1 times [2021-08-27 16:30:33,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,575 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308272444] [2021-08-27 16:30:33,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,576 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,590 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308272444] [2021-08-27 16:30:33,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308272444] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,590 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,590 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617294625] [2021-08-27 16:30:33,591 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,592 INFO L87 Difference]: Start difference. First operand 2332 states and 3420 transitions. cyclomatic complexity: 1092 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,609 INFO L93 Difference]: Finished difference Result 2332 states and 3394 transitions. [2021-08-27 16:30:33,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,609 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2332 states and 3394 transitions. [2021-08-27 16:30:33,619 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2021-08-27 16:30:33,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2332 states to 2332 states and 3394 transitions. [2021-08-27 16:30:33,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2332 [2021-08-27 16:30:33,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2332 [2021-08-27 16:30:33,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2332 states and 3394 transitions. [2021-08-27 16:30:33,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,632 INFO L681 BuchiCegarLoop]: Abstraction has 2332 states and 3394 transitions. [2021-08-27 16:30:33,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2332 states and 3394 transitions. [2021-08-27 16:30:33,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2332 to 2332. [2021-08-27 16:30:33,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2332 states, 2332 states have (on average 1.4554030874785593) internal successors, (3394), 2331 states have internal predecessors, (3394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2332 states to 2332 states and 3394 transitions. [2021-08-27 16:30:33,681 INFO L704 BuchiCegarLoop]: Abstraction has 2332 states and 3394 transitions. [2021-08-27 16:30:33,682 INFO L587 BuchiCegarLoop]: Abstraction has 2332 states and 3394 transitions. [2021-08-27 16:30:33,682 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-08-27 16:30:33,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2332 states and 3394 transitions. [2021-08-27 16:30:33,689 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2021-08-27 16:30:33,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,690 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,690 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,691 INFO L791 eck$LassoCheckResult]: Stem: 16458#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16432#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16433#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16142#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 16143#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16211#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16212#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16286#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16412#L377-1 assume !(0 == ~M_E~0); 16215#L518-1 assume !(0 == ~T1_E~0); 16216#L523-1 assume !(0 == ~T2_E~0); 16346#L528-1 assume !(0 == ~T3_E~0); 16347#L533-1 assume !(0 == ~T4_E~0); 16240#L538-1 assume !(0 == ~E_M~0); 16126#L543-1 assume !(0 == ~E_1~0); 16127#L548-1 assume !(0 == ~E_2~0); 16448#L553-1 assume !(0 == ~E_3~0); 16385#L558-1 assume !(0 == ~E_4~0); 16386#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16349#L254 assume !(1 == ~m_pc~0); 16020#L254-2 is_master_triggered_~__retres1~0 := 0; 16021#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16326#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16221#L641 assume !(0 != activate_threads_~tmp~1); 16222#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16289#L273 assume !(1 == ~t1_pc~0); 16121#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 16077#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16078#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16301#L649 assume !(0 != activate_threads_~tmp___0~0); 16440#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16123#L292 assume !(1 == ~t2_pc~0); 16124#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 16225#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16312#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16179#L657 assume !(0 != activate_threads_~tmp___1~0); 16180#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16344#L311 assume !(1 == ~t3_pc~0); 16175#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 16174#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15991#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15992#L665 assume !(0 != activate_threads_~tmp___2~0); 16041#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16042#L330 assume !(1 == ~t4_pc~0); 16325#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 16125#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16029#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16030#L673 assume !(0 != activate_threads_~tmp___3~0); 16022#L673-2 assume !(1 == ~M_E~0); 16023#L576-1 assume !(1 == ~T1_E~0); 16202#L581-1 assume !(1 == ~T2_E~0); 16217#L586-1 assume !(1 == ~T3_E~0); 16303#L591-1 assume !(1 == ~T4_E~0); 16273#L596-1 assume !(1 == ~E_M~0); 16274#L601-1 assume !(1 == ~E_1~0); 16318#L606-1 assume !(1 == ~E_2~0); 16319#L611-1 assume !(1 == ~E_3~0); 16374#L616-1 assume 1 == ~E_4~0;~E_4~0 := 2; 16375#L807-1 [2021-08-27 16:30:33,691 INFO L793 eck$LassoCheckResult]: Loop: 16375#L807-1 assume !false; 17196#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 17112#L493 assume !false; 17193#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 17190#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 17185#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 17184#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 17182#L432 assume !(0 != eval_~tmp~0); 17183#L508 start_simulation_~kernel_st~0 := 2; 18292#L350-1 start_simulation_~kernel_st~0 := 3; 18290#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 18288#L518-4 assume !(0 == ~T1_E~0); 18287#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18286#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18237#L533-3 assume !(0 == ~T4_E~0); 18236#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18235#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16048#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16049#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16363#L558-3 assume !(0 == ~E_4~0); 16427#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16423#L254-18 assume !(1 == ~m_pc~0); 16071#L254-20 is_master_triggered_~__retres1~0 := 0; 16072#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16200#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16201#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16102#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16103#L273-18 assume !(1 == ~t1_pc~0); 16112#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 16111#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16214#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16438#L649-18 assume !(0 != activate_threads_~tmp___0~0); 16016#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16017#L292-18 assume !(1 == ~t2_pc~0); 16168#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 18092#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18090#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 18088#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18086#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18084#L311-18 assume !(1 == ~t3_pc~0); 18081#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 18078#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18076#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18074#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18072#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18070#L330-18 assume !(1 == ~t4_pc~0); 18068#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 18067#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18066#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 18065#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16290#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 16251#L576-3 assume !(1 == ~T1_E~0); 16252#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16258#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16284#L591-3 assume !(1 == ~T4_E~0); 16151#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16152#L601-3 assume !(1 == ~E_1~0); 16296#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16329#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16330#L616-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16050#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16051#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16165#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16411#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 16345#L826 assume !(0 == start_simulation_~tmp~3); 16057#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16058#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16254#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16255#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 16413#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17204#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 17201#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 17199#L839 assume !(0 != start_simulation_~tmp___0~1); 16375#L807-1 [2021-08-27 16:30:33,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,691 INFO L82 PathProgramCache]: Analyzing trace with hash -139829374, now seen corresponding path program 1 times [2021-08-27 16:30:33,691 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,692 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019419696] [2021-08-27 16:30:33,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,692 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,709 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,710 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019419696] [2021-08-27 16:30:33,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019419696] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,710 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,710 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2021-08-27 16:30:33,710 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758632180] [2021-08-27 16:30:33,710 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,711 INFO L82 PathProgramCache]: Analyzing trace with hash -1349755483, now seen corresponding path program 1 times [2021-08-27 16:30:33,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,711 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229484831] [2021-08-27 16:30:33,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,711 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,726 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,726 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,726 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229484831] [2021-08-27 16:30:33,726 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229484831] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,727 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [153285427] [2021-08-27 16:30:33,727 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,727 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,728 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,728 INFO L87 Difference]: Start difference. First operand 2332 states and 3394 transitions. cyclomatic complexity: 1066 Second operand has 3 states, 2 states have (on average 29.0) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,758 INFO L93 Difference]: Finished difference Result 2332 states and 3348 transitions. [2021-08-27 16:30:33,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2332 states and 3348 transitions. [2021-08-27 16:30:33,767 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2021-08-27 16:30:33,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2332 states to 2332 states and 3348 transitions. [2021-08-27 16:30:33,775 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2332 [2021-08-27 16:30:33,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2332 [2021-08-27 16:30:33,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2332 states and 3348 transitions. [2021-08-27 16:30:33,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,778 INFO L681 BuchiCegarLoop]: Abstraction has 2332 states and 3348 transitions. [2021-08-27 16:30:33,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2332 states and 3348 transitions. [2021-08-27 16:30:33,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2332 to 2332. [2021-08-27 16:30:33,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2332 states, 2332 states have (on average 1.4356775300171527) internal successors, (3348), 2331 states have internal predecessors, (3348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2332 states to 2332 states and 3348 transitions. [2021-08-27 16:30:33,802 INFO L704 BuchiCegarLoop]: Abstraction has 2332 states and 3348 transitions. [2021-08-27 16:30:33,802 INFO L587 BuchiCegarLoop]: Abstraction has 2332 states and 3348 transitions. [2021-08-27 16:30:33,802 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-08-27 16:30:33,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2332 states and 3348 transitions. [2021-08-27 16:30:33,808 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2260 [2021-08-27 16:30:33,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,809 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,809 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,809 INFO L791 eck$LassoCheckResult]: Stem: 21131#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 21109#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21110#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20814#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 20815#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20880#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20881#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20954#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21089#L377-1 assume !(0 == ~M_E~0); 20884#L518-1 assume !(0 == ~T1_E~0); 20885#L523-1 assume !(0 == ~T2_E~0); 21020#L528-1 assume !(0 == ~T3_E~0); 21021#L533-1 assume !(0 == ~T4_E~0); 20908#L538-1 assume !(0 == ~E_M~0); 20799#L543-1 assume !(0 == ~E_1~0); 20800#L548-1 assume !(0 == ~E_2~0); 21119#L553-1 assume !(0 == ~E_3~0); 21061#L558-1 assume !(0 == ~E_4~0); 21062#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21023#L254 assume !(1 == ~m_pc~0); 20691#L254-2 is_master_triggered_~__retres1~0 := 0; 20692#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20995#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20890#L641 assume !(0 != activate_threads_~tmp~1); 20891#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20959#L273 assume !(1 == ~t1_pc~0); 20794#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 20749#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20750#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20971#L649 assume !(0 != activate_threads_~tmp___0~0); 21113#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20796#L292 assume !(1 == ~t2_pc~0); 20797#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 20894#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20982#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20851#L657 assume !(0 != activate_threads_~tmp___1~0); 20852#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21017#L311 assume !(1 == ~t3_pc~0); 20846#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 20845#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20662#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20663#L665 assume !(0 != activate_threads_~tmp___2~0); 20712#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20713#L330 assume !(1 == ~t4_pc~0); 20994#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 20798#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20700#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20701#L673 assume !(0 != activate_threads_~tmp___3~0); 20693#L673-2 assume !(1 == ~M_E~0); 20694#L576-1 assume !(1 == ~T1_E~0); 20869#L581-1 assume !(1 == ~T2_E~0); 20886#L586-1 assume !(1 == ~T3_E~0); 20973#L591-1 assume !(1 == ~T4_E~0); 20940#L596-1 assume !(1 == ~E_M~0); 20941#L601-1 assume !(1 == ~E_1~0); 20987#L606-1 assume !(1 == ~E_2~0); 20988#L611-1 assume !(1 == ~E_3~0); 21048#L616-1 assume !(1 == ~E_4~0); 20902#L807-1 [2021-08-27 16:30:33,809 INFO L793 eck$LassoCheckResult]: Loop: 20902#L807-1 assume !false; 20903#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 20933#L493 assume !false; 21091#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20945#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20790#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20679#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 20680#L432 assume !(0 != eval_~tmp~0); 21118#L508 start_simulation_~kernel_st~0 := 2; 22928#L350-1 start_simulation_~kernel_st~0 := 3; 22926#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 22924#L518-4 assume !(0 == ~T1_E~0); 22922#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22920#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22918#L533-3 assume !(0 == ~T4_E~0); 22916#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22914#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22911#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22909#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22908#L558-3 assume !(0 == ~E_4~0); 22907#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22906#L254-18 assume !(1 == ~m_pc~0); 22905#L254-20 is_master_triggered_~__retres1~0 := 0; 22904#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22903#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22902#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22901#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22900#L273-18 assume 1 == ~t1_pc~0; 22898#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 22897#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22896#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22743#L649-18 assume !(0 != activate_threads_~tmp___0~0); 22742#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22741#L292-18 assume !(1 == ~t2_pc~0); 21641#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 22739#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22738#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 22737#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22736#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22735#L311-18 assume !(1 == ~t3_pc~0); 22733#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 22732#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22731#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22730#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22729#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21043#L330-18 assume !(1 == ~t4_pc~0); 21035#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 20936#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20874#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20875#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20960#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 20920#L576-3 assume !(1 == ~T1_E~0); 20921#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22777#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22776#L591-3 assume !(1 == ~T4_E~0); 22775#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22774#L601-3 assume !(1 == ~E_1~0); 22773#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22772#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22771#L616-3 assume !(1 == ~E_4~0); 22770#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22768#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22764#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22763#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22762#L826 assume !(0 == start_simulation_~tmp~3); 20730#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 20731#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 20922#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 20923#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 20808#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20809#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 20850#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 21009#L839 assume !(0 != start_simulation_~tmp___0~1); 20902#L807-1 [2021-08-27 16:30:33,809 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,810 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 1 times [2021-08-27 16:30:33,810 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,810 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012286556] [2021-08-27 16:30:33,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,810 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:33,818 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:33,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:33,845 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:33,846 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1052867964, now seen corresponding path program 1 times [2021-08-27 16:30:33,846 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,846 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019694794] [2021-08-27 16:30:33,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,846 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,884 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,884 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019694794] [2021-08-27 16:30:33,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019694794] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,884 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,884 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,884 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075837751] [2021-08-27 16:30:33,885 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,885 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,885 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,885 INFO L87 Difference]: Start difference. First operand 2332 states and 3348 transitions. cyclomatic complexity: 1020 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,940 INFO L93 Difference]: Finished difference Result 4190 states and 5942 transitions. [2021-08-27 16:30:33,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4190 states and 5942 transitions. [2021-08-27 16:30:33,952 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4064 [2021-08-27 16:30:33,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4190 states to 4190 states and 5942 transitions. [2021-08-27 16:30:33,965 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4190 [2021-08-27 16:30:33,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4190 [2021-08-27 16:30:33,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4190 states and 5942 transitions. [2021-08-27 16:30:33,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,970 INFO L681 BuchiCegarLoop]: Abstraction has 4190 states and 5942 transitions. [2021-08-27 16:30:33,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4190 states and 5942 transitions. [2021-08-27 16:30:34,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4190 to 4138. [2021-08-27 16:30:34,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4138 states, 4138 states have (on average 1.417593040115998) internal successors, (5866), 4137 states have internal predecessors, (5866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4138 states to 4138 states and 5866 transitions. [2021-08-27 16:30:34,018 INFO L704 BuchiCegarLoop]: Abstraction has 4138 states and 5866 transitions. [2021-08-27 16:30:34,018 INFO L587 BuchiCegarLoop]: Abstraction has 4138 states and 5866 transitions. [2021-08-27 16:30:34,018 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-08-27 16:30:34,018 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4138 states and 5866 transitions. [2021-08-27 16:30:34,026 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4016 [2021-08-27 16:30:34,026 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,027 INFO L791 eck$LassoCheckResult]: Stem: 27681#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 27652#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27653#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27342#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 27343#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27405#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27406#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27485#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27628#L377-1 assume !(0 == ~M_E~0); 27409#L518-1 assume !(0 == ~T1_E~0); 27410#L523-1 assume !(0 == ~T2_E~0); 27554#L528-1 assume !(0 == ~T3_E~0); 27555#L533-1 assume !(0 == ~T4_E~0); 27436#L538-1 assume !(0 == ~E_M~0); 27325#L543-1 assume 0 == ~E_1~0;~E_1~0 := 1; 27326#L548-1 assume !(0 == ~E_2~0); 27675#L553-1 assume !(0 == ~E_3~0); 27598#L558-1 assume !(0 == ~E_4~0); 27599#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27713#L254 assume !(1 == ~m_pc~0); 27219#L254-2 is_master_triggered_~__retres1~0 := 0; 27220#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27524#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27416#L641 assume !(0 != activate_threads_~tmp~1); 27417#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27658#L273 assume !(1 == ~t1_pc~0); 27659#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 27321#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27500#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27501#L649 assume !(0 != activate_threads_~tmp___0~0); 27707#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27322#L292 assume !(1 == ~t2_pc~0); 27323#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 27420#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27512#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27380#L657 assume !(0 != activate_threads_~tmp___1~0); 27381#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27551#L311 assume !(1 == ~t3_pc~0); 27552#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 27700#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27190#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27191#L665 assume !(0 != activate_threads_~tmp___2~0); 27240#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27241#L330 assume !(1 == ~t4_pc~0); 27522#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 27523#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27692#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27691#L673 assume !(0 != activate_threads_~tmp___3~0); 27690#L673-2 assume !(1 == ~M_E~0); 27689#L576-1 assume !(1 == ~T1_E~0); 27688#L581-1 assume !(1 == ~T2_E~0); 27687#L586-1 assume !(1 == ~T3_E~0); 27503#L591-1 assume !(1 == ~T4_E~0); 27471#L596-1 assume !(1 == ~E_M~0); 27472#L601-1 assume 1 == ~E_1~0;~E_1~0 := 2; 27517#L606-1 assume !(1 == ~E_2~0); 27518#L611-1 assume !(1 == ~E_3~0); 27582#L616-1 assume !(1 == ~E_4~0); 27583#L807-1 [2021-08-27 16:30:34,028 INFO L793 eck$LassoCheckResult]: Loop: 27583#L807-1 assume !false; 29974#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 29970#L493 assume !false; 29968#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29966#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29960#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29959#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 29957#L432 assume !(0 != eval_~tmp~0); 29958#L508 start_simulation_~kernel_st~0 := 2; 30772#L350-1 start_simulation_~kernel_st~0 := 3; 30771#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30770#L518-4 assume !(0 == ~T1_E~0); 30769#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30768#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30767#L533-3 assume !(0 == ~T4_E~0); 30766#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30158#L543-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30156#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30154#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30152#L558-3 assume !(0 == ~E_4~0); 30150#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30148#L254-18 assume !(1 == ~m_pc~0); 30146#L254-20 is_master_triggered_~__retres1~0 := 0; 30144#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30142#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30140#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30138#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30136#L273-18 assume 1 == ~t1_pc~0; 30133#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30131#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30130#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30129#L649-18 assume !(0 != activate_threads_~tmp___0~0); 30128#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30127#L292-18 assume !(1 == ~t2_pc~0); 29803#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 30125#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30123#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30121#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30119#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30117#L311-18 assume !(1 == ~t3_pc~0); 30114#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 30112#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30109#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30108#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30106#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30104#L330-18 assume !(1 == ~t4_pc~0); 30102#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 30099#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30098#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30095#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30093#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 30091#L576-3 assume !(1 == ~T1_E~0); 30089#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30087#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30085#L591-3 assume !(1 == ~T4_E~0); 30082#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30080#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30077#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30075#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30073#L616-3 assume !(1 == ~E_4~0); 30071#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30066#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30061#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 30057#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 30055#L826 assume !(0 == start_simulation_~tmp~3); 30054#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 30050#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 30045#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 30044#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 30043#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30042#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 30041#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 30040#L839 assume !(0 != start_simulation_~tmp___0~1); 27583#L807-1 [2021-08-27 16:30:34,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,028 INFO L82 PathProgramCache]: Analyzing trace with hash 1909498888, now seen corresponding path program 1 times [2021-08-27 16:30:34,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,028 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205289679] [2021-08-27 16:30:34,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,029 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,051 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,051 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205289679] [2021-08-27 16:30:34,051 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205289679] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,052 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,052 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,052 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740028785] [2021-08-27 16:30:34,052 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,052 INFO L82 PathProgramCache]: Analyzing trace with hash 535479938, now seen corresponding path program 1 times [2021-08-27 16:30:34,053 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,053 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696901751] [2021-08-27 16:30:34,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,053 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,098 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696901751] [2021-08-27 16:30:34,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696901751] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,098 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,099 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,099 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613147851] [2021-08-27 16:30:34,099 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,099 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,099 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-27 16:30:34,100 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-27 16:30:34,100 INFO L87 Difference]: Start difference. First operand 4138 states and 5866 transitions. cyclomatic complexity: 1732 Second operand has 4 states, 4 states have (on average 14.5) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,196 INFO L93 Difference]: Finished difference Result 5912 states and 8349 transitions. [2021-08-27 16:30:34,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-27 16:30:34,197 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5912 states and 8349 transitions. [2021-08-27 16:30:34,215 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5446 [2021-08-27 16:30:34,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5912 states to 5912 states and 8349 transitions. [2021-08-27 16:30:34,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5912 [2021-08-27 16:30:34,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5912 [2021-08-27 16:30:34,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5912 states and 8349 transitions. [2021-08-27 16:30:34,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,246 INFO L681 BuchiCegarLoop]: Abstraction has 5912 states and 8349 transitions. [2021-08-27 16:30:34,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5912 states and 8349 transitions. [2021-08-27 16:30:34,328 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5912 to 5599. [2021-08-27 16:30:34,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5599 states, 5599 states have (on average 1.415967136988748) internal successors, (7928), 5598 states have internal predecessors, (7928), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5599 states to 5599 states and 7928 transitions. [2021-08-27 16:30:34,342 INFO L704 BuchiCegarLoop]: Abstraction has 5599 states and 7928 transitions. [2021-08-27 16:30:34,343 INFO L587 BuchiCegarLoop]: Abstraction has 5599 states and 7928 transitions. [2021-08-27 16:30:34,343 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-08-27 16:30:34,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5599 states and 7928 transitions. [2021-08-27 16:30:34,355 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5446 [2021-08-27 16:30:34,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,356 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,356 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,357 INFO L791 eck$LassoCheckResult]: Stem: 37786#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 37737#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 37738#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 37404#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 37405#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37471#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37472#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37559#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37708#L377-1 assume !(0 == ~M_E~0); 37477#L518-1 assume !(0 == ~T1_E~0); 37478#L523-1 assume !(0 == ~T2_E~0); 37625#L528-1 assume !(0 == ~T3_E~0); 37626#L533-1 assume !(0 == ~T4_E~0); 37507#L538-1 assume !(0 == ~E_M~0); 37388#L543-1 assume !(0 == ~E_1~0); 37389#L548-1 assume !(0 == ~E_2~0); 37764#L553-1 assume !(0 == ~E_3~0); 37676#L558-1 assume !(0 == ~E_4~0); 37677#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37628#L254 assume !(1 == ~m_pc~0); 37281#L254-2 is_master_triggered_~__retres1~0 := 0; 37282#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37600#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 37486#L641 assume !(0 != activate_threads_~tmp~1); 37487#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 37561#L273 assume !(1 == ~t1_pc~0); 37383#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 37778#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37573#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37574#L649 assume !(0 != activate_threads_~tmp___0~0); 37816#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37384#L292 assume !(1 == ~t2_pc~0); 37385#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 37587#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37588#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37442#L657 assume !(0 != activate_threads_~tmp___1~0); 37443#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37815#L311 assume !(1 == ~t3_pc~0); 37437#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 37436#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37252#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 37253#L665 assume !(0 != activate_threads_~tmp___2~0); 37814#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37813#L330 assume !(1 == ~t4_pc~0); 37812#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 37386#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37387#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 37811#L673 assume !(0 != activate_threads_~tmp___3~0); 37283#L673-2 assume !(1 == ~M_E~0); 37284#L576-1 assume !(1 == ~T1_E~0); 37462#L581-1 assume !(1 == ~T2_E~0); 37482#L586-1 assume !(1 == ~T3_E~0); 37576#L591-1 assume !(1 == ~T4_E~0); 37577#L596-1 assume 1 == ~E_M~0;~E_M~0 := 2; 37804#L601-1 assume !(1 == ~E_1~0); 37615#L606-1 assume !(1 == ~E_2~0); 37765#L611-1 assume !(1 == ~E_3~0); 37660#L616-1 assume !(1 == ~E_4~0); 37661#L807-1 [2021-08-27 16:30:34,357 INFO L793 eck$LassoCheckResult]: Loop: 37661#L807-1 assume !false; 37671#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 37531#L493 assume !false; 37711#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 37547#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 37304#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 37269#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 37270#L432 assume !(0 != eval_~tmp~0); 37762#L508 start_simulation_~kernel_st~0 := 2; 42709#L350-1 start_simulation_~kernel_st~0 := 3; 42707#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42705#L518-4 assume !(0 == ~T1_E~0); 42703#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42701#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42699#L533-3 assume !(0 == ~T4_E~0); 42698#L538-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42593#L543-3 assume !(0 == ~E_1~0); 42592#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42584#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42581#L558-3 assume !(0 == ~E_4~0); 42578#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42575#L254-18 assume !(1 == ~m_pc~0); 42573#L254-20 is_master_triggered_~__retres1~0 := 0; 42326#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42324#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42322#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 42320#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42309#L273-18 assume !(1 == ~t1_pc~0); 42307#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 42251#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42250#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42249#L649-18 assume !(0 != activate_threads_~tmp___0~0); 42247#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42245#L292-18 assume !(1 == ~t2_pc~0); 41369#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 42242#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42240#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 42238#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42236#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42234#L311-18 assume !(1 == ~t3_pc~0); 42231#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 42188#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42187#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 42186#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42185#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42184#L330-18 assume !(1 == ~t4_pc~0); 41965#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 41966#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41961#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 41962#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 41957#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 41958#L576-3 assume !(1 == ~T1_E~0); 41951#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41952#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41945#L591-3 assume !(1 == ~T4_E~0); 41946#L596-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41578#L601-3 assume !(1 == ~E_1~0); 37568#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37603#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37604#L616-3 assume !(1 == ~E_4~0); 37311#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 37312#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 37426#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 37785#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 37621#L826 assume !(0 == start_simulation_~tmp~3); 37319#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 37320#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 42212#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 37709#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 37397#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37398#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 37441#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 37640#L839 assume !(0 != start_simulation_~tmp___0~1); 37661#L807-1 [2021-08-27 16:30:34,357 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,357 INFO L82 PathProgramCache]: Analyzing trace with hash -141676414, now seen corresponding path program 1 times [2021-08-27 16:30:34,357 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,357 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141810264] [2021-08-27 16:30:34,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,358 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,371 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,372 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1141810264] [2021-08-27 16:30:34,372 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1141810264] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,372 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,372 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:34,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1251842124] [2021-08-27 16:30:34,372 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1099955483, now seen corresponding path program 1 times [2021-08-27 16:30:34,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,373 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1758747652] [2021-08-27 16:30:34,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,373 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,394 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1758747652] [2021-08-27 16:30:34,394 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1758747652] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,394 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794807429] [2021-08-27 16:30:34,395 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,395 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,395 INFO L87 Difference]: Start difference. First operand 5599 states and 7928 transitions. cyclomatic complexity: 2337 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 2 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,427 INFO L93 Difference]: Finished difference Result 5598 states and 7832 transitions. [2021-08-27 16:30:34,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5598 states and 7832 transitions. [2021-08-27 16:30:34,442 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5446 [2021-08-27 16:30:34,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5598 states to 5598 states and 7832 transitions. [2021-08-27 16:30:34,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5598 [2021-08-27 16:30:34,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5598 [2021-08-27 16:30:34,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5598 states and 7832 transitions. [2021-08-27 16:30:34,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,501 INFO L681 BuchiCegarLoop]: Abstraction has 5598 states and 7832 transitions. [2021-08-27 16:30:34,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5598 states and 7832 transitions. [2021-08-27 16:30:34,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5598 to 4125. [2021-08-27 16:30:34,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4125 states, 4125 states have (on average 1.3946666666666667) internal successors, (5753), 4124 states have internal predecessors, (5753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4125 states to 4125 states and 5753 transitions. [2021-08-27 16:30:34,558 INFO L704 BuchiCegarLoop]: Abstraction has 4125 states and 5753 transitions. [2021-08-27 16:30:34,558 INFO L587 BuchiCegarLoop]: Abstraction has 4125 states and 5753 transitions. [2021-08-27 16:30:34,558 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-08-27 16:30:34,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4125 states and 5753 transitions. [2021-08-27 16:30:34,567 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4016 [2021-08-27 16:30:34,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,568 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,568 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,568 INFO L791 eck$LassoCheckResult]: Stem: 48968#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 48927#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 48928#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48614#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 48615#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48680#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48681#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48766#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48904#L377-1 assume !(0 == ~M_E~0); 48687#L518-1 assume !(0 == ~T1_E~0); 48688#L523-1 assume !(0 == ~T2_E~0); 48835#L528-1 assume !(0 == ~T3_E~0); 48836#L533-1 assume !(0 == ~T4_E~0); 48714#L538-1 assume !(0 == ~E_M~0); 48597#L543-1 assume !(0 == ~E_1~0); 48598#L548-1 assume !(0 == ~E_2~0); 48949#L553-1 assume !(0 == ~E_3~0); 48879#L558-1 assume !(0 == ~E_4~0); 48880#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48838#L254 assume !(1 == ~m_pc~0); 48487#L254-2 is_master_triggered_~__retres1~0 := 0; 48488#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48806#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48695#L641 assume !(0 != activate_threads_~tmp~1); 48696#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48769#L273 assume !(1 == ~t1_pc~0); 48590#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 48544#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48545#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 48935#L649 assume !(0 != activate_threads_~tmp___0~0); 48936#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48593#L292 assume !(1 == ~t2_pc~0); 48594#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 48794#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48795#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 48652#L657 assume !(0 != activate_threads_~tmp___1~0); 48653#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48989#L311 assume !(1 == ~t3_pc~0); 48648#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 48647#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48458#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 48459#L665 assume !(0 != activate_threads_~tmp___2~0); 48988#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48987#L330 assume !(1 == ~t4_pc~0); 48986#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 48595#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48596#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 48985#L673 assume !(0 != activate_threads_~tmp___3~0); 48489#L673-2 assume !(1 == ~M_E~0); 48490#L576-1 assume !(1 == ~T1_E~0); 48671#L581-1 assume !(1 == ~T2_E~0); 48691#L586-1 assume !(1 == ~T3_E~0); 48783#L591-1 assume !(1 == ~T4_E~0); 48784#L596-1 assume !(1 == ~E_M~0); 48982#L601-1 assume !(1 == ~E_1~0); 48799#L606-1 assume !(1 == ~E_2~0); 48800#L611-1 assume !(1 == ~E_3~0); 48862#L616-1 assume !(1 == ~E_4~0); 48863#L807-1 [2021-08-27 16:30:34,569 INFO L793 eck$LassoCheckResult]: Loop: 48863#L807-1 assume !false; 51217#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 51149#L493 assume !false; 51214#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51212#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51206#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51204#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 51202#L432 assume !(0 != eval_~tmp~0); 51203#L508 start_simulation_~kernel_st~0 := 2; 52239#L350-1 start_simulation_~kernel_st~0 := 3; 52237#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52236#L518-4 assume !(0 == ~T1_E~0); 52234#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52232#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52230#L533-3 assume !(0 == ~T4_E~0); 52228#L538-3 assume !(0 == ~E_M~0); 52226#L543-3 assume !(0 == ~E_1~0); 52224#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52222#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 52220#L558-3 assume !(0 == ~E_4~0); 52218#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52213#L254-18 assume !(1 == ~m_pc~0); 52212#L254-20 is_master_triggered_~__retres1~0 := 0; 52211#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52210#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52209#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 52207#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52205#L273-18 assume !(1 == ~t1_pc~0); 52202#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 52200#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52198#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52196#L649-18 assume !(0 != activate_threads_~tmp___0~0); 52193#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51365#L292-18 assume !(1 == ~t2_pc~0); 51364#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 51363#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51362#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51359#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 51356#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51353#L311-18 assume !(1 == ~t3_pc~0); 51349#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 51346#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51343#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 51340#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 51337#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51334#L330-18 assume !(1 == ~t4_pc~0); 51331#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 51328#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51325#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 51321#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 51318#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 51316#L576-3 assume !(1 == ~T1_E~0); 51314#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 51312#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51310#L591-3 assume !(1 == ~T4_E~0); 51308#L596-3 assume !(1 == ~E_M~0); 51264#L601-3 assume !(1 == ~E_1~0); 51262#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 51260#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 51258#L616-3 assume !(1 == ~E_4~0); 51256#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51250#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51246#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51245#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 51242#L826 assume !(0 == start_simulation_~tmp~3); 51239#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 51237#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 51231#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 51229#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 51227#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 51224#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 51222#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 51220#L839 assume !(0 != start_simulation_~tmp___0~1); 48863#L807-1 [2021-08-27 16:30:34,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,569 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 2 times [2021-08-27 16:30:34,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,570 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915328270] [2021-08-27 16:30:34,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,570 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:34,575 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:34,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:34,587 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:34,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,588 INFO L82 PathProgramCache]: Analyzing trace with hash 1634596193, now seen corresponding path program 1 times [2021-08-27 16:30:34,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,588 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008069484] [2021-08-27 16:30:34,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,588 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,610 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008069484] [2021-08-27 16:30:34,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008069484] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,610 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015064443] [2021-08-27 16:30:34,610 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-27 16:30:34,611 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-27 16:30:34,612 INFO L87 Difference]: Start difference. First operand 4125 states and 5753 transitions. cyclomatic complexity: 1632 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,696 INFO L93 Difference]: Finished difference Result 7289 states and 10099 transitions. [2021-08-27 16:30:34,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-08-27 16:30:34,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7289 states and 10099 transitions. [2021-08-27 16:30:34,723 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7160 [2021-08-27 16:30:34,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7289 states to 7289 states and 10099 transitions. [2021-08-27 16:30:34,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7289 [2021-08-27 16:30:34,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7289 [2021-08-27 16:30:34,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7289 states and 10099 transitions. [2021-08-27 16:30:34,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,749 INFO L681 BuchiCegarLoop]: Abstraction has 7289 states and 10099 transitions. [2021-08-27 16:30:34,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7289 states and 10099 transitions. [2021-08-27 16:30:34,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7289 to 4173. [2021-08-27 16:30:34,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4173 states, 4173 states have (on average 1.390127006949437) internal successors, (5801), 4172 states have internal predecessors, (5801), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4173 states to 4173 states and 5801 transitions. [2021-08-27 16:30:34,846 INFO L704 BuchiCegarLoop]: Abstraction has 4173 states and 5801 transitions. [2021-08-27 16:30:34,846 INFO L587 BuchiCegarLoop]: Abstraction has 4173 states and 5801 transitions. [2021-08-27 16:30:34,846 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-08-27 16:30:34,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4173 states and 5801 transitions. [2021-08-27 16:30:34,855 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4064 [2021-08-27 16:30:34,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,855 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,856 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,856 INFO L791 eck$LassoCheckResult]: Stem: 60389#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 60353#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 60354#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 60040#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 60041#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60104#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60105#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60192#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60332#L377-1 assume !(0 == ~M_E~0); 60110#L518-1 assume !(0 == ~T1_E~0); 60111#L523-1 assume !(0 == ~T2_E~0); 60263#L528-1 assume !(0 == ~T3_E~0); 60264#L533-1 assume !(0 == ~T4_E~0); 60139#L538-1 assume !(0 == ~E_M~0); 60024#L543-1 assume !(0 == ~E_1~0); 60025#L548-1 assume !(0 == ~E_2~0); 60374#L553-1 assume !(0 == ~E_3~0); 60307#L558-1 assume !(0 == ~E_4~0); 60308#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60265#L254 assume !(1 == ~m_pc~0); 59917#L254-2 is_master_triggered_~__retres1~0 := 0; 59918#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60234#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 60118#L641 assume !(0 != activate_threads_~tmp~1); 60119#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60195#L273 assume !(1 == ~t1_pc~0); 60019#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 60382#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60209#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 60210#L649 assume !(0 != activate_threads_~tmp___0~0); 60405#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60021#L292 assume !(1 == ~t2_pc~0); 60022#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 60404#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60378#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 60077#L657 assume !(0 != activate_threads_~tmp___1~0); 60078#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60402#L311 assume !(1 == ~t3_pc~0); 60073#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 60072#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59888#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 59889#L665 assume !(0 != activate_threads_~tmp___2~0); 60401#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60400#L330 assume !(1 == ~t4_pc~0); 60399#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 60023#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59926#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 59927#L673 assume !(0 != activate_threads_~tmp___3~0); 60106#L673-2 assume !(1 == ~M_E~0); 60396#L576-1 assume !(1 == ~T1_E~0); 60395#L581-1 assume !(1 == ~T2_E~0); 60394#L586-1 assume !(1 == ~T3_E~0); 60393#L591-1 assume !(1 == ~T4_E~0); 60392#L596-1 assume !(1 == ~E_M~0); 60391#L601-1 assume !(1 == ~E_1~0); 60226#L606-1 assume !(1 == ~E_2~0); 60227#L611-1 assume !(1 == ~E_3~0); 60292#L616-1 assume !(1 == ~E_4~0); 60293#L807-1 [2021-08-27 16:30:34,856 INFO L793 eck$LassoCheckResult]: Loop: 60293#L807-1 assume !false; 61137#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 61134#L493 assume !false; 61133#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 61132#L390 assume !(0 == ~m_st~0); 61127#L394 assume !(0 == ~t1_st~0); 61128#L398 assume !(0 == ~t2_st~0); 61131#L402 assume !(0 == ~t3_st~0); 61129#L406 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 61130#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 60542#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 60543#L432 assume !(0 != eval_~tmp~0); 61287#L508 start_simulation_~kernel_st~0 := 2; 61285#L350-1 start_simulation_~kernel_st~0 := 3; 61283#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 61281#L518-4 assume !(0 == ~T1_E~0); 61279#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61277#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61275#L533-3 assume !(0 == ~T4_E~0); 61273#L538-3 assume !(0 == ~E_M~0); 61271#L543-3 assume !(0 == ~E_1~0); 61269#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61267#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61265#L558-3 assume !(0 == ~E_4~0); 61263#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61261#L254-18 assume !(1 == ~m_pc~0); 61259#L254-20 is_master_triggered_~__retres1~0 := 0; 61257#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61255#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 61253#L641-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 61251#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 61244#L273-18 assume !(1 == ~t1_pc~0); 61240#L273-20 is_transmit1_triggered_~__retres1~1 := 0; 61238#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61236#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 61234#L649-18 assume !(0 != activate_threads_~tmp___0~0); 61232#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 61230#L292-18 assume !(1 == ~t2_pc~0); 60657#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 61228#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61226#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 61224#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 61222#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 61220#L311-18 assume !(1 == ~t3_pc~0); 61216#L311-20 is_transmit3_triggered_~__retres1~3 := 0; 61214#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61212#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 61210#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 61208#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 61206#L330-18 assume !(1 == ~t4_pc~0); 61204#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 61202#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 61200#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 61198#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 61196#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 61194#L576-3 assume !(1 == ~T1_E~0); 61192#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61190#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61188#L591-3 assume !(1 == ~T4_E~0); 61186#L596-3 assume !(1 == ~E_M~0); 61184#L601-3 assume !(1 == ~E_1~0); 61183#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61182#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61181#L616-3 assume !(1 == ~E_4~0); 61180#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 61178#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 61171#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 61168#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 61164#L826 assume !(0 == start_simulation_~tmp~3); 61161#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 61160#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 61154#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 61152#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 61150#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 61148#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 61144#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 61142#L839 assume !(0 != start_simulation_~tmp___0~1); 60293#L807-1 [2021-08-27 16:30:34,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,858 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 3 times [2021-08-27 16:30:34,858 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,858 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263210835] [2021-08-27 16:30:34,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,859 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:34,866 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:34,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:34,884 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:34,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,884 INFO L82 PathProgramCache]: Analyzing trace with hash -1205949459, now seen corresponding path program 1 times [2021-08-27 16:30:34,885 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,885 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114459897] [2021-08-27 16:30:34,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,885 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,934 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,934 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114459897] [2021-08-27 16:30:34,934 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114459897] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,934 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,934 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,935 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402200240] [2021-08-27 16:30:34,935 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,935 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-27 16:30:34,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-27 16:30:34,936 INFO L87 Difference]: Start difference. First operand 4173 states and 5801 transitions. cyclomatic complexity: 1632 Second operand has 5 states, 5 states have (on average 15.4) internal successors, (77), 5 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,028 INFO L93 Difference]: Finished difference Result 4897 states and 6780 transitions. [2021-08-27 16:30:35,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-08-27 16:30:35,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4897 states and 6780 transitions. [2021-08-27 16:30:35,040 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4788 [2021-08-27 16:30:35,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4897 states to 4897 states and 6780 transitions. [2021-08-27 16:30:35,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4897 [2021-08-27 16:30:35,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4897 [2021-08-27 16:30:35,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4897 states and 6780 transitions. [2021-08-27 16:30:35,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,055 INFO L681 BuchiCegarLoop]: Abstraction has 4897 states and 6780 transitions. [2021-08-27 16:30:35,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4897 states and 6780 transitions. [2021-08-27 16:30:35,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4897 to 4185. [2021-08-27 16:30:35,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4185 states, 4185 states have (on average 1.3715651135005973) internal successors, (5740), 4184 states have internal predecessors, (5740), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4185 states to 4185 states and 5740 transitions. [2021-08-27 16:30:35,090 INFO L704 BuchiCegarLoop]: Abstraction has 4185 states and 5740 transitions. [2021-08-27 16:30:35,090 INFO L587 BuchiCegarLoop]: Abstraction has 4185 states and 5740 transitions. [2021-08-27 16:30:35,090 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-08-27 16:30:35,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4185 states and 5740 transitions. [2021-08-27 16:30:35,096 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4076 [2021-08-27 16:30:35,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,099 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,099 INFO L791 eck$LassoCheckResult]: Stem: 69562#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 69507#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 69508#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 69129#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 69130#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69199#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69200#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69305#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69474#L377-1 assume !(0 == ~M_E~0); 69205#L518-1 assume !(0 == ~T1_E~0); 69206#L523-1 assume !(0 == ~T2_E~0); 69377#L528-1 assume !(0 == ~T3_E~0); 69378#L533-1 assume !(0 == ~T4_E~0); 69239#L538-1 assume !(0 == ~E_M~0); 69111#L543-1 assume !(0 == ~E_1~0); 69112#L548-1 assume !(0 == ~E_2~0); 69538#L553-1 assume !(0 == ~E_3~0); 69436#L558-1 assume !(0 == ~E_4~0); 69437#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69381#L254 assume !(1 == ~m_pc~0); 69000#L254-2 is_master_triggered_~__retres1~0 := 0; 69001#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69346#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 69215#L641 assume !(0 != activate_threads_~tmp~1); 69216#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69308#L273 assume !(1 == ~t1_pc~0); 69107#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 69550#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69319#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 69320#L649 assume !(0 != activate_threads_~tmp___0~0); 69587#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69108#L292 assume !(1 == ~t2_pc~0); 69109#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 69586#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69585#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 69584#L657 assume !(0 != activate_threads_~tmp___1~0); 69502#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69374#L311 assume !(1 == ~t3_pc~0); 69375#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 69283#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69284#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 69290#L665 assume !(0 != activate_threads_~tmp___2~0); 69021#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69022#L330 assume !(1 == ~t4_pc~0); 69345#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 69110#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69009#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 69010#L673 assume !(0 != activate_threads_~tmp___3~0); 69201#L673-2 assume !(1 == ~M_E~0); 69571#L576-1 assume !(1 == ~T1_E~0); 69570#L581-1 assume !(1 == ~T2_E~0); 69569#L586-1 assume !(1 == ~T3_E~0); 69568#L591-1 assume !(1 == ~T4_E~0); 69567#L596-1 assume !(1 == ~E_M~0); 69566#L601-1 assume !(1 == ~E_1~0); 69340#L606-1 assume !(1 == ~E_2~0); 69341#L611-1 assume !(1 == ~E_3~0); 69415#L616-1 assume !(1 == ~E_4~0); 69416#L807-1 [2021-08-27 16:30:35,099 INFO L793 eck$LassoCheckResult]: Loop: 69416#L807-1 assume !false; 70344#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 70340#L493 assume !false; 70322#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 70321#L390 assume !(0 == ~m_st~0); 70316#L394 assume !(0 == ~t1_st~0); 70317#L398 assume !(0 == ~t2_st~0); 70320#L402 assume !(0 == ~t3_st~0); 70318#L406 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 70319#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 70297#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 70298#L432 assume !(0 != eval_~tmp~0); 70615#L508 start_simulation_~kernel_st~0 := 2; 70613#L350-1 start_simulation_~kernel_st~0 := 3; 70611#L518-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70609#L518-4 assume !(0 == ~T1_E~0); 70607#L523-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70605#L528-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 70603#L533-3 assume !(0 == ~T4_E~0); 70601#L538-3 assume !(0 == ~E_M~0); 70599#L543-3 assume !(0 == ~E_1~0); 70597#L548-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70595#L553-3 assume 0 == ~E_3~0;~E_3~0 := 1; 70593#L558-3 assume !(0 == ~E_4~0); 70591#L563-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70589#L254-18 assume !(1 == ~m_pc~0); 70587#L254-20 is_master_triggered_~__retres1~0 := 0; 70585#L265-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70583#L266-6 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70581#L641-18 assume !(0 != activate_threads_~tmp~1); 70579#L641-20 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 70577#L273-18 assume 1 == ~t1_pc~0; 70576#L274-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 70572#L284-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 70570#L285-6 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 70568#L649-18 assume !(0 != activate_threads_~tmp___0~0); 70566#L649-20 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70563#L292-18 assume !(1 == ~t2_pc~0); 69907#L292-20 is_transmit2_triggered_~__retres1~2 := 0; 70559#L303-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70556#L304-6 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 70554#L657-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 70551#L657-20 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70548#L311-18 assume 1 == ~t3_pc~0; 70545#L312-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 70540#L322-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70536#L323-6 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 70530#L665-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70525#L665-20 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70520#L330-18 assume !(1 == ~t4_pc~0); 70515#L330-20 is_transmit4_triggered_~__retres1~4 := 0; 70510#L341-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70505#L342-6 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 70497#L673-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 70493#L673-20 assume 1 == ~M_E~0;~M_E~0 := 2; 70488#L576-3 assume !(1 == ~T1_E~0); 70483#L581-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70478#L586-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70473#L591-3 assume !(1 == ~T4_E~0); 70469#L596-3 assume !(1 == ~E_M~0); 70465#L601-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70460#L606-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70456#L611-3 assume 1 == ~E_3~0;~E_3~0 := 2; 70452#L616-3 assume !(1 == ~E_4~0); 70449#L621-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 70405#L390-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 70397#L417-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 70393#L418-1 start_simulation_#t~ret21 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 70388#L826 assume !(0 == start_simulation_~tmp~3); 70384#L826-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret20, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 70381#L390-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 70374#L417-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 70371#L418-2 stop_simulation_#t~ret20 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret20;havoc stop_simulation_#t~ret20; 70368#L781 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 70363#L788 stop_simulation_#res := stop_simulation_~__retres2~0; 70358#L789 start_simulation_#t~ret22 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 70353#L839 assume !(0 != start_simulation_~tmp___0~1); 69416#L807-1 [2021-08-27 16:30:35,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,099 INFO L82 PathProgramCache]: Analyzing trace with hash -139829372, now seen corresponding path program 4 times [2021-08-27 16:30:35,100 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,100 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043092689] [2021-08-27 16:30:35,100 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,100 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,106 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:35,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,118 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:35,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,119 INFO L82 PathProgramCache]: Analyzing trace with hash 963248235, now seen corresponding path program 1 times [2021-08-27 16:30:35,119 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,119 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859013971] [2021-08-27 16:30:35,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,119 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,141 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,141 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859013971] [2021-08-27 16:30:35,142 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859013971] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,142 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,142 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:35,143 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242546279] [2021-08-27 16:30:35,143 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:35,143 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,143 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:35,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:35,144 INFO L87 Difference]: Start difference. First operand 4185 states and 5740 transitions. cyclomatic complexity: 1559 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,198 INFO L93 Difference]: Finished difference Result 5841 states and 7923 transitions. [2021-08-27 16:30:35,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:35,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5841 states and 7923 transitions. [2021-08-27 16:30:35,212 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5653 [2021-08-27 16:30:35,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5841 states to 5841 states and 7923 transitions. [2021-08-27 16:30:35,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5841 [2021-08-27 16:30:35,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5841 [2021-08-27 16:30:35,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5841 states and 7923 transitions. [2021-08-27 16:30:35,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,226 INFO L681 BuchiCegarLoop]: Abstraction has 5841 states and 7923 transitions. [2021-08-27 16:30:35,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5841 states and 7923 transitions. [2021-08-27 16:30:35,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5841 to 5841. [2021-08-27 16:30:35,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5841 states, 5841 states have (on average 1.3564458140729327) internal successors, (7923), 5840 states have internal predecessors, (7923), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5841 states to 5841 states and 7923 transitions. [2021-08-27 16:30:35,276 INFO L704 BuchiCegarLoop]: Abstraction has 5841 states and 7923 transitions. [2021-08-27 16:30:35,276 INFO L587 BuchiCegarLoop]: Abstraction has 5841 states and 7923 transitions. [2021-08-27 16:30:35,276 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-08-27 16:30:35,276 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5841 states and 7923 transitions. [2021-08-27 16:30:35,285 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5653 [2021-08-27 16:30:35,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,286 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,286 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,287 INFO L791 eck$LassoCheckResult]: Stem: 79495#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 79468#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 79469#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 79154#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 79155#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79220#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79221#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79306#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79443#L377-1 assume !(0 == ~M_E~0); 79225#L518-1 assume !(0 == ~T1_E~0); 79226#L523-1 assume !(0 == ~T2_E~0); 79370#L528-1 assume !(0 == ~T3_E~0); 79371#L533-1 assume !(0 == ~T4_E~0); 79252#L538-1 assume !(0 == ~E_M~0); 79139#L543-1 assume !(0 == ~E_1~0); 79140#L548-1 assume !(0 == ~E_2~0); 79481#L553-1 assume !(0 == ~E_3~0); 79411#L558-1 assume !(0 == ~E_4~0); 79412#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79372#L254 assume !(1 == ~m_pc~0); 79032#L254-2 is_master_triggered_~__retres1~0 := 0; 79033#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 79345#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 79233#L641 assume !(0 != activate_threads_~tmp~1); 79234#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 79308#L273 assume !(1 == ~t1_pc~0); 79134#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 79490#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 79319#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 79320#L649 assume !(0 != activate_threads_~tmp___0~0); 79521#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 79135#L292 assume !(1 == ~t2_pc~0); 79136#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 79515#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 79514#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 79513#L657 assume !(0 != activate_threads_~tmp___1~0); 79464#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 79369#L311 assume !(1 == ~t3_pc~0); 79187#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 79186#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 79003#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 79004#L665 assume !(0 != activate_threads_~tmp___2~0); 79509#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79508#L330 assume !(1 == ~t4_pc~0); 79507#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 79137#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79138#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 79505#L673 assume !(0 != activate_threads_~tmp___3~0); 79504#L673-2 assume !(1 == ~M_E~0); 79503#L576-1 assume !(1 == ~T1_E~0); 79502#L581-1 assume !(1 == ~T2_E~0); 79501#L586-1 assume !(1 == ~T3_E~0); 79500#L591-1 assume !(1 == ~T4_E~0); 79499#L596-1 assume !(1 == ~E_M~0); 79498#L601-1 assume !(1 == ~E_1~0); 79336#L606-1 assume !(1 == ~E_2~0); 79337#L611-1 assume !(1 == ~E_3~0); 79397#L616-1 assume !(1 == ~E_4~0); 79398#L807-1 assume !false; 79832#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 79829#L493 [2021-08-27 16:30:35,287 INFO L793 eck$LassoCheckResult]: Loop: 79829#L493 assume !false; 79826#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 79823#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 79698#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 79693#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 79643#L432 assume 0 != eval_~tmp~0; 79607#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 79482#L440 assume !(0 != eval_~tmp_ndt_1~0); 79483#L437 assume !(0 == ~t1_st~0); 80466#L451 assume !(0 == ~t2_st~0); 79834#L465 assume !(0 == ~t3_st~0); 79833#L479 assume !(0 == ~t4_st~0); 79829#L493 [2021-08-27 16:30:35,287 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,287 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 1 times [2021-08-27 16:30:35,287 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,287 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680119010] [2021-08-27 16:30:35,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,288 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,292 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:35,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,306 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:35,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,307 INFO L82 PathProgramCache]: Analyzing trace with hash 1357783123, now seen corresponding path program 1 times [2021-08-27 16:30:35,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,307 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429146702] [2021-08-27 16:30:35,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,307 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,309 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:35,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,311 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:35,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1573772616, now seen corresponding path program 1 times [2021-08-27 16:30:35,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,312 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [703786632] [2021-08-27 16:30:35,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,312 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,330 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,330 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [703786632] [2021-08-27 16:30:35,330 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [703786632] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,330 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,330 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:35,330 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1604246609] [2021-08-27 16:30:35,407 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:35,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:35,408 INFO L87 Difference]: Start difference. First operand 5841 states and 7923 transitions. cyclomatic complexity: 2090 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,455 INFO L93 Difference]: Finished difference Result 10665 states and 14362 transitions. [2021-08-27 16:30:35,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:35,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10665 states and 14362 transitions. [2021-08-27 16:30:35,485 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10294 [2021-08-27 16:30:35,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10665 states to 10665 states and 14362 transitions. [2021-08-27 16:30:35,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10665 [2021-08-27 16:30:35,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10665 [2021-08-27 16:30:35,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10665 states and 14362 transitions. [2021-08-27 16:30:35,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,551 INFO L681 BuchiCegarLoop]: Abstraction has 10665 states and 14362 transitions. [2021-08-27 16:30:35,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10665 states and 14362 transitions. [2021-08-27 16:30:35,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10665 to 10019. [2021-08-27 16:30:35,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10019 states, 10019 states have (on average 1.3506337957880028) internal successors, (13532), 10018 states have internal predecessors, (13532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10019 states to 10019 states and 13532 transitions. [2021-08-27 16:30:35,640 INFO L704 BuchiCegarLoop]: Abstraction has 10019 states and 13532 transitions. [2021-08-27 16:30:35,640 INFO L587 BuchiCegarLoop]: Abstraction has 10019 states and 13532 transitions. [2021-08-27 16:30:35,640 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-08-27 16:30:35,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10019 states and 13532 transitions. [2021-08-27 16:30:35,658 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9648 [2021-08-27 16:30:35,658 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,658 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,659 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,659 INFO L791 eck$LassoCheckResult]: Stem: 96046#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 96005#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 96006#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 95669#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 95670#L357-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 95736#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95737#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95825#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95978#L377-1 assume !(0 == ~M_E~0); 95743#L518-1 assume !(0 == ~T1_E~0); 95744#L523-1 assume !(0 == ~T2_E~0); 95901#L528-1 assume !(0 == ~T3_E~0); 95902#L533-1 assume !(0 == ~T4_E~0); 95774#L538-1 assume !(0 == ~E_M~0); 95652#L543-1 assume !(0 == ~E_1~0); 95653#L548-1 assume !(0 == ~E_2~0); 96031#L553-1 assume !(0 == ~E_3~0); 95953#L558-1 assume !(0 == ~E_4~0); 95954#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96626#L254 assume !(1 == ~m_pc~0); 96624#L254-2 is_master_triggered_~__retres1~0 := 0; 96622#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 96620#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 96617#L641 assume !(0 != activate_threads_~tmp~1); 96615#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96614#L273 assume !(1 == ~t1_pc~0); 96611#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 96610#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96609#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 96608#L649 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 96018#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 95648#L292 assume !(1 == ~t2_pc~0); 95649#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 95759#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 95855#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 95706#L657 assume !(0 != activate_threads_~tmp___1~0); 95707#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96078#L311 assume !(1 == ~t3_pc~0); 95702#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 95701#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 95517#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 95518#L665 assume !(0 != activate_threads_~tmp___2~0); 95567#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 95568#L330 assume !(1 == ~t4_pc~0); 95869#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 95650#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 95651#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 96060#L673 assume !(0 != activate_threads_~tmp___3~0); 96061#L673-2 assume !(1 == ~M_E~0); 96056#L576-1 assume !(1 == ~T1_E~0); 96057#L581-1 assume !(1 == ~T2_E~0); 96052#L586-1 assume !(1 == ~T3_E~0); 96053#L591-1 assume !(1 == ~T4_E~0); 96048#L596-1 assume !(1 == ~E_M~0); 96049#L601-1 assume !(1 == ~E_1~0); 95862#L606-1 assume !(1 == ~E_2~0); 95863#L611-1 assume !(1 == ~E_3~0); 95935#L616-1 assume !(1 == ~E_4~0); 95936#L807-1 assume !false; 96185#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 96186#L493 [2021-08-27 16:30:35,659 INFO L793 eck$LassoCheckResult]: Loop: 96186#L493 assume !false; 96698#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 96695#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 96684#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 96682#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 96670#L432 assume 0 != eval_~tmp~0; 96667#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 96663#L440 assume !(0 != eval_~tmp_ndt_1~0); 96659#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 96558#L454 assume !(0 != eval_~tmp_ndt_2~0); 96655#L451 assume !(0 == ~t2_st~0); 96542#L465 assume !(0 == ~t3_st~0); 96705#L479 assume !(0 == ~t4_st~0); 96186#L493 [2021-08-27 16:30:35,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,660 INFO L82 PathProgramCache]: Analyzing trace with hash -1892956382, now seen corresponding path program 1 times [2021-08-27 16:30:35,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,660 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115348539] [2021-08-27 16:30:35,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,660 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,671 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,672 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115348539] [2021-08-27 16:30:35,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115348539] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,672 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,672 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:35,672 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518394686] [2021-08-27 16:30:35,672 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:35,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,673 INFO L82 PathProgramCache]: Analyzing trace with hash -1003661710, now seen corresponding path program 1 times [2021-08-27 16:30:35,673 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,673 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787868803] [2021-08-27 16:30:35,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,673 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,675 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:35,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,677 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:35,757 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,758 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:35,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:35,758 INFO L87 Difference]: Start difference. First operand 10019 states and 13532 transitions. cyclomatic complexity: 3521 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,792 INFO L93 Difference]: Finished difference Result 9933 states and 13417 transitions. [2021-08-27 16:30:35,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:35,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9933 states and 13417 transitions. [2021-08-27 16:30:35,911 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9648 [2021-08-27 16:30:35,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9933 states to 9933 states and 13417 transitions. [2021-08-27 16:30:35,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9933 [2021-08-27 16:30:35,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9933 [2021-08-27 16:30:35,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9933 states and 13417 transitions. [2021-08-27 16:30:35,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,949 INFO L681 BuchiCegarLoop]: Abstraction has 9933 states and 13417 transitions. [2021-08-27 16:30:35,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9933 states and 13417 transitions. [2021-08-27 16:30:36,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9933 to 9933. [2021-08-27 16:30:36,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.3507500251686297) internal successors, (13417), 9932 states have internal predecessors, (13417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 13417 transitions. [2021-08-27 16:30:36,052 INFO L704 BuchiCegarLoop]: Abstraction has 9933 states and 13417 transitions. [2021-08-27 16:30:36,052 INFO L587 BuchiCegarLoop]: Abstraction has 9933 states and 13417 transitions. [2021-08-27 16:30:36,053 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-08-27 16:30:36,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 13417 transitions. [2021-08-27 16:30:36,073 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9648 [2021-08-27 16:30:36,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:36,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:36,074 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,074 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,074 INFO L791 eck$LassoCheckResult]: Stem: 115982#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 115943#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 115944#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 115623#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 115624#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115686#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115687#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 115774#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 115917#L377-1 assume !(0 == ~M_E~0); 115693#L518-1 assume !(0 == ~T1_E~0); 115694#L523-1 assume !(0 == ~T2_E~0); 115842#L528-1 assume !(0 == ~T3_E~0); 115843#L533-1 assume !(0 == ~T4_E~0); 115722#L538-1 assume !(0 == ~E_M~0); 115608#L543-1 assume !(0 == ~E_1~0); 115609#L548-1 assume !(0 == ~E_2~0); 115965#L553-1 assume !(0 == ~E_3~0); 115883#L558-1 assume !(0 == ~E_4~0); 115884#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 115844#L254 assume !(1 == ~m_pc~0); 115504#L254-2 is_master_triggered_~__retres1~0 := 0; 115505#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 115817#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 115702#L641 assume !(0 != activate_threads_~tmp~1); 115703#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 115777#L273 assume !(1 == ~t1_pc~0); 115603#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 115975#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 115789#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 115790#L649 assume !(0 != activate_threads_~tmp___0~0); 116002#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 115605#L292 assume !(1 == ~t2_pc~0); 115606#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 116001#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 115968#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 115659#L657 assume !(0 != activate_threads_~tmp___1~0); 115660#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 115999#L311 assume !(1 == ~t3_pc~0); 115654#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 115653#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 115475#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 115476#L665 assume !(0 != activate_threads_~tmp___2~0); 115998#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 115997#L330 assume !(1 == ~t4_pc~0); 115996#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 115607#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 115513#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 115514#L673 assume !(0 != activate_threads_~tmp___3~0); 115688#L673-2 assume !(1 == ~M_E~0); 115993#L576-1 assume !(1 == ~T1_E~0); 115992#L581-1 assume !(1 == ~T2_E~0); 115991#L586-1 assume !(1 == ~T3_E~0); 115990#L591-1 assume !(1 == ~T4_E~0); 115989#L596-1 assume !(1 == ~E_M~0); 115988#L601-1 assume !(1 == ~E_1~0); 115807#L606-1 assume !(1 == ~E_2~0); 115808#L611-1 assume !(1 == ~E_3~0); 115869#L616-1 assume !(1 == ~E_4~0); 115870#L807-1 assume !false; 120249#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 120245#L493 [2021-08-27 16:30:36,074 INFO L793 eck$LassoCheckResult]: Loop: 120245#L493 assume !false; 120243#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 120240#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 120238#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 120235#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 120233#L432 assume 0 != eval_~tmp~0; 120210#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 120205#L440 assume !(0 != eval_~tmp_ndt_1~0); 120199#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 120174#L454 assume !(0 != eval_~tmp_ndt_2~0); 120194#L451 assume !(0 == ~t2_st~0); 120252#L465 assume !(0 == ~t3_st~0); 120250#L479 assume !(0 == ~t4_st~0); 120245#L493 [2021-08-27 16:30:36,075 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,075 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 2 times [2021-08-27 16:30:36,075 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,075 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982426716] [2021-08-27 16:30:36,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,075 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,082 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,096 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,097 INFO L82 PathProgramCache]: Analyzing trace with hash -1003661710, now seen corresponding path program 2 times [2021-08-27 16:30:36,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464680136] [2021-08-27 16:30:36,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,098 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,100 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,104 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1687576403, now seen corresponding path program 1 times [2021-08-27 16:30:36,105 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,105 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030523042] [2021-08-27 16:30:36,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,105 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:36,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:36,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:36,131 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030523042] [2021-08-27 16:30:36,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030523042] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:36,131 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:36,131 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:36,131 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089197760] [2021-08-27 16:30:36,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:36,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:36,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:36,212 INFO L87 Difference]: Start difference. First operand 9933 states and 13417 transitions. cyclomatic complexity: 3492 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:36,281 INFO L93 Difference]: Finished difference Result 18307 states and 24581 transitions. [2021-08-27 16:30:36,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:36,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18307 states and 24581 transitions. [2021-08-27 16:30:36,351 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17828 [2021-08-27 16:30:36,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18307 states to 18307 states and 24581 transitions. [2021-08-27 16:30:36,393 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18307 [2021-08-27 16:30:36,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18307 [2021-08-27 16:30:36,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18307 states and 24581 transitions. [2021-08-27 16:30:36,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:36,418 INFO L681 BuchiCegarLoop]: Abstraction has 18307 states and 24581 transitions. [2021-08-27 16:30:36,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18307 states and 24581 transitions. [2021-08-27 16:30:36,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18307 to 17843. [2021-08-27 16:30:36,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17843 states, 17843 states have (on average 1.3444488034523343) internal successors, (23989), 17842 states have internal predecessors, (23989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17843 states to 17843 states and 23989 transitions. [2021-08-27 16:30:36,606 INFO L704 BuchiCegarLoop]: Abstraction has 17843 states and 23989 transitions. [2021-08-27 16:30:36,606 INFO L587 BuchiCegarLoop]: Abstraction has 17843 states and 23989 transitions. [2021-08-27 16:30:36,606 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-08-27 16:30:36,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17843 states and 23989 transitions. [2021-08-27 16:30:36,746 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17364 [2021-08-27 16:30:36,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:36,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:36,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,748 INFO L791 eck$LassoCheckResult]: Stem: 144245#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 144207#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 144208#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 143875#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 143876#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143941#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143942#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144031#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144179#L377-1 assume !(0 == ~M_E~0); 143948#L518-1 assume !(0 == ~T1_E~0); 143949#L523-1 assume !(0 == ~T2_E~0); 144099#L528-1 assume !(0 == ~T3_E~0); 144100#L533-1 assume !(0 == ~T4_E~0); 143977#L538-1 assume !(0 == ~E_M~0); 143859#L543-1 assume !(0 == ~E_1~0); 143860#L548-1 assume !(0 == ~E_2~0); 144225#L553-1 assume !(0 == ~E_3~0); 144147#L558-1 assume !(0 == ~E_4~0); 144148#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 144102#L254 assume !(1 == ~m_pc~0); 143752#L254-2 is_master_triggered_~__retres1~0 := 0; 143753#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 144072#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 143957#L641 assume !(0 != activate_threads_~tmp~1); 143958#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 144034#L273 assume !(1 == ~t1_pc~0); 143855#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 144236#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 144045#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 144046#L649 assume !(0 != activate_threads_~tmp___0~0); 144264#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143856#L292 assume !(1 == ~t2_pc~0); 143857#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 144263#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 144226#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 143914#L657 assume !(0 != activate_threads_~tmp___1~0); 143915#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 144261#L311 assume !(1 == ~t3_pc~0); 143908#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 143907#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 143723#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 143724#L665 assume !(0 != activate_threads_~tmp___2~0); 144260#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 144259#L330 assume !(1 == ~t4_pc~0); 144258#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 143858#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 143761#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 143762#L673 assume !(0 != activate_threads_~tmp___3~0); 143943#L673-2 assume !(1 == ~M_E~0); 144255#L576-1 assume !(1 == ~T1_E~0); 144254#L581-1 assume !(1 == ~T2_E~0); 144253#L586-1 assume !(1 == ~T3_E~0); 144252#L591-1 assume !(1 == ~T4_E~0); 144251#L596-1 assume !(1 == ~E_M~0); 144250#L601-1 assume !(1 == ~E_1~0); 144062#L606-1 assume !(1 == ~E_2~0); 144063#L611-1 assume !(1 == ~E_3~0); 144129#L616-1 assume !(1 == ~E_4~0); 144130#L807-1 assume !false; 144420#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 144413#L493 [2021-08-27 16:30:36,748 INFO L793 eck$LassoCheckResult]: Loop: 144413#L493 assume !false; 144411#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 144408#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 144401#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 144395#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 144388#L432 assume 0 != eval_~tmp~0; 144389#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 145167#L440 assume !(0 != eval_~tmp_ndt_1~0); 144634#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 144608#L454 assume !(0 != eval_~tmp_ndt_2~0); 144444#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 144438#L468 assume !(0 != eval_~tmp_ndt_3~0); 144440#L465 assume !(0 == ~t3_st~0); 144421#L479 assume !(0 == ~t4_st~0); 144413#L493 [2021-08-27 16:30:36,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 3 times [2021-08-27 16:30:36,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,749 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835871335] [2021-08-27 16:30:36,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,749 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,754 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,767 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,767 INFO L82 PathProgramCache]: Analyzing trace with hash -1053426655, now seen corresponding path program 1 times [2021-08-27 16:30:36,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520744502] [2021-08-27 16:30:36,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,768 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,773 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,774 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,775 INFO L82 PathProgramCache]: Analyzing trace with hash -779945658, now seen corresponding path program 1 times [2021-08-27 16:30:36,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,775 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220062557] [2021-08-27 16:30:36,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,776 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:36,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:36,792 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:36,792 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220062557] [2021-08-27 16:30:36,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220062557] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:36,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:36,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:36,793 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609289675] [2021-08-27 16:30:36,872 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:36,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:36,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:36,873 INFO L87 Difference]: Start difference. First operand 17843 states and 23989 transitions. cyclomatic complexity: 6154 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:36,968 INFO L93 Difference]: Finished difference Result 31099 states and 41563 transitions. [2021-08-27 16:30:36,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:36,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31099 states and 41563 transitions. [2021-08-27 16:30:37,083 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 30232 [2021-08-27 16:30:37,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31099 states to 31099 states and 41563 transitions. [2021-08-27 16:30:37,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31099 [2021-08-27 16:30:37,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31099 [2021-08-27 16:30:37,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31099 states and 41563 transitions. [2021-08-27 16:30:37,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:37,199 INFO L681 BuchiCegarLoop]: Abstraction has 31099 states and 41563 transitions. [2021-08-27 16:30:37,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31099 states and 41563 transitions. [2021-08-27 16:30:37,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31099 to 30027. [2021-08-27 16:30:37,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30027 states, 30027 states have (on average 1.3404935557997801) internal successors, (40251), 30026 states have internal predecessors, (40251), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30027 states to 30027 states and 40251 transitions. [2021-08-27 16:30:37,491 INFO L704 BuchiCegarLoop]: Abstraction has 30027 states and 40251 transitions. [2021-08-27 16:30:37,491 INFO L587 BuchiCegarLoop]: Abstraction has 30027 states and 40251 transitions. [2021-08-27 16:30:37,491 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-08-27 16:30:37,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30027 states and 40251 transitions. [2021-08-27 16:30:37,678 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 29160 [2021-08-27 16:30:37,678 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:37,678 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:37,679 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,679 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,679 INFO L791 eck$LassoCheckResult]: Stem: 193194#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 193152#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 193153#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 192823#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 192824#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 192890#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 192891#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 192980#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193128#L377-1 assume !(0 == ~M_E~0); 192896#L518-1 assume !(0 == ~T1_E~0); 192897#L523-1 assume !(0 == ~T2_E~0); 193051#L528-1 assume !(0 == ~T3_E~0); 193052#L533-1 assume !(0 == ~T4_E~0); 192928#L538-1 assume !(0 == ~E_M~0); 192808#L543-1 assume !(0 == ~E_1~0); 192809#L548-1 assume !(0 == ~E_2~0); 193174#L553-1 assume !(0 == ~E_3~0); 193096#L558-1 assume !(0 == ~E_4~0); 193097#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 193054#L254 assume !(1 == ~m_pc~0); 192702#L254-2 is_master_triggered_~__retres1~0 := 0; 192703#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 193026#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 192906#L641 assume !(0 != activate_threads_~tmp~1); 192907#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 192984#L273 assume !(1 == ~t1_pc~0); 192803#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 193188#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 192998#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 192999#L649 assume !(0 != activate_threads_~tmp___0~0); 193212#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 192805#L292 assume !(1 == ~t2_pc~0); 192806#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 193211#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 193179#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 192860#L657 assume !(0 != activate_threads_~tmp___1~0); 192861#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 193209#L311 assume !(1 == ~t3_pc~0); 192856#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 192855#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 192673#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 192674#L665 assume !(0 != activate_threads_~tmp___2~0); 193208#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 193207#L330 assume !(1 == ~t4_pc~0); 193206#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 192807#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 192711#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 192712#L673 assume !(0 != activate_threads_~tmp___3~0); 192892#L673-2 assume !(1 == ~M_E~0); 193203#L576-1 assume !(1 == ~T1_E~0); 193202#L581-1 assume !(1 == ~T2_E~0); 193201#L586-1 assume !(1 == ~T3_E~0); 193200#L591-1 assume !(1 == ~T4_E~0); 193199#L596-1 assume !(1 == ~E_M~0); 193198#L601-1 assume !(1 == ~E_1~0); 193018#L606-1 assume !(1 == ~E_2~0); 193019#L611-1 assume !(1 == ~E_3~0); 193080#L616-1 assume !(1 == ~E_4~0); 193081#L807-1 assume !false; 200500#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 200496#L493 [2021-08-27 16:30:37,679 INFO L793 eck$LassoCheckResult]: Loop: 200496#L493 assume !false; 200494#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 200491#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 200488#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 200485#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 200483#L432 assume 0 != eval_~tmp~0; 200480#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 200477#L440 assume !(0 != eval_~tmp_ndt_1~0); 200473#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 197693#L454 assume !(0 != eval_~tmp_ndt_2~0); 199772#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 199764#L468 assume !(0 != eval_~tmp_ndt_3~0); 199765#L465 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 200505#L482 assume !(0 != eval_~tmp_ndt_4~0); 200501#L479 assume !(0 == ~t4_st~0); 200496#L493 [2021-08-27 16:30:37,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 4 times [2021-08-27 16:30:37,680 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,680 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745124729] [2021-08-27 16:30:37,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,680 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,685 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:37,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,693 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:37,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,694 INFO L82 PathProgramCache]: Analyzing trace with hash 1703362212, now seen corresponding path program 1 times [2021-08-27 16:30:37,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,694 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [643839709] [2021-08-27 16:30:37,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,694 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,696 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:37,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,698 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:37,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,698 INFO L82 PathProgramCache]: Analyzing trace with hash 1591338527, now seen corresponding path program 1 times [2021-08-27 16:30:37,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671118026] [2021-08-27 16:30:37,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,698 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:37,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:37,711 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:37,712 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671118026] [2021-08-27 16:30:37,712 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671118026] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:37,712 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:37,712 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:37,712 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365863951] [2021-08-27 16:30:37,813 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:37,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:37,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:37,814 INFO L87 Difference]: Start difference. First operand 30027 states and 40251 transitions. cyclomatic complexity: 10232 Second operand has 3 states, 2 states have (on average 37.5) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:37,933 INFO L93 Difference]: Finished difference Result 38391 states and 51239 transitions. [2021-08-27 16:30:37,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:37,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38391 states and 51239 transitions. [2021-08-27 16:30:38,066 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 37508 [2021-08-27 16:30:38,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38391 states to 38391 states and 51239 transitions. [2021-08-27 16:30:38,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38391 [2021-08-27 16:30:38,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38391 [2021-08-27 16:30:38,171 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38391 states and 51239 transitions. [2021-08-27 16:30:38,207 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:38,207 INFO L681 BuchiCegarLoop]: Abstraction has 38391 states and 51239 transitions. [2021-08-27 16:30:38,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38391 states and 51239 transitions. [2021-08-27 16:30:38,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38391 to 38007. [2021-08-27 16:30:38,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38007 states, 38007 states have (on average 1.3380429920804062) internal successors, (50855), 38006 states have internal predecessors, (50855), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:38,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38007 states to 38007 states and 50855 transitions. [2021-08-27 16:30:38,873 INFO L704 BuchiCegarLoop]: Abstraction has 38007 states and 50855 transitions. [2021-08-27 16:30:38,873 INFO L587 BuchiCegarLoop]: Abstraction has 38007 states and 50855 transitions. [2021-08-27 16:30:38,873 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-08-27 16:30:38,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38007 states and 50855 transitions. [2021-08-27 16:30:38,973 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 37124 [2021-08-27 16:30:38,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:38,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:38,974 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:38,974 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:38,974 INFO L791 eck$LassoCheckResult]: Stem: 261632#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 261580#L-1 havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 261581#L770 havoc start_simulation_#t~ret21, start_simulation_#t~ret22, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 261248#L350 assume 1 == ~m_i~0;~m_st~0 := 0; 261249#L357-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 261316#L362-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 261317#L367-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 261406#L372-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 261550#L377-1 assume !(0 == ~M_E~0); 261322#L518-1 assume !(0 == ~T1_E~0); 261323#L523-1 assume !(0 == ~T2_E~0); 261476#L528-1 assume !(0 == ~T3_E~0); 261477#L533-1 assume !(0 == ~T4_E~0); 261353#L538-1 assume !(0 == ~E_M~0); 261232#L543-1 assume !(0 == ~E_1~0); 261233#L548-1 assume !(0 == ~E_2~0); 261606#L553-1 assume !(0 == ~E_3~0); 261524#L558-1 assume !(0 == ~E_4~0); 261525#L563-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 261479#L254 assume !(1 == ~m_pc~0); 261128#L254-2 is_master_triggered_~__retres1~0 := 0; 261129#L265 is_master_triggered_#res := is_master_triggered_~__retres1~0; 261447#L266 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 261333#L641 assume !(0 != activate_threads_~tmp~1); 261334#L641-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 261411#L273 assume !(1 == ~t1_pc~0); 261227#L273-2 is_transmit1_triggered_~__retres1~1 := 0; 261622#L284 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 261420#L285 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 261421#L649 assume !(0 != activate_threads_~tmp___0~0); 261651#L649-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 261229#L292 assume !(1 == ~t2_pc~0); 261230#L292-2 is_transmit2_triggered_~__retres1~2 := 0; 261650#L303 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 261612#L304 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 261286#L657 assume !(0 != activate_threads_~tmp___1~0); 261287#L657-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 261648#L311 assume !(1 == ~t3_pc~0); 261282#L311-2 is_transmit3_triggered_~__retres1~3 := 0; 261281#L322 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 261099#L323 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 261100#L665 assume !(0 != activate_threads_~tmp___2~0); 261647#L665-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 261646#L330 assume !(1 == ~t4_pc~0); 261645#L330-2 is_transmit4_triggered_~__retres1~4 := 0; 261231#L341 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 261137#L342 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 261138#L673 assume !(0 != activate_threads_~tmp___3~0); 261318#L673-2 assume !(1 == ~M_E~0); 261642#L576-1 assume !(1 == ~T1_E~0); 261641#L581-1 assume !(1 == ~T2_E~0); 261640#L586-1 assume !(1 == ~T3_E~0); 261639#L591-1 assume !(1 == ~T4_E~0); 261638#L596-1 assume !(1 == ~E_M~0); 261637#L601-1 assume !(1 == ~E_1~0); 261439#L606-1 assume !(1 == ~E_2~0); 261440#L611-1 assume !(1 == ~E_3~0); 261508#L616-1 assume !(1 == ~E_4~0); 261509#L807-1 assume !false; 269053#L808 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 269046#L493 [2021-08-27 16:30:38,974 INFO L793 eck$LassoCheckResult]: Loop: 269046#L493 assume !false; 269042#L428 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 269036#L390 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 269031#L417 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 269026#L418 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 269021#L432 assume 0 != eval_~tmp~0; 269016#L432-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 269010#L440 assume !(0 != eval_~tmp_ndt_1~0); 269004#L437 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 268619#L454 assume !(0 != eval_~tmp_ndt_2~0); 269001#L451 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 266554#L468 assume !(0 != eval_~tmp_ndt_3~0); 269069#L465 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 269064#L482 assume !(0 != eval_~tmp_ndt_4~0); 269059#L479 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 269051#L496 assume !(0 != eval_~tmp_ndt_5~0); 269046#L493 [2021-08-27 16:30:38,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:38,975 INFO L82 PathProgramCache]: Analyzing trace with hash -1232031258, now seen corresponding path program 5 times [2021-08-27 16:30:38,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:38,975 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145524777] [2021-08-27 16:30:38,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:38,975 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:38,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,984 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:38,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,994 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:38,995 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:38,995 INFO L82 PathProgramCache]: Analyzing trace with hash 1264617455, now seen corresponding path program 1 times [2021-08-27 16:30:38,995 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:38,995 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134843006] [2021-08-27 16:30:38,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:38,995 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:38,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,997 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:38,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,999 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:39,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:39,000 INFO L82 PathProgramCache]: Analyzing trace with hash 2086850516, now seen corresponding path program 1 times [2021-08-27 16:30:39,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:39,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902496374] [2021-08-27 16:30:39,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:39,001 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:39,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,008 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:39,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,020 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:40,615 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 27.08 04:30:40 BoogieIcfgContainer [2021-08-27 16:30:40,615 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-08-27 16:30:40,615 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-08-27 16:30:40,615 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-08-27 16:30:40,616 INFO L275 PluginConnector]: Witness Printer initialized [2021-08-27 16:30:40,616 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:32" (3/4) ... [2021-08-27 16:30:40,617 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-08-27 16:30:40,642 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-08-27 16:30:40,643 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-08-27 16:30:40,644 INFO L168 Benchmark]: Toolchain (without parser) took 9607.13 ms. Allocated memory was 67.1 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 46.4 MB in the beginning and 2.2 GB in the end (delta: -2.1 GB). Peak memory consumption was 395.0 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,644 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 67.1 MB. Free memory was 47.7 MB in the beginning and 47.7 MB in the end (delta: 32.5 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-08-27 16:30:40,644 INFO L168 Benchmark]: CACSL2BoogieTranslator took 314.29 ms. Allocated memory is still 67.1 MB. Free memory was 46.2 MB in the beginning and 47.2 MB in the end (delta: -1.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,644 INFO L168 Benchmark]: Boogie Procedure Inliner took 51.67 ms. Allocated memory is still 67.1 MB. Free memory was 47.2 MB in the beginning and 42.9 MB in the end (delta: 4.3 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,645 INFO L168 Benchmark]: Boogie Preprocessor took 47.22 ms. Allocated memory is still 67.1 MB. Free memory was 42.9 MB in the beginning and 39.1 MB in the end (delta: 3.8 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,645 INFO L168 Benchmark]: RCFGBuilder took 845.58 ms. Allocated memory was 67.1 MB in the beginning and 88.1 MB in the end (delta: 21.0 MB). Free memory was 39.1 MB in the beginning and 62.4 MB in the end (delta: -23.3 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,645 INFO L168 Benchmark]: BuchiAutomizer took 8315.98 ms. Allocated memory was 88.1 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 62.4 MB in the beginning and 2.2 GB in the end (delta: -2.1 GB). Peak memory consumption was 616.8 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,645 INFO L168 Benchmark]: Witness Printer took 27.50 ms. Allocated memory is still 2.6 GB. Free memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:40,646 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 67.1 MB. Free memory was 47.7 MB in the beginning and 47.7 MB in the end (delta: 32.5 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 314.29 ms. Allocated memory is still 67.1 MB. Free memory was 46.2 MB in the beginning and 47.2 MB in the end (delta: -1.0 MB). Peak memory consumption was 14.7 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 51.67 ms. Allocated memory is still 67.1 MB. Free memory was 47.2 MB in the beginning and 42.9 MB in the end (delta: 4.3 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 47.22 ms. Allocated memory is still 67.1 MB. Free memory was 42.9 MB in the beginning and 39.1 MB in the end (delta: 3.8 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 845.58 ms. Allocated memory was 67.1 MB in the beginning and 88.1 MB in the end (delta: 21.0 MB). Free memory was 39.1 MB in the beginning and 62.4 MB in the end (delta: -23.3 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 8315.98 ms. Allocated memory was 88.1 MB in the beginning and 2.6 GB in the end (delta: 2.5 GB). Free memory was 62.4 MB in the beginning and 2.2 GB in the end (delta: -2.1 GB). Peak memory consumption was 616.8 MB. Max. memory is 16.1 GB. * Witness Printer took 27.50 ms. Allocated memory is still 2.6 GB. Free memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 38007 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.2s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.4s. Büchi inclusion checks took 0.7s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 1885.7ms AutomataMinimizationTime, 21 MinimizatonAttempts, 8610 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 1.0s Buchi closure took 0.0s. Biggest automaton had 38007 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 13237 SDtfs, 13944 SDslu, 8297 SDs, 0 SdLazy, 473 SolverSat, 231 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 412.7ms Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 427]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=17006} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=17006, tmp=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e232198=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f1495e0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6f4cdaa6=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e32335c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ced02f2=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1160aa63=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1870cb03=0, tmp=0, \result=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@279b190=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f79aa57=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57fe754a=0, NULL=17008, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3908294a=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6aaf012a=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28b00998=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, NULL=17009, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=17007, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 427]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int m_i ; [L27] int t1_i ; [L28] int t2_i ; [L29] int t3_i ; [L30] int t4_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int T2_E = 2; [L34] int T3_E = 2; [L35] int T4_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L39] int E_3 = 2; [L40] int E_4 = 2; [L47] int token ; [L49] int local ; [L852] int __retres1 ; [L764] m_i = 1 [L765] t1_i = 1 [L766] t2_i = 1 [L767] t3_i = 1 [L768] t4_i = 1 [L793] int kernel_st ; [L794] int tmp ; [L795] int tmp___0 ; [L799] kernel_st = 0 [L357] COND TRUE m_i == 1 [L358] m_st = 0 [L362] COND TRUE t1_i == 1 [L363] t1_st = 0 [L367] COND TRUE t2_i == 1 [L368] t2_st = 0 [L372] COND TRUE t3_i == 1 [L373] t3_st = 0 [L377] COND TRUE t4_i == 1 [L378] t4_st = 0 [L518] COND FALSE !(M_E == 0) [L523] COND FALSE !(T1_E == 0) [L528] COND FALSE !(T2_E == 0) [L533] COND FALSE !(T3_E == 0) [L538] COND FALSE !(T4_E == 0) [L543] COND FALSE !(E_M == 0) [L548] COND FALSE !(E_1 == 0) [L553] COND FALSE !(E_2 == 0) [L558] COND FALSE !(E_3 == 0) [L563] COND FALSE !(E_4 == 0) [L631] int tmp ; [L632] int tmp___0 ; [L633] int tmp___1 ; [L634] int tmp___2 ; [L635] int tmp___3 ; [L251] int __retres1 ; [L254] COND FALSE !(m_pc == 1) [L264] __retres1 = 0 [L266] return (__retres1); [L639] tmp = is_master_triggered() [L641] COND FALSE !(\read(tmp)) [L270] int __retres1 ; [L273] COND FALSE !(t1_pc == 1) [L283] __retres1 = 0 [L285] return (__retres1); [L647] tmp___0 = is_transmit1_triggered() [L649] COND FALSE !(\read(tmp___0)) [L289] int __retres1 ; [L292] COND FALSE !(t2_pc == 1) [L302] __retres1 = 0 [L304] return (__retres1); [L655] tmp___1 = is_transmit2_triggered() [L657] COND FALSE !(\read(tmp___1)) [L308] int __retres1 ; [L311] COND FALSE !(t3_pc == 1) [L321] __retres1 = 0 [L323] return (__retres1); [L663] tmp___2 = is_transmit3_triggered() [L665] COND FALSE !(\read(tmp___2)) [L327] int __retres1 ; [L330] COND FALSE !(t4_pc == 1) [L340] __retres1 = 0 [L342] return (__retres1); [L671] tmp___3 = is_transmit4_triggered() [L673] COND FALSE !(\read(tmp___3)) [L576] COND FALSE !(M_E == 1) [L581] COND FALSE !(T1_E == 1) [L586] COND FALSE !(T2_E == 1) [L591] COND FALSE !(T3_E == 1) [L596] COND FALSE !(T4_E == 1) [L601] COND FALSE !(E_M == 1) [L606] COND FALSE !(E_1 == 1) [L611] COND FALSE !(E_2 == 1) [L616] COND FALSE !(E_3 == 1) [L621] COND FALSE !(E_4 == 1) [L807] COND TRUE 1 [L810] kernel_st = 1 [L423] int tmp ; Loop: [L427] COND TRUE 1 [L387] int __retres1 ; [L390] COND TRUE m_st == 0 [L391] __retres1 = 1 [L418] return (__retres1); [L430] tmp = exists_runnable_thread() [L432] COND TRUE \read(tmp) [L437] COND TRUE m_st == 0 [L438] int tmp_ndt_1; [L439] tmp_ndt_1 = __VERIFIER_nondet_int() [L440] COND FALSE !(\read(tmp_ndt_1)) [L451] COND TRUE t1_st == 0 [L452] int tmp_ndt_2; [L453] tmp_ndt_2 = __VERIFIER_nondet_int() [L454] COND FALSE !(\read(tmp_ndt_2)) [L465] COND TRUE t2_st == 0 [L466] int tmp_ndt_3; [L467] tmp_ndt_3 = __VERIFIER_nondet_int() [L468] COND FALSE !(\read(tmp_ndt_3)) [L479] COND TRUE t3_st == 0 [L480] int tmp_ndt_4; [L481] tmp_ndt_4 = __VERIFIER_nondet_int() [L482] COND FALSE !(\read(tmp_ndt_4)) [L493] COND TRUE t4_st == 0 [L494] int tmp_ndt_5; [L495] tmp_ndt_5 = __VERIFIER_nondet_int() [L496] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-08-27 16:30:40,684 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...