./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 20ed64ec Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c23fa9fd10aa70a52586ccd054da306bf699445a ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.2.1-dev-20ed64e [2021-08-27 16:30:31,044 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-08-27 16:30:31,046 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-08-27 16:30:31,074 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-08-27 16:30:31,074 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-08-27 16:30:31,075 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-08-27 16:30:31,076 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-08-27 16:30:31,077 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-08-27 16:30:31,081 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-08-27 16:30:31,087 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-08-27 16:30:31,088 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-08-27 16:30:31,088 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-08-27 16:30:31,089 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-08-27 16:30:31,089 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-08-27 16:30:31,090 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-08-27 16:30:31,093 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-08-27 16:30:31,094 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-08-27 16:30:31,096 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-08-27 16:30:31,097 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-08-27 16:30:31,101 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-08-27 16:30:31,102 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-08-27 16:30:31,103 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-08-27 16:30:31,107 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-08-27 16:30:31,109 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-08-27 16:30:31,112 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-08-27 16:30:31,115 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-08-27 16:30:31,116 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-08-27 16:30:31,116 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-08-27 16:30:31,117 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-08-27 16:30:31,117 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-08-27 16:30:31,119 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-08-27 16:30:31,119 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-08-27 16:30:31,120 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-08-27 16:30:31,120 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-08-27 16:30:31,122 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-08-27 16:30:31,124 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-08-27 16:30:31,124 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-08-27 16:30:31,125 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-08-27 16:30:31,125 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-08-27 16:30:31,126 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-08-27 16:30:31,127 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-08-27 16:30:31,128 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-08-27 16:30:31,154 INFO L113 SettingsManager]: Loading preferences was successful [2021-08-27 16:30:31,154 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-08-27 16:30:31,155 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-08-27 16:30:31,156 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-08-27 16:30:31,157 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-08-27 16:30:31,158 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-08-27 16:30:31,158 INFO L138 SettingsManager]: * Use SBE=true [2021-08-27 16:30:31,158 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-08-27 16:30:31,158 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-08-27 16:30:31,158 INFO L138 SettingsManager]: * Use old map elimination=false [2021-08-27 16:30:31,159 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-08-27 16:30:31,159 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-08-27 16:30:31,159 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-08-27 16:30:31,159 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * sizeof long=4 [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-08-27 16:30:31,160 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * sizeof long double=12 [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * Use constant arrays=true [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-08-27 16:30:31,161 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-08-27 16:30:31,161 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-08-27 16:30:31,162 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-08-27 16:30:31,162 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-08-27 16:30:31,162 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-08-27 16:30:31,163 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-08-27 16:30:31,163 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c23fa9fd10aa70a52586ccd054da306bf699445a [2021-08-27 16:30:31,436 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-08-27 16:30:31,459 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-08-27 16:30:31,461 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-08-27 16:30:31,462 INFO L271 PluginConnector]: Initializing CDTParser... [2021-08-27 16:30:31,463 INFO L275 PluginConnector]: CDTParser initialized [2021-08-27 16:30:31,463 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-08-27 16:30:31,524 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8917ab9f2/730cd23636b7492588660e62608f6930/FLAG1975e21c4 [2021-08-27 16:30:31,927 INFO L306 CDTParser]: Found 1 translation units. [2021-08-27 16:30:31,927 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2021-08-27 16:30:31,940 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8917ab9f2/730cd23636b7492588660e62608f6930/FLAG1975e21c4 [2021-08-27 16:30:31,954 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8917ab9f2/730cd23636b7492588660e62608f6930 [2021-08-27 16:30:31,956 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-08-27 16:30:31,957 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-08-27 16:30:31,958 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-08-27 16:30:31,958 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-08-27 16:30:31,961 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-08-27 16:30:31,961 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,962 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2a03fb06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:31, skipping insertion in model container [2021-08-27 16:30:31,962 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.08 04:30:31" (1/1) ... [2021-08-27 16:30:31,967 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-08-27 16:30:31,994 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-08-27 16:30:32,074 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-08-27 16:30:32,157 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-27 16:30:32,165 INFO L203 MainTranslator]: Completed pre-run [2021-08-27 16:30:32,174 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.05.cil-1.c[366,379] [2021-08-27 16:30:32,203 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-27 16:30:32,216 INFO L208 MainTranslator]: Completed translation [2021-08-27 16:30:32,217 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32 WrapperNode [2021-08-27 16:30:32,217 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-08-27 16:30:32,218 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-08-27 16:30:32,218 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-08-27 16:30:32,218 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-08-27 16:30:32,223 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,230 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,262 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-08-27 16:30:32,263 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-08-27 16:30:32,263 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-08-27 16:30:32,263 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-08-27 16:30:32,271 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,282 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,287 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,288 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,300 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,336 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,339 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,343 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-08-27 16:30:32,344 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-08-27 16:30:32,344 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-08-27 16:30:32,344 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-08-27 16:30:32,345 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (1/1) ... [2021-08-27 16:30:32,349 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-08-27 16:30:32,354 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-08-27 16:30:32,402 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-08-27 16:30:32,422 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-08-27 16:30:32,448 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-08-27 16:30:32,448 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-08-27 16:30:32,448 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-08-27 16:30:32,448 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-08-27 16:30:33,411 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-08-27 16:30:33,412 INFO L299 CfgBuilder]: Removed 196 assume(true) statements. [2021-08-27 16:30:33,414 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:33 BoogieIcfgContainer [2021-08-27 16:30:33,414 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-08-27 16:30:33,414 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-08-27 16:30:33,414 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-08-27 16:30:33,416 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-08-27 16:30:33,417 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:33,417 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.08 04:30:31" (1/3) ... [2021-08-27 16:30:33,418 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5cc7dfcd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.08 04:30:33, skipping insertion in model container [2021-08-27 16:30:33,418 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:33,418 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.08 04:30:32" (2/3) ... [2021-08-27 16:30:33,418 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5cc7dfcd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.08 04:30:33, skipping insertion in model container [2021-08-27 16:30:33,418 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-27 16:30:33,418 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:33" (3/3) ... [2021-08-27 16:30:33,419 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2021-08-27 16:30:33,457 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-08-27 16:30:33,457 INFO L360 BuchiCegarLoop]: Hoare is false [2021-08-27 16:30:33,458 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-08-27 16:30:33,458 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-08-27 16:30:33,458 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-08-27 16:30:33,458 INFO L364 BuchiCegarLoop]: Difference is false [2021-08-27 16:30:33,458 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-08-27 16:30:33,458 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-08-27 16:30:33,482 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-08-27 16:30:33,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,511 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,519 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,519 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,519 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-08-27 16:30:33,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 453 [2021-08-27 16:30:33,533 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,536 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,538 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,547 INFO L791 eck$LassoCheckResult]: Stem: 515#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 439#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 435#L883true havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 66#L399true assume !(1 == ~m_i~0);~m_st~0 := 2; 109#L406-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 429#L411-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 407#L416-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 482#L421-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 330#L426-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 132#L431-1true assume !(0 == ~M_E~0); 245#L591-1true assume !(0 == ~T1_E~0); 219#L596-1true assume !(0 == ~T2_E~0); 293#L601-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 260#L606-1true assume !(0 == ~T4_E~0); 491#L611-1true assume !(0 == ~T5_E~0); 342#L616-1true assume !(0 == ~E_M~0); 352#L621-1true assume !(0 == ~E_1~0); 58#L626-1true assume !(0 == ~E_2~0); 308#L631-1true assume !(0 == ~E_3~0); 153#L636-1true assume !(0 == ~E_4~0); 71#L641-1true assume 0 == ~E_5~0;~E_5~0 := 1; 163#L646-1true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63#L284true assume 1 == ~m_pc~0; 243#L285true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 134#L295true is_master_triggered_#res := is_master_triggered_~__retres1~0; 56#L296true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 522#L735true assume !(0 != activate_threads_~tmp~1); 113#L735-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 252#L303true assume !(1 == ~t1_pc~0); 487#L303-2true is_transmit1_triggered_~__retres1~1 := 0; 509#L314true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52#L315true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 455#L743true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 67#L743-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217#L322true assume 1 == ~t2_pc~0; 5#L323true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 194#L333true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40#L334true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26#L751true assume !(0 != activate_threads_~tmp___1~0); 397#L751-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 74#L341true assume !(1 == ~t3_pc~0); 492#L341-2true is_transmit3_triggered_~__retres1~3 := 0; 501#L352true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83#L353true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 436#L759true assume !(0 != activate_threads_~tmp___2~0); 443#L759-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 274#L360true assume 1 == ~t4_pc~0; 204#L361true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 462#L371true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 427#L372true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 505#L767true assume !(0 != activate_threads_~tmp___3~0); 424#L767-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 358#L379true assume !(1 == ~t5_pc~0); 95#L379-2true is_transmit5_triggered_~__retres1~5 := 0; 223#L390true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 333#L391true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 412#L775true assume !(0 != activate_threads_~tmp___4~0); 15#L775-2true assume !(1 == ~M_E~0); 284#L659-1true assume !(1 == ~T1_E~0); 170#L664-1true assume !(1 == ~T2_E~0); 44#L669-1true assume !(1 == ~T3_E~0); 322#L674-1true assume !(1 == ~T4_E~0); 332#L679-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 94#L684-1true assume !(1 == ~E_M~0); 218#L689-1true assume !(1 == ~E_1~0); 512#L694-1true assume !(1 == ~E_2~0); 216#L699-1true assume !(1 == ~E_3~0); 319#L704-1true assume !(1 == ~E_4~0); 188#L709-1true assume !(1 == ~E_5~0); 51#L920-1true [2021-08-27 16:30:33,548 INFO L793 eck$LassoCheckResult]: Loop: 51#L920-1true assume !false; 106#L921true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 103#L566true assume !true; 258#L581true start_simulation_~kernel_st~0 := 2; 376#L399-1true start_simulation_~kernel_st~0 := 3; 110#L591-2true assume 0 == ~M_E~0;~M_E~0 := 1; 477#L591-4true assume !(0 == ~T1_E~0); 107#L596-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 241#L601-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 388#L606-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 271#L611-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 278#L616-3true assume 0 == ~E_M~0;~E_M~0 := 1; 54#L621-3true assume 0 == ~E_1~0;~E_1~0 := 1; 30#L626-3true assume 0 == ~E_2~0;~E_2~0 := 1; 527#L631-3true assume !(0 == ~E_3~0); 31#L636-3true assume 0 == ~E_4~0;~E_4~0 := 1; 59#L641-3true assume 0 == ~E_5~0;~E_5~0 := 1; 208#L646-3true havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27#L284-21true assume 1 == ~m_pc~0; 414#L285-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 49#L295-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 61#L296-7true activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 195#L735-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12#L735-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 143#L303-21true assume 1 == ~t1_pc~0; 336#L304-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 175#L314-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 248#L315-7true activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 400#L743-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 177#L743-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 345#L322-21true assume 1 == ~t2_pc~0; 192#L323-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 359#L333-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 365#L334-7true activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 440#L751-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 73#L751-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24#L341-21true assume !(1 == ~t3_pc~0); 426#L341-23true is_transmit3_triggered_~__retres1~3 := 0; 246#L352-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 239#L353-7true activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 259#L759-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65#L759-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 445#L360-21true assume !(1 == ~t4_pc~0); 102#L360-23true is_transmit4_triggered_~__retres1~4 := 0; 430#L371-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 449#L372-7true activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 296#L767-21true assume !(0 != activate_threads_~tmp___3~0); 434#L767-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 272#L379-21true assume !(1 == ~t5_pc~0); 32#L379-23true is_transmit5_triggered_~__retres1~5 := 0; 100#L390-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 77#L391-7true activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 331#L775-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13#L775-23true assume 1 == ~M_E~0;~M_E~0 := 2; 81#L659-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 474#L664-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 33#L669-3true assume !(1 == ~T3_E~0); 507#L674-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 29#L679-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 196#L684-3true assume 1 == ~E_M~0;~E_M~0 := 2; 3#L689-3true assume 1 == ~E_1~0;~E_1~0 := 2; 146#L694-3true assume 1 == ~E_2~0;~E_2~0 := 2; 21#L699-3true assume 1 == ~E_3~0;~E_3~0 := 2; 273#L704-3true assume 1 == ~E_4~0;~E_4~0 := 2; 360#L709-3true assume !(1 == ~E_5~0); 265#L714-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 133#L444-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 46#L476-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 346#L477-1true start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 385#L939true assume !(0 == start_simulation_~tmp~3); 279#L939-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 410#L444-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 451#L476-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 214#L477-2true stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 39#L894true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 529#L901true stop_simulation_#res := stop_simulation_~__retres2~0; 348#L902true start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 125#L952true assume !(0 != start_simulation_~tmp___0~1); 51#L920-1true [2021-08-27 16:30:33,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,553 INFO L82 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-08-27 16:30:33,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,560 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889419760] [2021-08-27 16:30:33,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,561 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,672 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889419760] [2021-08-27 16:30:33,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889419760] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,672 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,673 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,674 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269141060] [2021-08-27 16:30:33,677 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,677 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,677 INFO L82 PathProgramCache]: Analyzing trace with hash 1122134720, now seen corresponding path program 1 times [2021-08-27 16:30:33,678 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,678 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509952367] [2021-08-27 16:30:33,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,678 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,695 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [509952367] [2021-08-27 16:30:33,695 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [509952367] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:33,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925119193] [2021-08-27 16:30:33,697 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,697 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,712 INFO L87 Difference]: Start difference. First operand has 532 states, 531 states have (on average 1.5480225988700564) internal successors, (822), 531 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,759 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-08-27 16:30:33,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-08-27 16:30:33,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:33,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 527 states and 799 transitions. [2021-08-27 16:30:33,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:33,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:33,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 799 transitions. [2021-08-27 16:30:33,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,796 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-08-27 16:30:33,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 799 transitions. [2021-08-27 16:30:33,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:33,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5161290322580645) internal successors, (799), 526 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 799 transitions. [2021-08-27 16:30:33,835 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-08-27 16:30:33,835 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 799 transitions. [2021-08-27 16:30:33,835 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-08-27 16:30:33,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 799 transitions. [2021-08-27 16:30:33,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:33,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:33,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:33,845 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:33,847 INFO L791 eck$LassoCheckResult]: Stem: 1598#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1582#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1579#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1199#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 1200#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1280#L411-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1567#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1568#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1536#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1321#L431-1 assume !(0 == ~M_E~0); 1322#L591-1 assume !(0 == ~T1_E~0); 1434#L596-1 assume !(0 == ~T2_E~0); 1435#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1477#L606-1 assume !(0 == ~T4_E~0); 1478#L611-1 assume !(0 == ~T5_E~0); 1540#L616-1 assume !(0 == ~E_M~0); 1541#L621-1 assume !(0 == ~E_1~0); 1184#L626-1 assume !(0 == ~E_2~0); 1185#L631-1 assume !(0 == ~E_3~0); 1348#L636-1 assume !(0 == ~E_4~0); 1210#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1211#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1193#L284 assume 1 == ~m_pc~0; 1194#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1324#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1180#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1181#L735 assume !(0 != activate_threads_~tmp~1); 1286#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1287#L303 assume !(1 == ~t1_pc~0); 1467#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 1595#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1174#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1175#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1201#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1202#L322 assume 1 == ~t2_pc~0; 1077#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1078#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1150#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1125#L751 assume !(0 != activate_threads_~tmp___1~0); 1126#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1218#L341 assume !(1 == ~t3_pc~0); 1154#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 1155#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1230#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1231#L759 assume !(0 != activate_threads_~tmp___2~0); 1580#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1498#L360 assume 1 == ~t4_pc~0; 1415#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1416#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1575#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1576#L767 assume !(0 != activate_threads_~tmp___3~0); 1574#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1551#L379 assume !(1 == ~t5_pc~0); 1256#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 1257#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1438#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1537#L775 assume !(0 != activate_threads_~tmp___4~0); 1102#L775-2 assume !(1 == ~M_E~0); 1103#L659-1 assume !(1 == ~T1_E~0); 1371#L664-1 assume !(1 == ~T2_E~0); 1157#L669-1 assume !(1 == ~T3_E~0); 1158#L674-1 assume !(1 == ~T4_E~0); 1528#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1253#L684-1 assume !(1 == ~E_M~0); 1254#L689-1 assume !(1 == ~E_1~0); 1433#L694-1 assume !(1 == ~E_2~0); 1431#L699-1 assume !(1 == ~E_3~0); 1432#L704-1 assume !(1 == ~E_4~0); 1398#L709-1 assume !(1 == ~E_5~0); 1172#L920-1 [2021-08-27 16:30:33,848 INFO L793 eck$LassoCheckResult]: Loop: 1172#L920-1 assume !false; 1173#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1269#L566 assume !false; 1270#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1546#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1266#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1363#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1364#L491 assume !(0 != eval_~tmp~0); 1475#L581 start_simulation_~kernel_st~0 := 2; 1476#L399-1 start_simulation_~kernel_st~0 := 3; 1281#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1282#L591-4 assume !(0 == ~T1_E~0); 1276#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1277#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1459#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1494#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1495#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1177#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1134#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1135#L631-3 assume !(0 == ~E_3~0); 1136#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1137#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1186#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1127#L284-21 assume 1 == ~m_pc~0; 1128#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1167#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1168#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1189#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1095#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1096#L303-21 assume !(1 == ~t1_pc~0); 1336#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 1378#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1379#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1463#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1383#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1384#L322-21 assume 1 == ~t2_pc~0; 1403#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1404#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1552#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1554#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1215#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1122#L341-21 assume 1 == ~t3_pc~0; 1123#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1250#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1456#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1457#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1197#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1198#L360-21 assume !(1 == ~t4_pc~0); 1267#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 1268#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1577#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1511#L767-21 assume !(0 != activate_threads_~tmp___3~0); 1512#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1496#L379-21 assume 1 == ~t5_pc~0; 1092#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1093#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1220#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1221#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1097#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1098#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1226#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1140#L669-3 assume !(1 == ~T3_E~0); 1141#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1132#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1133#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1073#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1074#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1114#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1115#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1497#L709-3 assume !(1 == ~E_5~0); 1486#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1323#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1147#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1161#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 1544#L939 assume !(0 == start_simulation_~tmp~3); 1500#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1501#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1213#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1428#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 1148#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1149#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 1545#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1309#L952 assume !(0 != start_simulation_~tmp___0~1); 1172#L920-1 [2021-08-27 16:30:33,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,850 INFO L82 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-08-27 16:30:33,850 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,850 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [644920593] [2021-08-27 16:30:33,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,851 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,916 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,917 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [644920593] [2021-08-27 16:30:33,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [644920593] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,917 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1889084742] [2021-08-27 16:30:33,918 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:33,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:33,920 INFO L82 PathProgramCache]: Analyzing trace with hash -1521170952, now seen corresponding path program 1 times [2021-08-27 16:30:33,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:33,921 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839320203] [2021-08-27 16:30:33,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:33,921 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:33,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:33,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:33,976 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:33,976 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839320203] [2021-08-27 16:30:33,976 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839320203] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:33,976 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:33,977 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:33,977 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1513858243] [2021-08-27 16:30:33,977 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:33,977 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:33,978 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:33,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:33,978 INFO L87 Difference]: Start difference. First operand 527 states and 799 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:33,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:33,987 INFO L93 Difference]: Finished difference Result 527 states and 798 transitions. [2021-08-27 16:30:33,987 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:33,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 798 transitions. [2021-08-27 16:30:33,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:33,993 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 798 transitions. [2021-08-27 16:30:33,993 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:33,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:33,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 798 transitions. [2021-08-27 16:30:33,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:33,996 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-08-27 16:30:33,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 798 transitions. [2021-08-27 16:30:34,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5142314990512333) internal successors, (798), 526 states have internal predecessors, (798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 798 transitions. [2021-08-27 16:30:34,030 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-08-27 16:30:34,030 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 798 transitions. [2021-08-27 16:30:34,030 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-08-27 16:30:34,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 798 transitions. [2021-08-27 16:30:34,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,034 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,034 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,034 INFO L791 eck$LassoCheckResult]: Stem: 2659#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2643#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2640#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2260#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 2261#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2341#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2628#L416-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2629#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2597#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2382#L431-1 assume !(0 == ~M_E~0); 2383#L591-1 assume !(0 == ~T1_E~0); 2495#L596-1 assume !(0 == ~T2_E~0); 2496#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2538#L606-1 assume !(0 == ~T4_E~0); 2539#L611-1 assume !(0 == ~T5_E~0); 2601#L616-1 assume !(0 == ~E_M~0); 2602#L621-1 assume !(0 == ~E_1~0); 2245#L626-1 assume !(0 == ~E_2~0); 2246#L631-1 assume !(0 == ~E_3~0); 2409#L636-1 assume !(0 == ~E_4~0); 2271#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2272#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2254#L284 assume 1 == ~m_pc~0; 2255#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2385#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2241#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2242#L735 assume !(0 != activate_threads_~tmp~1); 2347#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2348#L303 assume !(1 == ~t1_pc~0); 2528#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 2656#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2235#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2236#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2262#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2263#L322 assume 1 == ~t2_pc~0; 2138#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2139#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2211#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2186#L751 assume !(0 != activate_threads_~tmp___1~0); 2187#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2279#L341 assume !(1 == ~t3_pc~0); 2215#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 2216#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2291#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2292#L759 assume !(0 != activate_threads_~tmp___2~0); 2641#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2559#L360 assume 1 == ~t4_pc~0; 2476#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2477#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2636#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2637#L767 assume !(0 != activate_threads_~tmp___3~0); 2635#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2612#L379 assume !(1 == ~t5_pc~0); 2317#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 2318#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2499#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2598#L775 assume !(0 != activate_threads_~tmp___4~0); 2163#L775-2 assume !(1 == ~M_E~0); 2164#L659-1 assume !(1 == ~T1_E~0); 2432#L664-1 assume !(1 == ~T2_E~0); 2218#L669-1 assume !(1 == ~T3_E~0); 2219#L674-1 assume !(1 == ~T4_E~0); 2589#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2314#L684-1 assume !(1 == ~E_M~0); 2315#L689-1 assume !(1 == ~E_1~0); 2494#L694-1 assume !(1 == ~E_2~0); 2492#L699-1 assume !(1 == ~E_3~0); 2493#L704-1 assume !(1 == ~E_4~0); 2459#L709-1 assume !(1 == ~E_5~0); 2233#L920-1 [2021-08-27 16:30:34,034 INFO L793 eck$LassoCheckResult]: Loop: 2233#L920-1 assume !false; 2234#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2330#L566 assume !false; 2331#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2607#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2327#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2424#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2425#L491 assume !(0 != eval_~tmp~0); 2536#L581 start_simulation_~kernel_st~0 := 2; 2537#L399-1 start_simulation_~kernel_st~0 := 3; 2342#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2343#L591-4 assume !(0 == ~T1_E~0); 2337#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2338#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2520#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2555#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2556#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2238#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2195#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2196#L631-3 assume !(0 == ~E_3~0); 2197#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2198#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2247#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2190#L284-21 assume !(1 == ~m_pc~0); 2192#L284-23 is_master_triggered_~__retres1~0 := 0; 2228#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2229#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2250#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2156#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2157#L303-21 assume !(1 == ~t1_pc~0); 2397#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 2439#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2440#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2524#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2444#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2445#L322-21 assume 1 == ~t2_pc~0; 2464#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2465#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2613#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2615#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2276#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2183#L341-21 assume 1 == ~t3_pc~0; 2184#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2313#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2517#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2518#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2258#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2259#L360-21 assume 1 == ~t4_pc~0; 2644#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2329#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2638#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2572#L767-21 assume !(0 != activate_threads_~tmp___3~0); 2573#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2557#L379-21 assume 1 == ~t5_pc~0; 2153#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2154#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2281#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2282#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2158#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2159#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2287#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2199#L669-3 assume !(1 == ~T3_E~0); 2200#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2188#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2189#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2134#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2135#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2174#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2175#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2558#L709-3 assume !(1 == ~E_5~0); 2547#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2384#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2208#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2220#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 2605#L939 assume !(0 == start_simulation_~tmp~3); 2561#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2562#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2274#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2489#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 2209#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2210#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 2606#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2368#L952 assume !(0 != start_simulation_~tmp___0~1); 2233#L920-1 [2021-08-27 16:30:34,035 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,035 INFO L82 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-08-27 16:30:34,035 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,035 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710192046] [2021-08-27 16:30:34,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,036 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,062 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710192046] [2021-08-27 16:30:34,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710192046] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,063 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238971436] [2021-08-27 16:30:34,063 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,064 INFO L82 PathProgramCache]: Analyzing trace with hash -1662838536, now seen corresponding path program 1 times [2021-08-27 16:30:34,064 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,064 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093916623] [2021-08-27 16:30:34,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,064 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,100 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,100 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093916623] [2021-08-27 16:30:34,101 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093916623] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,101 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [322962572] [2021-08-27 16:30:34,101 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,101 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,102 INFO L87 Difference]: Start difference. First operand 527 states and 798 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,112 INFO L93 Difference]: Finished difference Result 527 states and 797 transitions. [2021-08-27 16:30:34,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 797 transitions. [2021-08-27 16:30:34,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 797 transitions. [2021-08-27 16:30:34,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:34,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:34,118 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 797 transitions. [2021-08-27 16:30:34,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,119 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-08-27 16:30:34,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 797 transitions. [2021-08-27 16:30:34,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5123339658444024) internal successors, (797), 526 states have internal predecessors, (797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 797 transitions. [2021-08-27 16:30:34,134 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-08-27 16:30:34,134 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 797 transitions. [2021-08-27 16:30:34,135 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-08-27 16:30:34,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 797 transitions. [2021-08-27 16:30:34,137 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,142 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,142 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,142 INFO L791 eck$LassoCheckResult]: Stem: 3720#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3704#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3701#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3321#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 3322#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3402#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3689#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3690#L421-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3658#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3443#L431-1 assume !(0 == ~M_E~0); 3444#L591-1 assume !(0 == ~T1_E~0); 3556#L596-1 assume !(0 == ~T2_E~0); 3557#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3599#L606-1 assume !(0 == ~T4_E~0); 3600#L611-1 assume !(0 == ~T5_E~0); 3662#L616-1 assume !(0 == ~E_M~0); 3663#L621-1 assume !(0 == ~E_1~0); 3306#L626-1 assume !(0 == ~E_2~0); 3307#L631-1 assume !(0 == ~E_3~0); 3470#L636-1 assume !(0 == ~E_4~0); 3332#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3333#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3315#L284 assume 1 == ~m_pc~0; 3316#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3446#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3302#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3303#L735 assume !(0 != activate_threads_~tmp~1); 3408#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3409#L303 assume !(1 == ~t1_pc~0); 3589#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 3717#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3296#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3297#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3323#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3324#L322 assume 1 == ~t2_pc~0; 3199#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3200#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3272#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3247#L751 assume !(0 != activate_threads_~tmp___1~0); 3248#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3340#L341 assume !(1 == ~t3_pc~0); 3277#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 3278#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3352#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3353#L759 assume !(0 != activate_threads_~tmp___2~0); 3702#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3620#L360 assume 1 == ~t4_pc~0; 3537#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3538#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3697#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3698#L767 assume !(0 != activate_threads_~tmp___3~0); 3696#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3673#L379 assume !(1 == ~t5_pc~0); 3378#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 3379#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3560#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3659#L775 assume !(0 != activate_threads_~tmp___4~0); 3224#L775-2 assume !(1 == ~M_E~0); 3225#L659-1 assume !(1 == ~T1_E~0); 3493#L664-1 assume !(1 == ~T2_E~0); 3279#L669-1 assume !(1 == ~T3_E~0); 3280#L674-1 assume !(1 == ~T4_E~0); 3650#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3375#L684-1 assume !(1 == ~E_M~0); 3376#L689-1 assume !(1 == ~E_1~0); 3555#L694-1 assume !(1 == ~E_2~0); 3553#L699-1 assume !(1 == ~E_3~0); 3554#L704-1 assume !(1 == ~E_4~0); 3520#L709-1 assume !(1 == ~E_5~0); 3294#L920-1 [2021-08-27 16:30:34,144 INFO L793 eck$LassoCheckResult]: Loop: 3294#L920-1 assume !false; 3295#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3391#L566 assume !false; 3392#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3668#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3388#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3485#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3486#L491 assume !(0 != eval_~tmp~0); 3597#L581 start_simulation_~kernel_st~0 := 2; 3598#L399-1 start_simulation_~kernel_st~0 := 3; 3403#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3404#L591-4 assume !(0 == ~T1_E~0); 3398#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3399#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3581#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3616#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3617#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3299#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3256#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3257#L631-3 assume !(0 == ~E_3~0); 3258#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3259#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3308#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3253#L284-21 assume 1 == ~m_pc~0; 3254#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3289#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3290#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3311#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3217#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3218#L303-21 assume !(1 == ~t1_pc~0); 3458#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 3500#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3501#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3585#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3505#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3506#L322-21 assume 1 == ~t2_pc~0; 3525#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3526#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3674#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3676#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3337#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3244#L341-21 assume 1 == ~t3_pc~0; 3245#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3374#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3578#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3579#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3319#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3320#L360-21 assume 1 == ~t4_pc~0; 3705#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3390#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3699#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3633#L767-21 assume !(0 != activate_threads_~tmp___3~0); 3634#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3618#L379-21 assume 1 == ~t5_pc~0; 3212#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3213#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3342#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3343#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3219#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3220#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3348#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3260#L669-3 assume !(1 == ~T3_E~0); 3261#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3251#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3252#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3195#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3196#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3235#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3236#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3619#L709-3 assume !(1 == ~E_5~0); 3608#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3445#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3269#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3281#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 3666#L939 assume !(0 == start_simulation_~tmp~3); 3622#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3623#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3335#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3550#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 3270#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3271#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 3667#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3429#L952 assume !(0 != start_simulation_~tmp___0~1); 3294#L920-1 [2021-08-27 16:30:34,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,144 INFO L82 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-08-27 16:30:34,145 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,145 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987353269] [2021-08-27 16:30:34,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,145 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987353269] [2021-08-27 16:30:34,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987353269] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,191 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,191 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,191 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831084940] [2021-08-27 16:30:34,192 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,192 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,192 INFO L82 PathProgramCache]: Analyzing trace with hash 243645657, now seen corresponding path program 1 times [2021-08-27 16:30:34,192 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,193 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415967490] [2021-08-27 16:30:34,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,193 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,231 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,231 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415967490] [2021-08-27 16:30:34,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415967490] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,232 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,232 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,232 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742834739] [2021-08-27 16:30:34,232 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,233 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,234 INFO L87 Difference]: Start difference. First operand 527 states and 797 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,243 INFO L93 Difference]: Finished difference Result 527 states and 796 transitions. [2021-08-27 16:30:34,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 796 transitions. [2021-08-27 16:30:34,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 796 transitions. [2021-08-27 16:30:34,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:34,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:34,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 796 transitions. [2021-08-27 16:30:34,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,252 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-08-27 16:30:34,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 796 transitions. [2021-08-27 16:30:34,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.5104364326375712) internal successors, (796), 526 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 796 transitions. [2021-08-27 16:30:34,259 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-08-27 16:30:34,259 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 796 transitions. [2021-08-27 16:30:34,259 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-08-27 16:30:34,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 796 transitions. [2021-08-27 16:30:34,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,265 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,265 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,265 INFO L791 eck$LassoCheckResult]: Stem: 4781#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4765#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4762#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4382#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 4383#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4463#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4750#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4751#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4719#L426-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4504#L431-1 assume !(0 == ~M_E~0); 4505#L591-1 assume !(0 == ~T1_E~0); 4617#L596-1 assume !(0 == ~T2_E~0); 4618#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4660#L606-1 assume !(0 == ~T4_E~0); 4661#L611-1 assume !(0 == ~T5_E~0); 4723#L616-1 assume !(0 == ~E_M~0); 4724#L621-1 assume !(0 == ~E_1~0); 4367#L626-1 assume !(0 == ~E_2~0); 4368#L631-1 assume !(0 == ~E_3~0); 4531#L636-1 assume !(0 == ~E_4~0); 4393#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4394#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4376#L284 assume 1 == ~m_pc~0; 4377#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4507#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4363#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4364#L735 assume !(0 != activate_threads_~tmp~1); 4469#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4470#L303 assume !(1 == ~t1_pc~0); 4650#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 4778#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4357#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4358#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4384#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4385#L322 assume 1 == ~t2_pc~0; 4260#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4261#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4333#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4308#L751 assume !(0 != activate_threads_~tmp___1~0); 4309#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4401#L341 assume !(1 == ~t3_pc~0); 4338#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 4339#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4413#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4414#L759 assume !(0 != activate_threads_~tmp___2~0); 4763#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4681#L360 assume 1 == ~t4_pc~0; 4598#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4599#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4758#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4759#L767 assume !(0 != activate_threads_~tmp___3~0); 4757#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4734#L379 assume !(1 == ~t5_pc~0); 4439#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 4440#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4621#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4720#L775 assume !(0 != activate_threads_~tmp___4~0); 4285#L775-2 assume !(1 == ~M_E~0); 4286#L659-1 assume !(1 == ~T1_E~0); 4554#L664-1 assume !(1 == ~T2_E~0); 4340#L669-1 assume !(1 == ~T3_E~0); 4341#L674-1 assume !(1 == ~T4_E~0); 4711#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4436#L684-1 assume !(1 == ~E_M~0); 4437#L689-1 assume !(1 == ~E_1~0); 4616#L694-1 assume !(1 == ~E_2~0); 4614#L699-1 assume !(1 == ~E_3~0); 4615#L704-1 assume !(1 == ~E_4~0); 4581#L709-1 assume !(1 == ~E_5~0); 4355#L920-1 [2021-08-27 16:30:34,265 INFO L793 eck$LassoCheckResult]: Loop: 4355#L920-1 assume !false; 4356#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4452#L566 assume !false; 4453#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4729#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4449#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4546#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4547#L491 assume !(0 != eval_~tmp~0); 4658#L581 start_simulation_~kernel_st~0 := 2; 4659#L399-1 start_simulation_~kernel_st~0 := 3; 4464#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4465#L591-4 assume !(0 == ~T1_E~0); 4459#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4460#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4642#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4677#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4678#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4360#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4317#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4318#L631-3 assume !(0 == ~E_3~0); 4319#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4320#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4369#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4314#L284-21 assume 1 == ~m_pc~0; 4315#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4350#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4351#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4372#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4278#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4279#L303-21 assume !(1 == ~t1_pc~0); 4519#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 4561#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4562#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4646#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4566#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4567#L322-21 assume 1 == ~t2_pc~0; 4586#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4587#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4735#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4737#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4398#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4305#L341-21 assume 1 == ~t3_pc~0; 4306#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4435#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4638#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4639#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4380#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4381#L360-21 assume !(1 == ~t4_pc~0); 4450#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 4451#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4760#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4694#L767-21 assume !(0 != activate_threads_~tmp___3~0); 4695#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4679#L379-21 assume 1 == ~t5_pc~0; 4273#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4274#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4403#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4404#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4280#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4281#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4409#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4321#L669-3 assume !(1 == ~T3_E~0); 4322#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4312#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4313#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4256#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4257#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4296#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4297#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4680#L709-3 assume !(1 == ~E_5~0); 4669#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4506#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4330#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4342#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 4727#L939 assume !(0 == start_simulation_~tmp~3); 4683#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4684#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4396#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4611#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 4331#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4332#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 4728#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4490#L952 assume !(0 != start_simulation_~tmp___0~1); 4355#L920-1 [2021-08-27 16:30:34,266 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,266 INFO L82 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-08-27 16:30:34,266 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,266 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960755950] [2021-08-27 16:30:34,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,267 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,293 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,293 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [960755950] [2021-08-27 16:30:34,293 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [960755950] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,293 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,293 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,293 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292846476] [2021-08-27 16:30:34,294 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,294 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,294 INFO L82 PathProgramCache]: Analyzing trace with hash -1521170952, now seen corresponding path program 2 times [2021-08-27 16:30:34,294 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,294 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018038888] [2021-08-27 16:30:34,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,295 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,325 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,325 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018038888] [2021-08-27 16:30:34,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018038888] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,325 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301615546] [2021-08-27 16:30:34,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,326 INFO L87 Difference]: Start difference. First operand 527 states and 796 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,334 INFO L93 Difference]: Finished difference Result 527 states and 795 transitions. [2021-08-27 16:30:34,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 795 transitions. [2021-08-27 16:30:34,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 795 transitions. [2021-08-27 16:30:34,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:34,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:34,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 795 transitions. [2021-08-27 16:30:34,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,340 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-08-27 16:30:34,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 795 transitions. [2021-08-27 16:30:34,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.50853889943074) internal successors, (795), 526 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 795 transitions. [2021-08-27 16:30:34,346 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-08-27 16:30:34,346 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 795 transitions. [2021-08-27 16:30:34,346 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-08-27 16:30:34,347 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 795 transitions. [2021-08-27 16:30:34,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,349 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,349 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,350 INFO L791 eck$LassoCheckResult]: Stem: 5842#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5826#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5823#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5443#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 5444#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5524#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5811#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5812#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5780#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5565#L431-1 assume !(0 == ~M_E~0); 5566#L591-1 assume !(0 == ~T1_E~0); 5678#L596-1 assume !(0 == ~T2_E~0); 5679#L601-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5721#L606-1 assume !(0 == ~T4_E~0); 5722#L611-1 assume !(0 == ~T5_E~0); 5784#L616-1 assume !(0 == ~E_M~0); 5785#L621-1 assume !(0 == ~E_1~0); 5428#L626-1 assume !(0 == ~E_2~0); 5429#L631-1 assume !(0 == ~E_3~0); 5592#L636-1 assume !(0 == ~E_4~0); 5454#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5455#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5437#L284 assume 1 == ~m_pc~0; 5438#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5568#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5424#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5425#L735 assume !(0 != activate_threads_~tmp~1); 5530#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5531#L303 assume !(1 == ~t1_pc~0); 5711#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 5839#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5418#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5419#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5445#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5446#L322 assume 1 == ~t2_pc~0; 5321#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5322#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5394#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5369#L751 assume !(0 != activate_threads_~tmp___1~0); 5370#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5462#L341 assume !(1 == ~t3_pc~0); 5399#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 5400#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5474#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5475#L759 assume !(0 != activate_threads_~tmp___2~0); 5824#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5742#L360 assume 1 == ~t4_pc~0; 5659#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5660#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5819#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5820#L767 assume !(0 != activate_threads_~tmp___3~0); 5818#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5795#L379 assume !(1 == ~t5_pc~0); 5500#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 5501#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5682#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5781#L775 assume !(0 != activate_threads_~tmp___4~0); 5346#L775-2 assume !(1 == ~M_E~0); 5347#L659-1 assume !(1 == ~T1_E~0); 5615#L664-1 assume !(1 == ~T2_E~0); 5401#L669-1 assume !(1 == ~T3_E~0); 5402#L674-1 assume !(1 == ~T4_E~0); 5772#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5497#L684-1 assume !(1 == ~E_M~0); 5498#L689-1 assume !(1 == ~E_1~0); 5677#L694-1 assume !(1 == ~E_2~0); 5675#L699-1 assume !(1 == ~E_3~0); 5676#L704-1 assume !(1 == ~E_4~0); 5642#L709-1 assume !(1 == ~E_5~0); 5416#L920-1 [2021-08-27 16:30:34,350 INFO L793 eck$LassoCheckResult]: Loop: 5416#L920-1 assume !false; 5417#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5516#L566 assume !false; 5517#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5790#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5510#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5607#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5608#L491 assume !(0 != eval_~tmp~0); 5719#L581 start_simulation_~kernel_st~0 := 2; 5720#L399-1 start_simulation_~kernel_st~0 := 3; 5525#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5526#L591-4 assume !(0 == ~T1_E~0); 5520#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5521#L601-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5703#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5738#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5739#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5421#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5378#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5379#L631-3 assume !(0 == ~E_3~0); 5380#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5381#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5430#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5375#L284-21 assume 1 == ~m_pc~0; 5376#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5411#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5412#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5433#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5339#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5340#L303-21 assume !(1 == ~t1_pc~0); 5580#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 5622#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5623#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5707#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5627#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5628#L322-21 assume !(1 == ~t2_pc~0); 5649#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 5648#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5796#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5798#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5459#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5364#L341-21 assume 1 == ~t3_pc~0; 5365#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5494#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5699#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5700#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5441#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5442#L360-21 assume 1 == ~t4_pc~0; 5827#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5512#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5821#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5755#L767-21 assume !(0 != activate_threads_~tmp___3~0); 5756#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5740#L379-21 assume 1 == ~t5_pc~0; 5334#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5335#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5464#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5465#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5341#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5342#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5470#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5382#L669-3 assume !(1 == ~T3_E~0); 5383#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5373#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5374#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5317#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5318#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5357#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5358#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5741#L709-3 assume !(1 == ~E_5~0); 5730#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5567#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5391#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5403#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 5788#L939 assume !(0 == start_simulation_~tmp~3); 5744#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5745#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5457#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5672#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 5392#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5393#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 5789#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5553#L952 assume !(0 != start_simulation_~tmp___0~1); 5416#L920-1 [2021-08-27 16:30:34,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,350 INFO L82 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-08-27 16:30:34,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,351 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2134748141] [2021-08-27 16:30:34,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,351 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,369 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,369 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2134748141] [2021-08-27 16:30:34,369 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2134748141] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,370 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,370 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:34,370 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406277374] [2021-08-27 16:30:34,370 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,371 INFO L82 PathProgramCache]: Analyzing trace with hash 1676480376, now seen corresponding path program 1 times [2021-08-27 16:30:34,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,371 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728297455] [2021-08-27 16:30:34,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,371 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,397 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728297455] [2021-08-27 16:30:34,397 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728297455] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,397 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,398 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,398 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744099633] [2021-08-27 16:30:34,399 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,400 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,400 INFO L87 Difference]: Start difference. First operand 527 states and 795 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,420 INFO L93 Difference]: Finished difference Result 527 states and 790 transitions. [2021-08-27 16:30:34,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 790 transitions. [2021-08-27 16:30:34,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 790 transitions. [2021-08-27 16:30:34,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:34,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:34,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 790 transitions. [2021-08-27 16:30:34,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,431 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2021-08-27 16:30:34,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 790 transitions. [2021-08-27 16:30:34,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.4990512333965844) internal successors, (790), 526 states have internal predecessors, (790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 790 transitions. [2021-08-27 16:30:34,437 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2021-08-27 16:30:34,437 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 790 transitions. [2021-08-27 16:30:34,437 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-08-27 16:30:34,437 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 790 transitions. [2021-08-27 16:30:34,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,443 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,443 INFO L791 eck$LassoCheckResult]: Stem: 6903#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6887#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6884#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6504#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 6505#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6585#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6872#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6873#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6841#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6626#L431-1 assume !(0 == ~M_E~0); 6627#L591-1 assume !(0 == ~T1_E~0); 6739#L596-1 assume !(0 == ~T2_E~0); 6740#L601-1 assume !(0 == ~T3_E~0); 6782#L606-1 assume !(0 == ~T4_E~0); 6783#L611-1 assume !(0 == ~T5_E~0); 6845#L616-1 assume !(0 == ~E_M~0); 6846#L621-1 assume !(0 == ~E_1~0); 6489#L626-1 assume !(0 == ~E_2~0); 6490#L631-1 assume !(0 == ~E_3~0); 6653#L636-1 assume !(0 == ~E_4~0); 6515#L641-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6516#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6498#L284 assume 1 == ~m_pc~0; 6499#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6629#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6485#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6486#L735 assume !(0 != activate_threads_~tmp~1); 6591#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6592#L303 assume !(1 == ~t1_pc~0); 6772#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 6900#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6479#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6480#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6506#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6507#L322 assume 1 == ~t2_pc~0; 6382#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6383#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6455#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6430#L751 assume !(0 != activate_threads_~tmp___1~0); 6431#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6523#L341 assume !(1 == ~t3_pc~0); 6460#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 6461#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6535#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6536#L759 assume !(0 != activate_threads_~tmp___2~0); 6885#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6803#L360 assume 1 == ~t4_pc~0; 6720#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6721#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6880#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6881#L767 assume !(0 != activate_threads_~tmp___3~0); 6879#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6857#L379 assume !(1 == ~t5_pc~0); 6561#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 6562#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6743#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6842#L775 assume !(0 != activate_threads_~tmp___4~0); 6407#L775-2 assume !(1 == ~M_E~0); 6408#L659-1 assume !(1 == ~T1_E~0); 6676#L664-1 assume !(1 == ~T2_E~0); 6462#L669-1 assume !(1 == ~T3_E~0); 6463#L674-1 assume !(1 == ~T4_E~0); 6833#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6558#L684-1 assume !(1 == ~E_M~0); 6559#L689-1 assume !(1 == ~E_1~0); 6738#L694-1 assume !(1 == ~E_2~0); 6736#L699-1 assume !(1 == ~E_3~0); 6737#L704-1 assume !(1 == ~E_4~0); 6703#L709-1 assume !(1 == ~E_5~0); 6477#L920-1 [2021-08-27 16:30:34,443 INFO L793 eck$LassoCheckResult]: Loop: 6477#L920-1 assume !false; 6478#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6577#L566 assume !false; 6578#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6851#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6571#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6668#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 6669#L491 assume !(0 != eval_~tmp~0); 6780#L581 start_simulation_~kernel_st~0 := 2; 6781#L399-1 start_simulation_~kernel_st~0 := 3; 6586#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6587#L591-4 assume !(0 == ~T1_E~0); 6581#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6582#L601-3 assume !(0 == ~T3_E~0); 6764#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6799#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6800#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6482#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6439#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6440#L631-3 assume !(0 == ~E_3~0); 6441#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6442#L641-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6491#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6436#L284-21 assume 1 == ~m_pc~0; 6437#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6472#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6473#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6494#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6400#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6401#L303-21 assume !(1 == ~t1_pc~0); 6641#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 6683#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6684#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6768#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6688#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6689#L322-21 assume 1 == ~t2_pc~0; 6708#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6709#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6856#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6859#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6520#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6425#L341-21 assume 1 == ~t3_pc~0; 6426#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6555#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6760#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6761#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6502#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6503#L360-21 assume 1 == ~t4_pc~0; 6888#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6573#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6882#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6816#L767-21 assume !(0 != activate_threads_~tmp___3~0); 6817#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6801#L379-21 assume 1 == ~t5_pc~0; 6395#L380-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6396#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6525#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6526#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6402#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6403#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6531#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6443#L669-3 assume !(1 == ~T3_E~0); 6444#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6434#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6435#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6378#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6379#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6418#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6419#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6802#L709-3 assume !(1 == ~E_5~0); 6791#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6628#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6452#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6464#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 6849#L939 assume !(0 == start_simulation_~tmp~3); 6805#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6806#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6518#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6733#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 6453#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6454#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 6850#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6614#L952 assume !(0 != start_simulation_~tmp___0~1); 6477#L920-1 [2021-08-27 16:30:34,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,444 INFO L82 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2021-08-27 16:30:34,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,444 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008137104] [2021-08-27 16:30:34,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,445 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,475 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008137104] [2021-08-27 16:30:34,475 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008137104] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,475 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,475 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:34,476 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908544486] [2021-08-27 16:30:34,476 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,476 INFO L82 PathProgramCache]: Analyzing trace with hash -2142863849, now seen corresponding path program 1 times [2021-08-27 16:30:34,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,477 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290215366] [2021-08-27 16:30:34,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,477 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,504 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290215366] [2021-08-27 16:30:34,504 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290215366] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,505 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,505 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:34,505 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784208440] [2021-08-27 16:30:34,506 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,506 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,507 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,507 INFO L87 Difference]: Start difference. First operand 527 states and 790 transitions. cyclomatic complexity: 264 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,538 INFO L93 Difference]: Finished difference Result 527 states and 777 transitions. [2021-08-27 16:30:34,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 777 transitions. [2021-08-27 16:30:34,541 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,542 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 777 transitions. [2021-08-27 16:30:34,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2021-08-27 16:30:34,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2021-08-27 16:30:34,543 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 777 transitions. [2021-08-27 16:30:34,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,544 INFO L681 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2021-08-27 16:30:34,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 777 transitions. [2021-08-27 16:30:34,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 527. [2021-08-27 16:30:34,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 527 states, 527 states have (on average 1.4743833017077799) internal successors, (777), 526 states have internal predecessors, (777), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 527 states to 527 states and 777 transitions. [2021-08-27 16:30:34,550 INFO L704 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2021-08-27 16:30:34,550 INFO L587 BuchiCegarLoop]: Abstraction has 527 states and 777 transitions. [2021-08-27 16:30:34,550 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-08-27 16:30:34,550 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 527 states and 777 transitions. [2021-08-27 16:30:34,552 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 452 [2021-08-27 16:30:34,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,552 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,553 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,553 INFO L791 eck$LassoCheckResult]: Stem: 7964#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7948#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7945#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7564#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 7565#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7645#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7933#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7934#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7902#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7685#L431-1 assume !(0 == ~M_E~0); 7686#L591-1 assume !(0 == ~T1_E~0); 7800#L596-1 assume !(0 == ~T2_E~0); 7801#L601-1 assume !(0 == ~T3_E~0); 7843#L606-1 assume !(0 == ~T4_E~0); 7844#L611-1 assume !(0 == ~T5_E~0); 7906#L616-1 assume !(0 == ~E_M~0); 7907#L621-1 assume !(0 == ~E_1~0); 7550#L626-1 assume !(0 == ~E_2~0); 7551#L631-1 assume !(0 == ~E_3~0); 7713#L636-1 assume !(0 == ~E_4~0); 7575#L641-1 assume !(0 == ~E_5~0); 7576#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7558#L284 assume 1 == ~m_pc~0; 7559#L285 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7688#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7546#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7547#L735 assume !(0 != activate_threads_~tmp~1); 7651#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7652#L303 assume !(1 == ~t1_pc~0); 7833#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 7961#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7540#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7541#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7566#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7567#L322 assume 1 == ~t2_pc~0; 7443#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7444#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7516#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7490#L751 assume !(0 != activate_threads_~tmp___1~0); 7491#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7583#L341 assume !(1 == ~t3_pc~0); 7521#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 7522#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7595#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7596#L759 assume !(0 != activate_threads_~tmp___2~0); 7946#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7864#L360 assume 1 == ~t4_pc~0; 7781#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7782#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7941#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7942#L767 assume !(0 != activate_threads_~tmp___3~0); 7940#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7918#L379 assume !(1 == ~t5_pc~0); 7622#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 7623#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7804#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7903#L775 assume !(0 != activate_threads_~tmp___4~0); 7467#L775-2 assume !(1 == ~M_E~0); 7468#L659-1 assume !(1 == ~T1_E~0); 7736#L664-1 assume !(1 == ~T2_E~0); 7523#L669-1 assume !(1 == ~T3_E~0); 7524#L674-1 assume !(1 == ~T4_E~0); 7894#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7618#L684-1 assume !(1 == ~E_M~0); 7619#L689-1 assume !(1 == ~E_1~0); 7799#L694-1 assume !(1 == ~E_2~0); 7797#L699-1 assume !(1 == ~E_3~0); 7798#L704-1 assume !(1 == ~E_4~0); 7764#L709-1 assume !(1 == ~E_5~0); 7538#L920-1 [2021-08-27 16:30:34,553 INFO L793 eck$LassoCheckResult]: Loop: 7538#L920-1 assume !false; 7539#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7637#L566 assume !false; 7638#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7912#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7631#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7728#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7729#L491 assume !(0 != eval_~tmp~0); 7841#L581 start_simulation_~kernel_st~0 := 2; 7842#L399-1 start_simulation_~kernel_st~0 := 3; 7646#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7647#L591-4 assume !(0 == ~T1_E~0); 7641#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7642#L601-3 assume !(0 == ~T3_E~0); 7825#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7860#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7861#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7543#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7499#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7500#L631-3 assume !(0 == ~E_3~0); 7501#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7502#L641-3 assume !(0 == ~E_5~0); 7552#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7496#L284-21 assume 1 == ~m_pc~0; 7497#L285-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7533#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7534#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7555#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7460#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7461#L303-21 assume !(1 == ~t1_pc~0); 7700#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 7743#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7744#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7829#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7748#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7749#L322-21 assume 1 == ~t2_pc~0; 7769#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7770#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7917#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7920#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7580#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7485#L341-21 assume 1 == ~t3_pc~0; 7486#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7615#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7821#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7822#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7562#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7563#L360-21 assume !(1 == ~t4_pc~0); 7632#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 7633#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7943#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7877#L767-21 assume !(0 != activate_threads_~tmp___3~0); 7878#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7862#L379-21 assume !(1 == ~t5_pc~0); 7457#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 7503#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7585#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7586#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7462#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7463#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7591#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7504#L669-3 assume !(1 == ~T3_E~0); 7505#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7494#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7495#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7439#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7440#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7478#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7479#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7863#L709-3 assume !(1 == ~E_5~0); 7852#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7687#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7513#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7525#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 7910#L939 assume !(0 == start_simulation_~tmp~3); 7866#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7867#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7578#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7794#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 7514#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7515#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 7911#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7673#L952 assume !(0 != start_simulation_~tmp___0~1); 7538#L920-1 [2021-08-27 16:30:34,553 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,553 INFO L82 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2021-08-27 16:30:34,554 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,554 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093013902] [2021-08-27 16:30:34,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,554 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,587 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093013902] [2021-08-27 16:30:34,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093013902] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,588 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:34,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501853860] [2021-08-27 16:30:34,588 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,589 INFO L82 PathProgramCache]: Analyzing trace with hash 1009414867, now seen corresponding path program 1 times [2021-08-27 16:30:34,589 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,589 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [300286634] [2021-08-27 16:30:34,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,590 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,617 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,618 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [300286634] [2021-08-27 16:30:34,622 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [300286634] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,622 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,622 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382895695] [2021-08-27 16:30:34,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,622 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:34,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:34,623 INFO L87 Difference]: Start difference. First operand 527 states and 777 transitions. cyclomatic complexity: 251 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,682 INFO L93 Difference]: Finished difference Result 968 states and 1410 transitions. [2021-08-27 16:30:34,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:34,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 968 states and 1410 transitions. [2021-08-27 16:30:34,687 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 893 [2021-08-27 16:30:34,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 968 states to 968 states and 1410 transitions. [2021-08-27 16:30:34,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 968 [2021-08-27 16:30:34,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 968 [2021-08-27 16:30:34,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 968 states and 1410 transitions. [2021-08-27 16:30:34,692 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,692 INFO L681 BuchiCegarLoop]: Abstraction has 968 states and 1410 transitions. [2021-08-27 16:30:34,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 968 states and 1410 transitions. [2021-08-27 16:30:34,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 968 to 928. [2021-08-27 16:30:34,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 928 states, 928 states have (on average 1.4601293103448276) internal successors, (1355), 927 states have internal predecessors, (1355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 928 states to 928 states and 1355 transitions. [2021-08-27 16:30:34,706 INFO L704 BuchiCegarLoop]: Abstraction has 928 states and 1355 transitions. [2021-08-27 16:30:34,706 INFO L587 BuchiCegarLoop]: Abstraction has 928 states and 1355 transitions. [2021-08-27 16:30:34,706 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-08-27 16:30:34,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 928 states and 1355 transitions. [2021-08-27 16:30:34,709 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 853 [2021-08-27 16:30:34,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:34,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:34,710 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,710 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:34,710 INFO L791 eck$LassoCheckResult]: Stem: 9495#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9476#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9473#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9067#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 9068#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9149#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9455#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9456#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9415#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9188#L431-1 assume !(0 == ~M_E~0); 9189#L591-1 assume !(0 == ~T1_E~0); 9307#L596-1 assume !(0 == ~T2_E~0); 9308#L601-1 assume !(0 == ~T3_E~0); 9352#L606-1 assume !(0 == ~T4_E~0); 9353#L611-1 assume !(0 == ~T5_E~0); 9424#L616-1 assume !(0 == ~E_M~0); 9425#L621-1 assume !(0 == ~E_1~0); 9055#L626-1 assume !(0 == ~E_2~0); 9056#L631-1 assume !(0 == ~E_3~0); 9217#L636-1 assume !(0 == ~E_4~0); 9078#L641-1 assume !(0 == ~E_5~0); 9079#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9062#L284 assume !(1 == ~m_pc~0); 9063#L284-2 is_master_triggered_~__retres1~0 := 0; 9191#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9050#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9051#L735 assume !(0 != activate_threads_~tmp~1); 9155#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9156#L303 assume !(1 == ~t1_pc~0); 9343#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 9491#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9044#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9045#L743 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9069#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9070#L322 assume 1 == ~t2_pc~0; 8949#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8950#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9019#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8994#L751 assume !(0 != activate_threads_~tmp___1~0); 8995#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9087#L341 assume !(1 == ~t3_pc~0); 9024#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 9025#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9098#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9099#L759 assume !(0 != activate_threads_~tmp___2~0); 9474#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9373#L360 assume 1 == ~t4_pc~0; 9287#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9288#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9469#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9470#L767 assume !(0 != activate_threads_~tmp___3~0); 9468#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9434#L379 assume !(1 == ~t5_pc~0); 9126#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 9127#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9312#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9417#L775 assume !(0 != activate_threads_~tmp___4~0); 8971#L775-2 assume !(1 == ~M_E~0); 8972#L659-1 assume !(1 == ~T1_E~0); 9242#L664-1 assume !(1 == ~T2_E~0); 9026#L669-1 assume !(1 == ~T3_E~0); 9027#L674-1 assume !(1 == ~T4_E~0); 9408#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9122#L684-1 assume !(1 == ~E_M~0); 9123#L689-1 assume !(1 == ~E_1~0); 9306#L694-1 assume !(1 == ~E_2~0); 9304#L699-1 assume !(1 == ~E_3~0); 9305#L704-1 assume !(1 == ~E_4~0); 9272#L709-1 assume !(1 == ~E_5~0); 9041#L920-1 [2021-08-27 16:30:34,710 INFO L793 eck$LassoCheckResult]: Loop: 9041#L920-1 assume !false; 9042#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9143#L566 assume !false; 9144#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9428#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9135#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9231#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 9232#L491 assume !(0 != eval_~tmp~0); 9350#L581 start_simulation_~kernel_st~0 := 2; 9351#L399-1 start_simulation_~kernel_st~0 := 3; 9150#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9151#L591-4 assume !(0 == ~T1_E~0); 9145#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9146#L601-3 assume !(0 == ~T3_E~0); 9333#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9369#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9370#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9046#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9047#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9533#L631-3 assume !(0 == ~E_3~0); 9512#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9509#L641-3 assume !(0 == ~E_5~0); 9507#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9000#L284-21 assume !(1 == ~m_pc~0); 9001#L284-23 is_master_triggered_~__retres1~0 := 0; 9036#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9037#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9059#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8964#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8965#L303-21 assume !(1 == ~t1_pc~0); 9203#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 9249#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9250#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9339#L743-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9254#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9255#L322-21 assume 1 == ~t2_pc~0; 9275#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9276#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9433#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9436#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9083#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8989#L341-21 assume 1 == ~t3_pc~0; 8990#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9119#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9329#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9330#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9065#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9066#L360-21 assume !(1 == ~t4_pc~0); 9136#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 9137#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9471#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9388#L767-21 assume !(0 != activate_threads_~tmp___3~0); 9389#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9371#L379-21 assume !(1 == ~t5_pc~0); 8961#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 9006#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9088#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9089#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8966#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 8967#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9094#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9007#L669-3 assume !(1 == ~T3_E~0); 9008#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8998#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8999#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8943#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8944#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8983#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8984#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9372#L709-3 assume !(1 == ~E_5~0); 9361#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9190#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9016#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9030#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 9426#L939 assume !(0 == start_simulation_~tmp~3); 9375#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9376#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9081#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9301#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 9017#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9018#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 9427#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9176#L952 assume !(0 != start_simulation_~tmp___0~1); 9041#L920-1 [2021-08-27 16:30:34,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,711 INFO L82 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2021-08-27 16:30:34,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,711 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071392489] [2021-08-27 16:30:34,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,711 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,746 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,747 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071392489] [2021-08-27 16:30:34,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071392489] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,747 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,747 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1469086136] [2021-08-27 16:30:34,748 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:34,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:34,748 INFO L82 PathProgramCache]: Analyzing trace with hash -897069326, now seen corresponding path program 1 times [2021-08-27 16:30:34,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:34,749 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279594863] [2021-08-27 16:30:34,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:34,749 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:34,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:34,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:34,778 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:34,778 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279594863] [2021-08-27 16:30:34,778 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279594863] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:34,779 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:34,779 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:34,779 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1728007517] [2021-08-27 16:30:34,780 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:34,780 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:34,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-27 16:30:34,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-27 16:30:34,781 INFO L87 Difference]: Start difference. First operand 928 states and 1355 transitions. cyclomatic complexity: 429 Second operand has 5 states, 5 states have (on average 13.8) internal successors, (69), 5 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:34,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:34,952 INFO L93 Difference]: Finished difference Result 2485 states and 3615 transitions. [2021-08-27 16:30:34,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-08-27 16:30:34,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2485 states and 3615 transitions. [2021-08-27 16:30:34,963 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2325 [2021-08-27 16:30:34,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2485 states to 2485 states and 3615 transitions. [2021-08-27 16:30:34,971 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2485 [2021-08-27 16:30:34,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2485 [2021-08-27 16:30:34,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2485 states and 3615 transitions. [2021-08-27 16:30:34,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:34,974 INFO L681 BuchiCegarLoop]: Abstraction has 2485 states and 3615 transitions. [2021-08-27 16:30:34,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2485 states and 3615 transitions. [2021-08-27 16:30:35,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2485 to 976. [2021-08-27 16:30:35,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 976 states, 976 states have (on average 1.4375) internal successors, (1403), 975 states have internal predecessors, (1403), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 976 states to 976 states and 1403 transitions. [2021-08-27 16:30:35,010 INFO L704 BuchiCegarLoop]: Abstraction has 976 states and 1403 transitions. [2021-08-27 16:30:35,010 INFO L587 BuchiCegarLoop]: Abstraction has 976 states and 1403 transitions. [2021-08-27 16:30:35,011 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-08-27 16:30:35,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 976 states and 1403 transitions. [2021-08-27 16:30:35,014 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 898 [2021-08-27 16:30:35,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,014 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,015 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,015 INFO L791 eck$LassoCheckResult]: Stem: 12967#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 12937#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12934#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12495#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 12496#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12581#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12916#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12917#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12864#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12621#L431-1 assume !(0 == ~M_E~0); 12622#L591-1 assume !(0 == ~T1_E~0); 12746#L596-1 assume !(0 == ~T2_E~0); 12747#L601-1 assume !(0 == ~T3_E~0); 12796#L606-1 assume !(0 == ~T4_E~0); 12797#L611-1 assume !(0 == ~T5_E~0); 12876#L616-1 assume !(0 == ~E_M~0); 12877#L621-1 assume !(0 == ~E_1~0); 12482#L626-1 assume !(0 == ~E_2~0); 12483#L631-1 assume !(0 == ~E_3~0); 12651#L636-1 assume !(0 == ~E_4~0); 12506#L641-1 assume !(0 == ~E_5~0); 12507#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12490#L284 assume !(1 == ~m_pc~0); 12491#L284-2 is_master_triggered_~__retres1~0 := 0; 12624#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12478#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12479#L735 assume !(0 != activate_threads_~tmp~1); 12587#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12588#L303 assume !(1 == ~t1_pc~0); 12785#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 12958#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12962#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12943#L743 assume !(0 != activate_threads_~tmp___0~0); 12497#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12498#L322 assume 1 == ~t2_pc~0; 12375#L323 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12376#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12448#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12423#L751 assume !(0 != activate_threads_~tmp___1~0); 12424#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12512#L341 assume !(1 == ~t3_pc~0); 12452#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 12453#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12529#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 12530#L759 assume !(0 != activate_threads_~tmp___2~0); 12935#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12819#L360 assume 1 == ~t4_pc~0; 12726#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12727#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12929#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12930#L767 assume !(0 != activate_threads_~tmp___3~0); 12928#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12888#L379 assume !(1 == ~t5_pc~0); 12556#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 12557#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12752#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12865#L775 assume !(0 != activate_threads_~tmp___4~0); 12399#L775-2 assume !(1 == ~M_E~0); 12400#L659-1 assume !(1 == ~T1_E~0); 12677#L664-1 assume !(1 == ~T2_E~0); 12455#L669-1 assume !(1 == ~T3_E~0); 12456#L674-1 assume !(1 == ~T4_E~0); 12857#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12553#L684-1 assume !(1 == ~E_M~0); 12554#L689-1 assume !(1 == ~E_1~0); 12745#L694-1 assume !(1 == ~E_2~0); 12743#L699-1 assume !(1 == ~E_3~0); 12744#L704-1 assume !(1 == ~E_4~0); 12707#L709-1 assume !(1 == ~E_5~0); 12708#L920-1 [2021-08-27 16:30:35,015 INFO L793 eck$LassoCheckResult]: Loop: 12708#L920-1 assume !false; 13034#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12569#L566 assume !false; 12570#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12882#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12566#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12668#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12669#L491 assume !(0 != eval_~tmp~0); 12810#L581 start_simulation_~kernel_st~0 := 2; 13107#L399-1 start_simulation_~kernel_st~0 := 3; 13106#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13029#L591-4 assume !(0 == ~T1_E~0); 13028#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13022#L601-3 assume !(0 == ~T3_E~0); 13021#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13020#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13019#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12998#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12994#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12989#L631-3 assume !(0 == ~E_3~0); 12986#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12982#L641-3 assume !(0 == ~E_5~0); 12732#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12425#L284-21 assume !(1 == ~m_pc~0); 12426#L284-23 is_master_triggered_~__retres1~0 := 0; 13227#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13226#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13225#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13224#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12636#L303-21 assume !(1 == ~t1_pc~0); 12637#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 13223#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13221#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13219#L743-21 assume !(0 != activate_threads_~tmp___0~0); 13217#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13215#L322-21 assume 1 == ~t2_pc~0; 13212#L323-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13210#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13208#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13206#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13203#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13201#L341-21 assume !(1 == ~t3_pc~0); 13198#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 13196#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13194#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13192#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13189#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13187#L360-21 assume 1 == ~t4_pc~0; 13184#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13182#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13181#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13180#L767-21 assume !(0 != activate_threads_~tmp___3~0); 13179#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13178#L379-21 assume !(1 == ~t5_pc~0); 13166#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 13164#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13162#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13159#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13157#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 13155#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13153#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13151#L669-3 assume !(1 == ~T3_E~0); 13149#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13146#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13144#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13142#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13140#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13138#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13136#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13133#L709-3 assume !(1 == ~E_5~0); 13131#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 13003#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12995#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12990#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 12979#L939 assume !(0 == start_simulation_~tmp~3); 12821#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12822#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 13122#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 13119#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 13117#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13115#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 13113#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 13111#L952 assume !(0 != start_simulation_~tmp___0~1); 12708#L920-1 [2021-08-27 16:30:35,015 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1507063107, now seen corresponding path program 1 times [2021-08-27 16:30:35,016 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,016 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58253300] [2021-08-27 16:30:35,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,016 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,036 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,037 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58253300] [2021-08-27 16:30:35,037 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58253300] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,037 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,037 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:35,037 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806595923] [2021-08-27 16:30:35,037 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:35,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,038 INFO L82 PathProgramCache]: Analyzing trace with hash -1768847376, now seen corresponding path program 1 times [2021-08-27 16:30:35,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,038 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119629345] [2021-08-27 16:30:35,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,038 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,061 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119629345] [2021-08-27 16:30:35,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119629345] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,061 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,061 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:35,061 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900354473] [2021-08-27 16:30:35,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:35,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-27 16:30:35,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-27 16:30:35,062 INFO L87 Difference]: Start difference. First operand 976 states and 1403 transitions. cyclomatic complexity: 429 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,184 INFO L93 Difference]: Finished difference Result 2236 states and 3174 transitions. [2021-08-27 16:30:35,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-27 16:30:35,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2236 states and 3174 transitions. [2021-08-27 16:30:35,194 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2108 [2021-08-27 16:30:35,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2236 states to 2236 states and 3174 transitions. [2021-08-27 16:30:35,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2236 [2021-08-27 16:30:35,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2236 [2021-08-27 16:30:35,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2236 states and 3174 transitions. [2021-08-27 16:30:35,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,205 INFO L681 BuchiCegarLoop]: Abstraction has 2236 states and 3174 transitions. [2021-08-27 16:30:35,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2236 states and 3174 transitions. [2021-08-27 16:30:35,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2236 to 1766. [2021-08-27 16:30:35,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1766 states, 1766 states have (on average 1.4280860702151756) internal successors, (2522), 1765 states have internal predecessors, (2522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1766 states to 1766 states and 2522 transitions. [2021-08-27 16:30:35,245 INFO L704 BuchiCegarLoop]: Abstraction has 1766 states and 2522 transitions. [2021-08-27 16:30:35,245 INFO L587 BuchiCegarLoop]: Abstraction has 1766 states and 2522 transitions. [2021-08-27 16:30:35,245 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-08-27 16:30:35,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1766 states and 2522 transitions. [2021-08-27 16:30:35,250 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1688 [2021-08-27 16:30:35,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,251 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,251 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,252 INFO L791 eck$LassoCheckResult]: Stem: 16177#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16153#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16150#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15716#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 15717#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15800#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16130#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16131#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16076#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15841#L431-1 assume !(0 == ~M_E~0); 15842#L591-1 assume !(0 == ~T1_E~0); 15963#L596-1 assume !(0 == ~T2_E~0); 15964#L601-1 assume !(0 == ~T3_E~0); 16012#L606-1 assume !(0 == ~T4_E~0); 16013#L611-1 assume !(0 == ~T5_E~0); 16084#L616-1 assume !(0 == ~E_M~0); 16085#L621-1 assume !(0 == ~E_1~0); 15703#L626-1 assume !(0 == ~E_2~0); 15704#L631-1 assume !(0 == ~E_3~0); 15870#L636-1 assume !(0 == ~E_4~0); 15727#L641-1 assume !(0 == ~E_5~0); 15728#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15711#L284 assume !(1 == ~m_pc~0); 15712#L284-2 is_master_triggered_~__retres1~0 := 0; 15844#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15699#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15700#L735 assume !(0 != activate_threads_~tmp~1); 15806#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15807#L303 assume !(1 == ~t1_pc~0); 16001#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 16171#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15693#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15694#L743 assume !(0 != activate_threads_~tmp___0~0); 15718#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15719#L322 assume !(1 == ~t2_pc~0); 15937#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 15934#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15669#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15642#L751 assume !(0 != activate_threads_~tmp___1~0); 15643#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15733#L341 assume !(1 == ~t3_pc~0); 15673#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 15674#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15748#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15749#L759 assume !(0 != activate_threads_~tmp___2~0); 16151#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16034#L360 assume 1 == ~t4_pc~0; 15943#L361 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15944#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16146#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16147#L767 assume !(0 != activate_threads_~tmp___3~0); 16145#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16100#L379 assume !(1 == ~t5_pc~0); 15775#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 15776#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15968#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16077#L775 assume !(0 != activate_threads_~tmp___4~0); 15619#L775-2 assume !(1 == ~M_E~0); 15620#L659-1 assume !(1 == ~T1_E~0); 15894#L664-1 assume !(1 == ~T2_E~0); 15676#L669-1 assume !(1 == ~T3_E~0); 15677#L674-1 assume !(1 == ~T4_E~0); 16069#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15773#L684-1 assume !(1 == ~E_M~0); 15774#L689-1 assume !(1 == ~E_1~0); 15962#L694-1 assume !(1 == ~E_2~0); 15960#L699-1 assume !(1 == ~E_3~0); 15961#L704-1 assume !(1 == ~E_4~0); 15923#L709-1 assume !(1 == ~E_5~0); 15691#L920-1 [2021-08-27 16:30:35,252 INFO L793 eck$LassoCheckResult]: Loop: 15691#L920-1 assume !false; 15692#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 15789#L566 assume !false; 15790#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16094#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15786#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15885#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 15886#L491 assume !(0 != eval_~tmp~0); 16025#L581 start_simulation_~kernel_st~0 := 2; 17244#L399-1 start_simulation_~kernel_st~0 := 3; 17242#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17240#L591-4 assume !(0 == ~T1_E~0); 17238#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17236#L601-3 assume !(0 == ~T3_E~0); 16119#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16030#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16031#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15696#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15650#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15651#L631-3 assume !(0 == ~E_3~0); 15652#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15653#L641-3 assume !(0 == ~E_5~0); 15705#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15644#L284-21 assume !(1 == ~m_pc~0); 15645#L284-23 is_master_triggered_~__retres1~0 := 0; 17318#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17317#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17316#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17315#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17314#L303-21 assume !(1 == ~t1_pc~0); 17312#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 17310#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17308#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17307#L743-21 assume !(0 != activate_threads_~tmp___0~0); 17305#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17304#L322-21 assume !(1 == ~t2_pc~0); 17099#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 17303#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17302#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17301#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17300#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17299#L341-21 assume !(1 == ~t3_pc~0); 17297#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 17296#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17295#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16011#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15714#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15715#L360-21 assume 1 == ~t4_pc~0; 16154#L361-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15788#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16148#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16050#L767-21 assume !(0 != activate_threads_~tmp___3~0); 16051#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16032#L379-21 assume !(1 == ~t5_pc~0); 15610#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 15654#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15737#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15738#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15615#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 15616#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15744#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15655#L669-3 assume !(1 == ~T3_E~0); 15656#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15648#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15649#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15595#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15596#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15631#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15632#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16033#L709-3 assume !(1 == ~E_5~0); 16021#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15843#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15666#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15680#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 16092#L939 assume !(0 == start_simulation_~tmp~3); 16036#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16037#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15730#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15957#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 15667#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15668#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 16093#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 15829#L952 assume !(0 != start_simulation_~tmp___0~1); 15691#L920-1 [2021-08-27 16:30:35,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,252 INFO L82 PathProgramCache]: Analyzing trace with hash -455614018, now seen corresponding path program 1 times [2021-08-27 16:30:35,253 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,253 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049172258] [2021-08-27 16:30:35,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,253 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,270 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,270 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049172258] [2021-08-27 16:30:35,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049172258] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,271 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,271 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:35,271 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059830673] [2021-08-27 16:30:35,271 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:35,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,272 INFO L82 PathProgramCache]: Analyzing trace with hash -336012657, now seen corresponding path program 1 times [2021-08-27 16:30:35,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,272 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265125670] [2021-08-27 16:30:35,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,272 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,296 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,296 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265125670] [2021-08-27 16:30:35,296 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265125670] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,296 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,296 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:35,297 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111433094] [2021-08-27 16:30:35,297 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:35,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:35,297 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:35,297 INFO L87 Difference]: Start difference. First operand 1766 states and 2522 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,345 INFO L93 Difference]: Finished difference Result 3251 states and 4611 transitions. [2021-08-27 16:30:35,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:35,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3251 states and 4611 transitions. [2021-08-27 16:30:35,358 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3164 [2021-08-27 16:30:35,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3251 states to 3251 states and 4611 transitions. [2021-08-27 16:30:35,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3251 [2021-08-27 16:30:35,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3251 [2021-08-27 16:30:35,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3251 states and 4611 transitions. [2021-08-27 16:30:35,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,375 INFO L681 BuchiCegarLoop]: Abstraction has 3251 states and 4611 transitions. [2021-08-27 16:30:35,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3251 states and 4611 transitions. [2021-08-27 16:30:35,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3251 to 3243. [2021-08-27 16:30:35,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3243 states, 3243 states have (on average 1.4193647856922602) internal successors, (4603), 3242 states have internal predecessors, (4603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3243 states to 3243 states and 4603 transitions. [2021-08-27 16:30:35,440 INFO L704 BuchiCegarLoop]: Abstraction has 3243 states and 4603 transitions. [2021-08-27 16:30:35,440 INFO L587 BuchiCegarLoop]: Abstraction has 3243 states and 4603 transitions. [2021-08-27 16:30:35,440 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-08-27 16:30:35,440 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3243 states and 4603 transitions. [2021-08-27 16:30:35,449 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3156 [2021-08-27 16:30:35,449 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,449 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,450 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,450 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,450 INFO L791 eck$LassoCheckResult]: Stem: 21241#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21209#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21206#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20745#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 20746#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20829#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21179#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21180#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21116#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20870#L431-1 assume !(0 == ~M_E~0); 20871#L591-1 assume !(0 == ~T1_E~0); 20993#L596-1 assume !(0 == ~T2_E~0); 20994#L601-1 assume !(0 == ~T3_E~0); 21047#L606-1 assume !(0 == ~T4_E~0); 21048#L611-1 assume !(0 == ~T5_E~0); 21126#L616-1 assume !(0 == ~E_M~0); 21127#L621-1 assume !(0 == ~E_1~0); 20732#L626-1 assume !(0 == ~E_2~0); 20733#L631-1 assume !(0 == ~E_3~0); 20901#L636-1 assume !(0 == ~E_4~0); 20756#L641-1 assume !(0 == ~E_5~0); 20757#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20740#L284 assume !(1 == ~m_pc~0); 20741#L284-2 is_master_triggered_~__retres1~0 := 0; 20873#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20728#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20729#L735 assume !(0 != activate_threads_~tmp~1); 20835#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20836#L303 assume !(1 == ~t1_pc~0); 21036#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 21234#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20720#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20721#L743 assume !(0 != activate_threads_~tmp___0~0); 20747#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20748#L322 assume !(1 == ~t2_pc~0); 20970#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 20964#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20695#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20669#L751 assume !(0 != activate_threads_~tmp___1~0); 20670#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20762#L341 assume !(1 == ~t3_pc~0); 20699#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 20700#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20777#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20778#L759 assume !(0 != activate_threads_~tmp___2~0); 21207#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21072#L360 assume !(1 == ~t4_pc~0); 20996#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 20997#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21198#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21199#L767 assume !(0 != activate_threads_~tmp___3~0); 21197#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21144#L379 assume !(1 == ~t5_pc~0); 20803#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 20804#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21000#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21117#L775 assume !(0 != activate_threads_~tmp___4~0); 20645#L775-2 assume !(1 == ~M_E~0); 20646#L659-1 assume !(1 == ~T1_E~0); 20924#L664-1 assume !(1 == ~T2_E~0); 20703#L669-1 assume !(1 == ~T3_E~0); 20704#L674-1 assume !(1 == ~T4_E~0); 21107#L679-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20801#L684-1 assume !(1 == ~E_M~0); 20802#L689-1 assume !(1 == ~E_1~0); 20992#L694-1 assume !(1 == ~E_2~0); 20990#L699-1 assume !(1 == ~E_3~0); 20991#L704-1 assume !(1 == ~E_4~0); 20953#L709-1 assume !(1 == ~E_5~0); 20718#L920-1 [2021-08-27 16:30:35,450 INFO L793 eck$LassoCheckResult]: Loop: 20718#L920-1 assume !false; 20719#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 20818#L566 assume !false; 20819#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 21136#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 20815#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 20915#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 20916#L491 assume !(0 != eval_~tmp~0); 21062#L581 start_simulation_~kernel_st~0 := 2; 23399#L399-1 start_simulation_~kernel_st~0 := 3; 23398#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23395#L591-4 assume !(0 == ~T1_E~0); 23393#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23391#L601-3 assume !(0 == ~T3_E~0); 23389#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23387#L611-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23384#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23382#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23381#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23380#L631-3 assume !(0 == ~E_3~0); 23379#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23374#L641-3 assume !(0 == ~E_5~0); 23371#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20671#L284-21 assume !(1 == ~m_pc~0); 20672#L284-23 is_master_triggered_~__retres1~0 := 0; 23622#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23620#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23619#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23618#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23613#L303-21 assume !(1 == ~t1_pc~0); 23611#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 23609#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23607#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23605#L743-21 assume !(0 != activate_threads_~tmp___0~0); 23602#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23600#L322-21 assume !(1 == ~t2_pc~0); 23321#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 23597#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23596#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23595#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20761#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20666#L341-21 assume 1 == ~t3_pc~0; 20667#L342-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20798#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21022#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21023#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20743#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20744#L360-21 assume !(1 == ~t4_pc~0); 20816#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 20817#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21213#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21088#L767-21 assume !(0 != activate_threads_~tmp___3~0); 21089#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21069#L379-21 assume !(1 == ~t5_pc~0); 20636#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 20812#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20766#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20767#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 20641#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 20642#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20773#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20683#L669-3 assume !(1 == ~T3_E~0); 20684#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21239#L679-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20966#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20967#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23500#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23498#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21070#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21071#L709-3 assume !(1 == ~E_5~0); 23495#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23492#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 23486#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23484#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 23480#L939 assume !(0 == start_simulation_~tmp~3); 23479#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 21182#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 20759#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 20987#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 20693#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20694#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 21135#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 20858#L952 assume !(0 != start_simulation_~tmp___0~1); 20718#L920-1 [2021-08-27 16:30:35,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,451 INFO L82 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-08-27 16:30:35,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024591123] [2021-08-27 16:30:35,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,451 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,475 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,476 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024591123] [2021-08-27 16:30:35,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024591123] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,476 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,476 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:35,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103933618] [2021-08-27 16:30:35,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:35,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,477 INFO L82 PathProgramCache]: Analyzing trace with hash 54685135, now seen corresponding path program 1 times [2021-08-27 16:30:35,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,478 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1870397167] [2021-08-27 16:30:35,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,478 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,507 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,507 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1870397167] [2021-08-27 16:30:35,507 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1870397167] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,507 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,507 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:35,507 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526172486] [2021-08-27 16:30:35,507 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:35,508 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:35,508 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:35,509 INFO L87 Difference]: Start difference. First operand 3243 states and 4603 transitions. cyclomatic complexity: 1364 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,533 INFO L93 Difference]: Finished difference Result 3243 states and 4577 transitions. [2021-08-27 16:30:35,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:35,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3243 states and 4577 transitions. [2021-08-27 16:30:35,551 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3156 [2021-08-27 16:30:35,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3243 states to 3243 states and 4577 transitions. [2021-08-27 16:30:35,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3243 [2021-08-27 16:30:35,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3243 [2021-08-27 16:30:35,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3243 states and 4577 transitions. [2021-08-27 16:30:35,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,597 INFO L681 BuchiCegarLoop]: Abstraction has 3243 states and 4577 transitions. [2021-08-27 16:30:35,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3243 states and 4577 transitions. [2021-08-27 16:30:35,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3243 to 3243. [2021-08-27 16:30:35,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3243 states, 3243 states have (on average 1.4113475177304964) internal successors, (4577), 3242 states have internal predecessors, (4577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3243 states to 3243 states and 4577 transitions. [2021-08-27 16:30:35,655 INFO L704 BuchiCegarLoop]: Abstraction has 3243 states and 4577 transitions. [2021-08-27 16:30:35,655 INFO L587 BuchiCegarLoop]: Abstraction has 3243 states and 4577 transitions. [2021-08-27 16:30:35,655 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-08-27 16:30:35,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3243 states and 4577 transitions. [2021-08-27 16:30:35,664 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3156 [2021-08-27 16:30:35,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,666 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,666 INFO L791 eck$LassoCheckResult]: Stem: 27714#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 27687#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 27683#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27237#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 27238#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27325#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27660#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27661#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27605#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27365#L431-1 assume !(0 == ~M_E~0); 27366#L591-1 assume !(0 == ~T1_E~0); 27486#L596-1 assume !(0 == ~T2_E~0); 27487#L601-1 assume !(0 == ~T3_E~0); 27539#L606-1 assume !(0 == ~T4_E~0); 27540#L611-1 assume !(0 == ~T5_E~0); 27617#L616-1 assume !(0 == ~E_M~0); 27618#L621-1 assume !(0 == ~E_1~0); 27224#L626-1 assume !(0 == ~E_2~0); 27225#L631-1 assume !(0 == ~E_3~0); 27395#L636-1 assume !(0 == ~E_4~0); 27248#L641-1 assume !(0 == ~E_5~0); 27249#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27231#L284 assume !(1 == ~m_pc~0); 27232#L284-2 is_master_triggered_~__retres1~0 := 0; 27368#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27219#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27220#L735 assume !(0 != activate_threads_~tmp~1); 27331#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27332#L303 assume !(1 == ~t1_pc~0); 27528#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 27708#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27213#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27214#L743 assume !(0 != activate_threads_~tmp___0~0); 27239#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27240#L322 assume !(1 == ~t2_pc~0); 27464#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 27461#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27188#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27163#L751 assume !(0 != activate_threads_~tmp___1~0); 27164#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27258#L341 assume !(1 == ~t3_pc~0); 27193#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 27194#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27272#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27273#L759 assume !(0 != activate_threads_~tmp___2~0); 27684#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27561#L360 assume !(1 == ~t4_pc~0); 27489#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 27490#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27679#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27680#L767 assume !(0 != activate_threads_~tmp___3~0); 27677#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27633#L379 assume !(1 == ~t5_pc~0); 27301#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 27302#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27494#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27608#L775 assume !(0 != activate_threads_~tmp___4~0); 27140#L775-2 assume !(1 == ~M_E~0); 27141#L659-1 assume !(1 == ~T1_E~0); 27418#L664-1 assume !(1 == ~T2_E~0); 27195#L669-1 assume !(1 == ~T3_E~0); 27196#L674-1 assume !(1 == ~T4_E~0); 27598#L679-1 assume !(1 == ~T5_E~0); 27297#L684-1 assume !(1 == ~E_M~0); 27298#L689-1 assume !(1 == ~E_1~0); 27485#L694-1 assume !(1 == ~E_2~0); 27483#L699-1 assume !(1 == ~E_3~0); 27484#L704-1 assume !(1 == ~E_4~0); 27449#L709-1 assume !(1 == ~E_5~0); 27450#L920-1 [2021-08-27 16:30:35,666 INFO L793 eck$LassoCheckResult]: Loop: 27450#L920-1 assume !false; 28298#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 28296#L566 assume !false; 28295#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28289#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28288#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28287#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 28286#L491 assume !(0 != eval_~tmp~0); 27537#L581 start_simulation_~kernel_st~0 := 2; 27538#L399-1 start_simulation_~kernel_st~0 := 3; 27326#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 27327#L591-4 assume !(0 == ~T1_E~0); 27321#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27322#L601-3 assume !(0 == ~T3_E~0); 27648#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27557#L611-3 assume !(0 == ~T5_E~0); 27558#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27215#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27216#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30336#L631-3 assume !(0 == ~E_3~0); 27173#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27174#L641-3 assume !(0 == ~E_5~0); 27223#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27165#L284-21 assume !(1 == ~m_pc~0); 27166#L284-23 is_master_triggered_~__retres1~0 := 0; 27205#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27206#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27228#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27134#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27135#L303-21 assume !(1 == ~t1_pc~0); 27380#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 27425#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27426#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27524#L743-21 assume !(0 != activate_threads_~tmp___0~0); 27430#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27431#L322-21 assume !(1 == ~t2_pc~0); 29027#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 29026#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29025#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29024#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29023#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29022#L341-21 assume !(1 == ~t3_pc~0); 29020#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 29018#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29016#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 29014#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29011#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29009#L360-21 assume !(1 == ~t4_pc~0); 29007#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 29005#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29003#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 29001#L767-21 assume !(0 != activate_threads_~tmp___3~0); 28999#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28997#L379-21 assume !(1 == ~t5_pc~0); 28994#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 28992#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28989#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 28987#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 28985#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 28983#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28981#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28979#L669-3 assume !(1 == ~T3_E~0); 28976#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28974#L679-3 assume !(1 == ~T5_E~0); 28972#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28970#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28968#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28965#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28963#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28961#L709-3 assume !(1 == ~E_5~0); 28959#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28954#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28948#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28946#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 28587#L939 assume !(0 == start_simulation_~tmp~3); 28585#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28576#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28569#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28565#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 28559#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28557#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 28555#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 28554#L952 assume !(0 != start_simulation_~tmp___0~1); 27450#L920-1 [2021-08-27 16:30:35,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,667 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-08-27 16:30:35,667 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,668 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293429571] [2021-08-27 16:30:35,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,669 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,684 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:35,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:35,721 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:35,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:35,722 INFO L82 PathProgramCache]: Analyzing trace with hash -1964537558, now seen corresponding path program 1 times [2021-08-27 16:30:35,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:35,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113709547] [2021-08-27 16:30:35,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:35,723 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:35,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:35,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:35,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:35,752 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113709547] [2021-08-27 16:30:35,752 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113709547] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:35,753 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:35,753 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:35,753 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446192153] [2021-08-27 16:30:35,753 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:35,753 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:35,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-27 16:30:35,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-27 16:30:35,754 INFO L87 Difference]: Start difference. First operand 3243 states and 4577 transitions. cyclomatic complexity: 1338 Second operand has 5 states, 5 states have (on average 16.6) internal successors, (83), 5 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:35,857 INFO L93 Difference]: Finished difference Result 5799 states and 8077 transitions. [2021-08-27 16:30:35,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-08-27 16:30:35,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5799 states and 8077 transitions. [2021-08-27 16:30:35,881 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5700 [2021-08-27 16:30:35,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5799 states to 5799 states and 8077 transitions. [2021-08-27 16:30:35,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5799 [2021-08-27 16:30:35,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5799 [2021-08-27 16:30:35,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5799 states and 8077 transitions. [2021-08-27 16:30:35,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:35,943 INFO L681 BuchiCegarLoop]: Abstraction has 5799 states and 8077 transitions. [2021-08-27 16:30:35,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5799 states and 8077 transitions. [2021-08-27 16:30:35,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5799 to 3267. [2021-08-27 16:30:35,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3267 states, 3267 states have (on average 1.4083256810529539) internal successors, (4601), 3266 states have internal predecessors, (4601), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:35,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3267 states to 3267 states and 4601 transitions. [2021-08-27 16:30:35,989 INFO L704 BuchiCegarLoop]: Abstraction has 3267 states and 4601 transitions. [2021-08-27 16:30:35,989 INFO L587 BuchiCegarLoop]: Abstraction has 3267 states and 4601 transitions. [2021-08-27 16:30:35,990 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-08-27 16:30:35,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3267 states and 4601 transitions. [2021-08-27 16:30:35,998 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3180 [2021-08-27 16:30:35,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:35,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:35,999 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,999 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:35,999 INFO L791 eck$LassoCheckResult]: Stem: 36798#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 36761#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36756#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36295#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 36296#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36384#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36730#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36731#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36668#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36426#L431-1 assume !(0 == ~M_E~0); 36427#L591-1 assume !(0 == ~T1_E~0); 36550#L596-1 assume !(0 == ~T2_E~0); 36551#L601-1 assume !(0 == ~T3_E~0); 36603#L606-1 assume !(0 == ~T4_E~0); 36604#L611-1 assume !(0 == ~T5_E~0); 36678#L616-1 assume !(0 == ~E_M~0); 36679#L621-1 assume !(0 == ~E_1~0); 36282#L626-1 assume !(0 == ~E_2~0); 36283#L631-1 assume !(0 == ~E_3~0); 36456#L636-1 assume !(0 == ~E_4~0); 36306#L641-1 assume !(0 == ~E_5~0); 36307#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36290#L284 assume !(1 == ~m_pc~0); 36291#L284-2 is_master_triggered_~__retres1~0 := 0; 36429#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36277#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36278#L735 assume !(0 != activate_threads_~tmp~1); 36390#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36391#L303 assume !(1 == ~t1_pc~0); 36591#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 36790#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36272#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36273#L743 assume !(0 != activate_threads_~tmp___0~0); 36297#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36298#L322 assume !(1 == ~t2_pc~0); 36528#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 36522#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36247#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36221#L751 assume !(0 != activate_threads_~tmp___1~0); 36222#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36317#L341 assume !(1 == ~t3_pc~0); 36252#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 36253#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36330#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36331#L759 assume !(0 != activate_threads_~tmp___2~0); 36757#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36625#L360 assume !(1 == ~t4_pc~0); 36553#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 36554#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36749#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36750#L767 assume !(0 != activate_threads_~tmp___3~0); 36748#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36694#L379 assume !(1 == ~t5_pc~0); 36358#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 36359#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36558#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36671#L775 assume !(0 != activate_threads_~tmp___4~0); 36198#L775-2 assume !(1 == ~M_E~0); 36199#L659-1 assume !(1 == ~T1_E~0); 36479#L664-1 assume !(1 == ~T2_E~0); 36254#L669-1 assume !(1 == ~T3_E~0); 36255#L674-1 assume !(1 == ~T4_E~0); 36658#L679-1 assume !(1 == ~T5_E~0); 36354#L684-1 assume !(1 == ~E_M~0); 36355#L689-1 assume !(1 == ~E_1~0); 36549#L694-1 assume !(1 == ~E_2~0); 36547#L699-1 assume !(1 == ~E_3~0); 36548#L704-1 assume !(1 == ~E_4~0); 36510#L709-1 assume !(1 == ~E_5~0); 36511#L920-1 [2021-08-27 16:30:35,999 INFO L793 eck$LassoCheckResult]: Loop: 36511#L920-1 assume !false; 39095#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 36375#L566 assume !false; 36376#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36687#L444 assume !(0 == ~m_st~0); 36392#L448 assume !(0 == ~t1_st~0); 36393#L452 assume !(0 == ~t2_st~0); 36367#L456 assume !(0 == ~t3_st~0); 36368#L460 assume !(0 == ~t4_st~0); 36650#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 36794#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 38586#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 37461#L491 assume !(0 != eval_~tmp~0); 36599#L581 start_simulation_~kernel_st~0 := 2; 36600#L399-1 start_simulation_~kernel_st~0 := 3; 36385#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36386#L591-4 assume !(0 == ~T1_E~0); 37164#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36581#L601-3 assume !(0 == ~T3_E~0); 36582#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36621#L611-3 assume !(0 == ~T5_E~0); 36622#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36274#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36229#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36230#L631-3 assume !(0 == ~E_3~0); 36231#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36232#L641-3 assume !(0 == ~E_5~0); 36281#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36227#L284-21 assume !(1 == ~m_pc~0); 36228#L284-23 is_master_triggered_~__retres1~0 := 0; 36264#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36265#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 36523#L735-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 36524#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36441#L303-21 assume !(1 == ~t1_pc~0); 36442#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 39089#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39087#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 39085#L743-21 assume !(0 != activate_threads_~tmp___0~0); 36492#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36493#L322-21 assume !(1 == ~t2_pc~0); 36685#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 36713#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36698#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 36699#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36311#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36312#L341-21 assume !(1 == ~t3_pc~0); 39144#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 36585#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36576#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 36577#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36293#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36294#L360-21 assume !(1 == ~t4_pc~0); 36370#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 36371#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36764#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36765#L767-21 assume !(0 != activate_threads_~tmp___3~0); 36754#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36755#L379-21 assume !(1 == ~t5_pc~0); 36233#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 36234#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36318#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36319#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 36194#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 36195#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36784#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36785#L669-3 assume !(1 == ~T3_E~0); 36795#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36796#L679-3 assume !(1 == ~T5_E~0); 39052#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39053#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39048#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39049#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39044#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39045#L709-3 assume !(1 == ~E_5~0); 36612#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 36613#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39136#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39133#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 39129#L939 assume !(0 == start_simulation_~tmp~3); 39121#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39118#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39112#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39110#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 39108#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39106#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 39104#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 39100#L952 assume !(0 != start_simulation_~tmp___0~1); 36511#L920-1 [2021-08-27 16:30:36,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,000 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-08-27 16:30:36,000 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,000 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774238022] [2021-08-27 16:30:36,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,001 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,006 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,021 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,021 INFO L82 PathProgramCache]: Analyzing trace with hash 1652645187, now seen corresponding path program 1 times [2021-08-27 16:30:36,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,021 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263482452] [2021-08-27 16:30:36,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,022 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:36,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:36,065 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:36,065 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263482452] [2021-08-27 16:30:36,065 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263482452] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:36,065 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:36,066 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-27 16:30:36,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37720354] [2021-08-27 16:30:36,066 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:36,066 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:36,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-27 16:30:36,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-27 16:30:36,067 INFO L87 Difference]: Start difference. First operand 3267 states and 4601 transitions. cyclomatic complexity: 1338 Second operand has 5 states, 5 states have (on average 17.6) internal successors, (88), 5 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:36,259 INFO L93 Difference]: Finished difference Result 6427 states and 8988 transitions. [2021-08-27 16:30:36,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-08-27 16:30:36,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6427 states and 8988 transitions. [2021-08-27 16:30:36,284 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6332 [2021-08-27 16:30:36,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6427 states to 6427 states and 8988 transitions. [2021-08-27 16:30:36,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6427 [2021-08-27 16:30:36,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6427 [2021-08-27 16:30:36,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6427 states and 8988 transitions. [2021-08-27 16:30:36,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:36,327 INFO L681 BuchiCegarLoop]: Abstraction has 6427 states and 8988 transitions. [2021-08-27 16:30:36,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6427 states and 8988 transitions. [2021-08-27 16:30:36,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6427 to 3351. [2021-08-27 16:30:36,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3351 states, 3351 states have (on average 1.3906296627872277) internal successors, (4660), 3350 states have internal predecessors, (4660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3351 states to 3351 states and 4660 transitions. [2021-08-27 16:30:36,386 INFO L704 BuchiCegarLoop]: Abstraction has 3351 states and 4660 transitions. [2021-08-27 16:30:36,386 INFO L587 BuchiCegarLoop]: Abstraction has 3351 states and 4660 transitions. [2021-08-27 16:30:36,386 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-08-27 16:30:36,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3351 states and 4660 transitions. [2021-08-27 16:30:36,395 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3264 [2021-08-27 16:30:36,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:36,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:36,396 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,396 INFO L791 eck$LassoCheckResult]: Stem: 46511#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 46478#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 46475#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 46002#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 46003#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46088#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46453#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46454#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46387#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46130#L431-1 assume !(0 == ~M_E~0); 46131#L591-1 assume !(0 == ~T1_E~0); 46257#L596-1 assume !(0 == ~T2_E~0); 46258#L601-1 assume !(0 == ~T3_E~0); 46312#L606-1 assume !(0 == ~T4_E~0); 46313#L611-1 assume !(0 == ~T5_E~0); 46395#L616-1 assume !(0 == ~E_M~0); 46396#L621-1 assume !(0 == ~E_1~0); 45989#L626-1 assume !(0 == ~E_2~0); 45990#L631-1 assume !(0 == ~E_3~0); 46160#L636-1 assume !(0 == ~E_4~0); 46013#L641-1 assume !(0 == ~E_5~0); 46014#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45997#L284 assume !(1 == ~m_pc~0); 45998#L284-2 is_master_triggered_~__retres1~0 := 0; 46133#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45985#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 45986#L735 assume !(0 != activate_threads_~tmp~1); 46094#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46095#L303 assume !(1 == ~t1_pc~0); 46299#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 46502#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45979#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 45980#L743 assume !(0 != activate_threads_~tmp___0~0); 46004#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46005#L322 assume !(1 == ~t2_pc~0); 46232#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 46227#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45954#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 45928#L751 assume !(0 != activate_threads_~tmp___1~0); 45929#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46019#L341 assume !(1 == ~t3_pc~0); 45958#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 45959#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46035#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 46036#L759 assume !(0 != activate_threads_~tmp___2~0); 46476#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46335#L360 assume !(1 == ~t4_pc~0); 46260#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 46261#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46470#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 46471#L767 assume !(0 != activate_threads_~tmp___3~0); 46469#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46414#L379 assume !(1 == ~t5_pc~0); 46061#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 46062#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46264#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 46388#L775 assume !(0 != activate_threads_~tmp___4~0); 45905#L775-2 assume !(1 == ~M_E~0); 45906#L659-1 assume !(1 == ~T1_E~0); 46184#L664-1 assume !(1 == ~T2_E~0); 45962#L669-1 assume !(1 == ~T3_E~0); 45963#L674-1 assume !(1 == ~T4_E~0); 46378#L679-1 assume !(1 == ~T5_E~0); 46059#L684-1 assume !(1 == ~E_M~0); 46060#L689-1 assume !(1 == ~E_1~0); 46256#L694-1 assume !(1 == ~E_2~0); 46254#L699-1 assume !(1 == ~E_3~0); 46255#L704-1 assume !(1 == ~E_4~0); 46214#L709-1 assume !(1 == ~E_5~0); 46215#L920-1 [2021-08-27 16:30:36,396 INFO L793 eck$LassoCheckResult]: Loop: 46215#L920-1 assume !false; 47726#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 47722#L566 assume !false; 47721#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47696#L444 assume !(0 == ~m_st~0); 47697#L448 assume !(0 == ~t1_st~0); 47700#L452 assume !(0 == ~t2_st~0); 47702#L456 assume !(0 == ~t3_st~0); 47698#L460 assume !(0 == ~t4_st~0); 47699#L464 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 47701#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47121#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 47122#L491 assume !(0 != eval_~tmp~0); 48429#L581 start_simulation_~kernel_st~0 := 2; 48428#L399-1 start_simulation_~kernel_st~0 := 3; 48427#L591-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48426#L591-4 assume !(0 == ~T1_E~0); 48425#L596-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48424#L601-3 assume !(0 == ~T3_E~0); 48423#L606-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48422#L611-3 assume !(0 == ~T5_E~0); 48421#L616-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48420#L621-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48419#L626-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48418#L631-3 assume !(0 == ~E_3~0); 48417#L636-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48416#L641-3 assume !(0 == ~E_5~0); 46243#L646-3 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45930#L284-21 assume !(1 == ~m_pc~0); 45931#L284-23 is_master_triggered_~__retres1~0 := 0; 48005#L295-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48004#L296-7 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 48003#L735-21 assume !(0 != activate_threads_~tmp~1); 48002#L735-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48001#L303-21 assume !(1 == ~t1_pc~0); 48000#L303-23 is_transmit1_triggered_~__retres1~1 := 0; 47997#L314-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47994#L315-7 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 47991#L743-21 assume !(0 != activate_threads_~tmp___0~0); 47988#L743-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47986#L322-21 assume !(1 == ~t2_pc~0); 47495#L322-23 is_transmit2_triggered_~__retres1~2 := 0; 47981#L333-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47978#L334-7 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 47975#L751-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 47973#L751-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47971#L341-21 assume !(1 == ~t3_pc~0); 47969#L341-23 is_transmit3_triggered_~__retres1~3 := 0; 47967#L352-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47965#L353-7 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 47963#L759-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 47961#L759-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 47958#L360-21 assume !(1 == ~t4_pc~0); 47954#L360-23 is_transmit4_triggered_~__retres1~4 := 0; 47951#L371-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47948#L372-7 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 47945#L767-21 assume !(0 != activate_threads_~tmp___3~0); 47942#L767-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 47939#L379-21 assume !(1 == ~t5_pc~0); 47935#L379-23 is_transmit5_triggered_~__retres1~5 := 0; 47931#L390-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 47927#L391-7 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 47923#L775-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 47919#L775-23 assume 1 == ~M_E~0;~M_E~0 := 2; 47914#L659-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47910#L664-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47906#L669-3 assume !(1 == ~T3_E~0); 47902#L674-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47898#L679-3 assume !(1 == ~T5_E~0); 47893#L684-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47888#L689-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47884#L694-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47880#L699-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47876#L704-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47871#L709-3 assume !(1 == ~E_5~0); 47867#L714-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47795#L444-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 47789#L476-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47787#L477-1 start_simulation_#t~ret22 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret22;havoc start_simulation_#t~ret22; 47778#L939 assume !(0 == start_simulation_~tmp~3); 47777#L939-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret21, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47768#L444-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 47760#L476-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47756#L477-2 stop_simulation_#t~ret21 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret21;havoc stop_simulation_#t~ret21; 47752#L894 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47747#L901 stop_simulation_#res := stop_simulation_~__retres2~0; 47743#L902 start_simulation_#t~ret23 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 47737#L952 assume !(0 != start_simulation_~tmp___0~1); 46215#L920-1 [2021-08-27 16:30:36,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,399 INFO L82 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-08-27 16:30:36,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,399 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497751921] [2021-08-27 16:30:36,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,399 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,407 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,422 INFO L82 PathProgramCache]: Analyzing trace with hash 1693319937, now seen corresponding path program 1 times [2021-08-27 16:30:36,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,422 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177429852] [2021-08-27 16:30:36,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,422 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:36,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:36,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:36,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177429852] [2021-08-27 16:30:36,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177429852] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:36,442 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:36,442 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:36,442 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545296462] [2021-08-27 16:30:36,443 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-27 16:30:36,443 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:36,443 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:36,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:36,444 INFO L87 Difference]: Start difference. First operand 3351 states and 4660 transitions. cyclomatic complexity: 1313 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:36,492 INFO L93 Difference]: Finished difference Result 5753 states and 7886 transitions. [2021-08-27 16:30:36,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:36,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5753 states and 7886 transitions. [2021-08-27 16:30:36,534 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5656 [2021-08-27 16:30:36,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5753 states to 5753 states and 7886 transitions. [2021-08-27 16:30:36,551 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5753 [2021-08-27 16:30:36,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5753 [2021-08-27 16:30:36,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5753 states and 7886 transitions. [2021-08-27 16:30:36,561 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:36,561 INFO L681 BuchiCegarLoop]: Abstraction has 5753 states and 7886 transitions. [2021-08-27 16:30:36,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5753 states and 7886 transitions. [2021-08-27 16:30:36,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5753 to 5601. [2021-08-27 16:30:36,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5601 states, 5601 states have (on average 1.3722549544724156) internal successors, (7686), 5600 states have internal predecessors, (7686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5601 states to 5601 states and 7686 transitions. [2021-08-27 16:30:36,638 INFO L704 BuchiCegarLoop]: Abstraction has 5601 states and 7686 transitions. [2021-08-27 16:30:36,638 INFO L587 BuchiCegarLoop]: Abstraction has 5601 states and 7686 transitions. [2021-08-27 16:30:36,638 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-08-27 16:30:36,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5601 states and 7686 transitions. [2021-08-27 16:30:36,656 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5504 [2021-08-27 16:30:36,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:36,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:36,657 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,657 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:36,657 INFO L791 eck$LassoCheckResult]: Stem: 55583#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 55551#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 55548#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55112#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 55113#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55196#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55526#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55527#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55470#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55238#L431-1 assume !(0 == ~M_E~0); 55239#L591-1 assume !(0 == ~T1_E~0); 55358#L596-1 assume !(0 == ~T2_E~0); 55359#L601-1 assume !(0 == ~T3_E~0); 55408#L606-1 assume !(0 == ~T4_E~0); 55409#L611-1 assume !(0 == ~T5_E~0); 55479#L616-1 assume !(0 == ~E_M~0); 55480#L621-1 assume !(0 == ~E_1~0); 55099#L626-1 assume !(0 == ~E_2~0); 55100#L631-1 assume !(0 == ~E_3~0); 55267#L636-1 assume !(0 == ~E_4~0); 55123#L641-1 assume !(0 == ~E_5~0); 55124#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55107#L284 assume !(1 == ~m_pc~0); 55108#L284-2 is_master_triggered_~__retres1~0 := 0; 55241#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55095#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 55096#L735 assume !(0 != activate_threads_~tmp~1); 55202#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55203#L303 assume !(1 == ~t1_pc~0); 55398#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 55574#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55087#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55088#L743 assume !(0 != activate_threads_~tmp___0~0); 55114#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55115#L322 assume !(1 == ~t2_pc~0); 55336#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 55332#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55064#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55038#L751 assume !(0 != activate_threads_~tmp___1~0); 55039#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55129#L341 assume !(1 == ~t3_pc~0); 55068#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 55069#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55144#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 55145#L759 assume !(0 != activate_threads_~tmp___2~0); 55549#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55429#L360 assume !(1 == ~t4_pc~0); 55361#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 55362#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55542#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 55543#L767 assume !(0 != activate_threads_~tmp___3~0); 55541#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55496#L379 assume !(1 == ~t5_pc~0); 55171#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 55172#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55365#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55471#L775 assume !(0 != activate_threads_~tmp___4~0); 55015#L775-2 assume !(1 == ~M_E~0); 55016#L659-1 assume !(1 == ~T1_E~0); 55290#L664-1 assume !(1 == ~T2_E~0); 55071#L669-1 assume !(1 == ~T3_E~0); 55072#L674-1 assume !(1 == ~T4_E~0); 55463#L679-1 assume !(1 == ~T5_E~0); 55169#L684-1 assume !(1 == ~E_M~0); 55170#L689-1 assume !(1 == ~E_1~0); 55357#L694-1 assume !(1 == ~E_2~0); 55355#L699-1 assume !(1 == ~E_3~0); 55356#L704-1 assume !(1 == ~E_4~0); 55320#L709-1 assume !(1 == ~E_5~0); 55321#L920-1 assume !false; 58523#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 58521#L566 [2021-08-27 16:30:36,658 INFO L793 eck$LassoCheckResult]: Loop: 58521#L566 assume !false; 58518#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 58515#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 58513#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 58511#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 58509#L491 assume 0 != eval_~tmp~0; 58504#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 58501#L499 assume !(0 != eval_~tmp_ndt_1~0); 58497#L496 assume !(0 == ~t1_st~0); 58496#L510 assume !(0 == ~t2_st~0); 58495#L524 assume !(0 == ~t3_st~0); 58532#L538 assume !(0 == ~t4_st~0); 58527#L552 assume !(0 == ~t5_st~0); 58521#L566 [2021-08-27 16:30:36,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,658 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-08-27 16:30:36,659 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,659 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482465504] [2021-08-27 16:30:36,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,659 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,667 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,690 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,691 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 1 times [2021-08-27 16:30:36,691 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,691 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [510711382] [2021-08-27 16:30:36,691 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,691 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,694 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:36,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:36,698 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:36,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:36,699 INFO L82 PathProgramCache]: Analyzing trace with hash 1743073375, now seen corresponding path program 1 times [2021-08-27 16:30:36,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:36,699 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [963150898] [2021-08-27 16:30:36,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:36,700 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:36,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:36,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:36,719 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:36,719 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [963150898] [2021-08-27 16:30:36,719 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [963150898] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:36,719 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:36,719 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:36,719 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535281638] [2021-08-27 16:30:36,834 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:36,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:36,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:36,835 INFO L87 Difference]: Start difference. First operand 5601 states and 7686 transitions. cyclomatic complexity: 2091 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:36,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:36,907 INFO L93 Difference]: Finished difference Result 10445 states and 14230 transitions. [2021-08-27 16:30:36,908 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:36,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10445 states and 14230 transitions. [2021-08-27 16:30:36,950 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10256 [2021-08-27 16:30:36,978 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10445 states to 10445 states and 14230 transitions. [2021-08-27 16:30:36,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10445 [2021-08-27 16:30:36,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10445 [2021-08-27 16:30:36,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10445 states and 14230 transitions. [2021-08-27 16:30:36,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:36,999 INFO L681 BuchiCegarLoop]: Abstraction has 10445 states and 14230 transitions. [2021-08-27 16:30:37,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10445 states and 14230 transitions. [2021-08-27 16:30:37,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10445 to 9965. [2021-08-27 16:30:37,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9965 states, 9965 states have (on average 1.3653788258906172) internal successors, (13606), 9964 states have internal predecessors, (13606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,133 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9965 states to 9965 states and 13606 transitions. [2021-08-27 16:30:37,134 INFO L704 BuchiCegarLoop]: Abstraction has 9965 states and 13606 transitions. [2021-08-27 16:30:37,134 INFO L587 BuchiCegarLoop]: Abstraction has 9965 states and 13606 transitions. [2021-08-27 16:30:37,134 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-08-27 16:30:37,134 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9965 states and 13606 transitions. [2021-08-27 16:30:37,163 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9776 [2021-08-27 16:30:37,164 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:37,164 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:37,164 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,164 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,165 INFO L791 eck$LassoCheckResult]: Stem: 71672#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 71643#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 71640#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 71168#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 71169#L406-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 71252#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76712#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76711#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76710#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76709#L431-1 assume !(0 == ~M_E~0); 76708#L591-1 assume !(0 == ~T1_E~0); 76707#L596-1 assume !(0 == ~T2_E~0); 76706#L601-1 assume !(0 == ~T3_E~0); 76705#L606-1 assume !(0 == ~T4_E~0); 76704#L611-1 assume !(0 == ~T5_E~0); 76703#L616-1 assume !(0 == ~E_M~0); 76702#L621-1 assume !(0 == ~E_1~0); 76701#L626-1 assume !(0 == ~E_2~0); 76700#L631-1 assume !(0 == ~E_3~0); 76699#L636-1 assume !(0 == ~E_4~0); 76698#L641-1 assume !(0 == ~E_5~0); 76697#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76696#L284 assume !(1 == ~m_pc~0); 76695#L284-2 is_master_triggered_~__retres1~0 := 0; 76694#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76693#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76692#L735 assume !(0 != activate_threads_~tmp~1); 76691#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76690#L303 assume !(1 == ~t1_pc~0); 76689#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 76714#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76713#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 76684#L743 assume !(0 != activate_threads_~tmp___0~0); 76683#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76682#L322 assume !(1 == ~t2_pc~0); 76681#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 76680#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76679#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 76678#L751 assume !(0 != activate_threads_~tmp___1~0); 76677#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76676#L341 assume !(1 == ~t3_pc~0); 76674#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 76673#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76672#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 76671#L759 assume !(0 != activate_threads_~tmp___2~0); 76670#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76669#L360 assume !(1 == ~t4_pc~0); 76668#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 76667#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76666#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 76665#L767 assume !(0 != activate_threads_~tmp___3~0); 76664#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76662#L379 assume !(1 == ~t5_pc~0); 76661#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 76660#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76659#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 76658#L775 assume !(0 != activate_threads_~tmp___4~0); 76657#L775-2 assume !(1 == ~M_E~0); 76656#L659-1 assume !(1 == ~T1_E~0); 76655#L664-1 assume !(1 == ~T2_E~0); 76654#L669-1 assume !(1 == ~T3_E~0); 76653#L674-1 assume !(1 == ~T4_E~0); 76652#L679-1 assume !(1 == ~T5_E~0); 76651#L684-1 assume !(1 == ~E_M~0); 76650#L689-1 assume !(1 == ~E_1~0); 76649#L694-1 assume !(1 == ~E_2~0); 76648#L699-1 assume !(1 == ~E_3~0); 76647#L704-1 assume !(1 == ~E_4~0); 76645#L709-1 assume !(1 == ~E_5~0); 76643#L920-1 assume !false; 76574#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 76573#L566 [2021-08-27 16:30:37,165 INFO L793 eck$LassoCheckResult]: Loop: 76573#L566 assume !false; 76569#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 76566#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 76564#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 76561#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 76559#L491 assume 0 != eval_~tmp~0; 76556#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 76159#L499 assume !(0 != eval_~tmp_ndt_1~0); 76160#L496 assume !(0 == ~t1_st~0); 76197#L510 assume !(0 == ~t2_st~0); 76196#L524 assume !(0 == ~t3_st~0); 76581#L538 assume !(0 == ~t4_st~0); 76578#L552 assume !(0 == ~t5_st~0); 76573#L566 [2021-08-27 16:30:37,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,165 INFO L82 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-08-27 16:30:37,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,165 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601564556] [2021-08-27 16:30:37,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,166 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:37,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:37,184 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:37,184 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601564556] [2021-08-27 16:30:37,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601564556] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:37,185 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:37,185 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:37,185 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769001956] [2021-08-27 16:30:37,185 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-27 16:30:37,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1714025377, now seen corresponding path program 2 times [2021-08-27 16:30:37,186 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,186 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1901809185] [2021-08-27 16:30:37,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,186 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,190 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:37,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,193 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:37,277 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:37,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:37,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:37,279 INFO L87 Difference]: Start difference. First operand 9965 states and 13606 transitions. cyclomatic complexity: 3647 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:37,352 INFO L93 Difference]: Finished difference Result 9893 states and 13505 transitions. [2021-08-27 16:30:37,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:37,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9893 states and 13505 transitions. [2021-08-27 16:30:37,388 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9776 [2021-08-27 16:30:37,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9893 states to 9893 states and 13505 transitions. [2021-08-27 16:30:37,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9893 [2021-08-27 16:30:37,418 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9893 [2021-08-27 16:30:37,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9893 states and 13505 transitions. [2021-08-27 16:30:37,428 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:37,428 INFO L681 BuchiCegarLoop]: Abstraction has 9893 states and 13505 transitions. [2021-08-27 16:30:37,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9893 states and 13505 transitions. [2021-08-27 16:30:37,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9893 to 9893. [2021-08-27 16:30:37,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9893 states, 9893 states have (on average 1.3651066410593349) internal successors, (13505), 9892 states have internal predecessors, (13505), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9893 states to 9893 states and 13505 transitions. [2021-08-27 16:30:37,544 INFO L704 BuchiCegarLoop]: Abstraction has 9893 states and 13505 transitions. [2021-08-27 16:30:37,544 INFO L587 BuchiCegarLoop]: Abstraction has 9893 states and 13505 transitions. [2021-08-27 16:30:37,544 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-08-27 16:30:37,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9893 states and 13505 transitions. [2021-08-27 16:30:37,570 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9776 [2021-08-27 16:30:37,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:37,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:37,571 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,571 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:37,572 INFO L791 eck$LassoCheckResult]: Stem: 91578#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 91530#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 91527#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 91036#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 91037#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91121#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91495#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91496#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91427#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91164#L431-1 assume !(0 == ~M_E~0); 91165#L591-1 assume !(0 == ~T1_E~0); 91296#L596-1 assume !(0 == ~T2_E~0); 91297#L601-1 assume !(0 == ~T3_E~0); 91351#L606-1 assume !(0 == ~T4_E~0); 91352#L611-1 assume !(0 == ~T5_E~0); 91444#L616-1 assume !(0 == ~E_M~0); 91445#L621-1 assume !(0 == ~E_1~0); 91023#L626-1 assume !(0 == ~E_2~0); 91024#L631-1 assume !(0 == ~E_3~0); 91196#L636-1 assume !(0 == ~E_4~0); 91047#L641-1 assume !(0 == ~E_5~0); 91048#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91030#L284 assume !(1 == ~m_pc~0); 91031#L284-2 is_master_triggered_~__retres1~0 := 0; 91167#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91018#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 91019#L735 assume !(0 != activate_threads_~tmp~1); 91127#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91128#L303 assume !(1 == ~t1_pc~0); 91340#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 91565#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 91013#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91014#L743 assume !(0 != activate_threads_~tmp___0~0); 91038#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91039#L322 assume !(1 == ~t2_pc~0); 91273#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 91267#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90985#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 90957#L751 assume !(0 != activate_threads_~tmp___1~0); 90958#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91055#L341 assume !(1 == ~t3_pc~0); 90991#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 90992#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91069#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 91070#L759 assume !(0 != activate_threads_~tmp___2~0); 91528#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91375#L360 assume !(1 == ~t4_pc~0); 91299#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 91300#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91520#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 91521#L767 assume !(0 != activate_threads_~tmp___3~0); 91517#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91457#L379 assume !(1 == ~t5_pc~0); 91096#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 91097#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91304#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 91430#L775 assume !(0 != activate_threads_~tmp___4~0); 90933#L775-2 assume !(1 == ~M_E~0); 90934#L659-1 assume !(1 == ~T1_E~0); 91224#L664-1 assume !(1 == ~T2_E~0); 90993#L669-1 assume !(1 == ~T3_E~0); 90994#L674-1 assume !(1 == ~T4_E~0); 91417#L679-1 assume !(1 == ~T5_E~0); 91092#L684-1 assume !(1 == ~E_M~0); 91093#L689-1 assume !(1 == ~E_1~0); 91295#L694-1 assume !(1 == ~E_2~0); 91293#L699-1 assume !(1 == ~E_3~0); 91294#L704-1 assume !(1 == ~E_4~0); 91258#L709-1 assume !(1 == ~E_5~0); 91259#L920-1 assume !false; 92265#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 92263#L566 [2021-08-27 16:30:37,572 INFO L793 eck$LassoCheckResult]: Loop: 92263#L566 assume !false; 92262#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 92258#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 92254#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 92249#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 92247#L491 assume 0 != eval_~tmp~0; 92245#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 92242#L499 assume !(0 != eval_~tmp_ndt_1~0); 92240#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 92196#L513 assume !(0 != eval_~tmp_ndt_2~0); 92236#L510 assume !(0 == ~t2_st~0); 92185#L524 assume !(0 == ~t3_st~0); 92474#L538 assume !(0 == ~t4_st~0); 92269#L552 assume !(0 == ~t5_st~0); 92263#L566 [2021-08-27 16:30:37,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,572 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-08-27 16:30:37,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,572 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317146801] [2021-08-27 16:30:37,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,573 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,579 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:37,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,592 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:37,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,593 INFO L82 PathProgramCache]: Analyzing trace with hash 706455497, now seen corresponding path program 1 times [2021-08-27 16:30:37,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,593 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530674737] [2021-08-27 16:30:37,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,593 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,596 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:37,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:37,598 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:37,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:37,598 INFO L82 PathProgramCache]: Analyzing trace with hash 1606943435, now seen corresponding path program 1 times [2021-08-27 16:30:37,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:37,599 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885214985] [2021-08-27 16:30:37,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:37,599 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:37,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:37,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:37,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:37,620 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885214985] [2021-08-27 16:30:37,620 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885214985] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:37,620 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:37,620 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:37,620 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779865754] [2021-08-27 16:30:37,709 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:37,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:37,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:37,710 INFO L87 Difference]: Start difference. First operand 9893 states and 13505 transitions. cyclomatic complexity: 3618 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:37,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:37,796 INFO L93 Difference]: Finished difference Result 18665 states and 25357 transitions. [2021-08-27 16:30:37,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:37,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18665 states and 25357 transitions. [2021-08-27 16:30:37,869 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18508 [2021-08-27 16:30:37,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18665 states to 18665 states and 25357 transitions. [2021-08-27 16:30:37,914 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18665 [2021-08-27 16:30:37,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18665 [2021-08-27 16:30:37,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18665 states and 25357 transitions. [2021-08-27 16:30:37,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:37,958 INFO L681 BuchiCegarLoop]: Abstraction has 18665 states and 25357 transitions. [2021-08-27 16:30:37,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18665 states and 25357 transitions. [2021-08-27 16:30:38,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18665 to 18289. [2021-08-27 16:30:38,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18289 states, 18289 states have (on average 1.3597791021925747) internal successors, (24869), 18288 states have internal predecessors, (24869), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:38,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18289 states to 18289 states and 24869 transitions. [2021-08-27 16:30:38,382 INFO L704 BuchiCegarLoop]: Abstraction has 18289 states and 24869 transitions. [2021-08-27 16:30:38,382 INFO L587 BuchiCegarLoop]: Abstraction has 18289 states and 24869 transitions. [2021-08-27 16:30:38,382 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-08-27 16:30:38,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18289 states and 24869 transitions. [2021-08-27 16:30:38,441 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18132 [2021-08-27 16:30:38,441 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:38,441 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:38,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:38,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:38,442 INFO L791 eck$LassoCheckResult]: Stem: 120163#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 120104#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 120101#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 119598#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 119599#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119680#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120074#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120075#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119996#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119720#L431-1 assume !(0 == ~M_E~0); 119721#L591-1 assume !(0 == ~T1_E~0); 119854#L596-1 assume !(0 == ~T2_E~0); 119855#L601-1 assume !(0 == ~T3_E~0); 119908#L606-1 assume !(0 == ~T4_E~0); 119909#L611-1 assume !(0 == ~T5_E~0); 120011#L616-1 assume !(0 == ~E_M~0); 120012#L621-1 assume !(0 == ~E_1~0); 119585#L626-1 assume !(0 == ~E_2~0); 119586#L631-1 assume !(0 == ~E_3~0); 119753#L636-1 assume !(0 == ~E_4~0); 119609#L641-1 assume !(0 == ~E_5~0); 119610#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 119593#L284 assume !(1 == ~m_pc~0); 119594#L284-2 is_master_triggered_~__retres1~0 := 0; 119723#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 119581#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 119582#L735 assume !(0 != activate_threads_~tmp~1); 119686#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 119687#L303 assume !(1 == ~t1_pc~0); 119895#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 120142#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119572#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 119573#L743 assume !(0 != activate_threads_~tmp___0~0); 119600#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 119601#L322 assume !(1 == ~t2_pc~0); 119828#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 119825#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 119548#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 119522#L751 assume !(0 != activate_threads_~tmp___1~0); 119523#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 119615#L341 assume !(1 == ~t3_pc~0); 119552#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 119553#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 119630#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 119631#L759 assume !(0 != activate_threads_~tmp___2~0); 120102#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 119931#L360 assume !(1 == ~t4_pc~0); 119859#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 119860#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120094#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 120095#L767 assume !(0 != activate_threads_~tmp___3~0); 120093#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120032#L379 assume !(1 == ~t5_pc~0); 119654#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 119655#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 119863#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 119999#L775 assume !(0 != activate_threads_~tmp___4~0); 119499#L775-2 assume !(1 == ~M_E~0); 119500#L659-1 assume !(1 == ~T1_E~0); 119781#L664-1 assume !(1 == ~T2_E~0); 119555#L669-1 assume !(1 == ~T3_E~0); 119556#L674-1 assume !(1 == ~T4_E~0); 119984#L679-1 assume !(1 == ~T5_E~0); 119652#L684-1 assume !(1 == ~E_M~0); 119653#L689-1 assume !(1 == ~E_1~0); 119853#L694-1 assume !(1 == ~E_2~0); 119851#L699-1 assume !(1 == ~E_3~0); 119852#L704-1 assume !(1 == ~E_4~0); 119812#L709-1 assume !(1 == ~E_5~0); 119813#L920-1 assume !false; 122340#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 122341#L566 [2021-08-27 16:30:38,442 INFO L793 eck$LassoCheckResult]: Loop: 122341#L566 assume !false; 123285#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 123282#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 123281#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 123280#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 122320#L491 assume 0 != eval_~tmp~0; 122316#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 122311#L499 assume !(0 != eval_~tmp_ndt_1~0); 122307#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 122280#L513 assume !(0 != eval_~tmp_ndt_2~0); 122304#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 121563#L527 assume !(0 != eval_~tmp_ndt_3~0); 123299#L524 assume !(0 == ~t3_st~0); 123295#L538 assume !(0 == ~t4_st~0); 123292#L552 assume !(0 == ~t5_st~0); 122341#L566 [2021-08-27 16:30:38,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:38,443 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-08-27 16:30:38,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:38,443 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2147253123] [2021-08-27 16:30:38,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:38,444 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:38,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,450 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:38,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,463 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:38,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:38,464 INFO L82 PathProgramCache]: Analyzing trace with hash 258069692, now seen corresponding path program 1 times [2021-08-27 16:30:38,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:38,464 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936469780] [2021-08-27 16:30:38,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:38,465 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:38,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,467 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:38,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:38,469 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:38,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:38,469 INFO L82 PathProgramCache]: Analyzing trace with hash -1891575302, now seen corresponding path program 1 times [2021-08-27 16:30:38,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:38,470 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613010111] [2021-08-27 16:30:38,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:38,470 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:38,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:38,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:38,488 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:38,488 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613010111] [2021-08-27 16:30:38,488 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613010111] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:38,488 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:38,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:38,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086162429] [2021-08-27 16:30:38,593 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:38,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:38,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:38,595 INFO L87 Difference]: Start difference. First operand 18289 states and 24869 transitions. cyclomatic complexity: 6586 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:38,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:38,737 INFO L93 Difference]: Finished difference Result 33433 states and 45309 transitions. [2021-08-27 16:30:38,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:38,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33433 states and 45309 transitions. [2021-08-27 16:30:38,882 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 33196 [2021-08-27 16:30:39,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33433 states to 33433 states and 45309 transitions. [2021-08-27 16:30:39,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33433 [2021-08-27 16:30:39,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33433 [2021-08-27 16:30:39,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33433 states and 45309 transitions. [2021-08-27 16:30:39,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:39,165 INFO L681 BuchiCegarLoop]: Abstraction has 33433 states and 45309 transitions. [2021-08-27 16:30:39,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33433 states and 45309 transitions. [2021-08-27 16:30:39,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33433 to 32377. [2021-08-27 16:30:39,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32377 states, 32377 states have (on average 1.3588967476912623) internal successors, (43997), 32376 states have internal predecessors, (43997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:39,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32377 states to 32377 states and 43997 transitions. [2021-08-27 16:30:39,608 INFO L704 BuchiCegarLoop]: Abstraction has 32377 states and 43997 transitions. [2021-08-27 16:30:39,608 INFO L587 BuchiCegarLoop]: Abstraction has 32377 states and 43997 transitions. [2021-08-27 16:30:39,609 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-08-27 16:30:39,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32377 states and 43997 transitions. [2021-08-27 16:30:39,716 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 32140 [2021-08-27 16:30:39,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:39,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:39,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:39,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:39,718 INFO L791 eck$LassoCheckResult]: Stem: 171888#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 171832#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 171829#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 171331#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 171332#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171416#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171798#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 171799#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171727#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171460#L431-1 assume !(0 == ~M_E~0); 171461#L591-1 assume !(0 == ~T1_E~0); 171592#L596-1 assume !(0 == ~T2_E~0); 171593#L601-1 assume !(0 == ~T3_E~0); 171649#L606-1 assume !(0 == ~T4_E~0); 171650#L611-1 assume !(0 == ~T5_E~0); 171738#L616-1 assume !(0 == ~E_M~0); 171739#L621-1 assume !(0 == ~E_1~0); 171316#L626-1 assume !(0 == ~E_2~0); 171317#L631-1 assume !(0 == ~E_3~0); 171493#L636-1 assume !(0 == ~E_4~0); 171342#L641-1 assume !(0 == ~E_5~0); 171343#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 171325#L284 assume !(1 == ~m_pc~0); 171326#L284-2 is_master_triggered_~__retres1~0 := 0; 171463#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 171312#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 171313#L735 assume !(0 != activate_threads_~tmp~1); 171422#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 171423#L303 assume !(1 == ~t1_pc~0); 171636#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 171867#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 171303#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 171304#L743 assume !(0 != activate_threads_~tmp___0~0); 171333#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 171334#L322 assume !(1 == ~t2_pc~0); 171570#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 171565#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 171279#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 171252#L751 assume !(0 != activate_threads_~tmp___1~0); 171253#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 171347#L341 assume !(1 == ~t3_pc~0); 171283#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 171284#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 171363#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 171364#L759 assume !(0 != activate_threads_~tmp___2~0); 171830#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 171674#L360 assume !(1 == ~t4_pc~0); 171597#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 171598#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 171821#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 171822#L767 assume !(0 != activate_threads_~tmp___3~0); 171819#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 171759#L379 assume !(1 == ~t5_pc~0); 171388#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 171389#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 171601#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 171729#L775 assume !(0 != activate_threads_~tmp___4~0); 171229#L775-2 assume !(1 == ~M_E~0); 171230#L659-1 assume !(1 == ~T1_E~0); 171520#L664-1 assume !(1 == ~T2_E~0); 171286#L669-1 assume !(1 == ~T3_E~0); 171287#L674-1 assume !(1 == ~T4_E~0); 171718#L679-1 assume !(1 == ~T5_E~0); 171386#L684-1 assume !(1 == ~E_M~0); 171387#L689-1 assume !(1 == ~E_1~0); 171591#L694-1 assume !(1 == ~E_2~0); 171589#L699-1 assume !(1 == ~E_3~0); 171590#L704-1 assume !(1 == ~E_4~0); 171552#L709-1 assume !(1 == ~E_5~0); 171553#L920-1 assume !false; 184566#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 184567#L566 [2021-08-27 16:30:39,718 INFO L793 eck$LassoCheckResult]: Loop: 184567#L566 assume !false; 185833#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 185831#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 184556#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184554#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 184553#L491 assume 0 != eval_~tmp~0; 184547#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 184548#L499 assume !(0 != eval_~tmp_ndt_1~0); 185662#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 185660#L513 assume !(0 != eval_~tmp_ndt_2~0); 180162#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 180159#L527 assume !(0 != eval_~tmp_ndt_3~0); 180160#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 185418#L541 assume !(0 != eval_~tmp_ndt_4~0); 184585#L538 assume !(0 == ~t4_st~0); 184583#L552 assume !(0 == ~t5_st~0); 184567#L566 [2021-08-27 16:30:39,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:39,719 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-08-27 16:30:39,719 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:39,719 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803585380] [2021-08-27 16:30:39,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:39,719 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:39,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,725 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:39,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,745 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:39,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:39,746 INFO L82 PathProgramCache]: Analyzing trace with hash -595166546, now seen corresponding path program 1 times [2021-08-27 16:30:39,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:39,746 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076629658] [2021-08-27 16:30:39,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:39,747 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:39,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,751 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:39,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:39,757 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:39,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:39,758 INFO L82 PathProgramCache]: Analyzing trace with hash 1485315376, now seen corresponding path program 1 times [2021-08-27 16:30:39,758 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:39,758 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969036881] [2021-08-27 16:30:39,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:39,758 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:39,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:39,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:39,781 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:39,781 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969036881] [2021-08-27 16:30:39,782 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [969036881] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:39,782 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:39,782 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-27 16:30:39,782 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236944258] [2021-08-27 16:30:39,912 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:39,913 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:39,913 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:39,913 INFO L87 Difference]: Start difference. First operand 32377 states and 43997 transitions. cyclomatic complexity: 11626 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:40,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:40,162 INFO L93 Difference]: Finished difference Result 41595 states and 56347 transitions. [2021-08-27 16:30:40,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:40,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41595 states and 56347 transitions. [2021-08-27 16:30:40,332 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 41342 [2021-08-27 16:30:40,419 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41595 states to 41595 states and 56347 transitions. [2021-08-27 16:30:40,419 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41595 [2021-08-27 16:30:40,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41595 [2021-08-27 16:30:40,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41595 states and 56347 transitions. [2021-08-27 16:30:40,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:40,459 INFO L681 BuchiCegarLoop]: Abstraction has 41595 states and 56347 transitions. [2021-08-27 16:30:40,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41595 states and 56347 transitions. [2021-08-27 16:30:40,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41595 to 40955. [2021-08-27 16:30:40,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40955 states, 40955 states have (on average 1.3555121474789402) internal successors, (55515), 40954 states have internal predecessors, (55515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:40,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40955 states to 40955 states and 55515 transitions. [2021-08-27 16:30:40,907 INFO L704 BuchiCegarLoop]: Abstraction has 40955 states and 55515 transitions. [2021-08-27 16:30:40,907 INFO L587 BuchiCegarLoop]: Abstraction has 40955 states and 55515 transitions. [2021-08-27 16:30:40,907 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-08-27 16:30:40,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40955 states and 55515 transitions. [2021-08-27 16:30:41,035 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40702 [2021-08-27 16:30:41,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:41,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:41,036 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:41,036 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:41,036 INFO L791 eck$LassoCheckResult]: Stem: 245860#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 245815#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 245812#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 245311#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 245312#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 245392#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 245780#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 245781#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 245711#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 245435#L431-1 assume !(0 == ~M_E~0); 245436#L591-1 assume !(0 == ~T1_E~0); 245572#L596-1 assume !(0 == ~T2_E~0); 245573#L601-1 assume !(0 == ~T3_E~0); 245633#L606-1 assume !(0 == ~T4_E~0); 245634#L611-1 assume !(0 == ~T5_E~0); 245720#L616-1 assume !(0 == ~E_M~0); 245721#L621-1 assume !(0 == ~E_1~0); 245295#L626-1 assume !(0 == ~E_2~0); 245296#L631-1 assume !(0 == ~E_3~0); 245468#L636-1 assume !(0 == ~E_4~0); 245322#L641-1 assume !(0 == ~E_5~0); 245323#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 245305#L284 assume !(1 == ~m_pc~0); 245306#L284-2 is_master_triggered_~__retres1~0 := 0; 245439#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 245291#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 245292#L735 assume !(0 != activate_threads_~tmp~1); 245398#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 245399#L303 assume !(1 == ~t1_pc~0); 245617#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 245847#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 245282#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 245283#L743 assume !(0 != activate_threads_~tmp___0~0); 245313#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 245314#L322 assume !(1 == ~t2_pc~0); 245546#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 245542#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 245258#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 245232#L751 assume !(0 != activate_threads_~tmp___1~0); 245233#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 245327#L341 assume !(1 == ~t3_pc~0); 245262#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 245263#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 245343#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 245344#L759 assume !(0 != activate_threads_~tmp___2~0); 245813#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 245655#L360 assume !(1 == ~t4_pc~0); 245575#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 245576#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 245803#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 245804#L767 assume !(0 != activate_threads_~tmp___3~0); 245802#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 245736#L379 assume !(1 == ~t5_pc~0); 245369#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 245370#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 245579#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 245712#L775 assume !(0 != activate_threads_~tmp___4~0); 245209#L775-2 assume !(1 == ~M_E~0); 245210#L659-1 assume !(1 == ~T1_E~0); 245499#L664-1 assume !(1 == ~T2_E~0); 245265#L669-1 assume !(1 == ~T3_E~0); 245266#L674-1 assume !(1 == ~T4_E~0); 245702#L679-1 assume !(1 == ~T5_E~0); 245367#L684-1 assume !(1 == ~E_M~0); 245368#L689-1 assume !(1 == ~E_1~0); 245571#L694-1 assume !(1 == ~E_2~0); 245569#L699-1 assume !(1 == ~E_3~0); 245570#L704-1 assume !(1 == ~E_4~0); 245530#L709-1 assume !(1 == ~E_5~0); 245531#L920-1 assume !false; 251514#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 251510#L566 [2021-08-27 16:30:41,036 INFO L793 eck$LassoCheckResult]: Loop: 251510#L566 assume !false; 251506#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 251501#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 251496#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 251493#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 251489#L491 assume 0 != eval_~tmp~0; 251483#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 251477#L499 assume !(0 != eval_~tmp_ndt_1~0); 249564#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 249560#L513 assume !(0 != eval_~tmp_ndt_2~0); 249558#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 249269#L527 assume !(0 != eval_~tmp_ndt_3~0); 249554#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 249538#L541 assume !(0 != eval_~tmp_ndt_4~0); 249552#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 251553#L555 assume !(0 != eval_~tmp_ndt_5~0); 251518#L552 assume !(0 == ~t5_st~0); 251510#L566 [2021-08-27 16:30:41,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:41,037 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-08-27 16:30:41,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:41,037 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380056056] [2021-08-27 16:30:41,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:41,037 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:41,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:41,045 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:41,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:41,058 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:41,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:41,059 INFO L82 PathProgramCache]: Analyzing trace with hash -1270466089, now seen corresponding path program 1 times [2021-08-27 16:30:41,059 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:41,059 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008070150] [2021-08-27 16:30:41,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:41,059 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:41,062 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:41,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:41,064 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:41,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:41,065 INFO L82 PathProgramCache]: Analyzing trace with hash -1200035947, now seen corresponding path program 1 times [2021-08-27 16:30:41,065 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:41,065 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328001638] [2021-08-27 16:30:41,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:41,065 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:41,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-27 16:30:41,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-27 16:30:41,217 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-27 16:30:41,217 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [328001638] [2021-08-27 16:30:41,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [328001638] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-27 16:30:41,217 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-27 16:30:41,217 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-27 16:30:41,217 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579668770] [2021-08-27 16:30:41,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-27 16:30:41,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-27 16:30:41,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-27 16:30:41,380 INFO L87 Difference]: Start difference. First operand 40955 states and 55515 transitions. cyclomatic complexity: 14566 Second operand has 3 states, 2 states have (on average 44.0) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:41,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-27 16:30:41,590 INFO L93 Difference]: Finished difference Result 71159 states and 96319 transitions. [2021-08-27 16:30:41,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-27 16:30:41,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71159 states and 96319 transitions. [2021-08-27 16:30:42,039 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 70730 [2021-08-27 16:30:42,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71159 states to 71159 states and 96319 transitions. [2021-08-27 16:30:42,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71159 [2021-08-27 16:30:42,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71159 [2021-08-27 16:30:42,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71159 states and 96319 transitions. [2021-08-27 16:30:42,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-27 16:30:42,362 INFO L681 BuchiCegarLoop]: Abstraction has 71159 states and 96319 transitions. [2021-08-27 16:30:42,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71159 states and 96319 transitions. [2021-08-27 16:30:43,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71159 to 70583. [2021-08-27 16:30:43,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70583 states, 70583 states have (on average 1.3564597707663317) internal successors, (95743), 70582 states have internal predecessors, (95743), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-27 16:30:43,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70583 states to 70583 states and 95743 transitions. [2021-08-27 16:30:43,187 INFO L704 BuchiCegarLoop]: Abstraction has 70583 states and 95743 transitions. [2021-08-27 16:30:43,187 INFO L587 BuchiCegarLoop]: Abstraction has 70583 states and 95743 transitions. [2021-08-27 16:30:43,187 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-08-27 16:30:43,187 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70583 states and 95743 transitions. [2021-08-27 16:30:43,398 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 70154 [2021-08-27 16:30:43,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-27 16:30:43,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-27 16:30:43,399 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:43,399 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-27 16:30:43,400 INFO L791 eck$LassoCheckResult]: Stem: 358011#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 357954#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 357951#L883 havoc start_simulation_#t~ret22, start_simulation_#t~ret23, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 357432#L399 assume 1 == ~m_i~0;~m_st~0 := 0; 357433#L406-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 357512#L411-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 357918#L416-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 357919#L421-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 357843#L426-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 357556#L431-1 assume !(0 == ~M_E~0); 357557#L591-1 assume !(0 == ~T1_E~0); 357694#L596-1 assume !(0 == ~T2_E~0); 357695#L601-1 assume !(0 == ~T3_E~0); 357758#L606-1 assume !(0 == ~T4_E~0); 357759#L611-1 assume !(0 == ~T5_E~0); 357853#L616-1 assume !(0 == ~E_M~0); 357854#L621-1 assume !(0 == ~E_1~0); 357417#L626-1 assume !(0 == ~E_2~0); 357418#L631-1 assume !(0 == ~E_3~0); 357587#L636-1 assume !(0 == ~E_4~0); 357443#L641-1 assume !(0 == ~E_5~0); 357444#L646-1 havoc activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 357427#L284 assume !(1 == ~m_pc~0); 357428#L284-2 is_master_triggered_~__retres1~0 := 0; 357560#L295 is_master_triggered_#res := is_master_triggered_~__retres1~0; 357413#L296 activate_threads_#t~ret15 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 357414#L735 assume !(0 != activate_threads_~tmp~1); 357518#L735-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 357519#L303 assume !(1 == ~t1_pc~0); 357743#L303-2 is_transmit1_triggered_~__retres1~1 := 0; 357996#L314 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 357404#L315 activate_threads_#t~ret16 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 357405#L743 assume !(0 != activate_threads_~tmp___0~0); 357434#L743-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 357435#L322 assume !(1 == ~t2_pc~0); 357666#L322-2 is_transmit2_triggered_~__retres1~2 := 0; 357661#L333 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 357380#L334 activate_threads_#t~ret17 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 357354#L751 assume !(0 != activate_threads_~tmp___1~0); 357355#L751-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 357448#L341 assume !(1 == ~t3_pc~0); 357384#L341-2 is_transmit3_triggered_~__retres1~3 := 0; 357385#L352 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 357463#L353 activate_threads_#t~ret18 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 357464#L759 assume !(0 != activate_threads_~tmp___2~0); 357952#L759-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 357781#L360 assume !(1 == ~t4_pc~0); 357697#L360-2 is_transmit4_triggered_~__retres1~4 := 0; 357698#L371 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 357942#L372 activate_threads_#t~ret19 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 357943#L767 assume !(0 != activate_threads_~tmp___3~0); 357940#L767-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 357873#L379 assume !(1 == ~t5_pc~0); 357488#L379-2 is_transmit5_triggered_~__retres1~5 := 0; 357489#L390 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 357701#L391 activate_threads_#t~ret20 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 357846#L775 assume !(0 != activate_threads_~tmp___4~0); 357331#L775-2 assume !(1 == ~M_E~0); 357332#L659-1 assume !(1 == ~T1_E~0); 357616#L664-1 assume !(1 == ~T2_E~0); 357387#L669-1 assume !(1 == ~T3_E~0); 357388#L674-1 assume !(1 == ~T4_E~0); 357833#L679-1 assume !(1 == ~T5_E~0); 357486#L684-1 assume !(1 == ~E_M~0); 357487#L689-1 assume !(1 == ~E_1~0); 357693#L694-1 assume !(1 == ~E_2~0); 357691#L699-1 assume !(1 == ~E_3~0); 357692#L704-1 assume !(1 == ~E_4~0); 357649#L709-1 assume !(1 == ~E_5~0); 357650#L920-1 assume !false; 379585#L921 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 379583#L566 [2021-08-27 16:30:43,400 INFO L793 eck$LassoCheckResult]: Loop: 379583#L566 assume !false; 379580#L487 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 379577#L444 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 379574#L476 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 379572#L477 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 379570#L491 assume 0 != eval_~tmp~0; 379567#L491-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 379568#L499 assume !(0 != eval_~tmp_ndt_1~0); 378156#L496 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 371846#L513 assume !(0 != eval_~tmp_ndt_2~0); 370222#L510 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 370079#L527 assume !(0 != eval_~tmp_ndt_3~0); 370080#L524 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 371322#L541 assume !(0 != eval_~tmp_ndt_4~0); 375206#L538 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 375204#L555 assume !(0 != eval_~tmp_ndt_5~0); 375205#L552 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 379586#L569 assume !(0 != eval_~tmp_ndt_6~0); 379583#L566 [2021-08-27 16:30:43,401 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:43,401 INFO L82 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-08-27 16:30:43,401 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:43,401 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058692322] [2021-08-27 16:30:43,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:43,401 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:43,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,407 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:43,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,419 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:43,420 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:43,420 INFO L82 PathProgramCache]: Analyzing trace with hash -729747053, now seen corresponding path program 1 times [2021-08-27 16:30:43,420 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:43,420 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1979617142] [2021-08-27 16:30:43,421 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:43,421 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:43,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,423 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:43,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,426 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:43,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-27 16:30:43,426 INFO L82 PathProgramCache]: Analyzing trace with hash 1453587349, now seen corresponding path program 1 times [2021-08-27 16:30:43,606 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-27 16:30:43,606 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981890168] [2021-08-27 16:30:43,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-27 16:30:43,606 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-27 16:30:43,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,612 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-27 16:30:43,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-27 16:30:43,628 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-27 16:30:45,811 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 27.08 04:30:45 BoogieIcfgContainer [2021-08-27 16:30:45,824 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-08-27 16:30:45,825 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-08-27 16:30:45,825 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-08-27 16:30:45,825 INFO L275 PluginConnector]: Witness Printer initialized [2021-08-27 16:30:45,826 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.08 04:30:33" (3/4) ... [2021-08-27 16:30:45,828 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-08-27 16:30:45,907 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2021-08-27 16:30:45,907 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-08-27 16:30:45,908 INFO L168 Benchmark]: Toolchain (without parser) took 13950.46 ms. Allocated memory was 54.5 MB in the beginning and 7.3 GB in the end (delta: 7.2 GB). Free memory was 32.5 MB in the beginning and 6.2 GB in the end (delta: -6.2 GB). Peak memory consumption was 1.0 GB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,908 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 54.5 MB. Free memory was 36.5 MB in the beginning and 36.5 MB in the end (delta: 29.1 kB). There was no memory consumed. Max. memory is 16.1 GB. [2021-08-27 16:30:45,909 INFO L168 Benchmark]: CACSL2BoogieTranslator took 259.09 ms. Allocated memory is still 54.5 MB. Free memory was 32.4 MB in the beginning and 32.3 MB in the end (delta: 131.5 kB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,909 INFO L168 Benchmark]: Boogie Procedure Inliner took 45.03 ms. Allocated memory is still 54.5 MB. Free memory was 32.3 MB in the beginning and 27.2 MB in the end (delta: 5.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,909 INFO L168 Benchmark]: Boogie Preprocessor took 79.86 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 27.2 MB in the beginning and 46.8 MB in the end (delta: -19.6 MB). Peak memory consumption was 7.2 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,909 INFO L168 Benchmark]: RCFGBuilder took 1070.13 ms. Allocated memory was 67.1 MB in the beginning and 81.8 MB in the end (delta: 14.7 MB). Free memory was 46.8 MB in the beginning and 38.9 MB in the end (delta: 8.0 MB). Peak memory consumption was 26.7 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,909 INFO L168 Benchmark]: BuchiAutomizer took 12410.16 ms. Allocated memory was 81.8 MB in the beginning and 7.3 GB in the end (delta: 7.2 GB). Free memory was 38.4 MB in the beginning and 6.2 GB in the end (delta: -6.2 GB). Peak memory consumption was 1.0 GB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,910 INFO L168 Benchmark]: Witness Printer took 81.96 ms. Allocated memory is still 7.3 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-08-27 16:30:45,911 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 54.5 MB. Free memory was 36.5 MB in the beginning and 36.5 MB in the end (delta: 29.1 kB). There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 259.09 ms. Allocated memory is still 54.5 MB. Free memory was 32.4 MB in the beginning and 32.3 MB in the end (delta: 131.5 kB). Peak memory consumption was 12.6 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 45.03 ms. Allocated memory is still 54.5 MB. Free memory was 32.3 MB in the beginning and 27.2 MB in the end (delta: 5.1 MB). Peak memory consumption was 6.3 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 79.86 ms. Allocated memory was 54.5 MB in the beginning and 67.1 MB in the end (delta: 12.6 MB). Free memory was 27.2 MB in the beginning and 46.8 MB in the end (delta: -19.6 MB). Peak memory consumption was 7.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1070.13 ms. Allocated memory was 67.1 MB in the beginning and 81.8 MB in the end (delta: 14.7 MB). Free memory was 46.8 MB in the beginning and 38.9 MB in the end (delta: 8.0 MB). Peak memory consumption was 26.7 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 12410.16 ms. Allocated memory was 81.8 MB in the beginning and 7.3 GB in the end (delta: 7.2 GB). Free memory was 38.4 MB in the beginning and 6.2 GB in the end (delta: -6.2 GB). Peak memory consumption was 1.0 GB. Max. memory is 16.1 GB. * Witness Printer took 81.96 ms. Allocated memory is still 7.3 GB. Free memory was 6.2 GB in the beginning and 6.2 GB in the end (delta: 3.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 70583 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.3s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 4.6s. Construction of modules took 0.4s. Büchi inclusion checks took 1.2s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 2885.0ms AutomataMinimizationTime, 21 MinimizatonAttempts, 10915 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 1.9s Buchi closure took 0.1s. Biggest automaton had 70583 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17132 SDtfs, 19803 SDslu, 15316 SDs, 0 SdLazy, 537 SolverSat, 285 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 492.7ms Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 486]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=29164} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=29164, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5f9de001=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c9c2fe4=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4eae3c2c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5695d50c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@583421a3=0, NULL=0, tmp___0=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@176a991b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a24671d=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@476c0326=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d92e91d=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@9671032=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f0b73d9=0, NULL=29165, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3eb56e5=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@37fdfff6=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@235005f0=0, T1_E=2, NULL=29167, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=29166, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6185c29c=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 486]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L16] int m_pc = 0; [L17] int t1_pc = 0; [L18] int t2_pc = 0; [L19] int t3_pc = 0; [L20] int t4_pc = 0; [L21] int t5_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int t2_i ; [L31] int t3_i ; [L32] int t4_i ; [L33] int t5_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int T3_E = 2; [L38] int T4_E = 2; [L39] int T5_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L44] int E_4 = 2; [L45] int E_5 = 2; [L53] int token ; [L55] int local ; [L965] int __retres1 ; [L876] m_i = 1 [L877] t1_i = 1 [L878] t2_i = 1 [L879] t3_i = 1 [L880] t4_i = 1 [L881] t5_i = 1 [L906] int kernel_st ; [L907] int tmp ; [L908] int tmp___0 ; [L912] kernel_st = 0 [L406] COND TRUE m_i == 1 [L407] m_st = 0 [L411] COND TRUE t1_i == 1 [L412] t1_st = 0 [L416] COND TRUE t2_i == 1 [L417] t2_st = 0 [L421] COND TRUE t3_i == 1 [L422] t3_st = 0 [L426] COND TRUE t4_i == 1 [L427] t4_st = 0 [L431] COND TRUE t5_i == 1 [L432] t5_st = 0 [L591] COND FALSE !(M_E == 0) [L596] COND FALSE !(T1_E == 0) [L601] COND FALSE !(T2_E == 0) [L606] COND FALSE !(T3_E == 0) [L611] COND FALSE !(T4_E == 0) [L616] COND FALSE !(T5_E == 0) [L621] COND FALSE !(E_M == 0) [L626] COND FALSE !(E_1 == 0) [L631] COND FALSE !(E_2 == 0) [L636] COND FALSE !(E_3 == 0) [L641] COND FALSE !(E_4 == 0) [L646] COND FALSE !(E_5 == 0) [L724] int tmp ; [L725] int tmp___0 ; [L726] int tmp___1 ; [L727] int tmp___2 ; [L728] int tmp___3 ; [L729] int tmp___4 ; [L281] int __retres1 ; [L284] COND FALSE !(m_pc == 1) [L294] __retres1 = 0 [L296] return (__retres1); [L733] tmp = is_master_triggered() [L735] COND FALSE !(\read(tmp)) [L300] int __retres1 ; [L303] COND FALSE !(t1_pc == 1) [L313] __retres1 = 0 [L315] return (__retres1); [L741] tmp___0 = is_transmit1_triggered() [L743] COND FALSE !(\read(tmp___0)) [L319] int __retres1 ; [L322] COND FALSE !(t2_pc == 1) [L332] __retres1 = 0 [L334] return (__retres1); [L749] tmp___1 = is_transmit2_triggered() [L751] COND FALSE !(\read(tmp___1)) [L338] int __retres1 ; [L341] COND FALSE !(t3_pc == 1) [L351] __retres1 = 0 [L353] return (__retres1); [L757] tmp___2 = is_transmit3_triggered() [L759] COND FALSE !(\read(tmp___2)) [L357] int __retres1 ; [L360] COND FALSE !(t4_pc == 1) [L370] __retres1 = 0 [L372] return (__retres1); [L765] tmp___3 = is_transmit4_triggered() [L767] COND FALSE !(\read(tmp___3)) [L376] int __retres1 ; [L379] COND FALSE !(t5_pc == 1) [L389] __retres1 = 0 [L391] return (__retres1); [L773] tmp___4 = is_transmit5_triggered() [L775] COND FALSE !(\read(tmp___4)) [L659] COND FALSE !(M_E == 1) [L664] COND FALSE !(T1_E == 1) [L669] COND FALSE !(T2_E == 1) [L674] COND FALSE !(T3_E == 1) [L679] COND FALSE !(T4_E == 1) [L684] COND FALSE !(T5_E == 1) [L689] COND FALSE !(E_M == 1) [L694] COND FALSE !(E_1 == 1) [L699] COND FALSE !(E_2 == 1) [L704] COND FALSE !(E_3 == 1) [L709] COND FALSE !(E_4 == 1) [L714] COND FALSE !(E_5 == 1) [L920] COND TRUE 1 [L923] kernel_st = 1 [L482] int tmp ; Loop: [L486] COND TRUE 1 [L441] int __retres1 ; [L444] COND TRUE m_st == 0 [L445] __retres1 = 1 [L477] return (__retres1); [L489] tmp = exists_runnable_thread() [L491] COND TRUE \read(tmp) [L496] COND TRUE m_st == 0 [L497] int tmp_ndt_1; [L498] tmp_ndt_1 = __VERIFIER_nondet_int() [L499] COND FALSE !(\read(tmp_ndt_1)) [L510] COND TRUE t1_st == 0 [L511] int tmp_ndt_2; [L512] tmp_ndt_2 = __VERIFIER_nondet_int() [L513] COND FALSE !(\read(tmp_ndt_2)) [L524] COND TRUE t2_st == 0 [L525] int tmp_ndt_3; [L526] tmp_ndt_3 = __VERIFIER_nondet_int() [L527] COND FALSE !(\read(tmp_ndt_3)) [L538] COND TRUE t3_st == 0 [L539] int tmp_ndt_4; [L540] tmp_ndt_4 = __VERIFIER_nondet_int() [L541] COND FALSE !(\read(tmp_ndt_4)) [L552] COND TRUE t4_st == 0 [L553] int tmp_ndt_5; [L554] tmp_ndt_5 = __VERIFIER_nondet_int() [L555] COND FALSE !(\read(tmp_ndt_5)) [L566] COND TRUE t5_st == 0 [L567] int tmp_ndt_6; [L568] tmp_ndt_6 = __VERIFIER_nondet_int() [L569] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-08-27 16:30:45,971 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...