./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5fbdf5bf Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ba5ca2b9b2a5f86416453e0608f62cc01593f29e ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) --- Real Ultimate output --- This is Ultimate 0.2.1-wip.dd.seqcomp-5fbdf5b [2021-08-31 04:18:24,517 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-08-31 04:18:24,518 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-08-31 04:18:24,540 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-08-31 04:18:24,540 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-08-31 04:18:24,544 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-08-31 04:18:24,546 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-08-31 04:18:24,550 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-08-31 04:18:24,552 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-08-31 04:18:24,555 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-08-31 04:18:24,556 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-08-31 04:18:24,559 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-08-31 04:18:24,559 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-08-31 04:18:24,561 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-08-31 04:18:24,562 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-08-31 04:18:24,564 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-08-31 04:18:24,564 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-08-31 04:18:24,565 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-08-31 04:18:24,568 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-08-31 04:18:24,571 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-08-31 04:18:24,571 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-08-31 04:18:24,573 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-08-31 04:18:24,574 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-08-31 04:18:24,575 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-08-31 04:18:24,582 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-08-31 04:18:24,583 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-08-31 04:18:24,583 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-08-31 04:18:24,583 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-08-31 04:18:24,584 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-08-31 04:18:24,584 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-08-31 04:18:24,584 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-08-31 04:18:24,585 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-08-31 04:18:24,585 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-08-31 04:18:24,585 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-08-31 04:18:24,586 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-08-31 04:18:24,586 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-08-31 04:18:24,586 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-08-31 04:18:24,587 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-08-31 04:18:24,587 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-08-31 04:18:24,587 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-08-31 04:18:24,588 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-08-31 04:18:24,591 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-08-31 04:18:24,616 INFO L113 SettingsManager]: Loading preferences was successful [2021-08-31 04:18:24,617 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-08-31 04:18:24,617 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-08-31 04:18:24,617 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-08-31 04:18:24,618 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Use SBE=true [2021-08-31 04:18:24,618 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Use old map elimination=false [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-08-31 04:18:24,618 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-08-31 04:18:24,618 INFO L138 SettingsManager]: * sizeof long=4 [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * sizeof long double=12 [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Use constant arrays=true [2021-08-31 04:18:24,619 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-08-31 04:18:24,620 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-08-31 04:18:24,620 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-08-31 04:18:24,620 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-08-31 04:18:24,620 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-08-31 04:18:24,620 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-08-31 04:18:24,620 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-08-31 04:18:24,621 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ba5ca2b9b2a5f86416453e0608f62cc01593f29e [2021-08-31 04:18:24,846 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-08-31 04:18:24,859 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-08-31 04:18:24,861 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-08-31 04:18:24,862 INFO L271 PluginConnector]: Initializing CDTParser... [2021-08-31 04:18:24,862 INFO L275 PluginConnector]: CDTParser initialized [2021-08-31 04:18:24,863 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-08-31 04:18:24,908 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e295ebf1/4c41103669b84fc4b3d4f6bbb9aed9c5/FLAG38bfc9252 [2021-08-31 04:18:25,269 INFO L306 CDTParser]: Found 1 translation units. [2021-08-31 04:18:25,269 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c [2021-08-31 04:18:25,278 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e295ebf1/4c41103669b84fc4b3d4f6bbb9aed9c5/FLAG38bfc9252 [2021-08-31 04:18:25,293 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0e295ebf1/4c41103669b84fc4b3d4f6bbb9aed9c5 [2021-08-31 04:18:25,295 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-08-31 04:18:25,296 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-08-31 04:18:25,298 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-08-31 04:18:25,299 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-08-31 04:18:25,301 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-08-31 04:18:25,301 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,302 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74cbe15e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25, skipping insertion in model container [2021-08-31 04:18:25,302 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,307 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-08-31 04:18:25,342 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-08-31 04:18:25,448 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[366,379] [2021-08-31 04:18:25,523 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-31 04:18:25,533 INFO L203 MainTranslator]: Completed pre-run [2021-08-31 04:18:25,543 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-1.c[366,379] [2021-08-31 04:18:25,575 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-31 04:18:25,593 INFO L208 MainTranslator]: Completed translation [2021-08-31 04:18:25,593 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25 WrapperNode [2021-08-31 04:18:25,593 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-08-31 04:18:25,595 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-08-31 04:18:25,595 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-08-31 04:18:25,595 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-08-31 04:18:25,599 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,617 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,641 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-08-31 04:18:25,642 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-08-31 04:18:25,642 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-08-31 04:18:25,642 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-08-31 04:18:25,653 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,653 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,655 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,655 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,662 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,669 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,670 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,672 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-08-31 04:18:25,673 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-08-31 04:18:25,673 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-08-31 04:18:25,673 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-08-31 04:18:25,674 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (1/1) ... [2021-08-31 04:18:25,678 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-08-31 04:18:25,685 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-08-31 04:18:25,693 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-08-31 04:18:25,706 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-08-31 04:18:25,729 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-08-31 04:18:25,729 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-08-31 04:18:25,729 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-08-31 04:18:25,729 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-08-31 04:18:25,969 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-08-31 04:18:25,970 INFO L299 CfgBuilder]: Removed 132 assume(true) statements. [2021-08-31 04:18:25,971 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.08 04:18:25 BoogieIcfgContainer [2021-08-31 04:18:25,972 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-08-31 04:18:25,972 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-08-31 04:18:25,972 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-08-31 04:18:25,980 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-08-31 04:18:25,980 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:25,981 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.08 04:18:25" (1/3) ... [2021-08-31 04:18:25,981 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@63ddf6f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.08 04:18:25, skipping insertion in model container [2021-08-31 04:18:25,981 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:25,982 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:25" (2/3) ... [2021-08-31 04:18:25,982 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@63ddf6f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.08 04:18:25, skipping insertion in model container [2021-08-31 04:18:25,982 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:25,982 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.08 04:18:25" (3/3) ... [2021-08-31 04:18:25,983 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-1.c [2021-08-31 04:18:26,009 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-08-31 04:18:26,010 INFO L360 BuchiCegarLoop]: Hoare is false [2021-08-31 04:18:26,010 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-08-31 04:18:26,010 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-08-31 04:18:26,010 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-08-31 04:18:26,010 INFO L364 BuchiCegarLoop]: Difference is false [2021-08-31 04:18:26,010 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-08-31 04:18:26,011 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-08-31 04:18:26,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 314 states, 313 states have (on average 1.5686900958466454) internal successors, (491), 313 states have internal predecessors, (491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 259 [2021-08-31 04:18:26,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:26,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:26,082 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,082 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,082 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-08-31 04:18:26,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 314 states, 313 states have (on average 1.5686900958466454) internal successors, (491), 313 states have internal predecessors, (491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 259 [2021-08-31 04:18:26,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:26,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:26,104 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,104 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,111 INFO L791 eck$LassoCheckResult]: Stem: 292#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 195#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 150#L645true havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 192#L289true assume !(1 == ~m_i~0);~m_st~0 := 2; 227#L296-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 103#L301-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 124#L306-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 219#L311-1true assume !(0 == ~M_E~0); 220#L433-1true assume !(0 == ~T1_E~0); 197#L438-1true assume !(0 == ~T2_E~0); 115#L443-1true assume !(0 == ~T3_E~0); 109#L448-1true assume !(0 == ~E_M~0); 193#L453-1true assume 0 == ~E_1~0;~E_1~0 := 1; 143#L458-1true assume !(0 == ~E_2~0); 308#L463-1true assume !(0 == ~E_3~0); 311#L468-1true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 231#L212true assume 1 == ~m_pc~0; 136#L213true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 81#L223true is_master_triggered_#res := is_master_triggered_~__retres1~0; 246#L224true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 254#L535true assume !(0 != activate_threads_~tmp~1); 131#L535-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90#L231true assume !(1 == ~t1_pc~0); 6#L231-2true is_transmit1_triggered_~__retres1~1 := 0; 312#L242true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 243#L243true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 62#L543true assume !(0 != activate_threads_~tmp___0~0); 306#L543-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 257#L250true assume 1 == ~t2_pc~0; 250#L251true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 151#L261true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217#L262true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 187#L551true assume !(0 != activate_threads_~tmp___1~0); 309#L551-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 77#L269true assume 1 == ~t3_pc~0; 10#L270true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 262#L280true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 169#L281true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 198#L559true assume !(0 != activate_threads_~tmp___2~0); 105#L559-2true assume 1 == ~M_E~0;~M_E~0 := 2; 285#L481-1true assume !(1 == ~T1_E~0); 132#L486-1true assume !(1 == ~T2_E~0); 58#L491-1true assume !(1 == ~T3_E~0); 209#L496-1true assume !(1 == ~E_M~0); 274#L501-1true assume !(1 == ~E_1~0); 228#L506-1true assume !(1 == ~E_2~0); 82#L511-1true assume !(1 == ~E_3~0); 36#L682-1true [2021-08-31 04:18:26,112 INFO L793 eck$LassoCheckResult]: Loop: 36#L682-1true assume !false; 245#L683true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 282#L408true assume !true; 21#L423true start_simulation_~kernel_st~0 := 2; 4#L289-1true start_simulation_~kernel_st~0 := 3; 205#L433-2true assume 0 == ~M_E~0;~M_E~0 := 1; 206#L433-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 178#L438-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 185#L443-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 7#L448-3true assume !(0 == ~E_M~0); 215#L453-3true assume 0 == ~E_1~0;~E_1~0 := 1; 66#L458-3true assume 0 == ~E_2~0;~E_2~0 := 1; 119#L463-3true assume 0 == ~E_3~0;~E_3~0 := 1; 166#L468-3true havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 72#L212-15true assume 1 == ~m_pc~0; 239#L213-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 51#L223-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 8#L224-5true activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35#L535-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 79#L535-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45#L231-15true assume 1 == ~t1_pc~0; 25#L232-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 56#L242-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44#L243-5true activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 196#L543-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 106#L543-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 247#L250-15true assume 1 == ~t2_pc~0; 314#L251-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 244#L261-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 283#L262-5true activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22#L551-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 298#L551-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 188#L269-15true assume 1 == ~t3_pc~0; 99#L270-5true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 160#L280-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 272#L281-5true activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 316#L559-15true assume !(0 != activate_threads_~tmp___2~0); 204#L559-17true assume 1 == ~M_E~0;~M_E~0 := 2; 117#L481-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L486-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 273#L491-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 155#L496-3true assume 1 == ~E_M~0;~E_M~0 := 2; 305#L501-3true assume 1 == ~E_1~0;~E_1~0 := 2; 268#L506-3true assume 1 == ~E_2~0;~E_2~0 := 2; 179#L511-3true assume !(1 == ~E_3~0); 95#L516-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 260#L324-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 32#L346-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 295#L347-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 297#L701true assume !(0 == start_simulation_~tmp~3); 175#L701-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 156#L324-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 165#L346-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 80#L347-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 102#L656true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17#L663true stop_simulation_#res := stop_simulation_~__retres2~0; 54#L664true start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 162#L714true assume !(0 != start_simulation_~tmp___0~1); 36#L682-1true [2021-08-31 04:18:26,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:26,125 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2021-08-31 04:18:26,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:26,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449239581] [2021-08-31 04:18:26,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:26,132 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:26,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:26,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:26,302 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:26,303 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449239581] [2021-08-31 04:18:26,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449239581] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:26,304 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:26,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:26,305 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158998293] [2021-08-31 04:18:26,309 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:26,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:26,312 INFO L82 PathProgramCache]: Analyzing trace with hash 2067746065, now seen corresponding path program 1 times [2021-08-31 04:18:26,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:26,312 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776943634] [2021-08-31 04:18:26,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:26,312 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:26,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:26,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:26,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:26,348 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776943634] [2021-08-31 04:18:26,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776943634] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:26,348 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:26,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:26,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268477120] [2021-08-31 04:18:26,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:26,350 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:26,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:26,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:26,382 INFO L87 Difference]: Start difference. First operand has 314 states, 313 states have (on average 1.5686900958466454) internal successors, (491), 313 states have internal predecessors, (491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:26,840 INFO L93 Difference]: Finished difference Result 314 states and 476 transitions. [2021-08-31 04:18:26,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:26,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 314 states and 476 transitions. [2021-08-31 04:18:26,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:26,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 314 states to 308 states and 470 transitions. [2021-08-31 04:18:26,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2021-08-31 04:18:26,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2021-08-31 04:18:26,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 470 transitions. [2021-08-31 04:18:26,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:26,873 INFO L681 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2021-08-31 04:18:26,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 470 transitions. [2021-08-31 04:18:26,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2021-08-31 04:18:26,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.525974025974026) internal successors, (470), 307 states have internal predecessors, (470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 470 transitions. [2021-08-31 04:18:26,903 INFO L704 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2021-08-31 04:18:26,903 INFO L587 BuchiCegarLoop]: Abstraction has 308 states and 470 transitions. [2021-08-31 04:18:26,903 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-08-31 04:18:26,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 470 transitions. [2021-08-31 04:18:26,904 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:26,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:26,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:26,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,906 INFO L791 eck$LassoCheckResult]: Stem: 941#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 903#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 869#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 870#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 901#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 806#L301-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 807#L306-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 842#L311-1 assume !(0 == ~M_E~0); 915#L433-1 assume !(0 == ~T1_E~0); 904#L438-1 assume !(0 == ~T2_E~0); 828#L443-1 assume !(0 == ~T3_E~0); 817#L448-1 assume !(0 == ~E_M~0); 818#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 862#L458-1 assume !(0 == ~E_2~0); 863#L463-1 assume !(0 == ~E_3~0); 944#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 919#L212 assume 1 == ~m_pc~0; 856#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 775#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 776#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 927#L535 assume !(0 != activate_threads_~tmp~1); 852#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 790#L231 assume !(1 == ~t1_pc~0); 643#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 644#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 924#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 748#L543 assume !(0 != activate_threads_~tmp___0~0); 749#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 933#L250 assume 1 == ~t2_pc~0; 928#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 831#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 871#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 895#L551 assume !(0 != activate_threads_~tmp___1~0); 896#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 771#L269 assume 1 == ~t3_pc~0; 651#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 652#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 883#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 884#L559 assume !(0 != activate_threads_~tmp___2~0); 814#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 815#L481-1 assume !(1 == ~T1_E~0); 853#L486-1 assume !(1 == ~T2_E~0); 744#L491-1 assume !(1 == ~T3_E~0); 745#L496-1 assume !(1 == ~E_M~0); 912#L501-1 assume !(1 == ~E_1~0); 916#L506-1 assume !(1 == ~E_2~0); 777#L511-1 assume !(1 == ~E_3~0); 706#L682-1 [2021-08-31 04:18:26,906 INFO L793 eck$LassoCheckResult]: Loop: 706#L682-1 assume !false; 707#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 670#L408 assume !false; 757#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 666#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 667#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 746#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 920#L361 assume !(0 != eval_~tmp~0); 675#L423 start_simulation_~kernel_st~0 := 2; 639#L289-1 start_simulation_~kernel_st~0 := 3; 640#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 911#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 890#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 891#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 645#L448-3 assume !(0 == ~E_M~0); 646#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 753#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 754#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 834#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 761#L212-15 assume !(1 == ~m_pc~0); 762#L212-17 is_master_triggered_~__retres1~0 := 0; 733#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 647#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 648#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 705#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 725#L231-15 assume 1 == ~t1_pc~0; 682#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 683#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 723#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 724#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 812#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 813#L250-15 assume 1 == ~t2_pc~0; 925#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 922#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 923#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 673#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 674#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 897#L269-15 assume 1 == ~t3_pc~0; 803#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 804#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 877#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 939#L559-15 assume !(0 != activate_threads_~tmp___2~0); 910#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 829#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 778#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 779#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 872#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 873#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 938#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 892#L511-3 assume !(1 == ~E_3~0); 796#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 797#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 700#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 701#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 943#L701 assume !(0 == start_simulation_~tmp~3); 732#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 874#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 781#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 773#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 774#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 664#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 665#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 739#L714 assume !(0 != start_simulation_~tmp___0~1); 706#L682-1 [2021-08-31 04:18:26,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:26,907 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2021-08-31 04:18:26,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:26,907 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1080744994] [2021-08-31 04:18:26,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:26,907 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:26,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:26,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:26,931 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:26,932 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1080744994] [2021-08-31 04:18:26,932 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1080744994] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:26,932 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:26,932 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:26,932 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436989337] [2021-08-31 04:18:26,932 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:26,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:26,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1004789665, now seen corresponding path program 1 times [2021-08-31 04:18:26,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:26,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563540891] [2021-08-31 04:18:26,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:26,933 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:26,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:26,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:26,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:26,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563540891] [2021-08-31 04:18:26,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563540891] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:26,972 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:26,972 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:26,972 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475876274] [2021-08-31 04:18:26,972 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:26,972 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:26,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:26,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:26,973 INFO L87 Difference]: Start difference. First operand 308 states and 470 transitions. cyclomatic complexity: 163 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:27,350 INFO L93 Difference]: Finished difference Result 308 states and 469 transitions. [2021-08-31 04:18:27,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:27,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 469 transitions. [2021-08-31 04:18:27,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:27,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 469 transitions. [2021-08-31 04:18:27,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2021-08-31 04:18:27,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2021-08-31 04:18:27,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 469 transitions. [2021-08-31 04:18:27,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:27,356 INFO L681 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2021-08-31 04:18:27,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 469 transitions. [2021-08-31 04:18:27,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2021-08-31 04:18:27,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.5227272727272727) internal successors, (469), 307 states have internal predecessors, (469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 469 transitions. [2021-08-31 04:18:27,367 INFO L704 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2021-08-31 04:18:27,367 INFO L587 BuchiCegarLoop]: Abstraction has 308 states and 469 transitions. [2021-08-31 04:18:27,367 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-08-31 04:18:27,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 469 transitions. [2021-08-31 04:18:27,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:27,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:27,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:27,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,370 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,370 INFO L791 eck$LassoCheckResult]: Stem: 1564#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1526#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1492#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1493#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 1524#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1429#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1430#L306-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1465#L311-1 assume !(0 == ~M_E~0); 1538#L433-1 assume !(0 == ~T1_E~0); 1527#L438-1 assume !(0 == ~T2_E~0); 1451#L443-1 assume !(0 == ~T3_E~0); 1440#L448-1 assume !(0 == ~E_M~0); 1441#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1485#L458-1 assume !(0 == ~E_2~0); 1486#L463-1 assume !(0 == ~E_3~0); 1567#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1542#L212 assume 1 == ~m_pc~0; 1479#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1398#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1399#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1550#L535 assume !(0 != activate_threads_~tmp~1); 1475#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1413#L231 assume !(1 == ~t1_pc~0); 1266#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 1267#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1547#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1371#L543 assume !(0 != activate_threads_~tmp___0~0); 1372#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1556#L250 assume 1 == ~t2_pc~0; 1551#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1454#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1494#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1518#L551 assume !(0 != activate_threads_~tmp___1~0); 1519#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1394#L269 assume 1 == ~t3_pc~0; 1274#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1275#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1507#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1508#L559 assume !(0 != activate_threads_~tmp___2~0); 1437#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1438#L481-1 assume !(1 == ~T1_E~0); 1477#L486-1 assume !(1 == ~T2_E~0); 1367#L491-1 assume !(1 == ~T3_E~0); 1368#L496-1 assume !(1 == ~E_M~0); 1535#L501-1 assume !(1 == ~E_1~0); 1539#L506-1 assume !(1 == ~E_2~0); 1400#L511-1 assume !(1 == ~E_3~0); 1331#L682-1 [2021-08-31 04:18:27,370 INFO L793 eck$LassoCheckResult]: Loop: 1331#L682-1 assume !false; 1332#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1293#L408 assume !false; 1383#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1289#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1290#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1369#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1543#L361 assume !(0 != eval_~tmp~0); 1298#L423 start_simulation_~kernel_st~0 := 2; 1262#L289-1 start_simulation_~kernel_st~0 := 3; 1263#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1534#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1513#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1514#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1268#L448-3 assume !(0 == ~E_M~0); 1269#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1376#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1377#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1457#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1384#L212-15 assume !(1 == ~m_pc~0); 1385#L212-17 is_master_triggered_~__retres1~0 := 0; 1356#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1270#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1271#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1328#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1348#L231-15 assume 1 == ~t1_pc~0; 1305#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1306#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1346#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1347#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1435#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1436#L250-15 assume 1 == ~t2_pc~0; 1548#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1545#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1546#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1296#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1297#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1520#L269-15 assume 1 == ~t3_pc~0; 1426#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1427#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1500#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1562#L559-15 assume !(0 != activate_threads_~tmp___2~0); 1533#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1452#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1401#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1402#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1495#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1496#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1561#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1515#L511-3 assume !(1 == ~E_3~0); 1419#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1420#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1323#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1324#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1566#L701 assume !(0 == start_simulation_~tmp~3); 1355#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1497#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1404#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1396#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1397#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1287#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 1288#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1362#L714 assume !(0 != start_simulation_~tmp___0~1); 1331#L682-1 [2021-08-31 04:18:27,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,371 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2021-08-31 04:18:27,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,371 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231535512] [2021-08-31 04:18:27,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,371 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,407 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,407 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,407 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [231535512] [2021-08-31 04:18:27,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [231535512] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,408 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,408 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,408 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2041614183] [2021-08-31 04:18:27,408 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:27,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1004789665, now seen corresponding path program 2 times [2021-08-31 04:18:27,409 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,409 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851773356] [2021-08-31 04:18:27,409 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,410 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,445 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,445 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851773356] [2021-08-31 04:18:27,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851773356] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,445 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,445 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,445 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6971773] [2021-08-31 04:18:27,445 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:27,446 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:27,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:27,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:27,446 INFO L87 Difference]: Start difference. First operand 308 states and 469 transitions. cyclomatic complexity: 162 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:27,745 INFO L93 Difference]: Finished difference Result 308 states and 468 transitions. [2021-08-31 04:18:27,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:27,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 468 transitions. [2021-08-31 04:18:27,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:27,749 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 308 states and 468 transitions. [2021-08-31 04:18:27,749 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 308 [2021-08-31 04:18:27,749 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 308 [2021-08-31 04:18:27,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 308 states and 468 transitions. [2021-08-31 04:18:27,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:27,750 INFO L681 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2021-08-31 04:18:27,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states and 468 transitions. [2021-08-31 04:18:27,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 308. [2021-08-31 04:18:27,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.5194805194805194) internal successors, (468), 307 states have internal predecessors, (468), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 468 transitions. [2021-08-31 04:18:27,756 INFO L704 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2021-08-31 04:18:27,756 INFO L587 BuchiCegarLoop]: Abstraction has 308 states and 468 transitions. [2021-08-31 04:18:27,756 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-08-31 04:18:27,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 468 transitions. [2021-08-31 04:18:27,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 257 [2021-08-31 04:18:27,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:27,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:27,758 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,759 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,759 INFO L791 eck$LassoCheckResult]: Stem: 2187#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2149#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2115#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2116#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 2147#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2052#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2053#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2088#L311-1 assume !(0 == ~M_E~0); 2161#L433-1 assume !(0 == ~T1_E~0); 2150#L438-1 assume !(0 == ~T2_E~0); 2074#L443-1 assume !(0 == ~T3_E~0); 2063#L448-1 assume !(0 == ~E_M~0); 2064#L453-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2108#L458-1 assume !(0 == ~E_2~0); 2109#L463-1 assume !(0 == ~E_3~0); 2190#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2164#L212 assume 1 == ~m_pc~0; 2102#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2021#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2022#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2171#L535 assume !(0 != activate_threads_~tmp~1); 2098#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2036#L231 assume !(1 == ~t1_pc~0); 1889#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 1890#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2168#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1994#L543 assume !(0 != activate_threads_~tmp___0~0); 1995#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2179#L250 assume 1 == ~t2_pc~0; 2174#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2076#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2117#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2141#L551 assume !(0 != activate_threads_~tmp___1~0); 2142#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2017#L269 assume 1 == ~t3_pc~0; 1897#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1898#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2129#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2130#L559 assume !(0 != activate_threads_~tmp___2~0); 2056#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2057#L481-1 assume !(1 == ~T1_E~0); 2099#L486-1 assume !(1 == ~T2_E~0); 1990#L491-1 assume !(1 == ~T3_E~0); 1991#L496-1 assume !(1 == ~E_M~0); 2158#L501-1 assume !(1 == ~E_1~0); 2162#L506-1 assume !(1 == ~E_2~0); 2023#L511-1 assume !(1 == ~E_3~0); 1952#L682-1 [2021-08-31 04:18:27,759 INFO L793 eck$LassoCheckResult]: Loop: 1952#L682-1 assume !false; 1953#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1916#L408 assume !false; 2003#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1910#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1911#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1992#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2166#L361 assume !(0 != eval_~tmp~0); 1919#L423 start_simulation_~kernel_st~0 := 2; 1885#L289-1 start_simulation_~kernel_st~0 := 3; 1886#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2157#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2136#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2137#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1891#L448-3 assume !(0 == ~E_M~0); 1892#L453-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1999#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2000#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2080#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2007#L212-15 assume !(1 == ~m_pc~0); 2008#L212-17 is_master_triggered_~__retres1~0 := 0; 1979#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1893#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1894#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1951#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1971#L231-15 assume 1 == ~t1_pc~0; 1928#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1929#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1969#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1970#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2060#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2061#L250-15 assume 1 == ~t2_pc~0; 2172#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2169#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2170#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1920#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1921#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2143#L269-15 assume 1 == ~t3_pc~0; 2049#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2050#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2123#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2185#L559-15 assume !(0 != activate_threads_~tmp___2~0); 2156#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2077#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2024#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2025#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2118#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2119#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2184#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2138#L511-3 assume !(1 == ~E_3~0); 2042#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2043#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1946#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1947#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2189#L701 assume !(0 == start_simulation_~tmp~3); 1978#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2120#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2027#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2019#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 2020#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1913#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 1914#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1985#L714 assume !(0 != start_simulation_~tmp___0~1); 1952#L682-1 [2021-08-31 04:18:27,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,760 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2021-08-31 04:18:27,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975638380] [2021-08-31 04:18:27,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,760 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,788 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975638380] [2021-08-31 04:18:27,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975638380] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,788 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,788 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,788 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538723816] [2021-08-31 04:18:27,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:27,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,789 INFO L82 PathProgramCache]: Analyzing trace with hash -1004789665, now seen corresponding path program 3 times [2021-08-31 04:18:27,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221275429] [2021-08-31 04:18:27,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,790 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,816 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,816 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221275429] [2021-08-31 04:18:27,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221275429] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,817 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,817 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,817 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1471144179] [2021-08-31 04:18:27,817 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:27,818 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:27,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:27,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:27,818 INFO L87 Difference]: Start difference. First operand 308 states and 468 transitions. cyclomatic complexity: 161 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:28,482 INFO L93 Difference]: Finished difference Result 512 states and 777 transitions. [2021-08-31 04:18:28,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:28,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 777 transitions. [2021-08-31 04:18:28,485 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 447 [2021-08-31 04:18:28,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 777 transitions. [2021-08-31 04:18:28,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2021-08-31 04:18:28,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2021-08-31 04:18:28,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 777 transitions. [2021-08-31 04:18:28,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:28,489 INFO L681 BuchiCegarLoop]: Abstraction has 512 states and 777 transitions. [2021-08-31 04:18:28,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 777 transitions. [2021-08-31 04:18:28,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 501. [2021-08-31 04:18:28,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 501 states, 501 states have (on average 1.5169660678642714) internal successors, (760), 500 states have internal predecessors, (760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 501 states to 501 states and 760 transitions. [2021-08-31 04:18:28,496 INFO L704 BuchiCegarLoop]: Abstraction has 501 states and 760 transitions. [2021-08-31 04:18:28,496 INFO L587 BuchiCegarLoop]: Abstraction has 501 states and 760 transitions. [2021-08-31 04:18:28,497 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-08-31 04:18:28,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 501 states and 760 transitions. [2021-08-31 04:18:28,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 447 [2021-08-31 04:18:28,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:28,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:28,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,500 INFO L791 eck$LassoCheckResult]: Stem: 3036#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2984#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2947#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2948#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 2982#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2884#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2885#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2920#L311-1 assume !(0 == ~M_E~0); 2999#L433-1 assume !(0 == ~T1_E~0); 2985#L438-1 assume !(0 == ~T2_E~0); 2906#L443-1 assume !(0 == ~T3_E~0); 2895#L448-1 assume !(0 == ~E_M~0); 2896#L453-1 assume !(0 == ~E_1~0); 2940#L458-1 assume !(0 == ~E_2~0); 2941#L463-1 assume !(0 == ~E_3~0); 3041#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3003#L212 assume 1 == ~m_pc~0; 2934#L213 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2852#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2853#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3014#L535 assume !(0 != activate_threads_~tmp~1); 2930#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2868#L231 assume !(1 == ~t1_pc~0); 2719#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 2720#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3010#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2824#L543 assume !(0 != activate_threads_~tmp___0~0); 2825#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3022#L250 assume 1 == ~t2_pc~0; 3017#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2908#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2949#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2976#L551 assume !(0 != activate_threads_~tmp___1~0); 2977#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2848#L269 assume 1 == ~t3_pc~0; 2727#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2728#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2961#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2962#L559 assume !(0 != activate_threads_~tmp___2~0); 2888#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2889#L481-1 assume !(1 == ~T1_E~0); 2931#L486-1 assume !(1 == ~T2_E~0); 2820#L491-1 assume !(1 == ~T3_E~0); 2821#L496-1 assume 1 == ~E_M~0;~E_M~0 := 2; 2993#L501-1 assume !(1 == ~E_1~0); 3032#L506-1 assume !(1 == ~E_2~0); 3063#L511-1 assume !(1 == ~E_3~0); 2782#L682-1 [2021-08-31 04:18:28,500 INFO L793 eck$LassoCheckResult]: Loop: 2782#L682-1 assume !false; 2783#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3053#L408 assume !false; 2833#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2834#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3049#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3035#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3007#L361 assume !(0 != eval_~tmp~0); 2749#L423 start_simulation_~kernel_st~0 := 2; 2715#L289-1 start_simulation_~kernel_st~0 := 3; 2716#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2992#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2970#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2971#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2975#L448-3 assume !(0 == ~E_M~0); 2997#L453-3 assume !(0 == ~E_1~0); 2829#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2830#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2912#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2838#L212-15 assume !(1 == ~m_pc~0); 2839#L212-17 is_master_triggered_~__retres1~0 := 0; 2809#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2723#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2724#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2781#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2801#L231-15 assume 1 == ~t1_pc~0; 2758#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2759#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2799#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2800#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2892#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2893#L250-15 assume 1 == ~t2_pc~0; 3015#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3011#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3012#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2750#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2751#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2978#L269-15 assume 1 == ~t3_pc~0; 2881#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2882#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2955#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3031#L559-15 assume !(0 != activate_threads_~tmp___2~0); 2991#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2909#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2856#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2857#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2950#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2951#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3028#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2972#L511-3 assume !(1 == ~E_3~0); 2874#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2875#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2776#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2777#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3038#L701 assume !(0 == start_simulation_~tmp~3); 2808#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2968#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3068#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3067#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3066#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3065#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 3064#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3062#L714 assume !(0 != start_simulation_~tmp___0~1); 2782#L682-1 [2021-08-31 04:18:28,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,501 INFO L82 PathProgramCache]: Analyzing trace with hash 989434402, now seen corresponding path program 1 times [2021-08-31 04:18:28,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555923465] [2021-08-31 04:18:28,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,502 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,521 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,521 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555923465] [2021-08-31 04:18:28,522 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555923465] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,522 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,522 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:28,522 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10379146] [2021-08-31 04:18:28,522 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:28,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,523 INFO L82 PathProgramCache]: Analyzing trace with hash 934372381, now seen corresponding path program 1 times [2021-08-31 04:18:28,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,523 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336179185] [2021-08-31 04:18:28,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,523 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,550 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,550 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336179185] [2021-08-31 04:18:28,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336179185] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,551 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,551 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:28,551 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344396644] [2021-08-31 04:18:28,551 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:28,551 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:28,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:28,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:28,552 INFO L87 Difference]: Start difference. First operand 501 states and 760 transitions. cyclomatic complexity: 261 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:29,062 INFO L93 Difference]: Finished difference Result 740 states and 1101 transitions. [2021-08-31 04:18:29,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:29,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 740 states and 1101 transitions. [2021-08-31 04:18:29,066 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 686 [2021-08-31 04:18:29,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 740 states to 740 states and 1101 transitions. [2021-08-31 04:18:29,069 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 740 [2021-08-31 04:18:29,069 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 740 [2021-08-31 04:18:29,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 740 states and 1101 transitions. [2021-08-31 04:18:29,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:29,070 INFO L681 BuchiCegarLoop]: Abstraction has 740 states and 1101 transitions. [2021-08-31 04:18:29,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 740 states and 1101 transitions. [2021-08-31 04:18:29,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 740 to 714. [2021-08-31 04:18:29,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 714 states, 714 states have (on average 1.4915966386554622) internal successors, (1065), 713 states have internal predecessors, (1065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 714 states to 714 states and 1065 transitions. [2021-08-31 04:18:29,078 INFO L704 BuchiCegarLoop]: Abstraction has 714 states and 1065 transitions. [2021-08-31 04:18:29,078 INFO L587 BuchiCegarLoop]: Abstraction has 714 states and 1065 transitions. [2021-08-31 04:18:29,079 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-08-31 04:18:29,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 714 states and 1065 transitions. [2021-08-31 04:18:29,081 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 660 [2021-08-31 04:18:29,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:29,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:29,082 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,082 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,082 INFO L791 eck$LassoCheckResult]: Stem: 4285#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4231#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4190#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4191#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 4229#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4128#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4129#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4163#L311-1 assume !(0 == ~M_E~0); 4246#L433-1 assume !(0 == ~T1_E~0); 4232#L438-1 assume !(0 == ~T2_E~0); 4150#L443-1 assume !(0 == ~T3_E~0); 4139#L448-1 assume !(0 == ~E_M~0); 4140#L453-1 assume !(0 == ~E_1~0); 4182#L458-1 assume !(0 == ~E_2~0); 4183#L463-1 assume !(0 == ~E_3~0); 4292#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4250#L212 assume !(1 == ~m_pc~0); 4185#L212-2 is_master_triggered_~__retres1~0 := 0; 4098#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4099#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4264#L535 assume !(0 != activate_threads_~tmp~1); 4172#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4113#L231 assume !(1 == ~t1_pc~0); 3967#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 3968#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4261#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4072#L543 assume !(0 != activate_threads_~tmp___0~0); 4073#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4272#L250 assume 1 == ~t2_pc~0; 4267#L251 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4152#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4192#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4223#L551 assume !(0 != activate_threads_~tmp___1~0); 4224#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4094#L269 assume 1 == ~t3_pc~0; 3975#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3976#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4208#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4209#L559 assume !(0 != activate_threads_~tmp___2~0); 4132#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 4133#L481-1 assume !(1 == ~T1_E~0); 4173#L486-1 assume !(1 == ~T2_E~0); 4068#L491-1 assume !(1 == ~T3_E~0); 4069#L496-1 assume 1 == ~E_M~0;~E_M~0 := 2; 4240#L501-1 assume !(1 == ~E_1~0); 4281#L506-1 assume !(1 == ~E_2~0); 4493#L511-1 assume !(1 == ~E_3~0); 4486#L682-1 [2021-08-31 04:18:29,083 INFO L793 eck$LassoCheckResult]: Loop: 4486#L682-1 assume !false; 4479#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 4477#L408 assume !false; 4476#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4474#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4471#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4470#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4469#L361 assume !(0 != eval_~tmp~0); 4468#L423 start_simulation_~kernel_st~0 := 2; 4467#L289-1 start_simulation_~kernel_st~0 := 3; 4466#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4465#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4464#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4463#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4462#L448-3 assume !(0 == ~E_M~0); 4244#L453-3 assume !(0 == ~E_1~0); 4077#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4078#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4156#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4085#L212-15 assume !(1 == ~m_pc~0); 4086#L212-17 is_master_triggered_~__retres1~0 := 0; 4057#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3971#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3972#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4029#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4049#L231-15 assume 1 == ~t1_pc~0; 4006#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4007#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4047#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4048#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4136#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4137#L250-15 assume 1 == ~t2_pc~0; 4265#L251-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4262#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4263#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3998#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3999#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4225#L269-15 assume 1 == ~t3_pc~0; 4125#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4126#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4199#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4279#L559-15 assume !(0 != activate_threads_~tmp___2~0); 4238#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4153#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4101#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4102#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4621#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4194#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4290#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4617#L511-3 assume !(1 == ~E_3~0); 4614#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4610#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4606#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4604#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4530#L701 assume !(0 == start_simulation_~tmp~3); 4528#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4521#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4506#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4502#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 4501#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4500#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 4499#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 4492#L714 assume !(0 != start_simulation_~tmp___0~1); 4486#L682-1 [2021-08-31 04:18:29,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,083 INFO L82 PathProgramCache]: Analyzing trace with hash -782036573, now seen corresponding path program 1 times [2021-08-31 04:18:29,083 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,083 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111517816] [2021-08-31 04:18:29,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,084 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,104 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111517816] [2021-08-31 04:18:29,105 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111517816] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,105 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,105 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:29,105 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141393778] [2021-08-31 04:18:29,105 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:29,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,106 INFO L82 PathProgramCache]: Analyzing trace with hash 934372381, now seen corresponding path program 2 times [2021-08-31 04:18:29,106 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,106 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [807289386] [2021-08-31 04:18:29,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,108 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,132 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [807289386] [2021-08-31 04:18:29,132 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [807289386] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,132 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,132 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:29,132 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423951018] [2021-08-31 04:18:29,132 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:29,132 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:29,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:29,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:29,133 INFO L87 Difference]: Start difference. First operand 714 states and 1065 transitions. cyclomatic complexity: 354 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:29,962 INFO L93 Difference]: Finished difference Result 1679 states and 2469 transitions. [2021-08-31 04:18:29,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:29,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1679 states and 2469 transitions. [2021-08-31 04:18:29,970 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1588 [2021-08-31 04:18:29,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1679 states to 1679 states and 2469 transitions. [2021-08-31 04:18:29,977 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1679 [2021-08-31 04:18:29,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1679 [2021-08-31 04:18:29,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1679 states and 2469 transitions. [2021-08-31 04:18:29,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:29,979 INFO L681 BuchiCegarLoop]: Abstraction has 1679 states and 2469 transitions. [2021-08-31 04:18:29,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1679 states and 2469 transitions. [2021-08-31 04:18:29,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1679 to 1271. [2021-08-31 04:18:29,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1271 states, 1271 states have (on average 1.4822974036191974) internal successors, (1884), 1270 states have internal predecessors, (1884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1271 states to 1271 states and 1884 transitions. [2021-08-31 04:18:29,995 INFO L704 BuchiCegarLoop]: Abstraction has 1271 states and 1884 transitions. [2021-08-31 04:18:29,995 INFO L587 BuchiCegarLoop]: Abstraction has 1271 states and 1884 transitions. [2021-08-31 04:18:29,995 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-08-31 04:18:29,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1271 states and 1884 transitions. [2021-08-31 04:18:29,999 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1217 [2021-08-31 04:18:29,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:29,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:30,000 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,000 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,000 INFO L791 eck$LassoCheckResult]: Stem: 6713#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 6643#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6605#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6606#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 6641#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6539#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6540#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6574#L311-1 assume !(0 == ~M_E~0); 6664#L433-1 assume !(0 == ~T1_E~0); 6644#L438-1 assume !(0 == ~T2_E~0); 6561#L443-1 assume !(0 == ~T3_E~0); 6550#L448-1 assume !(0 == ~E_M~0); 6551#L453-1 assume !(0 == ~E_1~0); 6596#L458-1 assume !(0 == ~E_2~0); 6597#L463-1 assume !(0 == ~E_3~0); 6719#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6669#L212 assume !(1 == ~m_pc~0); 6599#L212-2 is_master_triggered_~__retres1~0 := 0; 6507#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6508#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6685#L535 assume !(0 != activate_threads_~tmp~1); 6585#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6523#L231 assume !(1 == ~t1_pc~0); 6370#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 6371#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6682#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6480#L543 assume !(0 != activate_threads_~tmp___0~0); 6481#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6692#L250 assume !(1 == ~t2_pc~0); 6562#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 6563#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6607#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6636#L551 assume !(0 != activate_threads_~tmp___1~0); 6637#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6502#L269 assume 1 == ~t3_pc~0; 6378#L270 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6379#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6621#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6622#L559 assume !(0 != activate_threads_~tmp___2~0); 6543#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 6544#L481-1 assume !(1 == ~T1_E~0); 6586#L486-1 assume !(1 == ~T2_E~0); 6473#L491-1 assume !(1 == ~T3_E~0); 6474#L496-1 assume 1 == ~E_M~0;~E_M~0 := 2; 6657#L501-1 assume !(1 == ~E_1~0); 6666#L506-1 assume !(1 == ~E_2~0); 6667#L511-1 assume !(1 == ~E_3~0); 7532#L682-1 [2021-08-31 04:18:30,001 INFO L793 eck$LassoCheckResult]: Loop: 7532#L682-1 assume !false; 7528#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 7524#L408 assume !false; 7520#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7516#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7512#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7510#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7504#L361 assume !(0 != eval_~tmp~0); 7505#L423 start_simulation_~kernel_st~0 := 2; 7578#L289-1 start_simulation_~kernel_st~0 := 3; 7577#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7576#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7575#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7574#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7573#L448-3 assume !(0 == ~E_M~0); 6662#L453-3 assume !(0 == ~E_1~0); 6485#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6486#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6567#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6493#L212-15 assume !(1 == ~m_pc~0); 6494#L212-17 is_master_triggered_~__retres1~0 := 0; 6461#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6374#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6375#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6432#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6452#L231-15 assume 1 == ~t1_pc~0; 6409#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6410#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6450#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6451#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6545#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6546#L250-15 assume !(1 == ~t2_pc~0); 6686#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 6683#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6684#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6401#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6402#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6638#L269-15 assume 1 == ~t3_pc~0; 6535#L270-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6536#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6613#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6703#L559-15 assume !(0 != activate_threads_~tmp___2~0); 6652#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 6564#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6510#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6511#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6608#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6609#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6718#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7571#L511-3 assume !(1 == ~E_3~0); 7570#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7566#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7562#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7560#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7557#L701 assume !(0 == start_simulation_~tmp~3); 7555#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7548#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7545#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7543#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 7541#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7539#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 7537#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7536#L714 assume !(0 != start_simulation_~tmp___0~1); 7532#L682-1 [2021-08-31 04:18:30,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,001 INFO L82 PathProgramCache]: Analyzing trace with hash 209128100, now seen corresponding path program 1 times [2021-08-31 04:18:30,001 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,002 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074646228] [2021-08-31 04:18:30,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,002 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,029 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,029 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074646228] [2021-08-31 04:18:30,029 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074646228] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,029 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,030 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:30,030 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259474376] [2021-08-31 04:18:30,030 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:30,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,030 INFO L82 PathProgramCache]: Analyzing trace with hash 1853347004, now seen corresponding path program 1 times [2021-08-31 04:18:30,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,031 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026647791] [2021-08-31 04:18:30,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,031 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,053 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,053 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026647791] [2021-08-31 04:18:30,053 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026647791] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,053 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,053 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:30,053 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765040548] [2021-08-31 04:18:30,054 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:30,054 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:30,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:30,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:30,055 INFO L87 Difference]: Start difference. First operand 1271 states and 1884 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:30,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:30,872 INFO L93 Difference]: Finished difference Result 3091 states and 4515 transitions. [2021-08-31 04:18:30,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:30,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3091 states and 4515 transitions. [2021-08-31 04:18:30,884 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 2963 [2021-08-31 04:18:30,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3091 states to 3091 states and 4515 transitions. [2021-08-31 04:18:30,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3091 [2021-08-31 04:18:30,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3091 [2021-08-31 04:18:30,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3091 states and 4515 transitions. [2021-08-31 04:18:30,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:30,898 INFO L681 BuchiCegarLoop]: Abstraction has 3091 states and 4515 transitions. [2021-08-31 04:18:30,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3091 states and 4515 transitions. [2021-08-31 04:18:30,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3091 to 2342. [2021-08-31 04:18:30,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2342 states, 2342 states have (on average 1.4722459436379163) internal successors, (3448), 2341 states have internal predecessors, (3448), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:30,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2342 states to 2342 states and 3448 transitions. [2021-08-31 04:18:30,925 INFO L704 BuchiCegarLoop]: Abstraction has 2342 states and 3448 transitions. [2021-08-31 04:18:30,925 INFO L587 BuchiCegarLoop]: Abstraction has 2342 states and 3448 transitions. [2021-08-31 04:18:30,925 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-08-31 04:18:30,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2342 states and 3448 transitions. [2021-08-31 04:18:30,931 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2287 [2021-08-31 04:18:30,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:30,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:30,932 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,932 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,933 INFO L791 eck$LassoCheckResult]: Stem: 11098#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 11025#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10976#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10977#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 11021#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10908#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10909#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10944#L311-1 assume !(0 == ~M_E~0); 11048#L433-1 assume !(0 == ~T1_E~0); 11027#L438-1 assume !(0 == ~T2_E~0); 10930#L443-1 assume !(0 == ~T3_E~0); 10919#L448-1 assume !(0 == ~E_M~0); 10920#L453-1 assume !(0 == ~E_1~0); 10967#L458-1 assume !(0 == ~E_2~0); 10968#L463-1 assume !(0 == ~E_3~0); 11107#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11059#L212 assume !(1 == ~m_pc~0); 10970#L212-2 is_master_triggered_~__retres1~0 := 0; 10876#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10877#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11073#L535 assume !(0 != activate_threads_~tmp~1); 10955#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10892#L231 assume !(1 == ~t1_pc~0); 10742#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 10743#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11070#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10848#L543 assume !(0 != activate_threads_~tmp___0~0); 10849#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11079#L250 assume !(1 == ~t2_pc~0); 10932#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 10933#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10978#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11013#L551 assume !(0 != activate_threads_~tmp___1~0); 11014#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10870#L269 assume !(1 == ~t3_pc~0); 10871#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 10964#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10996#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10997#L559 assume !(0 != activate_threads_~tmp___2~0); 10916#L559-2 assume 1 == ~M_E~0;~M_E~0 := 2; 10917#L481-1 assume !(1 == ~T1_E~0); 10957#L486-1 assume !(1 == ~T2_E~0); 10844#L491-1 assume !(1 == ~T3_E~0); 10845#L496-1 assume 1 == ~E_M~0;~E_M~0 := 2; 11041#L501-1 assume !(1 == ~E_1~0); 11087#L506-1 assume !(1 == ~E_2~0); 10878#L511-1 assume !(1 == ~E_3~0); 10807#L682-1 [2021-08-31 04:18:30,933 INFO L793 eck$LassoCheckResult]: Loop: 10807#L682-1 assume !false; 10808#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 11071#L408 assume !false; 10860#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10761#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10762#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10846#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 11060#L361 assume !(0 != eval_~tmp~0); 11061#L423 start_simulation_~kernel_st~0 := 2; 13032#L289-1 start_simulation_~kernel_st~0 := 3; 13031#L433-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13030#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13029#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13028#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13026#L448-3 assume !(0 == ~E_M~0); 13024#L453-3 assume !(0 == ~E_1~0); 13022#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13020#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13019#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13017#L212-15 assume !(1 == ~m_pc~0); 13015#L212-17 is_master_triggered_~__retres1~0 := 0; 13013#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13011#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13009#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13007#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13006#L231-15 assume 1 == ~t1_pc~0; 13003#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13001#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13000#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11026#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10914#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10915#L250-15 assume !(1 == ~t2_pc~0); 11072#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 11068#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11069#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10771#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10772#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11015#L269-15 assume !(1 == ~t3_pc~0); 11016#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 10984#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10985#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11086#L559-15 assume !(0 != activate_threads_~tmp___2~0); 11035#L559-17 assume 1 == ~M_E~0;~M_E~0 := 2; 10931#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10879#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10880#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10979#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10980#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11085#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11006#L511-3 assume !(1 == ~E_3~0); 10897#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10898#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10798#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10799#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11100#L701 assume !(0 == start_simulation_~tmp~3); 10832#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 11001#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13062#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13061#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 13060#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13059#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 13058#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10988#L714 assume !(0 != start_simulation_~tmp___0~1); 10807#L682-1 [2021-08-31 04:18:30,933 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,933 INFO L82 PathProgramCache]: Analyzing trace with hash -1070196635, now seen corresponding path program 1 times [2021-08-31 04:18:30,933 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,933 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324192731] [2021-08-31 04:18:30,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,934 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,959 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324192731] [2021-08-31 04:18:30,960 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324192731] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,960 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,960 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:30,960 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1881391798] [2021-08-31 04:18:30,960 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:30,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,961 INFO L82 PathProgramCache]: Analyzing trace with hash -1802835813, now seen corresponding path program 1 times [2021-08-31 04:18:30,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,961 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718297005] [2021-08-31 04:18:30,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,962 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,988 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,989 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718297005] [2021-08-31 04:18:30,992 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718297005] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,993 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:30,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [861141727] [2021-08-31 04:18:30,993 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:30,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:30,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:30,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:30,994 INFO L87 Difference]: Start difference. First operand 2342 states and 3448 transitions. cyclomatic complexity: 1109 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:31,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:31,511 INFO L93 Difference]: Finished difference Result 4305 states and 6351 transitions. [2021-08-31 04:18:31,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:31,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4305 states and 6351 transitions. [2021-08-31 04:18:31,532 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4246 [2021-08-31 04:18:31,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4305 states to 4305 states and 6351 transitions. [2021-08-31 04:18:31,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4305 [2021-08-31 04:18:31,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4305 [2021-08-31 04:18:31,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4305 states and 6351 transitions. [2021-08-31 04:18:31,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:31,554 INFO L681 BuchiCegarLoop]: Abstraction has 4305 states and 6351 transitions. [2021-08-31 04:18:31,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4305 states and 6351 transitions. [2021-08-31 04:18:31,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4305 to 4305. [2021-08-31 04:18:31,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4305 states, 4305 states have (on average 1.4752613240418118) internal successors, (6351), 4304 states have internal predecessors, (6351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:31,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4305 states to 4305 states and 6351 transitions. [2021-08-31 04:18:31,621 INFO L704 BuchiCegarLoop]: Abstraction has 4305 states and 6351 transitions. [2021-08-31 04:18:31,622 INFO L587 BuchiCegarLoop]: Abstraction has 4305 states and 6351 transitions. [2021-08-31 04:18:31,622 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-08-31 04:18:31,622 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4305 states and 6351 transitions. [2021-08-31 04:18:31,633 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4246 [2021-08-31 04:18:31,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:31,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:31,634 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:31,635 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:31,635 INFO L791 eck$LassoCheckResult]: Stem: 17757#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 17677#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17631#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17632#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 17675#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17564#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17565#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17599#L311-1 assume !(0 == ~M_E~0); 17703#L433-1 assume !(0 == ~T1_E~0); 17679#L438-1 assume !(0 == ~T2_E~0); 17586#L443-1 assume !(0 == ~T3_E~0); 17576#L448-1 assume !(0 == ~E_M~0); 17577#L453-1 assume !(0 == ~E_1~0); 17623#L458-1 assume !(0 == ~E_2~0); 17624#L463-1 assume !(0 == ~E_3~0); 17769#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17710#L212 assume !(1 == ~m_pc~0); 17626#L212-2 is_master_triggered_~__retres1~0 := 0; 17530#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17531#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17727#L535 assume !(0 != activate_threads_~tmp~1); 17610#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17548#L231 assume !(1 == ~t1_pc~0); 17396#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 17397#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17724#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17502#L543 assume !(0 != activate_threads_~tmp___0~0); 17503#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17734#L250 assume !(1 == ~t2_pc~0); 17588#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 17589#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17633#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17667#L551 assume !(0 != activate_threads_~tmp___1~0); 17668#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17524#L269 assume !(1 == ~t3_pc~0); 17525#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 17619#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17651#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17652#L559 assume !(0 != activate_threads_~tmp___2~0); 17572#L559-2 assume !(1 == ~M_E~0); 17573#L481-1 assume !(1 == ~T1_E~0); 17611#L486-1 assume !(1 == ~T2_E~0); 17498#L491-1 assume !(1 == ~T3_E~0); 17499#L496-1 assume 1 == ~E_M~0;~E_M~0 := 2; 17695#L501-1 assume !(1 == ~E_1~0); 17747#L506-1 assume !(1 == ~E_2~0); 20743#L511-1 assume !(1 == ~E_3~0); 20741#L682-1 [2021-08-31 04:18:31,635 INFO L793 eck$LassoCheckResult]: Loop: 20741#L682-1 assume !false; 20740#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 19587#L408 assume !false; 20739#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20736#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20732#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 19617#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 19615#L361 assume !(0 != eval_~tmp~0); 19616#L423 start_simulation_~kernel_st~0 := 2; 17392#L289-1 start_simulation_~kernel_st~0 := 3; 17393#L433-2 assume !(0 == ~M_E~0); 17688#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17661#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17662#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17398#L448-3 assume !(0 == ~E_M~0); 17399#L453-3 assume !(0 == ~E_1~0); 17701#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21520#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21519#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21518#L212-15 assume !(1 == ~m_pc~0); 21517#L212-17 is_master_triggered_~__retres1~0 := 0; 21516#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17400#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17401#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17458#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17477#L231-15 assume 1 == ~t1_pc~0; 17432#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 17433#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17475#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17476#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17678#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17725#L250-15 assume !(1 == ~t2_pc~0); 17726#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 17732#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21406#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21400#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21395#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20791#L269-15 assume !(1 == ~t3_pc~0); 20790#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 20789#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20788#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20787#L559-15 assume !(0 != activate_threads_~tmp___2~0); 20786#L559-17 assume !(1 == ~M_E~0); 20783#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20782#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20781#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20780#L496-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19880#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19876#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20779#L511-3 assume !(1 == ~E_3~0); 20778#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20774#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20770#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20768#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 20754#L701 assume !(0 == start_simulation_~tmp~3); 20753#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 20750#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 20748#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 20747#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 20746#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20745#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 20744#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 20742#L714 assume !(0 != start_simulation_~tmp___0~1); 20741#L682-1 [2021-08-31 04:18:31,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:31,636 INFO L82 PathProgramCache]: Analyzing trace with hash -1879543261, now seen corresponding path program 1 times [2021-08-31 04:18:31,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:31,636 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773421055] [2021-08-31 04:18:31,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:31,636 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:31,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:31,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:31,650 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:31,650 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773421055] [2021-08-31 04:18:31,651 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773421055] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:31,651 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:31,651 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:31,651 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73591293] [2021-08-31 04:18:31,651 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:31,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:31,652 INFO L82 PathProgramCache]: Analyzing trace with hash -936233313, now seen corresponding path program 1 times [2021-08-31 04:18:31,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:31,652 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647697810] [2021-08-31 04:18:31,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:31,653 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:31,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:31,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:31,667 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:31,667 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1647697810] [2021-08-31 04:18:31,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1647697810] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:31,667 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:31,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:31,667 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181310172] [2021-08-31 04:18:31,668 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:31,668 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:31,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:31,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:31,668 INFO L87 Difference]: Start difference. First operand 4305 states and 6351 transitions. cyclomatic complexity: 2049 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:31,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:31,959 INFO L93 Difference]: Finished difference Result 4304 states and 6252 transitions. [2021-08-31 04:18:31,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:31,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4304 states and 6252 transitions. [2021-08-31 04:18:31,970 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4246 [2021-08-31 04:18:31,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4304 states to 4304 states and 6252 transitions. [2021-08-31 04:18:31,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4304 [2021-08-31 04:18:31,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4304 [2021-08-31 04:18:31,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4304 states and 6252 transitions. [2021-08-31 04:18:31,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:31,989 INFO L681 BuchiCegarLoop]: Abstraction has 4304 states and 6252 transitions. [2021-08-31 04:18:31,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4304 states and 6252 transitions. [2021-08-31 04:18:32,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4304 to 3076. [2021-08-31 04:18:32,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3076 states, 3076 states have (on average 1.4479843953185956) internal successors, (4454), 3075 states have internal predecessors, (4454), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3076 states to 3076 states and 4454 transitions. [2021-08-31 04:18:32,054 INFO L704 BuchiCegarLoop]: Abstraction has 3076 states and 4454 transitions. [2021-08-31 04:18:32,054 INFO L587 BuchiCegarLoop]: Abstraction has 3076 states and 4454 transitions. [2021-08-31 04:18:32,054 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-08-31 04:18:32,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3076 states and 4454 transitions. [2021-08-31 04:18:32,059 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3020 [2021-08-31 04:18:32,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:32,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:32,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,063 INFO L791 eck$LassoCheckResult]: Stem: 26356#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26290#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26247#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26248#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 26286#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26180#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26181#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26214#L311-1 assume !(0 == ~M_E~0); 26310#L433-1 assume !(0 == ~T1_E~0); 26291#L438-1 assume !(0 == ~T2_E~0); 26201#L443-1 assume !(0 == ~T3_E~0); 26191#L448-1 assume !(0 == ~E_M~0); 26192#L453-1 assume !(0 == ~E_1~0); 26238#L458-1 assume !(0 == ~E_2~0); 26239#L463-1 assume !(0 == ~E_3~0); 26361#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26317#L212 assume !(1 == ~m_pc~0); 26242#L212-2 is_master_triggered_~__retres1~0 := 0; 26148#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26149#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26332#L535 assume !(0 != activate_threads_~tmp~1); 26225#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26164#L231 assume !(1 == ~t1_pc~0); 26012#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 26013#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26329#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26119#L543 assume !(0 != activate_threads_~tmp___0~0); 26120#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26338#L250 assume !(1 == ~t2_pc~0); 26203#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 26204#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26249#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26279#L551 assume !(0 != activate_threads_~tmp___1~0); 26280#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26141#L269 assume !(1 == ~t3_pc~0); 26142#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 26233#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26265#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26266#L559 assume !(0 != activate_threads_~tmp___2~0); 26188#L559-2 assume !(1 == ~M_E~0); 26189#L481-1 assume !(1 == ~T1_E~0); 26227#L486-1 assume !(1 == ~T2_E~0); 26115#L491-1 assume !(1 == ~T3_E~0); 26116#L496-1 assume !(1 == ~E_M~0); 26305#L501-1 assume !(1 == ~E_1~0); 26315#L506-1 assume !(1 == ~E_2~0); 26150#L511-1 assume !(1 == ~E_3~0); 26151#L682-1 [2021-08-31 04:18:32,063 INFO L793 eck$LassoCheckResult]: Loop: 26151#L682-1 assume !false; 28298#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 28207#L408 assume !false; 28289#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28283#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28276#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28271#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 28263#L361 assume !(0 != eval_~tmp~0); 26042#L423 start_simulation_~kernel_st~0 := 2; 26008#L289-1 start_simulation_~kernel_st~0 := 3; 26009#L433-2 assume !(0 == ~M_E~0); 26300#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26274#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26275#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26014#L448-3 assume !(0 == ~E_M~0); 26015#L453-3 assume !(0 == ~E_1~0); 26124#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26125#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26207#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26132#L212-15 assume !(1 == ~m_pc~0); 26133#L212-17 is_master_triggered_~__retres1~0 := 0; 26102#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26103#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26072#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26073#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26145#L231-15 assume 1 == ~t1_pc~0; 29049#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 29046#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26090#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26091#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26184#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26185#L250-15 assume !(1 == ~t2_pc~0); 26331#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 29017#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29015#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28993#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28970#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28508#L269-15 assume !(1 == ~t3_pc~0); 28505#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 28472#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28465#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28458#L559-15 assume !(0 != activate_threads_~tmp___2~0); 28450#L559-17 assume !(1 == ~M_E~0); 28442#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28436#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28428#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28422#L496-3 assume !(1 == ~E_M~0); 28416#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28410#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28403#L511-3 assume !(1 == ~E_3~0); 28399#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28386#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28378#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28372#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 28366#L701 assume !(0 == start_simulation_~tmp~3); 28360#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28353#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28347#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28338#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 28331#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28325#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 28318#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 28313#L714 assume !(0 != start_simulation_~tmp___0~1); 26151#L682-1 [2021-08-31 04:18:32,063 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,063 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2021-08-31 04:18:32,063 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,064 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309930892] [2021-08-31 04:18:32,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,064 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:32,078 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:32,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:32,106 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:32,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,107 INFO L82 PathProgramCache]: Analyzing trace with hash 1770386081, now seen corresponding path program 1 times [2021-08-31 04:18:32,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542722601] [2021-08-31 04:18:32,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,108 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,120 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,120 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542722601] [2021-08-31 04:18:32,120 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542722601] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,121 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,121 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:32,121 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774212206] [2021-08-31 04:18:32,121 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:32,121 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:32,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:32,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:32,122 INFO L87 Difference]: Start difference. First operand 3076 states and 4454 transitions. cyclomatic complexity: 1380 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:32,616 INFO L93 Difference]: Finished difference Result 5301 states and 7626 transitions. [2021-08-31 04:18:32,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:32,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5301 states and 7626 transitions. [2021-08-31 04:18:32,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5204 [2021-08-31 04:18:32,671 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5301 states to 5301 states and 7626 transitions. [2021-08-31 04:18:32,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5301 [2021-08-31 04:18:32,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5301 [2021-08-31 04:18:32,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5301 states and 7626 transitions. [2021-08-31 04:18:32,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:32,679 INFO L681 BuchiCegarLoop]: Abstraction has 5301 states and 7626 transitions. [2021-08-31 04:18:32,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5301 states and 7626 transitions. [2021-08-31 04:18:32,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5301 to 5293. [2021-08-31 04:18:32,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5293 states, 5293 states have (on average 1.4392593992064993) internal successors, (7618), 5292 states have internal predecessors, (7618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5293 states to 5293 states and 7618 transitions. [2021-08-31 04:18:32,783 INFO L704 BuchiCegarLoop]: Abstraction has 5293 states and 7618 transitions. [2021-08-31 04:18:32,784 INFO L587 BuchiCegarLoop]: Abstraction has 5293 states and 7618 transitions. [2021-08-31 04:18:32,784 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-08-31 04:18:32,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5293 states and 7618 transitions. [2021-08-31 04:18:32,796 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5196 [2021-08-31 04:18:32,796 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:32,796 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:32,797 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,797 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,798 INFO L791 eck$LassoCheckResult]: Stem: 34738#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34673#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34627#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34628#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 34671#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34561#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34562#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34595#L311-1 assume !(0 == ~M_E~0); 34691#L433-1 assume !(0 == ~T1_E~0); 34674#L438-1 assume !(0 == ~T2_E~0); 34582#L443-1 assume !(0 == ~T3_E~0); 34572#L448-1 assume !(0 == ~E_M~0); 34573#L453-1 assume !(0 == ~E_1~0); 34619#L458-1 assume !(0 == ~E_2~0); 34620#L463-1 assume 0 == ~E_3~0;~E_3~0 := 1; 34747#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38657#L212 assume !(1 == ~m_pc~0); 38656#L212-2 is_master_triggered_~__retres1~0 := 0; 38655#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38654#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 38653#L535 assume !(0 != activate_threads_~tmp~1); 38649#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38647#L231 assume !(1 == ~t1_pc~0); 38645#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 38644#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38643#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 38642#L543 assume !(0 != activate_threads_~tmp___0~0); 38641#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38640#L250 assume !(1 == ~t2_pc~0); 38639#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 38638#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38637#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 38636#L551 assume !(0 != activate_threads_~tmp___1~0); 38635#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38634#L269 assume !(1 == ~t3_pc~0); 38633#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 38632#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38631#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 38630#L559 assume !(0 != activate_threads_~tmp___2~0); 38629#L559-2 assume !(1 == ~M_E~0); 38628#L481-1 assume !(1 == ~T1_E~0); 38627#L486-1 assume !(1 == ~T2_E~0); 38626#L491-1 assume !(1 == ~T3_E~0); 38625#L496-1 assume !(1 == ~E_M~0); 38624#L501-1 assume !(1 == ~E_1~0); 38621#L506-1 assume !(1 == ~E_2~0); 34532#L511-1 assume 1 == ~E_3~0;~E_3~0 := 2; 34533#L682-1 [2021-08-31 04:18:32,798 INFO L793 eck$LassoCheckResult]: Loop: 34533#L682-1 assume !false; 38572#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 38566#L408 assume !false; 38562#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38553#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 38545#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 38538#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 38530#L361 assume !(0 != eval_~tmp~0); 38531#L423 start_simulation_~kernel_st~0 := 2; 39144#L289-1 start_simulation_~kernel_st~0 := 3; 39142#L433-2 assume !(0 == ~M_E~0); 39140#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39138#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39136#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39134#L448-3 assume !(0 == ~E_M~0); 39132#L453-3 assume !(0 == ~E_1~0); 39130#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39125#L463-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39123#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39121#L212-15 assume !(1 == ~m_pc~0); 39119#L212-17 is_master_triggered_~__retres1~0 := 0; 39117#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39115#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 39114#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 39112#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 39110#L231-15 assume 1 == ~t1_pc~0; 39107#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 39105#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39103#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 39102#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39101#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 39100#L250-15 assume !(1 == ~t2_pc~0); 37899#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 39099#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39096#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 39094#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39092#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 39090#L269-15 assume !(1 == ~t3_pc~0); 38894#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 39087#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39085#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 39082#L559-15 assume !(0 != activate_threads_~tmp___2~0); 39080#L559-17 assume !(1 == ~M_E~0); 38300#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39077#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39075#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39073#L496-3 assume !(1 == ~E_M~0); 39070#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39068#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39066#L511-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39063#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 34858#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 34854#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 34829#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 34817#L701 assume !(0 == start_simulation_~tmp~3); 34818#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 38617#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 38614#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 38612#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 38610#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 38608#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 38605#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 38585#L714 assume !(0 != start_simulation_~tmp___0~1); 34533#L682-1 [2021-08-31 04:18:32,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1807097123, now seen corresponding path program 1 times [2021-08-31 04:18:32,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,802 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007017848] [2021-08-31 04:18:32,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,802 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,835 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007017848] [2021-08-31 04:18:32,835 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007017848] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,835 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:32,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623545664] [2021-08-31 04:18:32,835 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:32,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,836 INFO L82 PathProgramCache]: Analyzing trace with hash -1513463965, now seen corresponding path program 1 times [2021-08-31 04:18:32,836 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,836 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144793990] [2021-08-31 04:18:32,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,836 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,873 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144793990] [2021-08-31 04:18:32,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144793990] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,873 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:32,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346993296] [2021-08-31 04:18:32,874 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:32,874 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:32,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:32,874 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:32,875 INFO L87 Difference]: Start difference. First operand 5293 states and 7618 transitions. cyclomatic complexity: 2327 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:33,146 INFO L93 Difference]: Finished difference Result 3072 states and 4364 transitions. [2021-08-31 04:18:33,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:33,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3072 states and 4364 transitions. [2021-08-31 04:18:33,153 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3016 [2021-08-31 04:18:33,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3072 states to 3072 states and 4364 transitions. [2021-08-31 04:18:33,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3072 [2021-08-31 04:18:33,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3072 [2021-08-31 04:18:33,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3072 states and 4364 transitions. [2021-08-31 04:18:33,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:33,163 INFO L681 BuchiCegarLoop]: Abstraction has 3072 states and 4364 transitions. [2021-08-31 04:18:33,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3072 states and 4364 transitions. [2021-08-31 04:18:33,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3072 to 3072. [2021-08-31 04:18:33,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3072 states, 3072 states have (on average 1.4205729166666667) internal successors, (4364), 3071 states have internal predecessors, (4364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3072 states to 3072 states and 4364 transitions. [2021-08-31 04:18:33,190 INFO L704 BuchiCegarLoop]: Abstraction has 3072 states and 4364 transitions. [2021-08-31 04:18:33,190 INFO L587 BuchiCegarLoop]: Abstraction has 3072 states and 4364 transitions. [2021-08-31 04:18:33,190 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-08-31 04:18:33,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3072 states and 4364 transitions. [2021-08-31 04:18:33,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3016 [2021-08-31 04:18:33,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:33,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:33,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,204 INFO L791 eck$LassoCheckResult]: Stem: 43097#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 43038#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42999#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 43000#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 43036#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42933#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42934#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42968#L311-1 assume !(0 == ~M_E~0); 43057#L433-1 assume !(0 == ~T1_E~0); 43039#L438-1 assume !(0 == ~T2_E~0); 42954#L443-1 assume !(0 == ~T3_E~0); 42944#L448-1 assume !(0 == ~E_M~0); 42945#L453-1 assume !(0 == ~E_1~0); 42991#L458-1 assume !(0 == ~E_2~0); 42992#L463-1 assume !(0 == ~E_3~0); 43105#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43063#L212 assume !(1 == ~m_pc~0); 42994#L212-2 is_master_triggered_~__retres1~0 := 0; 42903#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42904#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 43072#L535 assume !(0 != activate_threads_~tmp~1); 42980#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42919#L231 assume !(1 == ~t1_pc~0); 42769#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 42770#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43070#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42873#L543 assume !(0 != activate_threads_~tmp___0~0); 42874#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43078#L250 assume !(1 == ~t2_pc~0); 42956#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 42957#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43001#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 43029#L551 assume !(0 != activate_threads_~tmp___1~0); 43030#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42897#L269 assume !(1 == ~t3_pc~0); 42898#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 42988#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43017#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43018#L559 assume !(0 != activate_threads_~tmp___2~0); 42941#L559-2 assume !(1 == ~M_E~0); 42942#L481-1 assume !(1 == ~T1_E~0); 42982#L486-1 assume !(1 == ~T2_E~0); 42869#L491-1 assume !(1 == ~T3_E~0); 42870#L496-1 assume !(1 == ~E_M~0); 43052#L501-1 assume !(1 == ~E_1~0); 43060#L506-1 assume !(1 == ~E_2~0); 42905#L511-1 assume !(1 == ~E_3~0); 42906#L682-1 [2021-08-31 04:18:33,204 INFO L793 eck$LassoCheckResult]: Loop: 42906#L682-1 assume !false; 44484#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 44453#L408 assume !false; 44481#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44471#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44467#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44465#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 44462#L361 assume !(0 != eval_~tmp~0); 44463#L423 start_simulation_~kernel_st~0 := 2; 44931#L289-1 start_simulation_~kernel_st~0 := 3; 44929#L433-2 assume !(0 == ~M_E~0); 44927#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44925#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44924#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44923#L448-3 assume !(0 == ~E_M~0); 44922#L453-3 assume !(0 == ~E_1~0); 44921#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44920#L463-3 assume !(0 == ~E_3~0); 44919#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44918#L212-15 assume !(1 == ~m_pc~0); 44917#L212-17 is_master_triggered_~__retres1~0 := 0; 44914#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44912#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 44910#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 44908#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44906#L231-15 assume 1 == ~t1_pc~0; 44903#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 44901#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44900#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 44848#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44839#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44574#L250-15 assume !(1 == ~t2_pc~0); 44571#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 44569#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44567#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 44565#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 44563#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44561#L269-15 assume !(1 == ~t3_pc~0); 43685#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 44558#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44556#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 44555#L559-15 assume !(0 != activate_threads_~tmp___2~0); 44550#L559-17 assume !(1 == ~M_E~0); 43877#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44547#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44544#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44543#L496-3 assume !(1 == ~E_M~0); 44541#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44539#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 44537#L511-3 assume !(1 == ~E_3~0); 44535#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44531#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44527#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44524#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 44508#L701 assume !(0 == start_simulation_~tmp~3); 44506#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44501#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44498#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44496#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 44494#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44491#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 44489#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 44487#L714 assume !(0 != start_simulation_~tmp___0~1); 42906#L682-1 [2021-08-31 04:18:33,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,205 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2021-08-31 04:18:33,205 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,205 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905529279] [2021-08-31 04:18:33,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,206 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:33,212 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:33,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:33,229 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:33,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,230 INFO L82 PathProgramCache]: Analyzing trace with hash -596308513, now seen corresponding path program 1 times [2021-08-31 04:18:33,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,231 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274058183] [2021-08-31 04:18:33,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,231 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:33,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:33,256 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:33,256 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274058183] [2021-08-31 04:18:33,256 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274058183] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:33,256 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:33,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:33,257 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659043959] [2021-08-31 04:18:33,257 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:33,257 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:33,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-31 04:18:33,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-31 04:18:33,258 INFO L87 Difference]: Start difference. First operand 3072 states and 4364 transitions. cyclomatic complexity: 1294 Second operand has 5 states, 5 states have (on average 12.6) internal successors, (63), 5 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:34,002 INFO L93 Difference]: Finished difference Result 5336 states and 7472 transitions. [2021-08-31 04:18:34,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-08-31 04:18:34,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5336 states and 7472 transitions. [2021-08-31 04:18:34,017 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5272 [2021-08-31 04:18:34,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5336 states to 5336 states and 7472 transitions. [2021-08-31 04:18:34,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5336 [2021-08-31 04:18:34,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5336 [2021-08-31 04:18:34,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5336 states and 7472 transitions. [2021-08-31 04:18:34,041 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:34,041 INFO L681 BuchiCegarLoop]: Abstraction has 5336 states and 7472 transitions. [2021-08-31 04:18:34,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5336 states and 7472 transitions. [2021-08-31 04:18:34,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5336 to 3120. [2021-08-31 04:18:34,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3120 states, 3120 states have (on average 1.4141025641025642) internal successors, (4412), 3119 states have internal predecessors, (4412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3120 states to 3120 states and 4412 transitions. [2021-08-31 04:18:34,095 INFO L704 BuchiCegarLoop]: Abstraction has 3120 states and 4412 transitions. [2021-08-31 04:18:34,095 INFO L587 BuchiCegarLoop]: Abstraction has 3120 states and 4412 transitions. [2021-08-31 04:18:34,095 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-08-31 04:18:34,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3120 states and 4412 transitions. [2021-08-31 04:18:34,100 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3064 [2021-08-31 04:18:34,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:34,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:34,101 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,101 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,101 INFO L791 eck$LassoCheckResult]: Stem: 51560#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 51479#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 51432#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 51433#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 51477#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51362#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51363#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51399#L311-1 assume !(0 == ~M_E~0); 51502#L433-1 assume !(0 == ~T1_E~0); 51481#L438-1 assume !(0 == ~T2_E~0); 51383#L443-1 assume !(0 == ~T3_E~0); 51373#L448-1 assume !(0 == ~E_M~0); 51374#L453-1 assume !(0 == ~E_1~0); 51423#L458-1 assume !(0 == ~E_2~0); 51424#L463-1 assume !(0 == ~E_3~0); 51566#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51513#L212 assume !(1 == ~m_pc~0); 51426#L212-2 is_master_triggered_~__retres1~0 := 0; 51332#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 51333#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51525#L535 assume !(0 != activate_threads_~tmp~1); 51411#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51348#L231 assume !(1 == ~t1_pc~0); 51193#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 51194#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51520#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51301#L543 assume !(0 != activate_threads_~tmp___0~0); 51302#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51533#L250 assume !(1 == ~t2_pc~0); 51386#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 51387#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51434#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 51470#L551 assume !(0 != activate_threads_~tmp___1~0); 51471#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 51324#L269 assume !(1 == ~t3_pc~0); 51325#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 51418#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51455#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 51456#L559 assume !(0 != activate_threads_~tmp___2~0); 51370#L559-2 assume !(1 == ~M_E~0); 51371#L481-1 assume !(1 == ~T1_E~0); 51413#L486-1 assume !(1 == ~T2_E~0); 51296#L491-1 assume !(1 == ~T3_E~0); 51297#L496-1 assume !(1 == ~E_M~0); 51496#L501-1 assume !(1 == ~E_1~0); 51506#L506-1 assume !(1 == ~E_2~0); 51334#L511-1 assume !(1 == ~E_3~0); 51335#L682-1 [2021-08-31 04:18:34,101 INFO L793 eck$LassoCheckResult]: Loop: 51335#L682-1 assume !false; 52774#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 52772#L408 assume !false; 52719#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 52715#L324 assume !(0 == ~m_st~0); 52716#L328 assume !(0 == ~t1_st~0); 52712#L332 assume !(0 == ~t2_st~0); 52713#L336 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 52714#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 52460#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 52461#L361 assume !(0 != eval_~tmp~0); 52705#L423 start_simulation_~kernel_st~0 := 2; 52916#L289-1 start_simulation_~kernel_st~0 := 3; 52915#L433-2 assume !(0 == ~M_E~0); 52914#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52913#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52912#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52911#L448-3 assume !(0 == ~E_M~0); 52910#L453-3 assume !(0 == ~E_1~0); 52909#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52908#L463-3 assume !(0 == ~E_3~0); 52907#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52906#L212-15 assume !(1 == ~m_pc~0); 52905#L212-17 is_master_triggered_~__retres1~0 := 0; 52904#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52903#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52902#L535-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 52901#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52900#L231-15 assume 1 == ~t1_pc~0; 52898#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 52682#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 52683#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52678#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52679#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52675#L250-15 assume !(1 == ~t2_pc~0); 52562#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 52672#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 52673#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52668#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 52669#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52665#L269-15 assume !(1 == ~t3_pc~0); 52664#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 52663#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52662#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 52661#L559-15 assume !(0 != activate_threads_~tmp___2~0); 52660#L559-17 assume !(1 == ~M_E~0); 52292#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52659#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52658#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52657#L496-3 assume !(1 == ~E_M~0); 52656#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52655#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52654#L511-3 assume !(1 == ~E_3~0); 52653#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 52651#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 52637#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 52635#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 52632#L701 assume !(0 == start_simulation_~tmp~3); 52633#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 52864#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 52862#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 52860#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 52858#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 52856#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 52854#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 52851#L714 assume !(0 != start_simulation_~tmp___0~1); 51335#L682-1 [2021-08-31 04:18:34,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,101 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2021-08-31 04:18:34,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487423446] [2021-08-31 04:18:34,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,102 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,109 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:34,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,123 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:34,124 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,124 INFO L82 PathProgramCache]: Analyzing trace with hash -446500323, now seen corresponding path program 1 times [2021-08-31 04:18:34,124 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,124 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569971084] [2021-08-31 04:18:34,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,124 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,132 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:34,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:34,174 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:34,176 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1569971084] [2021-08-31 04:18:34,176 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1569971084] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:34,176 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:34,176 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:34,176 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2089051800] [2021-08-31 04:18:34,176 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:34,176 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:34,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-31 04:18:34,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-31 04:18:34,177 INFO L87 Difference]: Start difference. First operand 3120 states and 4412 transitions. cyclomatic complexity: 1294 Second operand has 5 states, 5 states have (on average 13.2) internal successors, (66), 5 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:34,763 INFO L93 Difference]: Finished difference Result 3756 states and 5275 transitions. [2021-08-31 04:18:34,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-08-31 04:18:34,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3756 states and 5275 transitions. [2021-08-31 04:18:34,772 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3700 [2021-08-31 04:18:34,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3756 states to 3756 states and 5275 transitions. [2021-08-31 04:18:34,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3756 [2021-08-31 04:18:34,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3756 [2021-08-31 04:18:34,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3756 states and 5275 transitions. [2021-08-31 04:18:34,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:34,782 INFO L681 BuchiCegarLoop]: Abstraction has 3756 states and 5275 transitions. [2021-08-31 04:18:34,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3756 states and 5275 transitions. [2021-08-31 04:18:34,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3756 to 3132. [2021-08-31 04:18:34,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3132 states, 3132 states have (on average 1.3930395913154534) internal successors, (4363), 3131 states have internal predecessors, (4363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3132 states to 3132 states and 4363 transitions. [2021-08-31 04:18:34,809 INFO L704 BuchiCegarLoop]: Abstraction has 3132 states and 4363 transitions. [2021-08-31 04:18:34,809 INFO L587 BuchiCegarLoop]: Abstraction has 3132 states and 4363 transitions. [2021-08-31 04:18:34,810 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-08-31 04:18:34,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3132 states and 4363 transitions. [2021-08-31 04:18:34,826 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3076 [2021-08-31 04:18:34,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:34,826 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:34,827 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,827 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,827 INFO L791 eck$LassoCheckResult]: Stem: 58443#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 58363#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 58317#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58318#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 58361#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58247#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58248#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58283#L311-1 assume !(0 == ~M_E~0); 58386#L433-1 assume !(0 == ~T1_E~0); 58365#L438-1 assume !(0 == ~T2_E~0); 58268#L443-1 assume !(0 == ~T3_E~0); 58258#L448-1 assume !(0 == ~E_M~0); 58259#L453-1 assume !(0 == ~E_1~0); 58307#L458-1 assume !(0 == ~E_2~0); 58308#L463-1 assume !(0 == ~E_3~0); 58455#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58394#L212 assume !(1 == ~m_pc~0); 58311#L212-2 is_master_triggered_~__retres1~0 := 0; 58215#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58216#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58408#L535 assume !(0 != activate_threads_~tmp~1); 58295#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58231#L231 assume !(1 == ~t1_pc~0); 58082#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 58083#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58406#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58186#L543 assume !(0 != activate_threads_~tmp___0~0); 58187#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58416#L250 assume !(1 == ~t2_pc~0); 58270#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 58271#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58319#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58353#L551 assume !(0 != activate_threads_~tmp___1~0); 58354#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58209#L269 assume !(1 == ~t3_pc~0); 58210#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 58302#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58335#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 58336#L559 assume !(0 != activate_threads_~tmp___2~0); 58255#L559-2 assume !(1 == ~M_E~0); 58256#L481-1 assume !(1 == ~T1_E~0); 58296#L486-1 assume !(1 == ~T2_E~0); 58181#L491-1 assume !(1 == ~T3_E~0); 58182#L496-1 assume !(1 == ~E_M~0); 58379#L501-1 assume !(1 == ~E_1~0); 58392#L506-1 assume !(1 == ~E_2~0); 58217#L511-1 assume !(1 == ~E_3~0); 58218#L682-1 [2021-08-31 04:18:34,827 INFO L793 eck$LassoCheckResult]: Loop: 58218#L682-1 assume !false; 59953#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 59758#L408 assume !false; 59952#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 59951#L324 assume !(0 == ~m_st~0); 59950#L328 assume !(0 == ~t1_st~0); 59949#L332 assume !(0 == ~t2_st~0); 59947#L336 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 59946#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 59945#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 59944#L361 assume !(0 != eval_~tmp~0); 59943#L423 start_simulation_~kernel_st~0 := 2; 59942#L289-1 start_simulation_~kernel_st~0 := 3; 59941#L433-2 assume !(0 == ~M_E~0); 59940#L433-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59939#L438-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59938#L443-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59937#L448-3 assume !(0 == ~E_M~0); 59936#L453-3 assume !(0 == ~E_1~0); 59935#L458-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59934#L463-3 assume !(0 == ~E_3~0); 59933#L468-3 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59932#L212-15 assume !(1 == ~m_pc~0); 59931#L212-17 is_master_triggered_~__retres1~0 := 0; 59930#L223-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59929#L224-5 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59928#L535-15 assume !(0 != activate_threads_~tmp~1); 59927#L535-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59926#L231-15 assume 1 == ~t1_pc~0; 59924#L232-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 59923#L242-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59922#L243-5 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 59921#L543-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 59920#L543-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59919#L250-15 assume !(1 == ~t2_pc~0); 59093#L250-17 is_transmit2_triggered_~__retres1~2 := 0; 59918#L261-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59917#L262-5 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 59916#L551-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 59915#L551-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59914#L269-15 assume !(1 == ~t3_pc~0); 59656#L269-17 is_transmit3_triggered_~__retres1~3 := 0; 59913#L280-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 59912#L281-5 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 59910#L559-15 assume !(0 != activate_threads_~tmp___2~0); 59908#L559-17 assume !(1 == ~M_E~0); 59839#L481-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59905#L486-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59903#L491-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 59901#L496-3 assume !(1 == ~E_M~0); 59899#L501-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59897#L506-3 assume 1 == ~E_2~0;~E_2~0 := 2; 59895#L511-3 assume !(1 == ~E_3~0); 59893#L516-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 59890#L324-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 59886#L346-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 59884#L347-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 59881#L701 assume !(0 == start_simulation_~tmp~3); 59882#L701-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 59961#L324-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 59959#L346-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 59958#L347-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 59957#L656 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 59956#L663 stop_simulation_#res := stop_simulation_~__retres2~0; 59955#L664 start_simulation_#t~ret20 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 59954#L714 assume !(0 != start_simulation_~tmp___0~1); 58218#L682-1 [2021-08-31 04:18:34,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2021-08-31 04:18:34,828 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,828 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359856476] [2021-08-31 04:18:34,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,828 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,832 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:34,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,839 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:34,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,840 INFO L82 PathProgramCache]: Analyzing trace with hash -1818307621, now seen corresponding path program 1 times [2021-08-31 04:18:34,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,840 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [98799884] [2021-08-31 04:18:34,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,840 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:34,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:34,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:34,855 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [98799884] [2021-08-31 04:18:34,855 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [98799884] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:34,855 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:34,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:34,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246834933] [2021-08-31 04:18:34,856 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:34,856 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:34,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:34,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:34,856 INFO L87 Difference]: Start difference. First operand 3132 states and 4363 transitions. cyclomatic complexity: 1233 Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:35,204 INFO L93 Difference]: Finished difference Result 4081 states and 5589 transitions. [2021-08-31 04:18:35,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:35,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4081 states and 5589 transitions. [2021-08-31 04:18:35,213 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4027 [2021-08-31 04:18:35,219 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4081 states to 4081 states and 5589 transitions. [2021-08-31 04:18:35,219 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4081 [2021-08-31 04:18:35,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4081 [2021-08-31 04:18:35,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4081 states and 5589 transitions. [2021-08-31 04:18:35,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:35,222 INFO L681 BuchiCegarLoop]: Abstraction has 4081 states and 5589 transitions. [2021-08-31 04:18:35,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4081 states and 5589 transitions. [2021-08-31 04:18:35,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4081 to 4081. [2021-08-31 04:18:35,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4081 states, 4081 states have (on average 1.3695172751776525) internal successors, (5589), 4080 states have internal predecessors, (5589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4081 states to 4081 states and 5589 transitions. [2021-08-31 04:18:35,255 INFO L704 BuchiCegarLoop]: Abstraction has 4081 states and 5589 transitions. [2021-08-31 04:18:35,255 INFO L587 BuchiCegarLoop]: Abstraction has 4081 states and 5589 transitions. [2021-08-31 04:18:35,255 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-08-31 04:18:35,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4081 states and 5589 transitions. [2021-08-31 04:18:35,267 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4027 [2021-08-31 04:18:35,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:35,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:35,268 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,268 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,268 INFO L791 eck$LassoCheckResult]: Stem: 65644#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 65579#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 65535#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 65536#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 65575#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65464#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65465#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65500#L311-1 assume !(0 == ~M_E~0); 65601#L433-1 assume !(0 == ~T1_E~0); 65580#L438-1 assume !(0 == ~T2_E~0); 65485#L443-1 assume !(0 == ~T3_E~0); 65475#L448-1 assume !(0 == ~E_M~0); 65476#L453-1 assume !(0 == ~E_1~0); 65527#L458-1 assume !(0 == ~E_2~0); 65528#L463-1 assume !(0 == ~E_3~0); 65648#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 65606#L212 assume !(1 == ~m_pc~0); 65530#L212-2 is_master_triggered_~__retres1~0 := 0; 65431#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65432#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 65620#L535 assume !(0 != activate_threads_~tmp~1); 65513#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65449#L231 assume !(1 == ~t1_pc~0); 65301#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 65302#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65617#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 65403#L543 assume !(0 != activate_threads_~tmp___0~0); 65404#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 65627#L250 assume !(1 == ~t2_pc~0); 65486#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 65487#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65537#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 65568#L551 assume !(0 != activate_threads_~tmp___1~0); 65569#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 65425#L269 assume !(1 == ~t3_pc~0); 65426#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 65523#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65550#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 65551#L559 assume !(0 != activate_threads_~tmp___2~0); 65468#L559-2 assume !(1 == ~M_E~0); 65469#L481-1 assume !(1 == ~T1_E~0); 65514#L486-1 assume !(1 == ~T2_E~0); 65398#L491-1 assume !(1 == ~T3_E~0); 65399#L496-1 assume !(1 == ~E_M~0); 65594#L501-1 assume !(1 == ~E_1~0); 65604#L506-1 assume !(1 == ~E_2~0); 65433#L511-1 assume !(1 == ~E_3~0); 65434#L682-1 assume !false; 69006#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 68981#L408 [2021-08-31 04:18:35,269 INFO L793 eck$LassoCheckResult]: Loop: 68981#L408 assume !false; 69003#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 69002#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 69000#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 68998#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 68996#L361 assume 0 != eval_~tmp~0; 68995#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 68991#L369 assume !(0 != eval_~tmp_ndt_1~0); 68986#L366 assume !(0 == ~t1_st~0); 68985#L380 assume !(0 == ~t2_st~0); 68982#L394 assume !(0 == ~t3_st~0); 68981#L408 [2021-08-31 04:18:35,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2021-08-31 04:18:35,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939326890] [2021-08-31 04:18:35,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,270 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,275 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:35,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,296 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:35,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,298 INFO L82 PathProgramCache]: Analyzing trace with hash 527287816, now seen corresponding path program 1 times [2021-08-31 04:18:35,298 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,298 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274688969] [2021-08-31 04:18:35,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,300 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,302 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:35,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,304 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:35,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,304 INFO L82 PathProgramCache]: Analyzing trace with hash -1008144026, now seen corresponding path program 1 times [2021-08-31 04:18:35,304 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,305 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269201763] [2021-08-31 04:18:35,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,305 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:35,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:35,323 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:35,323 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269201763] [2021-08-31 04:18:35,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269201763] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:35,323 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:35,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:35,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529915894] [2021-08-31 04:18:35,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:35,379 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:35,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:35,380 INFO L87 Difference]: Start difference. First operand 4081 states and 5589 transitions. cyclomatic complexity: 1511 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:35,903 INFO L93 Difference]: Finished difference Result 7173 states and 9688 transitions. [2021-08-31 04:18:35,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:35,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7173 states and 9688 transitions. [2021-08-31 04:18:35,924 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 7070 [2021-08-31 04:18:35,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7173 states to 7173 states and 9688 transitions. [2021-08-31 04:18:35,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7173 [2021-08-31 04:18:35,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7173 [2021-08-31 04:18:35,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7173 states and 9688 transitions. [2021-08-31 04:18:35,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:35,945 INFO L681 BuchiCegarLoop]: Abstraction has 7173 states and 9688 transitions. [2021-08-31 04:18:35,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7173 states and 9688 transitions. [2021-08-31 04:18:36,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7173 to 6725. [2021-08-31 04:18:36,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6725 states, 6725 states have (on average 1.3594052044609666) internal successors, (9142), 6724 states have internal predecessors, (9142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:36,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6725 states to 6725 states and 9142 transitions. [2021-08-31 04:18:36,026 INFO L704 BuchiCegarLoop]: Abstraction has 6725 states and 9142 transitions. [2021-08-31 04:18:36,026 INFO L587 BuchiCegarLoop]: Abstraction has 6725 states and 9142 transitions. [2021-08-31 04:18:36,026 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-08-31 04:18:36,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6725 states and 9142 transitions. [2021-08-31 04:18:36,041 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6622 [2021-08-31 04:18:36,041 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:36,041 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:36,042 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,042 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,042 INFO L791 eck$LassoCheckResult]: Stem: 76929#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 76851#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 76802#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 76803#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 76848#L296-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 76882#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78898#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78897#L311-1 assume !(0 == ~M_E~0); 78896#L433-1 assume !(0 == ~T1_E~0); 78895#L438-1 assume !(0 == ~T2_E~0); 78894#L443-1 assume !(0 == ~T3_E~0); 78893#L448-1 assume !(0 == ~E_M~0); 78892#L453-1 assume !(0 == ~E_1~0); 78891#L458-1 assume !(0 == ~E_2~0); 78890#L463-1 assume !(0 == ~E_3~0); 78889#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78888#L212 assume !(1 == ~m_pc~0); 78887#L212-2 is_master_triggered_~__retres1~0 := 0; 78886#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78885#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78884#L535 assume !(0 != activate_threads_~tmp~1); 78883#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78882#L231 assume !(1 == ~t1_pc~0); 78880#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 78879#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78878#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 78877#L543 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 76670#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76910#L250 assume !(1 == ~t2_pc~0); 76757#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 76758#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76804#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 76841#L551 assume !(0 != activate_threads_~tmp___1~0); 76842#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76693#L269 assume !(1 == ~t3_pc~0); 76694#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 76789#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76823#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 76824#L559 assume !(0 != activate_threads_~tmp___2~0); 76738#L559-2 assume !(1 == ~M_E~0); 76739#L481-1 assume !(1 == ~T1_E~0); 76781#L486-1 assume !(1 == ~T2_E~0); 76664#L491-1 assume !(1 == ~T3_E~0); 76665#L496-1 assume !(1 == ~E_M~0); 78857#L501-1 assume !(1 == ~E_1~0); 78855#L506-1 assume !(1 == ~E_2~0); 76701#L511-1 assume !(1 == ~E_3~0); 76702#L682-1 assume !false; 79340#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 79339#L408 [2021-08-31 04:18:36,042 INFO L793 eck$LassoCheckResult]: Loop: 79339#L408 assume !false; 79335#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 79332#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 79329#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 79327#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 79325#L361 assume 0 != eval_~tmp~0; 79322#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 79319#L369 assume !(0 != eval_~tmp_ndt_1~0); 79317#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 78770#L383 assume !(0 != eval_~tmp_ndt_2~0); 79315#L380 assume !(0 == ~t2_st~0); 79212#L394 assume !(0 == ~t3_st~0); 79339#L408 [2021-08-31 04:18:36,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,043 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2021-08-31 04:18:36,043 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,043 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575566715] [2021-08-31 04:18:36,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,044 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:36,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:36,056 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:36,056 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [575566715] [2021-08-31 04:18:36,057 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [575566715] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:36,057 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:36,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:36,057 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413852534] [2021-08-31 04:18:36,057 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:36,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,058 INFO L82 PathProgramCache]: Analyzing trace with hash -837923902, now seen corresponding path program 1 times [2021-08-31 04:18:36,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,058 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236451919] [2021-08-31 04:18:36,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,059 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,062 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:36,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,068 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:36,122 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:36,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:36,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:36,122 INFO L87 Difference]: Start difference. First operand 6725 states and 9142 transitions. cyclomatic complexity: 2420 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:36,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:36,393 INFO L93 Difference]: Finished difference Result 6680 states and 9082 transitions. [2021-08-31 04:18:36,394 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:36,394 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6680 states and 9082 transitions. [2021-08-31 04:18:36,408 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6622 [2021-08-31 04:18:36,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6680 states to 6680 states and 9082 transitions. [2021-08-31 04:18:36,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6680 [2021-08-31 04:18:36,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6680 [2021-08-31 04:18:36,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6680 states and 9082 transitions. [2021-08-31 04:18:36,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:36,430 INFO L681 BuchiCegarLoop]: Abstraction has 6680 states and 9082 transitions. [2021-08-31 04:18:36,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6680 states and 9082 transitions. [2021-08-31 04:18:36,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6680 to 6680. [2021-08-31 04:18:36,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6680 states, 6680 states have (on average 1.3595808383233532) internal successors, (9082), 6679 states have internal predecessors, (9082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:36,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6680 states to 6680 states and 9082 transitions. [2021-08-31 04:18:36,516 INFO L704 BuchiCegarLoop]: Abstraction has 6680 states and 9082 transitions. [2021-08-31 04:18:36,516 INFO L587 BuchiCegarLoop]: Abstraction has 6680 states and 9082 transitions. [2021-08-31 04:18:36,516 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-08-31 04:18:36,516 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6680 states and 9082 transitions. [2021-08-31 04:18:36,527 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6622 [2021-08-31 04:18:36,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:36,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:36,527 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,527 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,528 INFO L791 eck$LassoCheckResult]: Stem: 90324#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 90253#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 90204#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 90205#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 90249#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 90138#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90139#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90173#L311-1 assume !(0 == ~M_E~0); 90279#L433-1 assume !(0 == ~T1_E~0); 90255#L438-1 assume !(0 == ~T2_E~0); 90159#L443-1 assume !(0 == ~T3_E~0); 90149#L448-1 assume !(0 == ~E_M~0); 90150#L453-1 assume !(0 == ~E_1~0); 90196#L458-1 assume !(0 == ~E_2~0); 90197#L463-1 assume !(0 == ~E_3~0); 90333#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90286#L212 assume !(1 == ~m_pc~0); 90199#L212-2 is_master_triggered_~__retres1~0 := 0; 90104#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 90105#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90297#L535 assume !(0 != activate_threads_~tmp~1); 90185#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90122#L231 assume !(1 == ~t1_pc~0); 89974#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 89975#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90294#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90076#L543 assume !(0 != activate_threads_~tmp___0~0); 90077#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90305#L250 assume !(1 == ~t2_pc~0); 90160#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 90161#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90206#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90242#L551 assume !(0 != activate_threads_~tmp___1~0); 90243#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90098#L269 assume !(1 == ~t3_pc~0); 90099#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 90193#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90220#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 90221#L559 assume !(0 != activate_threads_~tmp___2~0); 90142#L559-2 assume !(1 == ~M_E~0); 90143#L481-1 assume !(1 == ~T1_E~0); 90186#L486-1 assume !(1 == ~T2_E~0); 90071#L491-1 assume !(1 == ~T3_E~0); 90072#L496-1 assume !(1 == ~E_M~0); 90270#L501-1 assume !(1 == ~E_1~0); 90283#L506-1 assume !(1 == ~E_2~0); 90106#L511-1 assume !(1 == ~E_3~0); 90107#L682-1 assume !false; 93129#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 93123#L408 [2021-08-31 04:18:36,528 INFO L793 eck$LassoCheckResult]: Loop: 93123#L408 assume !false; 93120#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 93117#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 92980#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 92970#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 92937#L361 assume 0 != eval_~tmp~0; 92938#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 93101#L369 assume !(0 != eval_~tmp_ndt_1~0); 93097#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 93079#L383 assume !(0 != eval_~tmp_ndt_2~0); 93093#L380 assume !(0 == ~t2_st~0); 93132#L394 assume !(0 == ~t3_st~0); 93123#L408 [2021-08-31 04:18:36,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,528 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2021-08-31 04:18:36,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,529 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877446817] [2021-08-31 04:18:36,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,530 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,534 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:36,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,543 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:36,543 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,543 INFO L82 PathProgramCache]: Analyzing trace with hash -837923902, now seen corresponding path program 2 times [2021-08-31 04:18:36,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,544 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004406601] [2021-08-31 04:18:36,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,544 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,547 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:36,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,549 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:36,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,550 INFO L82 PathProgramCache]: Analyzing trace with hash -1191670748, now seen corresponding path program 1 times [2021-08-31 04:18:36,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,550 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321497781] [2021-08-31 04:18:36,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,550 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:36,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:36,567 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:36,567 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321497781] [2021-08-31 04:18:36,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321497781] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:36,567 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:36,568 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:36,568 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [791188199] [2021-08-31 04:18:36,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:36,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:36,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:36,617 INFO L87 Difference]: Start difference. First operand 6680 states and 9082 transitions. cyclomatic complexity: 2405 Second operand has 3 states, 3 states have (on average 20.333333333333332) internal successors, (61), 3 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:37,070 INFO L93 Difference]: Finished difference Result 11886 states and 15992 transitions. [2021-08-31 04:18:37,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:37,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11886 states and 15992 transitions. [2021-08-31 04:18:37,096 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11820 [2021-08-31 04:18:37,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11886 states to 11886 states and 15992 transitions. [2021-08-31 04:18:37,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11886 [2021-08-31 04:18:37,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11886 [2021-08-31 04:18:37,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11886 states and 15992 transitions. [2021-08-31 04:18:37,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:37,134 INFO L681 BuchiCegarLoop]: Abstraction has 11886 states and 15992 transitions. [2021-08-31 04:18:37,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11886 states and 15992 transitions. [2021-08-31 04:18:37,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11886 to 11634. [2021-08-31 04:18:37,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11634 states, 11634 states have (on average 1.3493209558191508) internal successors, (15698), 11633 states have internal predecessors, (15698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11634 states to 11634 states and 15698 transitions. [2021-08-31 04:18:37,274 INFO L704 BuchiCegarLoop]: Abstraction has 11634 states and 15698 transitions. [2021-08-31 04:18:37,274 INFO L587 BuchiCegarLoop]: Abstraction has 11634 states and 15698 transitions. [2021-08-31 04:18:37,274 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-08-31 04:18:37,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11634 states and 15698 transitions. [2021-08-31 04:18:37,297 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11568 [2021-08-31 04:18:37,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:37,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:37,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,298 INFO L791 eck$LassoCheckResult]: Stem: 108923#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 108842#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 108788#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 108789#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 108838#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 108714#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108715#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108751#L311-1 assume !(0 == ~M_E~0); 108869#L433-1 assume !(0 == ~T1_E~0); 108846#L438-1 assume !(0 == ~T2_E~0); 108736#L443-1 assume !(0 == ~T3_E~0); 108726#L448-1 assume !(0 == ~E_M~0); 108727#L453-1 assume !(0 == ~E_1~0); 108779#L458-1 assume !(0 == ~E_2~0); 108780#L463-1 assume !(0 == ~E_3~0); 108932#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 108877#L212 assume !(1 == ~m_pc~0); 108782#L212-2 is_master_triggered_~__retres1~0 := 0; 108680#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 108681#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 108892#L535 assume !(0 != activate_threads_~tmp~1); 108765#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 108698#L231 assume !(1 == ~t1_pc~0); 108548#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 108549#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 108887#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 108651#L543 assume !(0 != activate_threads_~tmp___0~0); 108652#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 108899#L250 assume !(1 == ~t2_pc~0); 108738#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 108739#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 108790#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 108828#L551 assume !(0 != activate_threads_~tmp___1~0); 108829#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 108674#L269 assume !(1 == ~t3_pc~0); 108675#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 108776#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 108810#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 108811#L559 assume !(0 != activate_threads_~tmp___2~0); 108722#L559-2 assume !(1 == ~M_E~0); 108723#L481-1 assume !(1 == ~T1_E~0); 108767#L486-1 assume !(1 == ~T2_E~0); 108646#L491-1 assume !(1 == ~T3_E~0); 108647#L496-1 assume !(1 == ~E_M~0); 108863#L501-1 assume !(1 == ~E_1~0); 108872#L506-1 assume !(1 == ~E_2~0); 108682#L511-1 assume !(1 == ~E_3~0); 108683#L682-1 assume !false; 117319#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 117288#L408 [2021-08-31 04:18:37,298 INFO L793 eck$LassoCheckResult]: Loop: 117288#L408 assume !false; 117316#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 117314#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 117312#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 117310#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 117308#L361 assume 0 != eval_~tmp~0; 117307#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 117303#L369 assume !(0 != eval_~tmp_ndt_1~0); 117301#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 117297#L383 assume !(0 != eval_~tmp_ndt_2~0); 117295#L380 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 114114#L397 assume !(0 != eval_~tmp_ndt_3~0); 117291#L394 assume !(0 == ~t3_st~0); 117288#L408 [2021-08-31 04:18:37,298 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,298 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2021-08-31 04:18:37,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,299 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464374250] [2021-08-31 04:18:37,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,299 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,304 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,311 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,312 INFO L82 PathProgramCache]: Analyzing trace with hash -205964527, now seen corresponding path program 1 times [2021-08-31 04:18:37,312 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,312 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482141427] [2021-08-31 04:18:37,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,312 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,314 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,317 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,318 INFO L82 PathProgramCache]: Analyzing trace with hash 1712785135, now seen corresponding path program 1 times [2021-08-31 04:18:37,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,318 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [879551537] [2021-08-31 04:18:37,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,318 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:37,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:37,332 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:37,332 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [879551537] [2021-08-31 04:18:37,332 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [879551537] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:37,332 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:37,332 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:37,332 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199757200] [2021-08-31 04:18:37,407 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:37,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:37,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:37,407 INFO L87 Difference]: Start difference. First operand 11634 states and 15698 transitions. cyclomatic complexity: 4067 Second operand has 3 states, 2 states have (on average 31.0) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:37,946 INFO L93 Difference]: Finished difference Result 20174 states and 27056 transitions. [2021-08-31 04:18:37,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:37,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20174 states and 27056 transitions. [2021-08-31 04:18:38,017 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20092 [2021-08-31 04:18:38,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20174 states to 20174 states and 27056 transitions. [2021-08-31 04:18:38,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20174 [2021-08-31 04:18:38,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20174 [2021-08-31 04:18:38,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20174 states and 27056 transitions. [2021-08-31 04:18:38,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:38,085 INFO L681 BuchiCegarLoop]: Abstraction has 20174 states and 27056 transitions. [2021-08-31 04:18:38,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20174 states and 27056 transitions. [2021-08-31 04:18:38,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20174 to 20006. [2021-08-31 04:18:38,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20006 states, 20006 states have (on average 1.343996800959712) internal successors, (26888), 20005 states have internal predecessors, (26888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:38,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20006 states to 20006 states and 26888 transitions. [2021-08-31 04:18:38,328 INFO L704 BuchiCegarLoop]: Abstraction has 20006 states and 26888 transitions. [2021-08-31 04:18:38,328 INFO L587 BuchiCegarLoop]: Abstraction has 20006 states and 26888 transitions. [2021-08-31 04:18:38,328 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-08-31 04:18:38,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20006 states and 26888 transitions. [2021-08-31 04:18:38,380 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19924 [2021-08-31 04:18:38,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:38,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:38,381 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:38,381 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:38,381 INFO L791 eck$LassoCheckResult]: Stem: 140746#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 140666#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 140609#L645 havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 140610#L289 assume 1 == ~m_i~0;~m_st~0 := 0; 140662#L296-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 140535#L301-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 140536#L306-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 140573#L311-1 assume !(0 == ~M_E~0); 140693#L433-1 assume !(0 == ~T1_E~0); 140670#L438-1 assume !(0 == ~T2_E~0); 140556#L443-1 assume !(0 == ~T3_E~0); 140546#L448-1 assume !(0 == ~E_M~0); 140547#L453-1 assume !(0 == ~E_1~0); 140601#L458-1 assume !(0 == ~E_2~0); 140602#L463-1 assume !(0 == ~E_3~0); 140756#L468-1 havoc activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 140701#L212 assume !(1 == ~m_pc~0); 140604#L212-2 is_master_triggered_~__retres1~0 := 0; 140501#L223 is_master_triggered_#res := is_master_triggered_~__retres1~0; 140502#L224 activate_threads_#t~ret14 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 140716#L535 assume !(0 != activate_threads_~tmp~1); 140587#L535-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 140518#L231 assume !(1 == ~t1_pc~0); 140364#L231-2 is_transmit1_triggered_~__retres1~1 := 0; 140365#L242 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 140710#L243 activate_threads_#t~ret15 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 140469#L543 assume !(0 != activate_threads_~tmp___0~0); 140470#L543-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 140721#L250 assume !(1 == ~t2_pc~0); 140558#L250-2 is_transmit2_triggered_~__retres1~2 := 0; 140559#L261 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 140611#L262 activate_threads_#t~ret16 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 140654#L551 assume !(0 != activate_threads_~tmp___1~0); 140655#L551-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 140495#L269 assume !(1 == ~t3_pc~0); 140496#L269-2 is_transmit3_triggered_~__retres1~3 := 0; 140597#L280 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 140636#L281 activate_threads_#t~ret17 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 140637#L559 assume !(0 != activate_threads_~tmp___2~0); 140543#L559-2 assume !(1 == ~M_E~0); 140544#L481-1 assume !(1 == ~T1_E~0); 140590#L486-1 assume !(1 == ~T2_E~0); 140464#L491-1 assume !(1 == ~T3_E~0); 140465#L496-1 assume !(1 == ~E_M~0); 140684#L501-1 assume !(1 == ~E_1~0); 140697#L506-1 assume !(1 == ~E_2~0); 140503#L511-1 assume !(1 == ~E_3~0); 140504#L682-1 assume !false; 148067#L683 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 147722#L408 [2021-08-31 04:18:38,381 INFO L793 eck$LassoCheckResult]: Loop: 147722#L408 assume !false; 148056#L357 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 148057#L324 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 148132#L346 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 148130#L347 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 146540#L361 assume 0 != eval_~tmp~0; 146534#L361-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 146531#L369 assume !(0 != eval_~tmp_ndt_1~0); 146527#L366 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 146454#L383 assume !(0 != eval_~tmp_ndt_2~0); 146027#L380 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 146024#L397 assume !(0 != eval_~tmp_ndt_3~0); 146025#L394 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 145247#L411 assume !(0 != eval_~tmp_ndt_4~0); 147722#L408 [2021-08-31 04:18:38,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:38,382 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2021-08-31 04:18:38,382 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:38,382 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305810046] [2021-08-31 04:18:38,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:38,382 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:38,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,388 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:38,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,398 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:38,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:38,399 INFO L82 PathProgramCache]: Analyzing trace with hash -2089936199, now seen corresponding path program 1 times [2021-08-31 04:18:38,399 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:38,399 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047472708] [2021-08-31 04:18:38,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:38,399 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:38,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,402 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:38,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,406 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:38,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:38,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1556728475, now seen corresponding path program 1 times [2021-08-31 04:18:38,407 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:38,407 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1322572904] [2021-08-31 04:18:38,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:38,408 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:38,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,417 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:38,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:38,435 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:39,402 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoopBenchmark.prettyprintBenchmarkData(BuchiCegarLoopBenchmark.java:178) at de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData.toString(StatisticsData.java:100) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerTimingBenchmark.toString(BuchiAutomizerTimingBenchmark.java:44) at de.uni_freiburg.informatik.ultimate.core.lib.results.StatisticsResult.getLongDescription(StatisticsResult.java:58) at de.uni_freiburg.informatik.ultimate.core.coreplugin.services.ResultService.reportResult(ResultService.java:86) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.reportResult(BuchiAutomizerObserver.java:375) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:161) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:398) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-08-31 04:18:39,404 INFO L158 Benchmark]: Toolchain (without parser) took 14107.50ms. Allocated memory was 60.8MB in the beginning and 490.7MB in the end (delta: 429.9MB). Free memory was 39.2MB in the beginning and 292.9MB in the end (delta: -253.7MB). Peak memory consumption was 287.9MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,404 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 60.8MB. Free memory was 41.7MB in the beginning and 41.7MB in the end (delta: 25.5kB). There was no memory consumed. Max. memory is 16.1GB. [2021-08-31 04:18:39,404 INFO L158 Benchmark]: CACSL2BoogieTranslator took 295.26ms. Allocated memory is still 60.8MB. Free memory was 39.0MB in the beginning and 39.9MB in the end (delta: -894.5kB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,405 INFO L158 Benchmark]: Boogie Procedure Inliner took 46.49ms. Allocated memory is still 60.8MB. Free memory was 39.9MB in the beginning and 36.2MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,405 INFO L158 Benchmark]: Boogie Preprocessor took 30.77ms. Allocated memory is still 60.8MB. Free memory was 36.2MB in the beginning and 33.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,405 INFO L158 Benchmark]: RCFGBuilder took 298.89ms. Allocated memory is still 60.8MB. Free memory was 33.1MB in the beginning and 25.4MB in the end (delta: 7.7MB). Peak memory consumption was 11.4MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,405 INFO L158 Benchmark]: BuchiAutomizer took 13430.89ms. Allocated memory was 60.8MB in the beginning and 490.7MB in the end (delta: 429.9MB). Free memory was 25.3MB in the beginning and 292.9MB in the end (delta: -267.6MB). Peak memory consumption was 275.6MB. Max. memory is 16.1GB. [2021-08-31 04:18:39,407 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 60.8MB. Free memory was 41.7MB in the beginning and 41.7MB in the end (delta: 25.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 295.26ms. Allocated memory is still 60.8MB. Free memory was 39.0MB in the beginning and 39.9MB in the end (delta: -894.5kB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 46.49ms. Allocated memory is still 60.8MB. Free memory was 39.9MB in the beginning and 36.2MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 30.77ms. Allocated memory is still 60.8MB. Free memory was 36.2MB in the beginning and 33.1MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 298.89ms. Allocated memory is still 60.8MB. Free memory was 33.1MB in the beginning and 25.4MB in the end (delta: 7.7MB). Peak memory consumption was 11.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 13430.89ms. Allocated memory was 60.8MB in the beginning and 490.7MB in the end (delta: 429.9MB). Free memory was 25.3MB in the beginning and 292.9MB in the end (delta: -267.6MB). Peak memory consumption was 275.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 20006 locations. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6): de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoopBenchmark.prettyprintBenchmarkData(BuchiCegarLoopBenchmark.java:178) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-08-31 04:18:39,432 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...