./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5fbdf5bf Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 6752fd2bdc3c2f1062040263247aacca41c7fdba ..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config using search string *Termination*32bit*_Bitvector*.epf No suitable settings file found using Termination*32bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) --- Real Ultimate output --- This is Ultimate 0.2.1-wip.dd.seqcomp-5fbdf5b [2021-08-31 04:18:24,952 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-08-31 04:18:24,954 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-08-31 04:18:24,984 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-08-31 04:18:24,984 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-08-31 04:18:24,986 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-08-31 04:18:24,987 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-08-31 04:18:24,991 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-08-31 04:18:24,993 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-08-31 04:18:24,996 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-08-31 04:18:24,996 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-08-31 04:18:24,999 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-08-31 04:18:24,999 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-08-31 04:18:25,001 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-08-31 04:18:25,005 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-08-31 04:18:25,006 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-08-31 04:18:25,006 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-08-31 04:18:25,007 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-08-31 04:18:25,008 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-08-31 04:18:25,009 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-08-31 04:18:25,009 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-08-31 04:18:25,010 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-08-31 04:18:25,011 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-08-31 04:18:25,011 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-08-31 04:18:25,013 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-08-31 04:18:25,013 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-08-31 04:18:25,013 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-08-31 04:18:25,013 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-08-31 04:18:25,014 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-08-31 04:18:25,014 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-08-31 04:18:25,014 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-08-31 04:18:25,015 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-08-31 04:18:25,015 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-08-31 04:18:25,016 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-08-31 04:18:25,016 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-08-31 04:18:25,016 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-08-31 04:18:25,017 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-08-31 04:18:25,017 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-08-31 04:18:25,017 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-08-31 04:18:25,017 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-08-31 04:18:25,018 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-08-31 04:18:25,021 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-08-31 04:18:25,035 INFO L113 SettingsManager]: Loading preferences was successful [2021-08-31 04:18:25,036 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-08-31 04:18:25,036 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-08-31 04:18:25,036 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-08-31 04:18:25,037 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Use SBE=true [2021-08-31 04:18:25,037 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Use old map elimination=false [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-08-31 04:18:25,037 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-08-31 04:18:25,037 INFO L138 SettingsManager]: * sizeof long=4 [2021-08-31 04:18:25,038 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-08-31 04:18:25,038 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-08-31 04:18:25,038 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-08-31 04:18:25,038 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-08-31 04:18:25,043 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-08-31 04:18:25,043 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-08-31 04:18:25,043 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-08-31 04:18:25,044 INFO L138 SettingsManager]: * sizeof long double=12 [2021-08-31 04:18:25,044 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-08-31 04:18:25,044 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-08-31 04:18:25,044 INFO L138 SettingsManager]: * Use constant arrays=true [2021-08-31 04:18:25,044 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-08-31 04:18:25,044 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-08-31 04:18:25,050 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-08-31 04:18:25,050 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-08-31 04:18:25,050 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-08-31 04:18:25,050 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-08-31 04:18:25,051 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-08-31 04:18:25,052 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 6752fd2bdc3c2f1062040263247aacca41c7fdba [2021-08-31 04:18:25,297 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-08-31 04:18:25,313 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-08-31 04:18:25,315 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-08-31 04:18:25,316 INFO L271 PluginConnector]: Initializing CDTParser... [2021-08-31 04:18:25,317 INFO L275 PluginConnector]: CDTParser initialized [2021-08-31 04:18:25,318 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-08-31 04:18:25,365 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/992eb2414/158bec8ab9ba4a1881164b9606fbc9da/FLAG91a6b2d31 [2021-08-31 04:18:25,708 INFO L306 CDTParser]: Found 1 translation units. [2021-08-31 04:18:25,709 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2021-08-31 04:18:25,715 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/992eb2414/158bec8ab9ba4a1881164b9606fbc9da/FLAG91a6b2d31 [2021-08-31 04:18:26,137 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/992eb2414/158bec8ab9ba4a1881164b9606fbc9da [2021-08-31 04:18:26,138 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-08-31 04:18:26,139 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-08-31 04:18:26,140 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-08-31 04:18:26,140 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-08-31 04:18:26,148 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-08-31 04:18:26,149 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,150 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6af2b6b0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26, skipping insertion in model container [2021-08-31 04:18:26,150 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,154 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-08-31 04:18:26,184 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-08-31 04:18:26,254 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[366,379] [2021-08-31 04:18:26,286 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-31 04:18:26,314 INFO L203 MainTranslator]: Completed pre-run [2021-08-31 04:18:26,327 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[366,379] [2021-08-31 04:18:26,349 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-08-31 04:18:26,359 INFO L208 MainTranslator]: Completed translation [2021-08-31 04:18:26,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26 WrapperNode [2021-08-31 04:18:26,360 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-08-31 04:18:26,361 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-08-31 04:18:26,361 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-08-31 04:18:26,361 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-08-31 04:18:26,365 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,370 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,393 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-08-31 04:18:26,393 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-08-31 04:18:26,393 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-08-31 04:18:26,394 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-08-31 04:18:26,399 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,399 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,401 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,401 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,408 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,415 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,417 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,420 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-08-31 04:18:26,420 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-08-31 04:18:26,421 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-08-31 04:18:26,421 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-08-31 04:18:26,421 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (1/1) ... [2021-08-31 04:18:26,438 INFO L170 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-08-31 04:18:26,445 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2021-08-31 04:18:26,466 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-08-31 04:18:26,500 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-08-31 04:18:26,509 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-08-31 04:18:26,509 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-08-31 04:18:26,509 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-08-31 04:18:26,510 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-08-31 04:18:26,769 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-08-31 04:18:26,779 INFO L299 CfgBuilder]: Removed 130 assume(true) statements. [2021-08-31 04:18:26,782 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.08 04:18:26 BoogieIcfgContainer [2021-08-31 04:18:26,783 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-08-31 04:18:26,783 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-08-31 04:18:26,783 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-08-31 04:18:26,785 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-08-31 04:18:26,786 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:26,786 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 31.08 04:18:26" (1/3) ... [2021-08-31 04:18:26,787 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57a91e22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.08 04:18:26, skipping insertion in model container [2021-08-31 04:18:26,787 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:26,787 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 31.08 04:18:26" (2/3) ... [2021-08-31 04:18:26,787 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@57a91e22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 31.08 04:18:26, skipping insertion in model container [2021-08-31 04:18:26,787 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-08-31 04:18:26,787 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 31.08 04:18:26" (3/3) ... [2021-08-31 04:18:26,788 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2021-08-31 04:18:26,815 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-08-31 04:18:26,816 INFO L360 BuchiCegarLoop]: Hoare is false [2021-08-31 04:18:26,816 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-08-31 04:18:26,816 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-08-31 04:18:26,816 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-08-31 04:18:26,816 INFO L364 BuchiCegarLoop]: Difference is false [2021-08-31 04:18:26,816 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-08-31 04:18:26,816 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-08-31 04:18:26,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 308 states, 307 states have (on average 1.5635179153094463) internal successors, (480), 307 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 253 [2021-08-31 04:18:26,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:26,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:26,862 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,862 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,862 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-08-31 04:18:26,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 308 states, 307 states have (on average 1.5635179153094463) internal successors, (480), 307 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:26,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 253 [2021-08-31 04:18:26,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:26,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:26,873 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,873 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:26,879 INFO L791 eck$LassoCheckResult]: Stem: 298#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 212#L-1true havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 158#L633true havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 162#L277true assume !(1 == ~m_i~0);~m_st~0 := 2; 66#L284-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 3#L289-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 111#L294-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 49#L299-1true assume !(0 == ~M_E~0); 267#L421-1true assume !(0 == ~T1_E~0); 102#L426-1true assume !(0 == ~T2_E~0); 179#L431-1true assume !(0 == ~T3_E~0); 33#L436-1true assume !(0 == ~E_M~0); 157#L441-1true assume 0 == ~E_1~0;~E_1~0 := 1; 248#L446-1true assume !(0 == ~E_2~0); 89#L451-1true assume !(0 == ~E_3~0); 268#L456-1true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 128#L200true assume 1 == ~m_pc~0; 233#L201true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 278#L211true is_master_triggered_#res := is_master_triggered_~__retres1~0; 241#L212true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 249#L523true assume !(0 != activate_threads_~tmp~1); 203#L523-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 309#L219true assume !(1 == ~t1_pc~0); 170#L219-2true is_transmit1_triggered_~__retres1~1 := 0; 245#L230true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 96#L231true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 54#L531true assume !(0 != activate_threads_~tmp___0~0); 135#L531-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 200#L238true assume 1 == ~t2_pc~0; 202#L239true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8#L249true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 264#L250true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 70#L539true assume !(0 != activate_threads_~tmp___1~0); 142#L539-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156#L257true assume 1 == ~t3_pc~0; 205#L258true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 195#L268true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78#L269true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 208#L547true assume !(0 != activate_threads_~tmp___2~0); 224#L547-2true assume 1 == ~M_E~0;~M_E~0 := 2; 63#L469-1true assume !(1 == ~T1_E~0); 184#L474-1true assume !(1 == ~T2_E~0); 83#L479-1true assume !(1 == ~T3_E~0); 125#L484-1true assume !(1 == ~E_M~0); 280#L489-1true assume !(1 == ~E_1~0); 140#L494-1true assume !(1 == ~E_2~0); 59#L499-1true assume !(1 == ~E_3~0); 100#L670-1true [2021-08-31 04:18:26,880 INFO L793 eck$LassoCheckResult]: Loop: 100#L670-1true assume !false; 144#L671true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 115#L396true assume !true; 229#L411true start_simulation_~kernel_st~0 := 2; 234#L277-1true start_simulation_~kernel_st~0 := 3; 113#L421-2true assume 0 == ~M_E~0;~M_E~0 := 1; 263#L421-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 291#L426-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 181#L431-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 296#L436-3true assume !(0 == ~E_M~0); 192#L441-3true assume 0 == ~E_1~0;~E_1~0 := 1; 250#L446-3true assume 0 == ~E_2~0;~E_2~0 := 1; 188#L451-3true assume 0 == ~E_3~0;~E_3~0 := 1; 32#L456-3true havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 82#L200-15true assume 1 == ~m_pc~0; 41#L201-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 310#L211-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 141#L212-5true activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 64#L523-15true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 300#L523-17true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 65#L219-15true assume 1 == ~t1_pc~0; 61#L220-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 232#L230-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 204#L231-5true activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 163#L531-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 75#L531-17true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 152#L238-15true assume 1 == ~t2_pc~0; 19#L239-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 185#L249-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 273#L250-5true activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 206#L539-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 193#L539-17true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29#L257-15true assume !(1 == ~t3_pc~0); 132#L257-17true is_transmit3_triggered_~__retres1~3 := 0; 231#L268-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 271#L269-5true activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 295#L547-15true assume !(0 != activate_threads_~tmp___2~0); 62#L547-17true assume 1 == ~M_E~0;~M_E~0 := 2; 189#L469-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 124#L474-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 123#L479-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 222#L484-3true assume 1 == ~E_M~0;~E_M~0 := 2; 24#L489-3true assume 1 == ~E_1~0;~E_1~0 := 2; 214#L494-3true assume 1 == ~E_2~0;~E_2~0 := 2; 290#L499-3true assume !(1 == ~E_3~0); 99#L504-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 45#L312-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 210#L334-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 134#L335-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 255#L689true assume !(0 == start_simulation_~tmp~3); 260#L689-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 95#L312-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 227#L334-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44#L335-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 283#L644true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 294#L651true stop_simulation_#res := stop_simulation_~__retres2~0; 308#L652true start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 198#L702true assume !(0 != start_simulation_~tmp___0~1); 100#L670-1true [2021-08-31 04:18:26,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:26,884 INFO L82 PathProgramCache]: Analyzing trace with hash 455904860, now seen corresponding path program 1 times [2021-08-31 04:18:26,889 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:26,889 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793957091] [2021-08-31 04:18:26,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:26,890 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:26,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,077 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,078 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793957091] [2021-08-31 04:18:27,079 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793957091] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,079 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,079 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705752305] [2021-08-31 04:18:27,093 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:27,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,094 INFO L82 PathProgramCache]: Analyzing trace with hash 1747710192, now seen corresponding path program 1 times [2021-08-31 04:18:27,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,095 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790426842] [2021-08-31 04:18:27,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,095 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,124 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1790426842] [2021-08-31 04:18:27,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1790426842] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,125 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:27,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568890872] [2021-08-31 04:18:27,132 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:27,133 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:27,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:27,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:27,158 INFO L87 Difference]: Start difference. First operand has 308 states, 307 states have (on average 1.5635179153094463) internal successors, (480), 307 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:27,712 INFO L93 Difference]: Finished difference Result 308 states and 466 transitions. [2021-08-31 04:18:27,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:27,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 466 transitions. [2021-08-31 04:18:27,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:27,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 303 states and 461 transitions. [2021-08-31 04:18:27,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2021-08-31 04:18:27,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2021-08-31 04:18:27,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 461 transitions. [2021-08-31 04:18:27,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:27,728 INFO L681 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2021-08-31 04:18:27,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 461 transitions. [2021-08-31 04:18:27,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2021-08-31 04:18:27,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.5214521452145215) internal successors, (461), 302 states have internal predecessors, (461), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:27,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 461 transitions. [2021-08-31 04:18:27,754 INFO L704 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2021-08-31 04:18:27,754 INFO L587 BuchiCegarLoop]: Abstraction has 303 states and 461 transitions. [2021-08-31 04:18:27,754 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-08-31 04:18:27,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 461 transitions. [2021-08-31 04:18:27,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:27,756 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:27,756 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:27,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,757 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:27,758 INFO L791 eck$LassoCheckResult]: Stem: 926#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 900#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 861#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 862#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 749#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 625#L289-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 626#L294-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 719#L299-1 assume !(0 == ~M_E~0); 720#L421-1 assume !(0 == ~T1_E~0); 804#L426-1 assume !(0 == ~T2_E~0); 805#L431-1 assume !(0 == ~T3_E~0); 686#L436-1 assume !(0 == ~E_M~0); 687#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 860#L446-1 assume !(0 == ~E_2~0); 789#L451-1 assume !(0 == ~E_3~0); 790#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 837#L200 assume 1 == ~m_pc~0; 838#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 910#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 912#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 913#L523 assume !(0 != activate_threads_~tmp~1); 894#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 895#L219 assume !(1 == ~t1_pc~0); 779#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 778#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 798#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 728#L531 assume !(0 != activate_threads_~tmp___0~0); 729#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 847#L238 assume 1 == ~t2_pc~0; 892#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 635#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 636#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 758#L539 assume !(0 != activate_threads_~tmp___1~0); 759#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 853#L257 assume 1 == ~t3_pc~0; 859#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 734#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 773#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 774#L547 assume !(0 != activate_threads_~tmp___2~0); 898#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 744#L469-1 assume !(1 == ~T1_E~0); 745#L474-1 assume !(1 == ~T2_E~0); 782#L479-1 assume !(1 == ~T3_E~0); 783#L484-1 assume !(1 == ~E_M~0); 835#L489-1 assume !(1 == ~E_1~0); 850#L494-1 assume !(1 == ~E_2~0); 735#L499-1 assume !(1 == ~E_3~0); 736#L670-1 [2021-08-31 04:18:27,758 INFO L793 eck$LassoCheckResult]: Loop: 736#L670-1 assume !false; 803#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 785#L396 assume !false; 823#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 855#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 663#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 682#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 683#L349 assume !(0 != eval_~tmp~0); 812#L411 start_simulation_~kernel_st~0 := 2; 907#L277-1 start_simulation_~kernel_st~0 := 3; 820#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 821#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 919#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 878#L436-3 assume !(0 == ~E_M~0); 888#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 889#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 886#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 684#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 685#L200-15 assume 1 == ~m_pc~0; 706#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 707#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 851#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 746#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 747#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 748#L219-15 assume 1 == ~t1_pc~0; 739#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 740#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 896#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 865#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 770#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 771#L238-15 assume !(1 == ~t2_pc~0); 657#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 656#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 880#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 897#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 890#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 677#L257-15 assume !(1 == ~t3_pc~0); 678#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 841#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 909#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 922#L547-15 assume !(0 != activate_threads_~tmp___2~0); 742#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 743#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 833#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 831#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 832#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 664#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 665#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 902#L499-3 assume !(1 == ~E_3~0); 797#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 713#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 693#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 843#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 844#L689 assume !(0 == start_simulation_~tmp~3); 681#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 793#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 794#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 711#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 712#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 924#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 925#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 891#L702 assume !(0 != start_simulation_~tmp___0~1); 736#L670-1 [2021-08-31 04:18:27,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1789674594, now seen corresponding path program 1 times [2021-08-31 04:18:27,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,759 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345258119] [2021-08-31 04:18:27,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,759 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,793 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,793 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345258119] [2021-08-31 04:18:27,793 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345258119] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,794 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,794 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443602567] [2021-08-31 04:18:27,794 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:27,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:27,794 INFO L82 PathProgramCache]: Analyzing trace with hash 1520047774, now seen corresponding path program 1 times [2021-08-31 04:18:27,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:27,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800459578] [2021-08-31 04:18:27,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:27,795 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:27,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:27,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:27,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:27,829 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800459578] [2021-08-31 04:18:27,829 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800459578] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:27,829 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:27,829 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:27,829 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988071032] [2021-08-31 04:18:27,829 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:27,829 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:27,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:27,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:27,830 INFO L87 Difference]: Start difference. First operand 303 states and 461 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:28,192 INFO L93 Difference]: Finished difference Result 303 states and 460 transitions. [2021-08-31 04:18:28,193 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:28,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 460 transitions. [2021-08-31 04:18:28,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:28,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 460 transitions. [2021-08-31 04:18:28,200 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2021-08-31 04:18:28,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2021-08-31 04:18:28,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 460 transitions. [2021-08-31 04:18:28,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:28,205 INFO L681 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2021-08-31 04:18:28,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 460 transitions. [2021-08-31 04:18:28,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2021-08-31 04:18:28,215 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.518151815181518) internal successors, (460), 302 states have internal predecessors, (460), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 460 transitions. [2021-08-31 04:18:28,216 INFO L704 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2021-08-31 04:18:28,216 INFO L587 BuchiCegarLoop]: Abstraction has 303 states and 460 transitions. [2021-08-31 04:18:28,216 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-08-31 04:18:28,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 460 transitions. [2021-08-31 04:18:28,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:28,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:28,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:28,218 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,219 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,219 INFO L791 eck$LassoCheckResult]: Stem: 1539#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1513#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1474#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1475#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 1362#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1238#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1239#L294-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1332#L299-1 assume !(0 == ~M_E~0); 1333#L421-1 assume !(0 == ~T1_E~0); 1417#L426-1 assume !(0 == ~T2_E~0); 1418#L431-1 assume !(0 == ~T3_E~0); 1301#L436-1 assume !(0 == ~E_M~0); 1302#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1473#L446-1 assume !(0 == ~E_2~0); 1402#L451-1 assume !(0 == ~E_3~0); 1403#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1450#L200 assume 1 == ~m_pc~0; 1451#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1523#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1527#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1528#L523 assume !(0 != activate_threads_~tmp~1); 1507#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1508#L219 assume !(1 == ~t1_pc~0); 1392#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 1391#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1415#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1341#L531 assume !(0 != activate_threads_~tmp___0~0); 1342#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1460#L238 assume 1 == ~t2_pc~0; 1505#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1248#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1249#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1371#L539 assume !(0 != activate_threads_~tmp___1~0); 1372#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1466#L257 assume 1 == ~t3_pc~0; 1472#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1347#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1386#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1387#L547 assume !(0 != activate_threads_~tmp___2~0); 1511#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1359#L469-1 assume !(1 == ~T1_E~0); 1360#L474-1 assume !(1 == ~T2_E~0); 1395#L479-1 assume !(1 == ~T3_E~0); 1396#L484-1 assume !(1 == ~E_M~0); 1449#L489-1 assume !(1 == ~E_1~0); 1463#L494-1 assume !(1 == ~E_2~0); 1348#L499-1 assume !(1 == ~E_3~0); 1349#L670-1 [2021-08-31 04:18:28,219 INFO L793 eck$LassoCheckResult]: Loop: 1349#L670-1 assume !false; 1416#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1398#L396 assume !false; 1436#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1468#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1276#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1295#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1296#L349 assume !(0 != eval_~tmp~0); 1429#L411 start_simulation_~kernel_st~0 := 2; 1520#L277-1 start_simulation_~kernel_st~0 := 3; 1433#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1434#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1532#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1490#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1491#L436-3 assume !(0 == ~E_M~0); 1501#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1502#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1499#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1297#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1298#L200-15 assume 1 == ~m_pc~0; 1317#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1318#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1464#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1357#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1358#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1361#L219-15 assume 1 == ~t1_pc~0; 1352#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1353#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1509#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1478#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1380#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1381#L238-15 assume 1 == ~t2_pc~0; 1268#L239-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1269#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1493#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1510#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1503#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1290#L257-15 assume !(1 == ~t3_pc~0); 1291#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 1455#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1522#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1535#L547-15 assume !(0 != activate_threads_~tmp___2~0); 1355#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1356#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1446#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1444#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1445#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1277#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1278#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1515#L499-3 assume !(1 == ~E_3~0); 1414#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1326#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1306#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1456#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 1457#L689 assume !(0 == start_simulation_~tmp~3); 1294#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1407#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1408#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1324#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1325#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1537#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 1538#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1504#L702 assume !(0 != start_simulation_~tmp___0~1); 1349#L670-1 [2021-08-31 04:18:28,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,219 INFO L82 PathProgramCache]: Analyzing trace with hash -2037821088, now seen corresponding path program 1 times [2021-08-31 04:18:28,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,220 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892626222] [2021-08-31 04:18:28,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,220 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,249 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,249 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892626222] [2021-08-31 04:18:28,249 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892626222] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,249 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,250 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:28,250 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967689364] [2021-08-31 04:18:28,250 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:28,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,250 INFO L82 PathProgramCache]: Analyzing trace with hash 601073151, now seen corresponding path program 1 times [2021-08-31 04:18:28,250 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,250 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056470692] [2021-08-31 04:18:28,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,251 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,296 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,296 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056470692] [2021-08-31 04:18:28,296 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056470692] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,297 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,297 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:28,297 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1510592761] [2021-08-31 04:18:28,298 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:28,298 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:28,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:28,299 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:28,299 INFO L87 Difference]: Start difference. First operand 303 states and 460 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:28,614 INFO L93 Difference]: Finished difference Result 303 states and 459 transitions. [2021-08-31 04:18:28,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:28,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 303 states and 459 transitions. [2021-08-31 04:18:28,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:28,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 303 states to 303 states and 459 transitions. [2021-08-31 04:18:28,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2021-08-31 04:18:28,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2021-08-31 04:18:28,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 303 states and 459 transitions. [2021-08-31 04:18:28,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:28,619 INFO L681 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2021-08-31 04:18:28,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states and 459 transitions. [2021-08-31 04:18:28,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 303. [2021-08-31 04:18:28,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 303 states, 303 states have (on average 1.5148514851485149) internal successors, (459), 302 states have internal predecessors, (459), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:28,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 303 states to 303 states and 459 transitions. [2021-08-31 04:18:28,625 INFO L704 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2021-08-31 04:18:28,625 INFO L587 BuchiCegarLoop]: Abstraction has 303 states and 459 transitions. [2021-08-31 04:18:28,625 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-08-31 04:18:28,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 303 states and 459 transitions. [2021-08-31 04:18:28,626 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 252 [2021-08-31 04:18:28,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:28,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:28,628 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,628 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:28,628 INFO L791 eck$LassoCheckResult]: Stem: 2152#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2126#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2087#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2088#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 1975#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1851#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1852#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1945#L299-1 assume !(0 == ~M_E~0); 1946#L421-1 assume !(0 == ~T1_E~0); 2030#L426-1 assume !(0 == ~T2_E~0); 2031#L431-1 assume !(0 == ~T3_E~0); 1912#L436-1 assume !(0 == ~E_M~0); 1913#L441-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2086#L446-1 assume !(0 == ~E_2~0); 2015#L451-1 assume !(0 == ~E_3~0); 2016#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2063#L200 assume 1 == ~m_pc~0; 2064#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2136#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2138#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2139#L523 assume !(0 != activate_threads_~tmp~1); 2120#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2121#L219 assume !(1 == ~t1_pc~0); 2003#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 2002#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2023#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1954#L531 assume !(0 != activate_threads_~tmp___0~0); 1955#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2073#L238 assume 1 == ~t2_pc~0; 2118#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1861#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1862#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1984#L539 assume !(0 != activate_threads_~tmp___1~0); 1985#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2078#L257 assume 1 == ~t3_pc~0; 2085#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1960#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1999#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2000#L547 assume !(0 != activate_threads_~tmp___2~0); 2124#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 1970#L469-1 assume !(1 == ~T1_E~0); 1971#L474-1 assume !(1 == ~T2_E~0); 2008#L479-1 assume !(1 == ~T3_E~0); 2009#L484-1 assume !(1 == ~E_M~0); 2060#L489-1 assume !(1 == ~E_1~0); 2076#L494-1 assume !(1 == ~E_2~0); 1961#L499-1 assume !(1 == ~E_3~0); 1962#L670-1 [2021-08-31 04:18:28,628 INFO L793 eck$LassoCheckResult]: Loop: 1962#L670-1 assume !false; 2029#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2011#L396 assume !false; 2049#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2081#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1889#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1906#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1907#L349 assume !(0 != eval_~tmp~0); 2038#L411 start_simulation_~kernel_st~0 := 2; 2133#L277-1 start_simulation_~kernel_st~0 := 3; 2046#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2047#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2145#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2103#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2104#L436-3 assume !(0 == ~E_M~0); 2114#L441-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2115#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2112#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1910#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1911#L200-15 assume 1 == ~m_pc~0; 1930#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1931#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2077#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1972#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1973#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1974#L219-15 assume 1 == ~t1_pc~0; 1965#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1966#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2122#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2091#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1993#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1994#L238-15 assume 1 == ~t2_pc~0; 1881#L239-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1882#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2106#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2123#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2116#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1903#L257-15 assume !(1 == ~t3_pc~0); 1904#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 2068#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2135#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2148#L547-15 assume !(0 != activate_threads_~tmp___2~0); 1968#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 1969#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2059#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2057#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2058#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1892#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1893#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2128#L499-3 assume !(1 == ~E_3~0); 2028#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1939#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1919#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2071#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2072#L689 assume !(0 == start_simulation_~tmp~3); 1909#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2020#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2021#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1937#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 1938#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2150#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 2151#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2117#L702 assume !(0 != start_simulation_~tmp___0~1); 1962#L670-1 [2021-08-31 04:18:28,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,629 INFO L82 PathProgramCache]: Analyzing trace with hash 1833499486, now seen corresponding path program 1 times [2021-08-31 04:18:28,629 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,629 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749324690] [2021-08-31 04:18:28,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,629 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,662 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,662 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749324690] [2021-08-31 04:18:28,662 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749324690] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,662 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,662 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:28,663 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348896947] [2021-08-31 04:18:28,663 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:28,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:28,663 INFO L82 PathProgramCache]: Analyzing trace with hash 601073151, now seen corresponding path program 2 times [2021-08-31 04:18:28,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:28,663 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442499665] [2021-08-31 04:18:28,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:28,664 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:28,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:28,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:28,729 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:28,729 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442499665] [2021-08-31 04:18:28,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442499665] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:28,729 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:28,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:28,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952205955] [2021-08-31 04:18:28,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:28,730 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:28,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:28,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:28,730 INFO L87 Difference]: Start difference. First operand 303 states and 459 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:29,350 INFO L93 Difference]: Finished difference Result 502 states and 759 transitions. [2021-08-31 04:18:29,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:29,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 502 states and 759 transitions. [2021-08-31 04:18:29,353 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 442 [2021-08-31 04:18:29,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 502 states to 502 states and 759 transitions. [2021-08-31 04:18:29,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 502 [2021-08-31 04:18:29,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 502 [2021-08-31 04:18:29,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 502 states and 759 transitions. [2021-08-31 04:18:29,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:29,356 INFO L681 BuchiCegarLoop]: Abstraction has 502 states and 759 transitions. [2021-08-31 04:18:29,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states and 759 transitions. [2021-08-31 04:18:29,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 496. [2021-08-31 04:18:29,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 496 states have (on average 1.5141129032258065) internal successors, (751), 495 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 751 transitions. [2021-08-31 04:18:29,369 INFO L704 BuchiCegarLoop]: Abstraction has 496 states and 751 transitions. [2021-08-31 04:18:29,370 INFO L587 BuchiCegarLoop]: Abstraction has 496 states and 751 transitions. [2021-08-31 04:18:29,370 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-08-31 04:18:29,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 751 transitions. [2021-08-31 04:18:29,371 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 442 [2021-08-31 04:18:29,372 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:29,372 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:29,372 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,373 INFO L791 eck$LassoCheckResult]: Stem: 2996#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2956#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2910#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2911#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 2791#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2666#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2667#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2761#L299-1 assume !(0 == ~M_E~0); 2762#L421-1 assume !(0 == ~T1_E~0); 2847#L426-1 assume !(0 == ~T2_E~0); 2848#L431-1 assume !(0 == ~T3_E~0); 2728#L436-1 assume !(0 == ~E_M~0); 2729#L441-1 assume !(0 == ~E_1~0); 2909#L446-1 assume !(0 == ~E_2~0); 2831#L451-1 assume !(0 == ~E_3~0); 2832#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2884#L200 assume 1 == ~m_pc~0; 2885#L201 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2966#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2968#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2969#L523 assume !(0 != activate_threads_~tmp~1); 2946#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2947#L219 assume !(1 == ~t1_pc~0); 2819#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 2818#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2839#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2770#L531 assume !(0 != activate_threads_~tmp___0~0); 2771#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2894#L238 assume 1 == ~t2_pc~0; 2944#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2676#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2677#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2800#L539 assume !(0 != activate_threads_~tmp___1~0); 2801#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2899#L257 assume 1 == ~t3_pc~0; 2908#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2776#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2815#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2816#L547 assume !(0 != activate_threads_~tmp___2~0); 2952#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 2786#L469-1 assume !(1 == ~T1_E~0); 2787#L474-1 assume !(1 == ~T2_E~0); 2824#L479-1 assume !(1 == ~T3_E~0); 2825#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 2880#L489-1 assume !(1 == ~E_1~0); 2897#L494-1 assume !(1 == ~E_2~0); 2777#L499-1 assume !(1 == ~E_3~0); 2778#L670-1 [2021-08-31 04:18:29,373 INFO L793 eck$LassoCheckResult]: Loop: 2778#L670-1 assume !false; 3019#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3017#L396 assume !false; 3016#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3014#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3011#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3010#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3008#L349 assume !(0 != eval_~tmp~0); 3007#L411 start_simulation_~kernel_st~0 := 2; 3006#L277-1 start_simulation_~kernel_st~0 := 3; 3005#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3004#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3003#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3002#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3001#L436-3 assume !(0 == ~E_M~0); 2939#L441-3 assume !(0 == ~E_1~0); 2940#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2937#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2726#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2727#L200-15 assume 1 == ~m_pc~0; 2746#L201-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2747#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2898#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2788#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2789#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2790#L219-15 assume 1 == ~t1_pc~0; 2781#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2782#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2948#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2914#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2809#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2810#L238-15 assume 1 == ~t2_pc~0; 2696#L239-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2697#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2931#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2985#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2941#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2719#L257-15 assume !(1 == ~t3_pc~0); 2720#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 2889#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2965#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2984#L547-15 assume !(0 != activate_threads_~tmp___2~0); 2784#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 2785#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2879#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2877#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2878#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2708#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2709#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2958#L499-3 assume !(1 == ~E_3~0); 2989#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3109#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2954#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2955#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2976#L689 assume !(0 == start_simulation_~tmp~3); 2725#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3095#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3093#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3092#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 3091#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2991#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 2992#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 2943#L702 assume !(0 != start_simulation_~tmp___0~1); 2778#L670-1 [2021-08-31 04:18:29,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,374 INFO L82 PathProgramCache]: Analyzing trace with hash 989434402, now seen corresponding path program 1 times [2021-08-31 04:18:29,374 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,374 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440481282] [2021-08-31 04:18:29,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,374 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,393 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,393 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,393 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440481282] [2021-08-31 04:18:29,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440481282] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,393 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,393 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:29,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610181364] [2021-08-31 04:18:29,394 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:29,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,394 INFO L82 PathProgramCache]: Analyzing trace with hash -1754732099, now seen corresponding path program 1 times [2021-08-31 04:18:29,394 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,395 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999790556] [2021-08-31 04:18:29,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,395 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,427 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,427 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [999790556] [2021-08-31 04:18:29,427 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [999790556] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,427 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,427 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:29,428 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [30265165] [2021-08-31 04:18:29,428 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:29,428 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:29,428 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:29,428 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:29,428 INFO L87 Difference]: Start difference. First operand 496 states and 751 transitions. cyclomatic complexity: 257 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:29,923 INFO L93 Difference]: Finished difference Result 735 states and 1092 transitions. [2021-08-31 04:18:29,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:29,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 735 states and 1092 transitions. [2021-08-31 04:18:29,928 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 681 [2021-08-31 04:18:29,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 735 states to 735 states and 1092 transitions. [2021-08-31 04:18:29,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 735 [2021-08-31 04:18:29,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 735 [2021-08-31 04:18:29,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 735 states and 1092 transitions. [2021-08-31 04:18:29,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:29,932 INFO L681 BuchiCegarLoop]: Abstraction has 735 states and 1092 transitions. [2021-08-31 04:18:29,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 735 states and 1092 transitions. [2021-08-31 04:18:29,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 735 to 709. [2021-08-31 04:18:29,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 709 states, 709 states have (on average 1.4894217207334273) internal successors, (1056), 708 states have internal predecessors, (1056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:29,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 709 states to 709 states and 1056 transitions. [2021-08-31 04:18:29,940 INFO L704 BuchiCegarLoop]: Abstraction has 709 states and 1056 transitions. [2021-08-31 04:18:29,940 INFO L587 BuchiCegarLoop]: Abstraction has 709 states and 1056 transitions. [2021-08-31 04:18:29,940 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-08-31 04:18:29,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 709 states and 1056 transitions. [2021-08-31 04:18:29,942 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 655 [2021-08-31 04:18:29,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:29,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:29,943 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,943 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:29,944 INFO L791 eck$LassoCheckResult]: Stem: 4251#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4207#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4158#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4159#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 4031#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3904#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3905#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4000#L299-1 assume !(0 == ~M_E~0); 4001#L421-1 assume !(0 == ~T1_E~0); 4091#L426-1 assume !(0 == ~T2_E~0); 4092#L431-1 assume !(0 == ~T3_E~0); 3966#L436-1 assume !(0 == ~E_M~0); 3967#L441-1 assume !(0 == ~E_1~0); 4157#L446-1 assume !(0 == ~E_2~0); 4072#L451-1 assume !(0 == ~E_3~0); 4073#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4128#L200 assume !(1 == ~m_pc~0); 4129#L200-2 is_master_triggered_~__retres1~0 := 0; 4236#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4229#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4230#L523 assume !(0 != activate_threads_~tmp~1); 4197#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4198#L219 assume !(1 == ~t1_pc~0); 4059#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 4058#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4083#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4009#L531 assume !(0 != activate_threads_~tmp___0~0); 4010#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4139#L238 assume 1 == ~t2_pc~0; 4195#L239 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3914#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3915#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4040#L539 assume !(0 != activate_threads_~tmp___1~0); 4041#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4149#L257 assume 1 == ~t3_pc~0; 4156#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4015#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4055#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4056#L547 assume !(0 != activate_threads_~tmp___2~0); 4202#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 4026#L469-1 assume !(1 == ~T1_E~0); 4027#L474-1 assume !(1 == ~T2_E~0); 4065#L479-1 assume !(1 == ~T3_E~0); 4066#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 4124#L489-1 assume !(1 == ~E_1~0); 4146#L494-1 assume !(1 == ~E_2~0); 4017#L499-1 assume !(1 == ~E_3~0); 4018#L670-1 [2021-08-31 04:18:29,944 INFO L793 eck$LassoCheckResult]: Loop: 4018#L670-1 assume !false; 4461#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 4460#L396 assume !false; 4459#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4457#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4454#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4453#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 4099#L349 assume !(0 != eval_~tmp~0); 4100#L411 start_simulation_~kernel_st~0 := 2; 4223#L277-1 start_simulation_~kernel_st~0 := 3; 4224#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4451#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4450#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4449#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4448#L436-3 assume !(0 == ~E_M~0); 4190#L441-3 assume !(0 == ~E_1~0); 4191#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4583#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4581#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4579#L200-15 assume !(1 == ~m_pc~0); 4212#L200-17 is_master_triggered_~__retres1~0 := 0; 4213#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4576#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4028#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4029#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4030#L219-15 assume 1 == ~t1_pc~0; 4021#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4022#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4199#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4163#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4049#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4050#L238-15 assume !(1 == ~t2_pc~0); 3936#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 3935#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4182#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4200#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4192#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3957#L257-15 assume !(1 == ~t3_pc~0); 3958#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 4134#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4222#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4242#L547-15 assume !(0 != activate_threads_~tmp___2~0); 4024#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 4025#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4123#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4121#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4122#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3946#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3947#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4209#L499-3 assume !(1 == ~E_3~0); 4247#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4501#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4204#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4137#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 4138#L689 assume !(0 == start_simulation_~tmp~3); 3963#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 4080#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 4081#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 4483#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 4481#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4478#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 4475#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4193#L702 assume !(0 != start_simulation_~tmp___0~1); 4018#L670-1 [2021-08-31 04:18:29,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,944 INFO L82 PathProgramCache]: Analyzing trace with hash -782036573, now seen corresponding path program 1 times [2021-08-31 04:18:29,944 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,944 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878793240] [2021-08-31 04:18:29,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,944 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,964 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,964 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878793240] [2021-08-31 04:18:29,964 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878793240] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,964 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,964 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:29,964 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561756507] [2021-08-31 04:18:29,964 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:29,965 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:29,965 INFO L82 PathProgramCache]: Analyzing trace with hash -2110860165, now seen corresponding path program 1 times [2021-08-31 04:18:29,965 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:29,965 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270316945] [2021-08-31 04:18:29,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:29,965 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:29,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:29,981 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:29,981 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:29,981 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270316945] [2021-08-31 04:18:29,981 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270316945] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:29,981 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:29,981 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:29,981 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430036205] [2021-08-31 04:18:29,981 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:29,982 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:29,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:29,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:29,982 INFO L87 Difference]: Start difference. First operand 709 states and 1056 transitions. cyclomatic complexity: 350 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:30,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:30,758 INFO L93 Difference]: Finished difference Result 1669 states and 2451 transitions. [2021-08-31 04:18:30,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:30,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1669 states and 2451 transitions. [2021-08-31 04:18:30,766 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 1578 [2021-08-31 04:18:30,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1669 states to 1669 states and 2451 transitions. [2021-08-31 04:18:30,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1669 [2021-08-31 04:18:30,773 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1669 [2021-08-31 04:18:30,773 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1669 states and 2451 transitions. [2021-08-31 04:18:30,775 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:30,775 INFO L681 BuchiCegarLoop]: Abstraction has 1669 states and 2451 transitions. [2021-08-31 04:18:30,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1669 states and 2451 transitions. [2021-08-31 04:18:30,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1669 to 1261. [2021-08-31 04:18:30,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1261 states, 1261 states have (on average 1.4797779540047582) internal successors, (1866), 1260 states have internal predecessors, (1866), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:30,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1261 states to 1261 states and 1866 transitions. [2021-08-31 04:18:30,797 INFO L704 BuchiCegarLoop]: Abstraction has 1261 states and 1866 transitions. [2021-08-31 04:18:30,797 INFO L587 BuchiCegarLoop]: Abstraction has 1261 states and 1866 transitions. [2021-08-31 04:18:30,797 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-08-31 04:18:30,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1261 states and 1866 transitions. [2021-08-31 04:18:30,801 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1207 [2021-08-31 04:18:30,801 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:30,801 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:30,801 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,802 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:30,802 INFO L791 eck$LassoCheckResult]: Stem: 6633#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 6594#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6544#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6545#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 6419#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6292#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6293#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6390#L299-1 assume !(0 == ~M_E~0); 6391#L421-1 assume !(0 == ~T1_E~0); 6477#L426-1 assume !(0 == ~T2_E~0); 6478#L431-1 assume !(0 == ~T3_E~0); 6354#L436-1 assume !(0 == ~E_M~0); 6355#L441-1 assume !(0 == ~E_1~0); 6543#L446-1 assume !(0 == ~E_2~0); 6460#L451-1 assume !(0 == ~E_3~0); 6461#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6512#L200 assume !(1 == ~m_pc~0); 6513#L200-2 is_master_triggered_~__retres1~0 := 0; 6620#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6614#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6615#L523 assume !(0 != activate_threads_~tmp~1); 6585#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6586#L219 assume !(1 == ~t1_pc~0); 6446#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 6445#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6469#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6399#L531 assume !(0 != activate_threads_~tmp___0~0); 6400#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6521#L238 assume !(1 == ~t2_pc~0); 6584#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 6302#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6303#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6427#L539 assume !(0 != activate_threads_~tmp___1~0); 6428#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6533#L257 assume 1 == ~t3_pc~0; 6542#L258 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6405#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6442#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6443#L547 assume !(0 != activate_threads_~tmp___2~0); 6589#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 6414#L469-1 assume !(1 == ~T1_E~0); 6415#L474-1 assume !(1 == ~T2_E~0); 6453#L479-1 assume !(1 == ~T3_E~0); 6454#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 6507#L489-1 assume !(1 == ~E_1~0); 6530#L494-1 assume !(1 == ~E_2~0); 6531#L499-1 assume !(1 == ~E_3~0); 7446#L670-1 [2021-08-31 04:18:30,802 INFO L793 eck$LassoCheckResult]: Loop: 7446#L670-1 assume !false; 7442#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 7434#L396 assume !false; 7430#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7426#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7421#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7418#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7413#L349 assume !(0 != eval_~tmp~0); 6608#L411 start_simulation_~kernel_st~0 := 2; 6609#L277-1 start_simulation_~kernel_st~0 := 3; 6493#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6494#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6622#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6565#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6566#L436-3 assume !(0 == ~E_M~0); 6580#L441-3 assume !(0 == ~E_1~0); 6581#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6576#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6352#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6353#L200-15 assume !(1 == ~m_pc~0); 6452#L200-17 is_master_triggered_~__retres1~0 := 0; 6602#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7540#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7539#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7538#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7537#L219-15 assume !(1 == ~t1_pc~0); 7536#L219-17 is_transmit1_triggered_~__retres1~1 := 0; 7534#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7533#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7532#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7531#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7530#L238-15 assume !(1 == ~t2_pc~0); 7338#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 7527#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7525#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7523#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7521#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7519#L257-15 assume 1 == ~t3_pc~0; 7516#L258-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7513#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7511#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7509#L547-15 assume !(0 != activate_threads_~tmp___2~0); 7507#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 7505#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7503#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7502#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7500#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6604#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6334#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7496#L499-3 assume !(1 == ~E_3~0); 7494#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7489#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7485#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7483#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 7470#L689 assume !(0 == start_simulation_~tmp~3); 7469#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 7465#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 7462#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 7459#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 7457#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7455#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 7453#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7451#L702 assume !(0 != start_simulation_~tmp___0~1); 7446#L670-1 [2021-08-31 04:18:30,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,803 INFO L82 PathProgramCache]: Analyzing trace with hash 209128100, now seen corresponding path program 1 times [2021-08-31 04:18:30,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665586077] [2021-08-31 04:18:30,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,803 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,842 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,843 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665586077] [2021-08-31 04:18:30,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665586077] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:30,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287577851] [2021-08-31 04:18:30,844 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:30,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:30,844 INFO L82 PathProgramCache]: Analyzing trace with hash 2068643323, now seen corresponding path program 1 times [2021-08-31 04:18:30,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:30,845 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627092486] [2021-08-31 04:18:30,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:30,845 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:30,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:30,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:30,867 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:30,867 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627092486] [2021-08-31 04:18:30,867 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627092486] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:30,867 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:30,867 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:30,867 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1789737048] [2021-08-31 04:18:30,868 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:30,868 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:30,868 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-08-31 04:18:30,868 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-08-31 04:18:30,869 INFO L87 Difference]: Start difference. First operand 1261 states and 1866 transitions. cyclomatic complexity: 608 Second operand has 4 states, 4 states have (on average 11.75) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:31,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:31,629 INFO L93 Difference]: Finished difference Result 3071 states and 4479 transitions. [2021-08-31 04:18:31,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-08-31 04:18:31,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3071 states and 4479 transitions. [2021-08-31 04:18:31,642 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 2943 [2021-08-31 04:18:31,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3071 states to 3071 states and 4479 transitions. [2021-08-31 04:18:31,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3071 [2021-08-31 04:18:31,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3071 [2021-08-31 04:18:31,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3071 states and 4479 transitions. [2021-08-31 04:18:31,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:31,664 INFO L681 BuchiCegarLoop]: Abstraction has 3071 states and 4479 transitions. [2021-08-31 04:18:31,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3071 states and 4479 transitions. [2021-08-31 04:18:31,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3071 to 2322. [2021-08-31 04:18:31,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2322 states, 2322 states have (on average 1.4694229112833763) internal successors, (3412), 2321 states have internal predecessors, (3412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:31,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2322 states to 2322 states and 3412 transitions. [2021-08-31 04:18:31,695 INFO L704 BuchiCegarLoop]: Abstraction has 2322 states and 3412 transitions. [2021-08-31 04:18:31,695 INFO L587 BuchiCegarLoop]: Abstraction has 2322 states and 3412 transitions. [2021-08-31 04:18:31,695 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-08-31 04:18:31,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2322 states and 3412 transitions. [2021-08-31 04:18:31,702 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2267 [2021-08-31 04:18:31,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:31,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:31,703 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:31,704 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:31,704 INFO L791 eck$LassoCheckResult]: Stem: 11009#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 10950#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 10897#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10898#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 10759#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10634#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10635#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10729#L299-1 assume !(0 == ~M_E~0); 10730#L421-1 assume !(0 == ~T1_E~0); 10824#L426-1 assume !(0 == ~T2_E~0); 10825#L431-1 assume !(0 == ~T3_E~0); 10697#L436-1 assume !(0 == ~E_M~0); 10698#L441-1 assume !(0 == ~E_1~0); 10896#L446-1 assume !(0 == ~E_2~0); 10805#L451-1 assume !(0 == ~E_3~0); 10806#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10859#L200 assume !(1 == ~m_pc~0); 10860#L200-2 is_master_triggered_~__retres1~0 := 0; 10986#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10976#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10977#L523 assume !(0 != activate_threads_~tmp~1); 10938#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10939#L219 assume !(1 == ~t1_pc~0); 10790#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 10789#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10821#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10739#L531 assume !(0 != activate_threads_~tmp___0~0); 10740#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10874#L238 assume !(1 == ~t2_pc~0); 10937#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 10644#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10645#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10768#L539 assume !(0 != activate_threads_~tmp___1~0); 10769#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10882#L257 assume !(1 == ~t3_pc~0); 10744#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 10745#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10783#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10784#L547 assume !(0 != activate_threads_~tmp___2~0); 10943#L547-2 assume 1 == ~M_E~0;~M_E~0 := 2; 10756#L469-1 assume !(1 == ~T1_E~0); 10757#L474-1 assume !(1 == ~T2_E~0); 10799#L479-1 assume !(1 == ~T3_E~0); 10800#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 10857#L489-1 assume !(1 == ~E_1~0); 10996#L494-1 assume !(1 == ~E_2~0); 10746#L499-1 assume !(1 == ~E_3~0); 10747#L670-1 [2021-08-31 04:18:31,704 INFO L793 eck$LassoCheckResult]: Loop: 10747#L670-1 assume !false; 10822#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 10844#L396 assume !false; 10845#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10905#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10673#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10689#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10690#L349 assume !(0 != eval_~tmp~0); 10836#L411 start_simulation_~kernel_st~0 := 2; 12897#L277-1 start_simulation_~kernel_st~0 := 3; 12895#L421-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12894#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12893#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12852#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12847#L436-3 assume !(0 == ~E_M~0); 12846#L441-3 assume !(0 == ~E_1~0); 12843#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12841#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12840#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12836#L200-15 assume !(1 == ~m_pc~0); 12834#L200-17 is_master_triggered_~__retres1~0 := 0; 12833#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12831#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12830#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11010#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10758#L219-15 assume 1 == ~t1_pc~0; 10749#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10750#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10940#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10941#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10777#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10778#L238-15 assume !(1 == ~t2_pc~0); 10890#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 12881#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12879#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12877#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12875#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12873#L257-15 assume !(1 == ~t3_pc~0); 12025#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 12869#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12867#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12865#L547-15 assume !(0 != activate_threads_~tmp___2~0); 12863#L547-17 assume 1 == ~M_E~0;~M_E~0 := 2; 12861#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12860#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12858#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12856#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12788#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12785#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12854#L499-3 assume !(1 == ~E_3~0); 12853#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12850#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 10945#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10946#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10983#L689 assume !(0 == start_simulation_~tmp~3); 10984#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12917#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12913#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12912#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 10998#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10999#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 11005#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10934#L702 assume !(0 != start_simulation_~tmp___0~1); 10747#L670-1 [2021-08-31 04:18:31,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:31,705 INFO L82 PathProgramCache]: Analyzing trace with hash -1070196635, now seen corresponding path program 1 times [2021-08-31 04:18:31,705 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:31,705 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855271475] [2021-08-31 04:18:31,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:31,705 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:31,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:31,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:31,722 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:31,722 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1855271475] [2021-08-31 04:18:31,722 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1855271475] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:31,722 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:31,722 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:31,723 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1296973618] [2021-08-31 04:18:31,723 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:31,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:31,723 INFO L82 PathProgramCache]: Analyzing trace with hash -2110860165, now seen corresponding path program 2 times [2021-08-31 04:18:31,723 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:31,724 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432350514] [2021-08-31 04:18:31,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:31,724 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:31,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:31,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:31,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:31,737 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432350514] [2021-08-31 04:18:31,737 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432350514] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:31,737 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:31,737 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:31,737 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2004872297] [2021-08-31 04:18:31,737 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:31,738 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:31,738 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:31,738 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:31,738 INFO L87 Difference]: Start difference. First operand 2322 states and 3412 transitions. cyclomatic complexity: 1093 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:32,229 INFO L93 Difference]: Finished difference Result 4265 states and 6279 transitions. [2021-08-31 04:18:32,229 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:32,230 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4265 states and 6279 transitions. [2021-08-31 04:18:32,247 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4206 [2021-08-31 04:18:32,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4265 states to 4265 states and 6279 transitions. [2021-08-31 04:18:32,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4265 [2021-08-31 04:18:32,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4265 [2021-08-31 04:18:32,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4265 states and 6279 transitions. [2021-08-31 04:18:32,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:32,267 INFO L681 BuchiCegarLoop]: Abstraction has 4265 states and 6279 transitions. [2021-08-31 04:18:32,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4265 states and 6279 transitions. [2021-08-31 04:18:32,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4265 to 4265. [2021-08-31 04:18:32,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4265 states, 4265 states have (on average 1.4722157092614303) internal successors, (6279), 4264 states have internal predecessors, (6279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4265 states to 4265 states and 6279 transitions. [2021-08-31 04:18:32,327 INFO L704 BuchiCegarLoop]: Abstraction has 4265 states and 6279 transitions. [2021-08-31 04:18:32,327 INFO L587 BuchiCegarLoop]: Abstraction has 4265 states and 6279 transitions. [2021-08-31 04:18:32,327 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-08-31 04:18:32,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4265 states and 6279 transitions. [2021-08-31 04:18:32,337 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4206 [2021-08-31 04:18:32,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:32,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:32,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,338 INFO L791 eck$LassoCheckResult]: Stem: 17594#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 17540#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17487#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 17488#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 17352#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17228#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17229#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17322#L299-1 assume !(0 == ~M_E~0); 17323#L421-1 assume !(0 == ~T1_E~0); 17413#L426-1 assume !(0 == ~T2_E~0); 17414#L431-1 assume !(0 == ~T3_E~0); 17290#L436-1 assume !(0 == ~E_M~0); 17291#L441-1 assume !(0 == ~E_1~0); 17486#L446-1 assume !(0 == ~E_2~0); 17394#L451-1 assume !(0 == ~E_3~0); 17395#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17449#L200 assume !(1 == ~m_pc~0); 17450#L200-2 is_master_triggered_~__retres1~0 := 0; 17578#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17568#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17569#L523 assume !(0 != activate_threads_~tmp~1); 17530#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17531#L219 assume !(1 == ~t1_pc~0); 17379#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 17378#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17409#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17331#L531 assume !(0 != activate_threads_~tmp___0~0); 17332#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17467#L238 assume !(1 == ~t2_pc~0); 17529#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 17238#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17239#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17360#L539 assume !(0 != activate_threads_~tmp___1~0); 17361#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17473#L257 assume !(1 == ~t3_pc~0); 17337#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 17338#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17375#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17376#L547 assume !(0 != activate_threads_~tmp___2~0); 17536#L547-2 assume !(1 == ~M_E~0); 17349#L469-1 assume !(1 == ~T1_E~0); 17350#L474-1 assume !(1 == ~T2_E~0); 17388#L479-1 assume !(1 == ~T3_E~0); 17389#L484-1 assume 1 == ~E_M~0;~E_M~0 := 2; 17446#L489-1 assume !(1 == ~E_1~0); 17471#L494-1 assume !(1 == ~E_2~0); 17339#L499-1 assume !(1 == ~E_3~0); 17340#L670-1 [2021-08-31 04:18:32,338 INFO L793 eck$LassoCheckResult]: Loop: 17340#L670-1 assume !false; 19503#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 19501#L396 assume !false; 19499#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 19493#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 19487#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 19485#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 19482#L349 assume !(0 != eval_~tmp~0); 17555#L411 start_simulation_~kernel_st~0 := 2; 17556#L277-1 start_simulation_~kernel_st~0 := 3; 17430#L421-2 assume !(0 == ~M_E~0); 17431#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17581#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17508#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17509#L436-3 assume !(0 == ~E_M~0); 17521#L441-3 assume !(0 == ~E_1~0); 17522#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17518#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17519#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21485#L200-15 assume !(1 == ~m_pc~0); 21484#L200-17 is_master_triggered_~__retres1~0 := 0; 21483#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21482#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21481#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21480#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21479#L219-15 assume 1 == ~t1_pc~0; 21477#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21476#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21463#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17493#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17369#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17370#L238-15 assume !(1 == ~t2_pc~0); 17481#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 21388#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21386#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 21384#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17523#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17524#L257-15 assume !(1 == ~t3_pc~0); 21045#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 21043#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21042#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21041#L547-15 assume !(0 != activate_threads_~tmp___2~0); 21039#L547-17 assume !(1 == ~M_E~0); 21035#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21033#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21031#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21029#L484-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20888#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20886#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21025#L499-3 assume !(1 == ~E_3~0); 21023#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 19608#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 19604#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 19602#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 19569#L689 assume !(0 == start_simulation_~tmp~3); 19568#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 19565#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 19563#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 19561#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 19559#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19557#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 19553#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 19550#L702 assume !(0 != start_simulation_~tmp___0~1); 17340#L670-1 [2021-08-31 04:18:32,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,339 INFO L82 PathProgramCache]: Analyzing trace with hash -1879543261, now seen corresponding path program 1 times [2021-08-31 04:18:32,339 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,339 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2072070467] [2021-08-31 04:18:32,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,340 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,353 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,353 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2072070467] [2021-08-31 04:18:32,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2072070467] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,353 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:32,354 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [670752665] [2021-08-31 04:18:32,354 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:32,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,354 INFO L82 PathProgramCache]: Analyzing trace with hash -1244257665, now seen corresponding path program 1 times [2021-08-31 04:18:32,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,355 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770418276] [2021-08-31 04:18:32,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,355 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,367 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,367 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770418276] [2021-08-31 04:18:32,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770418276] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,367 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:32,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325195428] [2021-08-31 04:18:32,368 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:32,368 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:32,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:32,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:32,368 INFO L87 Difference]: Start difference. First operand 4265 states and 6279 transitions. cyclomatic complexity: 2017 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:32,660 INFO L93 Difference]: Finished difference Result 4264 states and 6180 transitions. [2021-08-31 04:18:32,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:32,668 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4264 states and 6180 transitions. [2021-08-31 04:18:32,690 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4206 [2021-08-31 04:18:32,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4264 states to 4264 states and 6180 transitions. [2021-08-31 04:18:32,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4264 [2021-08-31 04:18:32,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4264 [2021-08-31 04:18:32,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4264 states and 6180 transitions. [2021-08-31 04:18:32,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:32,712 INFO L681 BuchiCegarLoop]: Abstraction has 4264 states and 6180 transitions. [2021-08-31 04:18:32,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4264 states and 6180 transitions. [2021-08-31 04:18:32,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4264 to 3036. [2021-08-31 04:18:32,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3036 states, 3036 states have (on average 1.4433465085639) internal successors, (4382), 3035 states have internal predecessors, (4382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:32,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3036 states to 3036 states and 4382 transitions. [2021-08-31 04:18:32,756 INFO L704 BuchiCegarLoop]: Abstraction has 3036 states and 4382 transitions. [2021-08-31 04:18:32,756 INFO L587 BuchiCegarLoop]: Abstraction has 3036 states and 4382 transitions. [2021-08-31 04:18:32,756 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-08-31 04:18:32,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3036 states and 4382 transitions. [2021-08-31 04:18:32,762 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2980 [2021-08-31 04:18:32,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:32,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:32,763 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:32,763 INFO L791 eck$LassoCheckResult]: Stem: 26121#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 26065#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 26015#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26016#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 25886#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25764#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25765#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25857#L299-1 assume !(0 == ~M_E~0); 25858#L421-1 assume !(0 == ~T1_E~0); 25948#L426-1 assume !(0 == ~T2_E~0); 25949#L431-1 assume !(0 == ~T3_E~0); 25827#L436-1 assume !(0 == ~E_M~0); 25828#L441-1 assume !(0 == ~E_1~0); 26014#L446-1 assume !(0 == ~E_2~0); 25930#L451-1 assume !(0 == ~E_3~0); 25931#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25983#L200 assume !(1 == ~m_pc~0); 25984#L200-2 is_master_triggered_~__retres1~0 := 0; 26102#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26094#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26095#L523 assume !(0 != activate_threads_~tmp~1); 26056#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26057#L219 assume !(1 == ~t1_pc~0); 25913#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 25912#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25944#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 25866#L531 assume !(0 != activate_threads_~tmp___0~0); 25867#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25995#L238 assume !(1 == ~t2_pc~0); 26055#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 25774#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25775#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 25894#L539 assume !(0 != activate_threads_~tmp___1~0); 25895#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26001#L257 assume !(1 == ~t3_pc~0); 25871#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 25872#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25909#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 25910#L547 assume !(0 != activate_threads_~tmp___2~0); 26060#L547-2 assume !(1 == ~M_E~0); 25883#L469-1 assume !(1 == ~T1_E~0); 25884#L474-1 assume !(1 == ~T2_E~0); 25925#L479-1 assume !(1 == ~T3_E~0); 25926#L484-1 assume !(1 == ~E_M~0); 25981#L489-1 assume !(1 == ~E_1~0); 25999#L494-1 assume !(1 == ~E_2~0); 25873#L499-1 assume !(1 == ~E_3~0); 25874#L670-1 [2021-08-31 04:18:32,764 INFO L793 eck$LassoCheckResult]: Loop: 25874#L670-1 assume !false; 28201#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 28199#L396 assume !false; 28197#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28193#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28189#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28187#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 28183#L349 assume !(0 != eval_~tmp~0); 28184#L411 start_simulation_~kernel_st~0 := 2; 28741#L277-1 start_simulation_~kernel_st~0 := 3; 28739#L421-2 assume !(0 == ~M_E~0); 28738#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28737#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28736#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28735#L436-3 assume !(0 == ~E_M~0); 28734#L441-3 assume !(0 == ~E_1~0); 28733#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28732#L451-3 assume 0 == ~E_3~0;~E_3~0 := 1; 28731#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28730#L200-15 assume !(1 == ~m_pc~0); 28729#L200-17 is_master_triggered_~__retres1~0 := 0; 28728#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28727#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28726#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28725#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28724#L219-15 assume 1 == ~t1_pc~0; 28722#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 28721#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28719#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28717#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28715#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26007#L238-15 assume !(1 == ~t2_pc~0); 26008#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 28678#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28677#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28676#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28674#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28104#L257-15 assume !(1 == ~t3_pc~0); 28102#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 28101#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28100#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28099#L547-15 assume !(0 != activate_threads_~tmp___2~0); 28098#L547-17 assume !(1 == ~M_E~0); 28038#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28097#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28096#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28095#L484-3 assume !(1 == ~E_M~0); 28094#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28092#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28090#L499-3 assume !(1 == ~E_3~0); 28088#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28084#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28080#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28078#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 28076#L689 assume !(0 == start_simulation_~tmp~3); 28077#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28231#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28228#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28226#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 28224#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28222#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 28220#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 28218#L702 assume !(0 != start_simulation_~tmp___0~1); 25874#L670-1 [2021-08-31 04:18:32,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,764 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 1 times [2021-08-31 04:18:32,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,765 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467846166] [2021-08-31 04:18:32,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,765 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:32,783 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:32,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:32,817 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:32,818 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:32,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1462361729, now seen corresponding path program 1 times [2021-08-31 04:18:32,818 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:32,818 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314599185] [2021-08-31 04:18:32,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:32,827 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:32,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:32,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:32,843 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:32,843 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314599185] [2021-08-31 04:18:32,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [314599185] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:32,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:32,844 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:32,844 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [355527794] [2021-08-31 04:18:32,844 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:32,844 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:32,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:32,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:32,845 INFO L87 Difference]: Start difference. First operand 3036 states and 4382 transitions. cyclomatic complexity: 1348 Second operand has 3 states, 3 states have (on average 21.0) internal successors, (63), 3 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:33,338 INFO L93 Difference]: Finished difference Result 5221 states and 7482 transitions. [2021-08-31 04:18:33,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:33,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5221 states and 7482 transitions. [2021-08-31 04:18:33,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5124 [2021-08-31 04:18:33,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5221 states to 5221 states and 7482 transitions. [2021-08-31 04:18:33,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5221 [2021-08-31 04:18:33,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5221 [2021-08-31 04:18:33,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5221 states and 7482 transitions. [2021-08-31 04:18:33,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:33,374 INFO L681 BuchiCegarLoop]: Abstraction has 5221 states and 7482 transitions. [2021-08-31 04:18:33,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5221 states and 7482 transitions. [2021-08-31 04:18:33,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5221 to 5213. [2021-08-31 04:18:33,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5213 states, 5213 states have (on average 1.433723383848072) internal successors, (7474), 5212 states have internal predecessors, (7474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5213 states to 5213 states and 7474 transitions. [2021-08-31 04:18:33,450 INFO L704 BuchiCegarLoop]: Abstraction has 5213 states and 7474 transitions. [2021-08-31 04:18:33,450 INFO L587 BuchiCegarLoop]: Abstraction has 5213 states and 7474 transitions. [2021-08-31 04:18:33,450 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-08-31 04:18:33,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5213 states and 7474 transitions. [2021-08-31 04:18:33,461 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5116 [2021-08-31 04:18:33,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:33,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:33,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,473 INFO L791 eck$LassoCheckResult]: Stem: 34391#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34331#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34281#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34282#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 34149#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34027#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34028#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34118#L299-1 assume !(0 == ~M_E~0); 34119#L421-1 assume !(0 == ~T1_E~0); 34212#L426-1 assume !(0 == ~T2_E~0); 34213#L431-1 assume !(0 == ~T3_E~0); 34088#L436-1 assume !(0 == ~E_M~0); 34089#L441-1 assume !(0 == ~E_1~0); 34280#L446-1 assume !(0 == ~E_2~0); 34194#L451-1 assume 0 == ~E_3~0;~E_3~0 := 1; 34195#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34246#L200 assume !(1 == ~m_pc~0); 34247#L200-2 is_master_triggered_~__retres1~0 := 0; 34370#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34382#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 34361#L523 assume !(0 != activate_threads_~tmp~1); 34322#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34323#L219 assume !(1 == ~t1_pc~0); 34176#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 34175#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34208#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34127#L531 assume !(0 != activate_threads_~tmp___0~0); 34128#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34260#L238 assume !(1 == ~t2_pc~0); 34321#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 34037#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34038#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 34158#L539 assume !(0 != activate_threads_~tmp___1~0); 34159#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34266#L257 assume !(1 == ~t3_pc~0); 34133#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 34134#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34172#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 34173#L547 assume !(0 != activate_threads_~tmp___2~0); 34326#L547-2 assume !(1 == ~M_E~0); 34146#L469-1 assume !(1 == ~T1_E~0); 34147#L474-1 assume !(1 == ~T2_E~0); 34188#L479-1 assume !(1 == ~T3_E~0); 34189#L484-1 assume !(1 == ~E_M~0); 34244#L489-1 assume !(1 == ~E_1~0); 34264#L494-1 assume !(1 == ~E_2~0); 34135#L499-1 assume 1 == ~E_3~0;~E_3~0 := 2; 34136#L670-1 [2021-08-31 04:18:33,474 INFO L793 eck$LassoCheckResult]: Loop: 34136#L670-1 assume !false; 36990#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 36987#L396 assume !false; 36985#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 36981#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 36977#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 36975#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 36972#L349 assume !(0 != eval_~tmp~0); 36973#L411 start_simulation_~kernel_st~0 := 2; 39219#L277-1 start_simulation_~kernel_st~0 := 3; 39217#L421-2 assume !(0 == ~M_E~0); 39215#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39213#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39212#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39211#L436-3 assume !(0 == ~E_M~0); 34314#L441-3 assume !(0 == ~E_1~0); 34315#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39208#L451-3 assume !(0 == ~E_3~0); 34084#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34085#L200-15 assume !(1 == ~m_pc~0); 34182#L200-17 is_master_triggered_~__retres1~0 := 0; 34339#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39111#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 38991#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38990#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38989#L219-15 assume 1 == ~t1_pc~0; 38987#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38986#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38985#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 38972#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38970#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38969#L238-15 assume !(1 == ~t2_pc~0); 37143#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 38948#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38747#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 38746#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 38745#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37117#L257-15 assume !(1 == ~t3_pc~0); 37115#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 37113#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37111#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 37109#L547-15 assume !(0 != activate_threads_~tmp___2~0); 37107#L547-17 assume !(1 == ~M_E~0); 37101#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37099#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37097#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37095#L484-3 assume !(1 == ~E_M~0); 37093#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37091#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37088#L499-3 assume !(1 == ~E_3~0); 37087#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37084#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 37080#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37078#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 37074#L689 assume !(0 == start_simulation_~tmp~3); 37073#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 37069#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 37066#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 37064#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 37062#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37059#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 37057#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 36995#L702 assume !(0 != start_simulation_~tmp___0~1); 34136#L670-1 [2021-08-31 04:18:33,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1807097123, now seen corresponding path program 1 times [2021-08-31 04:18:33,474 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994165690] [2021-08-31 04:18:33,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,490 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:33,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:33,520 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:33,520 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994165690] [2021-08-31 04:18:33,520 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994165690] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:33,520 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:33,520 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:33,520 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076104936] [2021-08-31 04:18:33,520 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:33,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,521 INFO L82 PathProgramCache]: Analyzing trace with hash -904332865, now seen corresponding path program 1 times [2021-08-31 04:18:33,522 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,522 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4343193] [2021-08-31 04:18:33,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,522 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:33,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:33,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:33,547 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4343193] [2021-08-31 04:18:33,547 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4343193] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:33,547 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:33,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:33,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568579577] [2021-08-31 04:18:33,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:33,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:33,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:33,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:33,548 INFO L87 Difference]: Start difference. First operand 5213 states and 7474 transitions. cyclomatic complexity: 2263 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 2 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:33,820 INFO L93 Difference]: Finished difference Result 3032 states and 4292 transitions. [2021-08-31 04:18:33,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:33,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3032 states and 4292 transitions. [2021-08-31 04:18:33,827 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2976 [2021-08-31 04:18:33,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3032 states to 3032 states and 4292 transitions. [2021-08-31 04:18:33,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3032 [2021-08-31 04:18:33,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3032 [2021-08-31 04:18:33,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3032 states and 4292 transitions. [2021-08-31 04:18:33,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:33,838 INFO L681 BuchiCegarLoop]: Abstraction has 3032 states and 4292 transitions. [2021-08-31 04:18:33,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3032 states and 4292 transitions. [2021-08-31 04:18:33,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3032 to 3032. [2021-08-31 04:18:33,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3032 states, 3032 states have (on average 1.4155672823218997) internal successors, (4292), 3031 states have internal predecessors, (4292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:33,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3032 states to 3032 states and 4292 transitions. [2021-08-31 04:18:33,881 INFO L704 BuchiCegarLoop]: Abstraction has 3032 states and 4292 transitions. [2021-08-31 04:18:33,881 INFO L587 BuchiCegarLoop]: Abstraction has 3032 states and 4292 transitions. [2021-08-31 04:18:33,881 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-08-31 04:18:33,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3032 states and 4292 transitions. [2021-08-31 04:18:33,886 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2976 [2021-08-31 04:18:33,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:33,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:33,887 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,887 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:33,887 INFO L791 eck$LassoCheckResult]: Stem: 42623#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 42575#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 42528#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 42529#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 42402#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42281#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42282#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42372#L299-1 assume !(0 == ~M_E~0); 42373#L421-1 assume !(0 == ~T1_E~0); 42463#L426-1 assume !(0 == ~T2_E~0); 42464#L431-1 assume !(0 == ~T3_E~0); 42342#L436-1 assume !(0 == ~E_M~0); 42343#L441-1 assume !(0 == ~E_1~0); 42527#L446-1 assume !(0 == ~E_2~0); 42446#L451-1 assume !(0 == ~E_3~0); 42447#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42497#L200 assume !(1 == ~m_pc~0); 42498#L200-2 is_master_triggered_~__retres1~0 := 0; 42608#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42601#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 42602#L523 assume !(0 != activate_threads_~tmp~1); 42566#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42567#L219 assume !(1 == ~t1_pc~0); 42430#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 42429#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42459#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 42382#L531 assume !(0 != activate_threads_~tmp___0~0); 42383#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42507#L238 assume !(1 == ~t2_pc~0); 42565#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 42291#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42292#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 42410#L539 assume !(0 != activate_threads_~tmp___1~0); 42411#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42515#L257 assume !(1 == ~t3_pc~0); 42387#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 42388#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42424#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 42425#L547 assume !(0 != activate_threads_~tmp___2~0); 42570#L547-2 assume !(1 == ~M_E~0); 42399#L469-1 assume !(1 == ~T1_E~0); 42400#L474-1 assume !(1 == ~T2_E~0); 42439#L479-1 assume !(1 == ~T3_E~0); 42440#L484-1 assume !(1 == ~E_M~0); 42496#L489-1 assume !(1 == ~E_1~0); 42511#L494-1 assume !(1 == ~E_2~0); 42389#L499-1 assume !(1 == ~E_3~0); 42390#L670-1 [2021-08-31 04:18:33,887 INFO L793 eck$LassoCheckResult]: Loop: 42390#L670-1 assume !false; 43938#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 43936#L396 assume !false; 43935#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43932#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43928#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43926#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 43922#L349 assume !(0 != eval_~tmp~0); 42592#L411 start_simulation_~kernel_st~0 := 2; 42593#L277-1 start_simulation_~kernel_st~0 := 3; 42479#L421-2 assume !(0 == ~M_E~0); 42480#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42610#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42546#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42547#L436-3 assume !(0 == ~E_M~0); 42559#L441-3 assume !(0 == ~E_1~0); 42560#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42556#L451-3 assume !(0 == ~E_3~0); 42338#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42339#L200-15 assume !(1 == ~m_pc~0); 42433#L200-17 is_master_triggered_~__retres1~0 := 0; 42584#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42512#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 42513#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45238#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45237#L219-15 assume 1 == ~t1_pc~0; 45235#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 45234#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45180#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 45146#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43911#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 43754#L238-15 assume !(1 == ~t2_pc~0); 43752#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 43740#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43732#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 43724#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 43718#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43712#L257-15 assume !(1 == ~t3_pc~0); 43577#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 43576#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43574#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 43572#L547-15 assume !(0 != activate_threads_~tmp___2~0); 43571#L547-17 assume !(1 == ~M_E~0); 43515#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 43569#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43567#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43565#L484-3 assume !(1 == ~E_M~0); 43563#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43562#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 43561#L499-3 assume !(1 == ~E_3~0); 43560#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43557#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43553#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43551#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 43549#L689 assume !(0 == start_simulation_~tmp~3); 43550#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 43954#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 43951#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 43949#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 43947#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43946#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 43944#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 43942#L702 assume !(0 != start_simulation_~tmp___0~1); 42390#L670-1 [2021-08-31 04:18:33,888 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,888 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 2 times [2021-08-31 04:18:33,888 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,888 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142833412] [2021-08-31 04:18:33,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,888 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:33,893 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:33,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:33,901 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:33,903 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:33,903 INFO L82 PathProgramCache]: Analyzing trace with hash -904332865, now seen corresponding path program 2 times [2021-08-31 04:18:33,903 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:33,903 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473946158] [2021-08-31 04:18:33,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:33,904 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:33,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:33,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:33,928 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:33,928 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473946158] [2021-08-31 04:18:33,928 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473946158] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:33,928 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:33,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:33,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471281039] [2021-08-31 04:18:33,928 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:33,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:33,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-31 04:18:33,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-31 04:18:33,929 INFO L87 Difference]: Start difference. First operand 3032 states and 4292 transitions. cyclomatic complexity: 1262 Second operand has 5 states, 5 states have (on average 12.6) internal successors, (63), 5 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:34,656 INFO L93 Difference]: Finished difference Result 5256 states and 7328 transitions. [2021-08-31 04:18:34,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-08-31 04:18:34,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5256 states and 7328 transitions. [2021-08-31 04:18:34,670 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5192 [2021-08-31 04:18:34,682 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5256 states to 5256 states and 7328 transitions. [2021-08-31 04:18:34,683 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5256 [2021-08-31 04:18:34,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5256 [2021-08-31 04:18:34,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5256 states and 7328 transitions. [2021-08-31 04:18:34,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:34,703 INFO L681 BuchiCegarLoop]: Abstraction has 5256 states and 7328 transitions. [2021-08-31 04:18:34,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5256 states and 7328 transitions. [2021-08-31 04:18:34,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5256 to 3080. [2021-08-31 04:18:34,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3080 states, 3080 states have (on average 1.4090909090909092) internal successors, (4340), 3079 states have internal predecessors, (4340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:34,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3080 states to 3080 states and 4340 transitions. [2021-08-31 04:18:34,742 INFO L704 BuchiCegarLoop]: Abstraction has 3080 states and 4340 transitions. [2021-08-31 04:18:34,742 INFO L587 BuchiCegarLoop]: Abstraction has 3080 states and 4340 transitions. [2021-08-31 04:18:34,742 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-08-31 04:18:34,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3080 states and 4340 transitions. [2021-08-31 04:18:34,748 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3024 [2021-08-31 04:18:34,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:34,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:34,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:34,750 INFO L791 eck$LassoCheckResult]: Stem: 50942#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 50885#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 50835#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 50836#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 50709#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50585#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50586#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50679#L299-1 assume !(0 == ~M_E~0); 50680#L421-1 assume !(0 == ~T1_E~0); 50771#L426-1 assume !(0 == ~T2_E~0); 50772#L431-1 assume !(0 == ~T3_E~0); 50647#L436-1 assume !(0 == ~E_M~0); 50648#L441-1 assume !(0 == ~E_1~0); 50834#L446-1 assume !(0 == ~E_2~0); 50753#L451-1 assume !(0 == ~E_3~0); 50754#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50806#L200 assume !(1 == ~m_pc~0); 50807#L200-2 is_master_triggered_~__retres1~0 := 0; 50919#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50910#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50911#L523 assume !(0 != activate_threads_~tmp~1); 50875#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50876#L219 assume !(1 == ~t1_pc~0); 50735#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 50734#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50767#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 50688#L531 assume !(0 != activate_threads_~tmp___0~0); 50689#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 50818#L238 assume !(1 == ~t2_pc~0); 50874#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 50595#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50596#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 50717#L539 assume !(0 != activate_threads_~tmp___1~0); 50718#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50824#L257 assume !(1 == ~t3_pc~0); 50694#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 50695#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50731#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 50732#L547 assume !(0 != activate_threads_~tmp___2~0); 50879#L547-2 assume !(1 == ~M_E~0); 50706#L469-1 assume !(1 == ~T1_E~0); 50707#L474-1 assume !(1 == ~T2_E~0); 50747#L479-1 assume !(1 == ~T3_E~0); 50748#L484-1 assume !(1 == ~E_M~0); 50804#L489-1 assume !(1 == ~E_1~0); 50822#L494-1 assume !(1 == ~E_2~0); 50696#L499-1 assume !(1 == ~E_3~0); 50697#L670-1 [2021-08-31 04:18:34,750 INFO L793 eck$LassoCheckResult]: Loop: 50697#L670-1 assume !false; 53240#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 53138#L396 assume !false; 53135#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 53124#L312 assume !(0 == ~m_st~0); 53125#L316 assume !(0 == ~t1_st~0); 53121#L320 assume !(0 == ~t2_st~0); 53122#L324 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 53123#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 52725#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 52726#L349 assume !(0 != eval_~tmp~0); 53100#L411 start_simulation_~kernel_st~0 := 2; 53101#L277-1 start_simulation_~kernel_st~0 := 3; 53092#L421-2 assume !(0 == ~M_E~0); 53093#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 50937#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50855#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50856#L436-3 assume !(0 == ~E_M~0); 50867#L441-3 assume !(0 == ~E_1~0); 50868#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50865#L451-3 assume !(0 == ~E_3~0); 50643#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50644#L200-15 assume !(1 == ~m_pc~0); 53319#L200-17 is_master_triggered_~__retres1~0 := 0; 50949#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50823#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50704#L523-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 50705#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53312#L219-15 assume 1 == ~t1_pc~0; 53304#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 53301#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53299#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 53297#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53295#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53293#L238-15 assume !(1 == ~t2_pc~0); 51045#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 53290#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53288#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 53286#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 53284#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53282#L257-15 assume !(1 == ~t3_pc~0); 53193#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 53280#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53278#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 53276#L547-15 assume !(0 != activate_threads_~tmp___2~0); 53274#L547-17 assume !(1 == ~M_E~0); 53271#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53270#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53269#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53268#L484-3 assume !(1 == ~E_M~0); 53267#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53266#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53265#L499-3 assume !(1 == ~E_3~0); 53264#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 53262#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 53258#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 53256#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 53254#L689 assume !(0 == start_simulation_~tmp~3); 53253#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 53250#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 53248#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 53247#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 53246#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 53245#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 53244#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 53243#L702 assume !(0 != start_simulation_~tmp___0~1); 50697#L670-1 [2021-08-31 04:18:34,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,751 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 3 times [2021-08-31 04:18:34,751 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,751 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195201480] [2021-08-31 04:18:34,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,751 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,762 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:34,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:34,780 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:34,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:34,781 INFO L82 PathProgramCache]: Analyzing trace with hash -754524675, now seen corresponding path program 1 times [2021-08-31 04:18:34,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:34,782 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676869095] [2021-08-31 04:18:34,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:34,782 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:34,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:34,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:34,828 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:34,828 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676869095] [2021-08-31 04:18:34,828 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676869095] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:34,828 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:34,829 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-08-31 04:18:34,829 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148617493] [2021-08-31 04:18:34,829 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:34,829 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:34,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-08-31 04:18:34,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-08-31 04:18:34,830 INFO L87 Difference]: Start difference. First operand 3080 states and 4340 transitions. cyclomatic complexity: 1262 Second operand has 5 states, 5 states have (on average 13.2) internal successors, (66), 5 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:35,431 INFO L93 Difference]: Finished difference Result 3676 states and 5131 transitions. [2021-08-31 04:18:35,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-08-31 04:18:35,431 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3676 states and 5131 transitions. [2021-08-31 04:18:35,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3620 [2021-08-31 04:18:35,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3676 states to 3676 states and 5131 transitions. [2021-08-31 04:18:35,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3676 [2021-08-31 04:18:35,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3676 [2021-08-31 04:18:35,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3676 states and 5131 transitions. [2021-08-31 04:18:35,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:35,449 INFO L681 BuchiCegarLoop]: Abstraction has 3676 states and 5131 transitions. [2021-08-31 04:18:35,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3676 states and 5131 transitions. [2021-08-31 04:18:35,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3676 to 3092. [2021-08-31 04:18:35,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3092 states, 3092 states have (on average 1.3877749029754205) internal successors, (4291), 3091 states have internal predecessors, (4291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3092 states to 3092 states and 4291 transitions. [2021-08-31 04:18:35,475 INFO L704 BuchiCegarLoop]: Abstraction has 3092 states and 4291 transitions. [2021-08-31 04:18:35,475 INFO L587 BuchiCegarLoop]: Abstraction has 3092 states and 4291 transitions. [2021-08-31 04:18:35,475 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-08-31 04:18:35,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3092 states and 4291 transitions. [2021-08-31 04:18:35,480 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3036 [2021-08-31 04:18:35,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:35,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:35,481 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,481 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,481 INFO L791 eck$LassoCheckResult]: Stem: 57718#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 57653#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 57605#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 57606#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 57479#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57354#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57355#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57446#L299-1 assume !(0 == ~M_E~0); 57447#L421-1 assume !(0 == ~T1_E~0); 57540#L426-1 assume !(0 == ~T2_E~0); 57541#L431-1 assume !(0 == ~T3_E~0); 57414#L436-1 assume !(0 == ~E_M~0); 57415#L441-1 assume !(0 == ~E_1~0); 57604#L446-1 assume !(0 == ~E_2~0); 57522#L451-1 assume !(0 == ~E_3~0); 57523#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57575#L200 assume !(1 == ~m_pc~0); 57576#L200-2 is_master_triggered_~__retres1~0 := 0; 57694#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57679#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 57680#L523 assume !(0 != activate_threads_~tmp~1); 57644#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57645#L219 assume !(1 == ~t1_pc~0); 57505#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 57504#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57532#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 57455#L531 assume !(0 != activate_threads_~tmp___0~0); 57456#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 57585#L238 assume !(1 == ~t2_pc~0); 57643#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 57364#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57365#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 57487#L539 assume !(0 != activate_threads_~tmp___1~0); 57488#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57593#L257 assume !(1 == ~t3_pc~0); 57460#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 57461#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57501#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 57502#L547 assume !(0 != activate_threads_~tmp___2~0); 57649#L547-2 assume !(1 == ~M_E~0); 57472#L469-1 assume !(1 == ~T1_E~0); 57473#L474-1 assume !(1 == ~T2_E~0); 57511#L479-1 assume !(1 == ~T3_E~0); 57512#L484-1 assume !(1 == ~E_M~0); 57572#L489-1 assume !(1 == ~E_1~0); 57591#L494-1 assume !(1 == ~E_2~0); 57464#L499-1 assume !(1 == ~E_3~0); 57465#L670-1 [2021-08-31 04:18:35,482 INFO L793 eck$LassoCheckResult]: Loop: 57465#L670-1 assume !false; 59155#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 59153#L396 assume !false; 59151#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 59149#L312 assume !(0 == ~m_st~0); 59147#L316 assume !(0 == ~t1_st~0); 59145#L320 assume !(0 == ~t2_st~0); 59142#L324 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 59140#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 58649#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 58650#L349 assume !(0 != eval_~tmp~0); 59131#L411 start_simulation_~kernel_st~0 := 2; 59127#L277-1 start_simulation_~kernel_st~0 := 3; 59123#L421-2 assume !(0 == ~M_E~0); 59119#L421-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59115#L426-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59111#L431-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 59107#L436-3 assume !(0 == ~E_M~0); 59103#L441-3 assume !(0 == ~E_1~0); 59099#L446-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59095#L451-3 assume !(0 == ~E_3~0); 59091#L456-3 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59087#L200-15 assume !(1 == ~m_pc~0); 59083#L200-17 is_master_triggered_~__retres1~0 := 0; 59079#L211-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59075#L212-5 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 59071#L523-15 assume !(0 != activate_threads_~tmp~1); 59067#L523-17 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59061#L219-15 assume 1 == ~t1_pc~0; 59053#L220-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 59050#L230-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59048#L231-5 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59046#L531-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 59044#L531-17 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59042#L238-15 assume !(1 == ~t2_pc~0); 58838#L238-17 is_transmit2_triggered_~__retres1~2 := 0; 59038#L249-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 59039#L250-5 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 58925#L539-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 58919#L539-17 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58733#L257-15 assume !(1 == ~t3_pc~0); 58729#L257-17 is_transmit3_triggered_~__retres1~3 := 0; 58725#L268-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58721#L269-5 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 58717#L547-15 assume !(0 != activate_threads_~tmp___2~0); 58712#L547-17 assume !(1 == ~M_E~0); 58708#L469-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 58706#L474-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58704#L479-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58702#L484-3 assume !(1 == ~E_M~0); 58699#L489-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58697#L494-3 assume 1 == ~E_2~0;~E_2~0 := 2; 58695#L499-3 assume !(1 == ~E_3~0); 58693#L504-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 58690#L312-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 57896#L334-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 57897#L335-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 57873#L689 assume !(0 == start_simulation_~tmp~3); 57874#L689-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 59203#L312-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 59197#L334-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 59193#L335-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 59188#L644 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 59181#L651 stop_simulation_#res := stop_simulation_~__retres2~0; 59175#L652 start_simulation_#t~ret19 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 59167#L702 assume !(0 != start_simulation_~tmp___0~1); 57465#L670-1 [2021-08-31 04:18:35,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,482 INFO L82 PathProgramCache]: Analyzing trace with hash -1879483679, now seen corresponding path program 4 times [2021-08-31 04:18:35,482 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,482 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1785567392] [2021-08-31 04:18:35,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,482 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,487 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:35,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,499 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:35,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,500 INFO L82 PathProgramCache]: Analyzing trace with hash -2126331973, now seen corresponding path program 1 times [2021-08-31 04:18:35,500 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77170572] [2021-08-31 04:18:35,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,502 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:35,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:35,516 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:35,516 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77170572] [2021-08-31 04:18:35,516 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77170572] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:35,516 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:35,516 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:35,517 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [211625250] [2021-08-31 04:18:35,517 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-08-31 04:18:35,517 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:35,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:35,517 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:35,517 INFO L87 Difference]: Start difference. First operand 3092 states and 4291 transitions. cyclomatic complexity: 1201 Second operand has 3 states, 3 states have (on average 22.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:35,865 INFO L93 Difference]: Finished difference Result 4041 states and 5517 transitions. [2021-08-31 04:18:35,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:35,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4041 states and 5517 transitions. [2021-08-31 04:18:35,874 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3987 [2021-08-31 04:18:35,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4041 states to 4041 states and 5517 transitions. [2021-08-31 04:18:35,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4041 [2021-08-31 04:18:35,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4041 [2021-08-31 04:18:35,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4041 states and 5517 transitions. [2021-08-31 04:18:35,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:35,883 INFO L681 BuchiCegarLoop]: Abstraction has 4041 states and 5517 transitions. [2021-08-31 04:18:35,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4041 states and 5517 transitions. [2021-08-31 04:18:35,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4041 to 4041. [2021-08-31 04:18:35,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4041 states, 4041 states have (on average 1.3652561247216035) internal successors, (5517), 4040 states have internal predecessors, (5517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:35,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4041 states to 4041 states and 5517 transitions. [2021-08-31 04:18:35,916 INFO L704 BuchiCegarLoop]: Abstraction has 4041 states and 5517 transitions. [2021-08-31 04:18:35,916 INFO L587 BuchiCegarLoop]: Abstraction has 4041 states and 5517 transitions. [2021-08-31 04:18:35,916 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-08-31 04:18:35,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4041 states and 5517 transitions. [2021-08-31 04:18:35,921 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3987 [2021-08-31 04:18:35,921 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:35,921 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:35,922 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,922 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:35,922 INFO L791 eck$LassoCheckResult]: Stem: 64855#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 64795#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 64742#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 64743#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 64615#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64493#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64494#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64585#L299-1 assume !(0 == ~M_E~0); 64586#L421-1 assume !(0 == ~T1_E~0); 64673#L426-1 assume !(0 == ~T2_E~0); 64674#L431-1 assume !(0 == ~T3_E~0); 64553#L436-1 assume !(0 == ~E_M~0); 64554#L441-1 assume !(0 == ~E_1~0); 64741#L446-1 assume !(0 == ~E_2~0); 64658#L451-1 assume !(0 == ~E_3~0); 64659#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64709#L200 assume !(1 == ~m_pc~0); 64710#L200-2 is_master_triggered_~__retres1~0 := 0; 64829#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64818#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 64819#L523 assume !(0 != activate_threads_~tmp~1); 64784#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64785#L219 assume !(1 == ~t1_pc~0); 64641#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 64640#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 64665#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 64594#L531 assume !(0 != activate_threads_~tmp___0~0); 64595#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64721#L238 assume !(1 == ~t2_pc~0); 64782#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 64503#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64504#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 64623#L539 assume !(0 != activate_threads_~tmp___1~0); 64624#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64730#L257 assume !(1 == ~t3_pc~0); 64599#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 64600#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64637#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 64638#L547 assume !(0 != activate_threads_~tmp___2~0); 64789#L547-2 assume !(1 == ~M_E~0); 64610#L469-1 assume !(1 == ~T1_E~0); 64611#L474-1 assume !(1 == ~T2_E~0); 64647#L479-1 assume !(1 == ~T3_E~0); 64648#L484-1 assume !(1 == ~E_M~0); 64706#L489-1 assume !(1 == ~E_1~0); 64728#L494-1 assume !(1 == ~E_2~0); 64602#L499-1 assume !(1 == ~E_3~0); 64603#L670-1 assume !false; 65741#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 65739#L396 [2021-08-31 04:18:35,922 INFO L793 eck$LassoCheckResult]: Loop: 65739#L396 assume !false; 65737#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 65734#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 65731#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 65729#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 65727#L349 assume 0 != eval_~tmp~0; 65724#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 65721#L357 assume !(0 != eval_~tmp_ndt_1~0); 65677#L354 assume !(0 == ~t1_st~0); 65573#L368 assume !(0 == ~t2_st~0); 65442#L382 assume !(0 == ~t3_st~0); 65739#L396 [2021-08-31 04:18:35,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 1 times [2021-08-31 04:18:35,922 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,923 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42729699] [2021-08-31 04:18:35,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,923 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,927 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:35,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,934 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:35,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,935 INFO L82 PathProgramCache]: Analyzing trace with hash 526302728, now seen corresponding path program 1 times [2021-08-31 04:18:35,935 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,935 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793602717] [2021-08-31 04:18:35,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,935 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,937 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:35,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:35,938 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:35,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:35,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1009129114, now seen corresponding path program 1 times [2021-08-31 04:18:35,939 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:35,939 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1388005091] [2021-08-31 04:18:35,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:35,939 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:35,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:35,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:35,952 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:35,952 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1388005091] [2021-08-31 04:18:35,952 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1388005091] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:35,952 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:35,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:35,952 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527758529] [2021-08-31 04:18:36,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:36,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:36,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:36,019 INFO L87 Difference]: Start difference. First operand 4041 states and 5517 transitions. cyclomatic complexity: 1479 Second operand has 3 states, 3 states have (on average 20.0) internal successors, (60), 3 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:36,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:36,549 INFO L93 Difference]: Finished difference Result 7093 states and 9544 transitions. [2021-08-31 04:18:36,549 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:36,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7093 states and 9544 transitions. [2021-08-31 04:18:36,570 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6990 [2021-08-31 04:18:36,585 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7093 states to 7093 states and 9544 transitions. [2021-08-31 04:18:36,585 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7093 [2021-08-31 04:18:36,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7093 [2021-08-31 04:18:36,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7093 states and 9544 transitions. [2021-08-31 04:18:36,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:36,593 INFO L681 BuchiCegarLoop]: Abstraction has 7093 states and 9544 transitions. [2021-08-31 04:18:36,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7093 states and 9544 transitions. [2021-08-31 04:18:36,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7093 to 6645. [2021-08-31 04:18:36,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6645 states, 6645 states have (on average 1.3541008276899924) internal successors, (8998), 6644 states have internal predecessors, (8998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:36,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6645 states to 6645 states and 8998 transitions. [2021-08-31 04:18:36,659 INFO L704 BuchiCegarLoop]: Abstraction has 6645 states and 8998 transitions. [2021-08-31 04:18:36,659 INFO L587 BuchiCegarLoop]: Abstraction has 6645 states and 8998 transitions. [2021-08-31 04:18:36,659 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-08-31 04:18:36,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6645 states and 8998 transitions. [2021-08-31 04:18:36,671 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6542 [2021-08-31 04:18:36,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:36,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:36,672 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,672 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:36,672 INFO L791 eck$LassoCheckResult]: Stem: 76059#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 75971#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 75908#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 75909#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 75760#L284-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 75761#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75842#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75843#L299-1 assume !(0 == ~M_E~0); 76032#L421-1 assume !(0 == ~T1_E~0); 76033#L426-1 assume !(0 == ~T2_E~0); 75931#L431-1 assume !(0 == ~T3_E~0); 75932#L436-1 assume !(0 == ~E_M~0); 75906#L441-1 assume !(0 == ~E_1~0); 75907#L446-1 assume !(0 == ~E_2~0); 75805#L451-1 assume !(0 == ~E_3~0); 75806#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75867#L200 assume !(1 == ~m_pc~0); 75868#L200-2 is_master_triggered_~__retres1~0 := 0; 76044#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76045#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76010#L523 assume !(0 != activate_threads_~tmp~1); 76011#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76063#L219 assume !(1 == ~t1_pc~0); 76064#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 76005#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76006#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 75737#L531 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 75738#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75879#L238 assume !(1 == ~t2_pc~0); 76039#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 76040#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76029#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76030#L539 assume !(0 != activate_threads_~tmp___1~0); 75887#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75888#L257 assume !(1 == ~t3_pc~0); 75743#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 75744#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75783#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 75784#L547 assume !(0 != activate_threads_~tmp___2~0); 75965#L547-2 assume !(1 == ~M_E~0); 75755#L469-1 assume !(1 == ~T1_E~0); 75756#L474-1 assume !(1 == ~T2_E~0); 77969#L479-1 assume !(1 == ~T3_E~0); 75863#L484-1 assume !(1 == ~E_M~0); 75864#L489-1 assume !(1 == ~E_1~0); 75884#L494-1 assume !(1 == ~E_2~0); 75885#L499-1 assume !(1 == ~E_3~0); 77956#L670-1 assume !false; 77949#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 77947#L396 [2021-08-31 04:18:36,672 INFO L793 eck$LassoCheckResult]: Loop: 77947#L396 assume !false; 77945#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 77940#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 77938#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 77936#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 77933#L349 assume 0 != eval_~tmp~0; 77930#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 77927#L357 assume !(0 != eval_~tmp_ndt_1~0); 77925#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 77890#L371 assume !(0 != eval_~tmp_ndt_2~0); 77922#L368 assume !(0 == ~t2_st~0); 77920#L382 assume !(0 == ~t3_st~0); 77947#L396 [2021-08-31 04:18:36,673 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,673 INFO L82 PathProgramCache]: Analyzing trace with hash 401380835, now seen corresponding path program 1 times [2021-08-31 04:18:36,673 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,673 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411535440] [2021-08-31 04:18:36,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,674 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:36,686 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:36,686 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:36,686 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411535440] [2021-08-31 04:18:36,686 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411535440] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:36,686 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:36,686 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:36,687 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068190975] [2021-08-31 04:18:36,687 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-08-31 04:18:36,688 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:36,688 INFO L82 PathProgramCache]: Analyzing trace with hash -868461662, now seen corresponding path program 1 times [2021-08-31 04:18:36,688 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:36,688 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354029057] [2021-08-31 04:18:36,688 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:36,688 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:36,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,691 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:36,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:36,698 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:36,750 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:36,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:36,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:36,751 INFO L87 Difference]: Start difference. First operand 6645 states and 8998 transitions. cyclomatic complexity: 2356 Second operand has 3 states, 3 states have (on average 16.333333333333332) internal successors, (49), 3 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:37,038 INFO L93 Difference]: Finished difference Result 6600 states and 8938 transitions. [2021-08-31 04:18:37,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:37,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6600 states and 8938 transitions. [2021-08-31 04:18:37,053 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6542 [2021-08-31 04:18:37,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6600 states to 6600 states and 8938 transitions. [2021-08-31 04:18:37,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6600 [2021-08-31 04:18:37,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6600 [2021-08-31 04:18:37,069 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6600 states and 8938 transitions. [2021-08-31 04:18:37,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:37,073 INFO L681 BuchiCegarLoop]: Abstraction has 6600 states and 8938 transitions. [2021-08-31 04:18:37,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6600 states and 8938 transitions. [2021-08-31 04:18:37,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6600 to 6600. [2021-08-31 04:18:37,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6600 states, 6600 states have (on average 1.3542424242424242) internal successors, (8938), 6599 states have internal predecessors, (8938), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6600 states to 6600 states and 8938 transitions. [2021-08-31 04:18:37,138 INFO L704 BuchiCegarLoop]: Abstraction has 6600 states and 8938 transitions. [2021-08-31 04:18:37,138 INFO L587 BuchiCegarLoop]: Abstraction has 6600 states and 8938 transitions. [2021-08-31 04:18:37,138 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-08-31 04:18:37,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6600 states and 8938 transitions. [2021-08-31 04:18:37,149 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6542 [2021-08-31 04:18:37,149 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:37,149 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:37,150 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,150 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,150 INFO L791 eck$LassoCheckResult]: Stem: 89256#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 89195#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 89137#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 89138#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 89008#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88886#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 88887#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88978#L299-1 assume !(0 == ~M_E~0); 88979#L421-1 assume !(0 == ~T1_E~0); 89072#L426-1 assume !(0 == ~T2_E~0); 89073#L431-1 assume !(0 == ~T3_E~0); 88946#L436-1 assume !(0 == ~E_M~0); 88947#L441-1 assume !(0 == ~E_1~0); 89136#L446-1 assume !(0 == ~E_2~0); 89054#L451-1 assume !(0 == ~E_3~0); 89055#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89107#L200 assume !(1 == ~m_pc~0); 89108#L200-2 is_master_triggered_~__retres1~0 := 0; 89236#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 89220#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 89221#L523 assume !(0 != activate_threads_~tmp~1); 89184#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 89185#L219 assume !(1 == ~t1_pc~0); 89035#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 89034#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89063#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 88988#L531 assume !(0 != activate_threads_~tmp___0~0); 88989#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 89116#L238 assume !(1 == ~t2_pc~0); 89181#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 88896#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88897#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 89017#L539 assume !(0 != activate_threads_~tmp___1~0); 89018#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 89123#L257 assume !(1 == ~t3_pc~0); 88993#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 88994#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 89031#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 89032#L547 assume !(0 != activate_threads_~tmp___2~0); 89190#L547-2 assume !(1 == ~M_E~0); 89003#L469-1 assume !(1 == ~T1_E~0); 89004#L474-1 assume !(1 == ~T2_E~0); 89043#L479-1 assume !(1 == ~T3_E~0); 89044#L484-1 assume !(1 == ~E_M~0); 89104#L489-1 assume !(1 == ~E_1~0); 89121#L494-1 assume !(1 == ~E_2~0); 88995#L499-1 assume !(1 == ~E_3~0); 88996#L670-1 assume !false; 93098#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 93096#L396 [2021-08-31 04:18:37,150 INFO L793 eck$LassoCheckResult]: Loop: 93096#L396 assume !false; 93093#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 93091#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 93089#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 93087#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 93085#L349 assume 0 != eval_~tmp~0; 93083#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 93081#L357 assume !(0 != eval_~tmp_ndt_1~0); 93079#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 93019#L371 assume !(0 != eval_~tmp_ndt_2~0); 93077#L368 assume !(0 == ~t2_st~0); 93101#L382 assume !(0 == ~t3_st~0); 93096#L396 [2021-08-31 04:18:37,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,150 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 2 times [2021-08-31 04:18:37,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,151 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494808069] [2021-08-31 04:18:37,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,151 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,174 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,183 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,183 INFO L82 PathProgramCache]: Analyzing trace with hash -868461662, now seen corresponding path program 2 times [2021-08-31 04:18:37,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35693605] [2021-08-31 04:18:37,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,183 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,185 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,187 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,187 INFO L82 PathProgramCache]: Analyzing trace with hash -1222208508, now seen corresponding path program 1 times [2021-08-31 04:18:37,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214643530] [2021-08-31 04:18:37,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,187 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:37,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:37,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:37,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214643530] [2021-08-31 04:18:37,206 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214643530] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:37,206 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:37,206 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-08-31 04:18:37,206 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999173426] [2021-08-31 04:18:37,258 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:37,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:37,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:37,258 INFO L87 Difference]: Start difference. First operand 6600 states and 8938 transitions. cyclomatic complexity: 2341 Second operand has 3 states, 3 states have (on average 20.333333333333332) internal successors, (61), 3 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:37,712 INFO L93 Difference]: Finished difference Result 11726 states and 15704 transitions. [2021-08-31 04:18:37,712 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:37,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11726 states and 15704 transitions. [2021-08-31 04:18:37,749 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11660 [2021-08-31 04:18:37,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11726 states to 11726 states and 15704 transitions. [2021-08-31 04:18:37,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11726 [2021-08-31 04:18:37,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11726 [2021-08-31 04:18:37,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11726 states and 15704 transitions. [2021-08-31 04:18:37,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:37,783 INFO L681 BuchiCegarLoop]: Abstraction has 11726 states and 15704 transitions. [2021-08-31 04:18:37,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11726 states and 15704 transitions. [2021-08-31 04:18:37,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11726 to 11474. [2021-08-31 04:18:37,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11474 states, 11474 states have (on average 1.3430364301899949) internal successors, (15410), 11473 states have internal predecessors, (15410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:37,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11474 states to 11474 states and 15410 transitions. [2021-08-31 04:18:37,929 INFO L704 BuchiCegarLoop]: Abstraction has 11474 states and 15410 transitions. [2021-08-31 04:18:37,929 INFO L587 BuchiCegarLoop]: Abstraction has 11474 states and 15410 transitions. [2021-08-31 04:18:37,929 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-08-31 04:18:37,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11474 states and 15410 transitions. [2021-08-31 04:18:37,952 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11408 [2021-08-31 04:18:37,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:37,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:37,953 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,953 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:37,954 INFO L791 eck$LassoCheckResult]: Stem: 107595#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 107526#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 107474#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 107475#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 107342#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 107220#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 107221#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107312#L299-1 assume !(0 == ~M_E~0); 107313#L421-1 assume !(0 == ~T1_E~0); 107406#L426-1 assume !(0 == ~T2_E~0); 107407#L431-1 assume !(0 == ~T3_E~0); 107283#L436-1 assume !(0 == ~E_M~0); 107284#L441-1 assume !(0 == ~E_1~0); 107473#L446-1 assume !(0 == ~E_2~0); 107385#L451-1 assume !(0 == ~E_3~0); 107386#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107439#L200 assume !(1 == ~m_pc~0); 107440#L200-2 is_master_triggered_~__retres1~0 := 0; 107569#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107559#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 107560#L523 assume !(0 != activate_threads_~tmp~1); 107515#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107516#L219 assume !(1 == ~t1_pc~0); 107371#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 107370#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107399#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 107321#L531 assume !(0 != activate_threads_~tmp___0~0); 107322#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 107455#L238 assume !(1 == ~t2_pc~0); 107514#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 107231#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 107232#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 107350#L539 assume !(0 != activate_threads_~tmp___1~0); 107351#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 107462#L257 assume !(1 == ~t3_pc~0); 107327#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 107328#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 107364#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 107365#L547 assume !(0 != activate_threads_~tmp___2~0); 107520#L547-2 assume !(1 == ~M_E~0); 107339#L469-1 assume !(1 == ~T1_E~0); 107340#L474-1 assume !(1 == ~T2_E~0); 107380#L479-1 assume !(1 == ~T3_E~0); 107381#L484-1 assume !(1 == ~E_M~0); 107438#L489-1 assume !(1 == ~E_1~0); 107459#L494-1 assume !(1 == ~E_2~0); 107329#L499-1 assume !(1 == ~E_3~0); 107330#L670-1 assume !false; 110352#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 110349#L396 [2021-08-31 04:18:37,954 INFO L793 eck$LassoCheckResult]: Loop: 110349#L396 assume !false; 110331#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 110316#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 110179#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 110173#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 110148#L349 assume 0 != eval_~tmp~0; 110139#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 110130#L357 assume !(0 != eval_~tmp_ndt_1~0); 110123#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 110124#L371 assume !(0 != eval_~tmp_ndt_2~0); 110112#L368 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 110100#L385 assume !(0 != eval_~tmp_ndt_3~0); 110101#L382 assume !(0 == ~t3_st~0); 110349#L396 [2021-08-31 04:18:37,954 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,954 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 3 times [2021-08-31 04:18:37,954 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,954 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639537422] [2021-08-31 04:18:37,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,955 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,964 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,973 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,974 INFO L82 PathProgramCache]: Analyzing trace with hash -1152635119, now seen corresponding path program 1 times [2021-08-31 04:18:37,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,974 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167247069] [2021-08-31 04:18:37,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,974 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,976 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:37,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:37,980 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:37,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:37,981 INFO L82 PathProgramCache]: Analyzing trace with hash 766114543, now seen corresponding path program 1 times [2021-08-31 04:18:37,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:37,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118054178] [2021-08-31 04:18:37,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:37,981 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:37,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-08-31 04:18:37,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-08-31 04:18:37,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-08-31 04:18:37,996 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118054178] [2021-08-31 04:18:37,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [118054178] provided 1 perfect and 0 imperfect interpolant sequences [2021-08-31 04:18:37,997 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-08-31 04:18:37,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-08-31 04:18:37,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962867049] [2021-08-31 04:18:38,058 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-08-31 04:18:38,058 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-08-31 04:18:38,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-08-31 04:18:38,059 INFO L87 Difference]: Start difference. First operand 11474 states and 15410 transitions. cyclomatic complexity: 3939 Second operand has 3 states, 2 states have (on average 31.0) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:38,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-08-31 04:18:38,514 INFO L93 Difference]: Finished difference Result 19854 states and 26480 transitions. [2021-08-31 04:18:38,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-08-31 04:18:38,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19854 states and 26480 transitions. [2021-08-31 04:18:38,577 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19772 [2021-08-31 04:18:38,709 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19854 states to 19854 states and 26480 transitions. [2021-08-31 04:18:38,709 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19854 [2021-08-31 04:18:38,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19854 [2021-08-31 04:18:38,721 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19854 states and 26480 transitions. [2021-08-31 04:18:38,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-08-31 04:18:38,731 INFO L681 BuchiCegarLoop]: Abstraction has 19854 states and 26480 transitions. [2021-08-31 04:18:38,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19854 states and 26480 transitions. [2021-08-31 04:18:38,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19854 to 19686. [2021-08-31 04:18:38,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19686 states, 19686 states have (on average 1.3365843746825155) internal successors, (26312), 19685 states have internal predecessors, (26312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-08-31 04:18:38,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19686 states to 19686 states and 26312 transitions. [2021-08-31 04:18:38,890 INFO L704 BuchiCegarLoop]: Abstraction has 19686 states and 26312 transitions. [2021-08-31 04:18:38,890 INFO L587 BuchiCegarLoop]: Abstraction has 19686 states and 26312 transitions. [2021-08-31 04:18:38,890 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-08-31 04:18:38,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19686 states and 26312 transitions. [2021-08-31 04:18:39,001 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19604 [2021-08-31 04:18:39,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-08-31 04:18:39,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-08-31 04:18:39,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:39,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-08-31 04:18:39,002 INFO L791 eck$LassoCheckResult]: Stem: 138962#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 138881#L-1 havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 138818#L633 havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 138819#L277 assume 1 == ~m_i~0;~m_st~0 := 0; 138682#L284-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 138556#L289-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138557#L294-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138652#L299-1 assume !(0 == ~M_E~0); 138653#L421-1 assume !(0 == ~T1_E~0); 138748#L426-1 assume !(0 == ~T2_E~0); 138749#L431-1 assume !(0 == ~T3_E~0); 138619#L436-1 assume !(0 == ~E_M~0); 138620#L441-1 assume !(0 == ~E_1~0); 138817#L446-1 assume !(0 == ~E_2~0); 138727#L451-1 assume !(0 == ~E_3~0); 138728#L456-1 havoc activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 138784#L200 assume !(1 == ~m_pc~0); 138785#L200-2 is_master_triggered_~__retres1~0 := 0; 138932#L211 is_master_triggered_#res := is_master_triggered_~__retres1~0; 138920#L212 activate_threads_#t~ret13 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 138921#L523 assume !(0 != activate_threads_~tmp~1); 138870#L523-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 138871#L219 assume !(1 == ~t1_pc~0); 138709#L219-2 is_transmit1_triggered_~__retres1~1 := 0; 138708#L230 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 138741#L231 activate_threads_#t~ret14 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 138662#L531 assume !(0 != activate_threads_~tmp___0~0); 138663#L531-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 138795#L238 assume !(1 == ~t2_pc~0); 138869#L238-2 is_transmit2_triggered_~__retres1~2 := 0; 138567#L249 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 138568#L250 activate_threads_#t~ret15 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 138690#L539 assume !(0 != activate_threads_~tmp___1~0); 138691#L539-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 138801#L257 assume !(1 == ~t3_pc~0); 138667#L257-2 is_transmit3_triggered_~__retres1~3 := 0; 138668#L268 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 138705#L269 activate_threads_#t~ret16 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 138706#L547 assume !(0 != activate_threads_~tmp___2~0); 138876#L547-2 assume !(1 == ~M_E~0); 138679#L469-1 assume !(1 == ~T1_E~0); 138680#L474-1 assume !(1 == ~T2_E~0); 138722#L479-1 assume !(1 == ~T3_E~0); 138723#L484-1 assume !(1 == ~E_M~0); 138782#L489-1 assume !(1 == ~E_1~0); 138799#L494-1 assume !(1 == ~E_2~0); 138669#L499-1 assume !(1 == ~E_3~0); 138670#L670-1 assume !false; 145585#L671 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 145581#L396 [2021-08-31 04:18:39,002 INFO L793 eck$LassoCheckResult]: Loop: 145581#L396 assume !false; 145579#L345 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 145574#L312 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 145571#L334 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 145566#L335 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 145562#L349 assume 0 != eval_~tmp~0; 145556#L349-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 145551#L357 assume !(0 != eval_~tmp_ndt_1~0); 145544#L354 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 145494#L371 assume !(0 != eval_~tmp_ndt_2~0); 145534#L368 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 145594#L385 assume !(0 != eval_~tmp_ndt_3~0); 145590#L382 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 145233#L399 assume !(0 != eval_~tmp_ndt_4~0); 145581#L396 [2021-08-31 04:18:39,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:39,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1997423459, now seen corresponding path program 4 times [2021-08-31 04:18:39,003 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:39,003 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698428038] [2021-08-31 04:18:39,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:39,003 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:39,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,012 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:39,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,021 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:39,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:39,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1371953511, now seen corresponding path program 1 times [2021-08-31 04:18:39,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:39,022 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563861533] [2021-08-31 04:18:39,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:39,023 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:39,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,025 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:39,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,027 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:39,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-08-31 04:18:39,028 INFO L82 PathProgramCache]: Analyzing trace with hash -2020256133, now seen corresponding path program 1 times [2021-08-31 04:18:39,028 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-08-31 04:18:39,028 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163276165] [2021-08-31 04:18:39,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-08-31 04:18:39,028 INFO L128 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-08-31 04:18:39,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,036 INFO L354 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-08-31 04:18:39,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-08-31 04:18:39,051 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-08-31 04:18:40,003 FATAL L? ?]: The Plugin de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer has thrown an exception: java.lang.ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoopBenchmark.prettyprintBenchmarkData(BuchiCegarLoopBenchmark.java:178) at de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData.toString(StatisticsData.java:100) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerTimingBenchmark.toString(BuchiAutomizerTimingBenchmark.java:44) at de.uni_freiburg.informatik.ultimate.core.lib.results.StatisticsResult.getLongDescription(StatisticsResult.java:58) at de.uni_freiburg.informatik.ultimate.core.coreplugin.services.ResultService.reportResult(ResultService.java:86) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.reportResult(BuchiAutomizerObserver.java:375) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.doTerminationAnalysis(BuchiAutomizerObserver.java:161) at de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver.finish(BuchiAutomizerObserver.java:398) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) [2021-08-31 04:18:40,007 INFO L158 Benchmark]: Toolchain (without parser) took 13867.36ms. Allocated memory was 65.0MB in the beginning and 788.5MB in the end (delta: 723.5MB). Free memory was 45.4MB in the beginning and 632.5MB in the end (delta: -587.1MB). Peak memory consumption was 263.9MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,008 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 65.0MB. Free memory was 47.0MB in the beginning and 47.0MB in the end (delta: 52.8kB). There was no memory consumed. Max. memory is 16.1GB. [2021-08-31 04:18:40,008 INFO L158 Benchmark]: CACSL2BoogieTranslator took 219.85ms. Allocated memory is still 65.0MB. Free memory was 45.3MB in the beginning and 45.7MB in the end (delta: -382.3kB). Peak memory consumption was 13.7MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,008 INFO L158 Benchmark]: Boogie Procedure Inliner took 32.36ms. Allocated memory is still 65.0MB. Free memory was 45.7MB in the beginning and 42.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,009 INFO L158 Benchmark]: Boogie Preprocessor took 26.63ms. Allocated memory is still 65.0MB. Free memory was 42.0MB in the beginning and 39.1MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,009 INFO L158 Benchmark]: RCFGBuilder took 362.14ms. Allocated memory was 65.0MB in the beginning and 79.7MB in the end (delta: 14.7MB). Free memory was 39.1MB in the beginning and 50.5MB in the end (delta: -11.4MB). Peak memory consumption was 15.9MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,009 INFO L158 Benchmark]: BuchiAutomizer took 13223.05ms. Allocated memory was 79.7MB in the beginning and 788.5MB in the end (delta: 708.8MB). Free memory was 50.1MB in the beginning and 632.5MB in the end (delta: -582.4MB). Peak memory consumption was 255.3MB. Max. memory is 16.1GB. [2021-08-31 04:18:40,010 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 65.0MB. Free memory was 47.0MB in the beginning and 47.0MB in the end (delta: 52.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 219.85ms. Allocated memory is still 65.0MB. Free memory was 45.3MB in the beginning and 45.7MB in the end (delta: -382.3kB). Peak memory consumption was 13.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 32.36ms. Allocated memory is still 65.0MB. Free memory was 45.7MB in the beginning and 42.3MB in the end (delta: 3.4MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 26.63ms. Allocated memory is still 65.0MB. Free memory was 42.0MB in the beginning and 39.1MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 362.14ms. Allocated memory was 65.0MB in the beginning and 79.7MB in the end (delta: 14.7MB). Free memory was 39.1MB in the beginning and 50.5MB in the end (delta: -11.4MB). Peak memory consumption was 15.9MB. Max. memory is 16.1GB. * BuchiAutomizer took 13223.05ms. Allocated memory was 79.7MB in the beginning and 788.5MB in the end (delta: 708.8MB). Free memory was 50.1MB in the beginning and 632.5MB in the end (delta: -582.4MB). Peak memory consumption was 255.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 19686 locations. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: - ExceptionOrErrorResult: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6) de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer: ClassCastException: class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator cannot be cast to class de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData (de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsAggregator and de.uni_freiburg.informatik.ultimate.util.statistics.StatisticsData are in unnamed module of loader org.eclipse.osgi.internal.loader.EquinoxClassLoader @560348e6): de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiCegarLoopBenchmark.prettyprintBenchmarkData(BuchiCegarLoopBenchmark.java:178) RESULT: Ultimate could not prove your program: Toolchain returned no result. [2021-08-31 04:18:40,034 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request...