./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:30,509 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:30,511 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:30,534 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:30,535 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:30,536 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:30,537 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:30,539 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:30,541 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:30,541 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:30,542 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:30,543 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:30,544 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:30,545 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:30,546 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:30,547 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:30,547 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:30,548 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:30,549 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:30,551 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:30,552 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:30,553 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:30,554 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:30,555 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:30,557 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:30,557 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:30,557 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:30,558 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:30,559 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:30,559 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:30,560 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:30,560 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:30,561 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:30,562 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:30,562 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:30,563 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:30,563 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:30,564 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:30,564 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:30,565 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:30,565 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:30,567 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:30,584 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:30,584 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:30,585 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:30,585 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:30,586 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:30,586 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:30,586 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:30,587 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:30,587 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:30,587 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:30,587 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:30,587 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:30,588 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:30,588 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:30,588 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:30,588 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:30,588 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:30,589 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:30,589 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:30,589 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:30,589 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:30,589 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:30,590 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:30,590 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:30,590 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:30,590 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:30,590 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:30,591 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:30,591 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:30,591 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:30,591 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:30,592 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:30,592 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5adc3402a12b42bc2aef7c382784898827eb467d1d3955bed162b3bd231708de [2022-02-21 04:21:30,821 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:30,866 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:30,868 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:30,871 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:30,871 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:30,873 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2022-02-21 04:21:30,933 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aed8a998f/1e3751d773d247c798ef8446264f073b/FLAG3e45b02d5 [2022-02-21 04:21:31,354 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:31,356 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c [2022-02-21 04:21:31,366 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aed8a998f/1e3751d773d247c798ef8446264f073b/FLAG3e45b02d5 [2022-02-21 04:21:31,378 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/aed8a998f/1e3751d773d247c798ef8446264f073b [2022-02-21 04:21:31,381 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:31,382 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:31,384 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:31,385 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:31,387 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:31,390 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,390 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@619d1eee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31, skipping insertion in model container [2022-02-21 04:21:31,391 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,406 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:31,439 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:31,529 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2022-02-21 04:21:31,565 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:31,599 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:31,617 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-2.c[643,656] [2022-02-21 04:21:31,648 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:31,659 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:31,659 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31 WrapperNode [2022-02-21 04:21:31,659 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:31,660 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:31,660 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:31,661 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:31,667 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,673 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,707 INFO L137 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 28, statements flattened = 308 [2022-02-21 04:21:31,713 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:31,714 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:31,714 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:31,714 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:31,719 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,719 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,735 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,735 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,740 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,768 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,770 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,772 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:31,773 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:31,773 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:31,773 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:31,774 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (1/1) ... [2022-02-21 04:21:31,787 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:31,798 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:31,818 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:31,837 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:31,897 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:31,897 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:31,897 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:31,897 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:31,981 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:31,982 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:32,256 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:32,263 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:32,265 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-02-21 04:21:32,268 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:32 BoogieIcfgContainer [2022-02-21 04:21:32,270 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:32,272 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:32,273 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:32,276 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:32,277 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:32,278 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:31" (1/3) ... [2022-02-21 04:21:32,279 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@91505ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:32, skipping insertion in model container [2022-02-21 04:21:32,279 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:32,279 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:31" (2/3) ... [2022-02-21 04:21:32,280 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@91505ed and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:32, skipping insertion in model container [2022-02-21 04:21:32,280 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:32,280 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:32" (3/3) ... [2022-02-21 04:21:32,281 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-2.c [2022-02-21 04:21:32,322 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:32,323 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:32,323 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:32,323 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:32,323 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:32,323 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:32,324 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:32,324 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:32,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:32,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2022-02-21 04:21:32,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:32,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:32,419 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:32,420 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:32,420 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:32,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:32,442 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2022-02-21 04:21:32,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:32,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:32,446 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:32,446 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:32,457 INFO L791 eck$LassoCheckResult]: Stem: 101#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 30#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 65#L462true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69#L222true assume !(1 == ~q_req_up~0); 10#L222-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81#L237true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 31#L237-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 37#L242-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87#L275true assume !(0 == ~q_read_ev~0); 95#L275-2true assume !(0 == ~q_write_ev~0); 23#L280-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 107#L65true assume !(1 == ~p_dw_pc~0); 29#L65-2true is_do_write_p_triggered_~__retres1~0#1 := 0; 54#L76true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 64#L77true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 34#L315true assume !(0 != activate_threads_~tmp~1#1); 66#L315-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 99#L84true assume 1 == ~c_dr_pc~0; 25#L85true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 72#L95true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 91#L96true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5#L323true assume !(0 != activate_threads_~tmp___0~1#1); 47#L323-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100#L293true assume !(1 == ~q_read_ev~0); 3#L293-2true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 35#L298-1true assume { :end_inline_reset_delta_events } true; 11#L419-2true [2022-02-21 04:21:32,464 INFO L793 eck$LassoCheckResult]: Loop: 11#L419-2true assume !false; 27#L420true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 103#L364true assume !true; 61#L380true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83#L222-3true assume !(1 == ~q_req_up~0); 32#L222-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 80#L275-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 39#L275-5true assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 53#L280-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 62#L65-3true assume !(1 == ~p_dw_pc~0); 18#L65-5true is_do_write_p_triggered_~__retres1~0#1 := 0; 96#L76-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 73#L77-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 40#L315-3true assume !(0 != activate_threads_~tmp~1#1); 84#L315-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 58#L84-3true assume 1 == ~c_dr_pc~0; 42#L85-1true assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 79#L95-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 59#L96-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 105#L323-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 78#L323-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92#L293-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 6#L293-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 52#L298-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24#L255-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 26#L267-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 56#L268-1true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12#L394true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 8#L401true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 71#L402true start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 28#L436true assume !(0 != start_simulation_~tmp~4#1); 11#L419-2true [2022-02-21 04:21:32,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:32,475 INFO L85 PathProgramCache]: Analyzing trace with hash -239976594, now seen corresponding path program 1 times [2022-02-21 04:21:32,483 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:32,484 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336559871] [2022-02-21 04:21:32,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:32,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:32,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:32,704 INFO L290 TraceCheckUtils]: 0: Hoare triple {109#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {109#true} is VALID [2022-02-21 04:21:32,706 INFO L290 TraceCheckUtils]: 1: Hoare triple {109#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {111#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:32,707 INFO L290 TraceCheckUtils]: 2: Hoare triple {111#(= 1 ~c_dr_i~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {111#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:32,711 INFO L290 TraceCheckUtils]: 3: Hoare triple {111#(= 1 ~c_dr_i~0)} assume !(1 == ~q_req_up~0); {111#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:32,714 INFO L290 TraceCheckUtils]: 4: Hoare triple {111#(= 1 ~c_dr_i~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {111#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:32,715 INFO L290 TraceCheckUtils]: 5: Hoare triple {111#(= 1 ~c_dr_i~0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {111#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:32,717 INFO L290 TraceCheckUtils]: 6: Hoare triple {111#(= 1 ~c_dr_i~0)} assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; {110#false} is VALID [2022-02-21 04:21:32,717 INFO L290 TraceCheckUtils]: 7: Hoare triple {110#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {110#false} is VALID [2022-02-21 04:21:32,718 INFO L290 TraceCheckUtils]: 8: Hoare triple {110#false} assume !(0 == ~q_read_ev~0); {110#false} is VALID [2022-02-21 04:21:32,718 INFO L290 TraceCheckUtils]: 9: Hoare triple {110#false} assume !(0 == ~q_write_ev~0); {110#false} is VALID [2022-02-21 04:21:32,718 INFO L290 TraceCheckUtils]: 10: Hoare triple {110#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {110#false} is VALID [2022-02-21 04:21:32,719 INFO L290 TraceCheckUtils]: 11: Hoare triple {110#false} assume !(1 == ~p_dw_pc~0); {110#false} is VALID [2022-02-21 04:21:32,719 INFO L290 TraceCheckUtils]: 12: Hoare triple {110#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {110#false} is VALID [2022-02-21 04:21:32,719 INFO L290 TraceCheckUtils]: 13: Hoare triple {110#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {110#false} is VALID [2022-02-21 04:21:32,719 INFO L290 TraceCheckUtils]: 14: Hoare triple {110#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {110#false} is VALID [2022-02-21 04:21:32,719 INFO L290 TraceCheckUtils]: 15: Hoare triple {110#false} assume !(0 != activate_threads_~tmp~1#1); {110#false} is VALID [2022-02-21 04:21:32,720 INFO L290 TraceCheckUtils]: 16: Hoare triple {110#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {110#false} is VALID [2022-02-21 04:21:32,720 INFO L290 TraceCheckUtils]: 17: Hoare triple {110#false} assume 1 == ~c_dr_pc~0; {110#false} is VALID [2022-02-21 04:21:32,720 INFO L290 TraceCheckUtils]: 18: Hoare triple {110#false} assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {110#false} is VALID [2022-02-21 04:21:32,720 INFO L290 TraceCheckUtils]: 19: Hoare triple {110#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {110#false} is VALID [2022-02-21 04:21:32,720 INFO L290 TraceCheckUtils]: 20: Hoare triple {110#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {110#false} is VALID [2022-02-21 04:21:32,721 INFO L290 TraceCheckUtils]: 21: Hoare triple {110#false} assume !(0 != activate_threads_~tmp___0~1#1); {110#false} is VALID [2022-02-21 04:21:32,722 INFO L290 TraceCheckUtils]: 22: Hoare triple {110#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {110#false} is VALID [2022-02-21 04:21:32,722 INFO L290 TraceCheckUtils]: 23: Hoare triple {110#false} assume !(1 == ~q_read_ev~0); {110#false} is VALID [2022-02-21 04:21:32,722 INFO L290 TraceCheckUtils]: 24: Hoare triple {110#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {110#false} is VALID [2022-02-21 04:21:32,722 INFO L290 TraceCheckUtils]: 25: Hoare triple {110#false} assume { :end_inline_reset_delta_events } true; {110#false} is VALID [2022-02-21 04:21:32,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:32,724 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:32,724 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336559871] [2022-02-21 04:21:32,725 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336559871] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:32,725 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:32,726 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:32,728 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [137821535] [2022-02-21 04:21:32,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:32,733 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:32,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:32,735 INFO L85 PathProgramCache]: Analyzing trace with hash -573197680, now seen corresponding path program 1 times [2022-02-21 04:21:32,735 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:32,735 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714190735] [2022-02-21 04:21:32,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:32,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:32,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:32,772 INFO L290 TraceCheckUtils]: 0: Hoare triple {112#true} assume !false; {112#true} is VALID [2022-02-21 04:21:32,772 INFO L290 TraceCheckUtils]: 1: Hoare triple {112#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {112#true} is VALID [2022-02-21 04:21:32,773 INFO L290 TraceCheckUtils]: 2: Hoare triple {112#true} assume !true; {113#false} is VALID [2022-02-21 04:21:32,773 INFO L290 TraceCheckUtils]: 3: Hoare triple {113#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {113#false} is VALID [2022-02-21 04:21:32,773 INFO L290 TraceCheckUtils]: 4: Hoare triple {113#false} assume !(1 == ~q_req_up~0); {113#false} is VALID [2022-02-21 04:21:32,773 INFO L290 TraceCheckUtils]: 5: Hoare triple {113#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {113#false} is VALID [2022-02-21 04:21:32,774 INFO L290 TraceCheckUtils]: 6: Hoare triple {113#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {113#false} is VALID [2022-02-21 04:21:32,774 INFO L290 TraceCheckUtils]: 7: Hoare triple {113#false} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {113#false} is VALID [2022-02-21 04:21:32,774 INFO L290 TraceCheckUtils]: 8: Hoare triple {113#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {113#false} is VALID [2022-02-21 04:21:32,774 INFO L290 TraceCheckUtils]: 9: Hoare triple {113#false} assume !(1 == ~p_dw_pc~0); {113#false} is VALID [2022-02-21 04:21:32,775 INFO L290 TraceCheckUtils]: 10: Hoare triple {113#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {113#false} is VALID [2022-02-21 04:21:32,775 INFO L290 TraceCheckUtils]: 11: Hoare triple {113#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {113#false} is VALID [2022-02-21 04:21:32,775 INFO L290 TraceCheckUtils]: 12: Hoare triple {113#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {113#false} is VALID [2022-02-21 04:21:32,775 INFO L290 TraceCheckUtils]: 13: Hoare triple {113#false} assume !(0 != activate_threads_~tmp~1#1); {113#false} is VALID [2022-02-21 04:21:32,776 INFO L290 TraceCheckUtils]: 14: Hoare triple {113#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {113#false} is VALID [2022-02-21 04:21:32,776 INFO L290 TraceCheckUtils]: 15: Hoare triple {113#false} assume 1 == ~c_dr_pc~0; {113#false} is VALID [2022-02-21 04:21:32,777 INFO L290 TraceCheckUtils]: 16: Hoare triple {113#false} assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {113#false} is VALID [2022-02-21 04:21:32,777 INFO L290 TraceCheckUtils]: 17: Hoare triple {113#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {113#false} is VALID [2022-02-21 04:21:32,777 INFO L290 TraceCheckUtils]: 18: Hoare triple {113#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {113#false} is VALID [2022-02-21 04:21:32,777 INFO L290 TraceCheckUtils]: 19: Hoare triple {113#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {113#false} is VALID [2022-02-21 04:21:32,778 INFO L290 TraceCheckUtils]: 20: Hoare triple {113#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {113#false} is VALID [2022-02-21 04:21:32,778 INFO L290 TraceCheckUtils]: 21: Hoare triple {113#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {113#false} is VALID [2022-02-21 04:21:32,779 INFO L290 TraceCheckUtils]: 22: Hoare triple {113#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {113#false} is VALID [2022-02-21 04:21:32,784 INFO L290 TraceCheckUtils]: 23: Hoare triple {113#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {113#false} is VALID [2022-02-21 04:21:32,784 INFO L290 TraceCheckUtils]: 24: Hoare triple {113#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {113#false} is VALID [2022-02-21 04:21:32,785 INFO L290 TraceCheckUtils]: 25: Hoare triple {113#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {113#false} is VALID [2022-02-21 04:21:32,785 INFO L290 TraceCheckUtils]: 26: Hoare triple {113#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {113#false} is VALID [2022-02-21 04:21:32,786 INFO L290 TraceCheckUtils]: 27: Hoare triple {113#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {113#false} is VALID [2022-02-21 04:21:32,787 INFO L290 TraceCheckUtils]: 28: Hoare triple {113#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {113#false} is VALID [2022-02-21 04:21:32,787 INFO L290 TraceCheckUtils]: 29: Hoare triple {113#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {113#false} is VALID [2022-02-21 04:21:32,787 INFO L290 TraceCheckUtils]: 30: Hoare triple {113#false} assume !(0 != start_simulation_~tmp~4#1); {113#false} is VALID [2022-02-21 04:21:32,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:32,788 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:32,789 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714190735] [2022-02-21 04:21:32,789 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714190735] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:32,790 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:32,790 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:32,790 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864265994] [2022-02-21 04:21:32,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:32,791 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:32,793 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:32,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:32,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:32,827 INFO L87 Difference]: Start difference. First operand has 105 states, 104 states have (on average 1.5288461538461537) internal successors, (159), 104 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,000 INFO L93 Difference]: Finished difference Result 102 states and 144 transitions. [2022-02-21 04:21:33,000 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:33,002 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,023 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:33,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 144 transitions. [2022-02-21 04:21:33,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-02-21 04:21:33,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 95 states and 137 transitions. [2022-02-21 04:21:33,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2022-02-21 04:21:33,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2022-02-21 04:21:33,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 137 transitions. [2022-02-21 04:21:33,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:33,036 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-02-21 04:21:33,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 137 transitions. [2022-02-21 04:21:33,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2022-02-21 04:21:33,055 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:33,056 INFO L82 GeneralOperation]: Start isEquivalent. First operand 95 states and 137 transitions. Second operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,057 INFO L74 IsIncluded]: Start isIncluded. First operand 95 states and 137 transitions. Second operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,059 INFO L87 Difference]: Start difference. First operand 95 states and 137 transitions. Second operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,063 INFO L93 Difference]: Finished difference Result 95 states and 137 transitions. [2022-02-21 04:21:33,063 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 137 transitions. [2022-02-21 04:21:33,064 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:33,064 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:33,065 INFO L74 IsIncluded]: Start isIncluded. First operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 95 states and 137 transitions. [2022-02-21 04:21:33,065 INFO L87 Difference]: Start difference. First operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 95 states and 137 transitions. [2022-02-21 04:21:33,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,068 INFO L93 Difference]: Finished difference Result 95 states and 137 transitions. [2022-02-21 04:21:33,068 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 137 transitions. [2022-02-21 04:21:33,069 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:33,069 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:33,069 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:33,069 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:33,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.4421052631578948) internal successors, (137), 94 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 137 transitions. [2022-02-21 04:21:33,074 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-02-21 04:21:33,074 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 137 transitions. [2022-02-21 04:21:33,074 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:33,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 137 transitions. [2022-02-21 04:21:33,075 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2022-02-21 04:21:33,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:33,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:33,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:33,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:33,077 INFO L791 eck$LassoCheckResult]: Stem: 310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 252#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253#L222 assume !(1 == ~q_req_up~0); 248#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 249#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 284#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 303#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 301#L275 assume !(0 == ~q_read_ev~0); 302#L275-2 assume !(0 == ~q_write_ev~0); 288#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 289#L65 assume !(1 == ~p_dw_pc~0); 287#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 286#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 244#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 245#L315 assume !(0 != activate_threads_~tmp~1#1); 254#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 255#L84 assume 1 == ~c_dr_pc~0; 294#L85 assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 265#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 266#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 227#L323 assume !(0 != activate_threads_~tmp___0~1#1); 228#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309#L293 assume !(1 == ~q_read_ev~0); 216#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 217#L298-1 assume { :end_inline_reset_delta_events } true; 250#L419-2 [2022-02-21 04:21:33,077 INFO L793 eck$LassoCheckResult]: Loop: 250#L419-2 assume !false; 251#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 239#L364 assume !false; 290#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 262#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 221#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 269#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 270#L344 assume !(0 != eval_~tmp___1~0#1); 233#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 234#L222-3 assume !(1 == ~q_req_up~0); 295#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 283#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 308#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 235#L65-3 assume !(1 == ~p_dw_pc~0); 236#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 273#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 267#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 268#L315-3 assume !(0 != activate_threads_~tmp~1#1); 296#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 222#L84-3 assume !(1 == ~c_dr_pc~0); 224#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 281#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 225#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 226#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 279#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 231#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 232#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 291#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 292#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 218#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 219#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 242#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 243#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 264#L436 assume !(0 != start_simulation_~tmp~4#1); 250#L419-2 [2022-02-21 04:21:33,078 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:33,078 INFO L85 PathProgramCache]: Analyzing trace with hash 577671856, now seen corresponding path program 1 times [2022-02-21 04:21:33,078 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:33,078 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291359090] [2022-02-21 04:21:33,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:33,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:33,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:33,132 INFO L290 TraceCheckUtils]: 0: Hoare triple {504#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {506#(= ~q_req_up~0 0)} is VALID [2022-02-21 04:21:33,133 INFO L290 TraceCheckUtils]: 1: Hoare triple {506#(= ~q_req_up~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {507#(= ~c_dr_pc~0 ~q_req_up~0)} is VALID [2022-02-21 04:21:33,134 INFO L290 TraceCheckUtils]: 2: Hoare triple {507#(= ~c_dr_pc~0 ~q_req_up~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {507#(= ~c_dr_pc~0 ~q_req_up~0)} is VALID [2022-02-21 04:21:33,134 INFO L290 TraceCheckUtils]: 3: Hoare triple {507#(= ~c_dr_pc~0 ~q_req_up~0)} assume !(1 == ~q_req_up~0); {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,135 INFO L290 TraceCheckUtils]: 4: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,135 INFO L290 TraceCheckUtils]: 5: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,135 INFO L290 TraceCheckUtils]: 6: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,136 INFO L290 TraceCheckUtils]: 7: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,136 INFO L290 TraceCheckUtils]: 8: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume !(0 == ~q_read_ev~0); {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,137 INFO L290 TraceCheckUtils]: 9: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume !(0 == ~q_write_ev~0); {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,137 INFO L290 TraceCheckUtils]: 10: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,138 INFO L290 TraceCheckUtils]: 11: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume !(1 == ~p_dw_pc~0); {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,138 INFO L290 TraceCheckUtils]: 12: Hoare triple {508#(not (= ~c_dr_pc~0 1))} is_do_write_p_triggered_~__retres1~0#1 := 0; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,138 INFO L290 TraceCheckUtils]: 13: Hoare triple {508#(not (= ~c_dr_pc~0 1))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,139 INFO L290 TraceCheckUtils]: 14: Hoare triple {508#(not (= ~c_dr_pc~0 1))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,139 INFO L290 TraceCheckUtils]: 15: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,140 INFO L290 TraceCheckUtils]: 16: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {508#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:33,140 INFO L290 TraceCheckUtils]: 17: Hoare triple {508#(not (= ~c_dr_pc~0 1))} assume 1 == ~c_dr_pc~0; {505#false} is VALID [2022-02-21 04:21:33,140 INFO L290 TraceCheckUtils]: 18: Hoare triple {505#false} assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 19: Hoare triple {505#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 20: Hoare triple {505#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 21: Hoare triple {505#false} assume !(0 != activate_threads_~tmp___0~1#1); {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 22: Hoare triple {505#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 23: Hoare triple {505#false} assume !(1 == ~q_read_ev~0); {505#false} is VALID [2022-02-21 04:21:33,141 INFO L290 TraceCheckUtils]: 24: Hoare triple {505#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {505#false} is VALID [2022-02-21 04:21:33,142 INFO L290 TraceCheckUtils]: 25: Hoare triple {505#false} assume { :end_inline_reset_delta_events } true; {505#false} is VALID [2022-02-21 04:21:33,142 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:33,142 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:33,143 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291359090] [2022-02-21 04:21:33,143 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291359090] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:33,143 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:33,143 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:33,143 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205912804] [2022-02-21 04:21:33,143 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:33,144 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:33,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:33,144 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 1 times [2022-02-21 04:21:33,145 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:33,145 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23117584] [2022-02-21 04:21:33,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:33,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:33,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:33,193 INFO L290 TraceCheckUtils]: 0: Hoare triple {509#true} assume !false; {509#true} is VALID [2022-02-21 04:21:33,194 INFO L290 TraceCheckUtils]: 1: Hoare triple {509#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {509#true} is VALID [2022-02-21 04:21:33,194 INFO L290 TraceCheckUtils]: 2: Hoare triple {509#true} assume !false; {509#true} is VALID [2022-02-21 04:21:33,194 INFO L290 TraceCheckUtils]: 3: Hoare triple {509#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {509#true} is VALID [2022-02-21 04:21:33,195 INFO L290 TraceCheckUtils]: 4: Hoare triple {509#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {511#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:33,196 INFO L290 TraceCheckUtils]: 5: Hoare triple {511#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {512#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:33,196 INFO L290 TraceCheckUtils]: 6: Hoare triple {512#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {513#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:33,197 INFO L290 TraceCheckUtils]: 7: Hoare triple {513#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {510#false} is VALID [2022-02-21 04:21:33,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {510#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {510#false} is VALID [2022-02-21 04:21:33,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {510#false} assume !(1 == ~q_req_up~0); {510#false} is VALID [2022-02-21 04:21:33,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {510#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {510#false} is VALID [2022-02-21 04:21:33,198 INFO L290 TraceCheckUtils]: 11: Hoare triple {510#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {510#false} is VALID [2022-02-21 04:21:33,198 INFO L290 TraceCheckUtils]: 12: Hoare triple {510#false} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {510#false} is VALID [2022-02-21 04:21:33,198 INFO L290 TraceCheckUtils]: 13: Hoare triple {510#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {510#false} is VALID [2022-02-21 04:21:33,198 INFO L290 TraceCheckUtils]: 14: Hoare triple {510#false} assume !(1 == ~p_dw_pc~0); {510#false} is VALID [2022-02-21 04:21:33,199 INFO L290 TraceCheckUtils]: 15: Hoare triple {510#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {510#false} is VALID [2022-02-21 04:21:33,199 INFO L290 TraceCheckUtils]: 16: Hoare triple {510#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {510#false} is VALID [2022-02-21 04:21:33,199 INFO L290 TraceCheckUtils]: 17: Hoare triple {510#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {510#false} is VALID [2022-02-21 04:21:33,199 INFO L290 TraceCheckUtils]: 18: Hoare triple {510#false} assume !(0 != activate_threads_~tmp~1#1); {510#false} is VALID [2022-02-21 04:21:33,199 INFO L290 TraceCheckUtils]: 19: Hoare triple {510#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 20: Hoare triple {510#false} assume !(1 == ~c_dr_pc~0); {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 21: Hoare triple {510#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 22: Hoare triple {510#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 23: Hoare triple {510#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 24: Hoare triple {510#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {510#false} is VALID [2022-02-21 04:21:33,200 INFO L290 TraceCheckUtils]: 25: Hoare triple {510#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {510#false} is VALID [2022-02-21 04:21:33,201 INFO L290 TraceCheckUtils]: 26: Hoare triple {510#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {510#false} is VALID [2022-02-21 04:21:33,201 INFO L290 TraceCheckUtils]: 27: Hoare triple {510#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {510#false} is VALID [2022-02-21 04:21:33,201 INFO L290 TraceCheckUtils]: 28: Hoare triple {510#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {510#false} is VALID [2022-02-21 04:21:33,201 INFO L290 TraceCheckUtils]: 29: Hoare triple {510#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {510#false} is VALID [2022-02-21 04:21:33,201 INFO L290 TraceCheckUtils]: 30: Hoare triple {510#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {510#false} is VALID [2022-02-21 04:21:33,202 INFO L290 TraceCheckUtils]: 31: Hoare triple {510#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {510#false} is VALID [2022-02-21 04:21:33,202 INFO L290 TraceCheckUtils]: 32: Hoare triple {510#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {510#false} is VALID [2022-02-21 04:21:33,202 INFO L290 TraceCheckUtils]: 33: Hoare triple {510#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {510#false} is VALID [2022-02-21 04:21:33,202 INFO L290 TraceCheckUtils]: 34: Hoare triple {510#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {510#false} is VALID [2022-02-21 04:21:33,202 INFO L290 TraceCheckUtils]: 35: Hoare triple {510#false} assume !(0 != start_simulation_~tmp~4#1); {510#false} is VALID [2022-02-21 04:21:33,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:33,203 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:33,203 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23117584] [2022-02-21 04:21:33,203 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23117584] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:33,203 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:33,203 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:33,203 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [751827630] [2022-02-21 04:21:33,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:33,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:33,204 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:33,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:33,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:33,205 INFO L87 Difference]: Start difference. First operand 95 states and 137 transitions. cyclomatic complexity: 43 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,611 INFO L93 Difference]: Finished difference Result 312 states and 441 transitions. [2022-02-21 04:21:33,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:33,612 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,634 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:33,635 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 312 states and 441 transitions. [2022-02-21 04:21:33,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 283 [2022-02-21 04:21:33,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 312 states to 312 states and 441 transitions. [2022-02-21 04:21:33,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 312 [2022-02-21 04:21:33,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 312 [2022-02-21 04:21:33,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 441 transitions. [2022-02-21 04:21:33,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:33,654 INFO L681 BuchiCegarLoop]: Abstraction has 312 states and 441 transitions. [2022-02-21 04:21:33,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 441 transitions. [2022-02-21 04:21:33,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 298. [2022-02-21 04:21:33,663 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:33,663 INFO L82 GeneralOperation]: Start isEquivalent. First operand 312 states and 441 transitions. Second operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,664 INFO L74 IsIncluded]: Start isIncluded. First operand 312 states and 441 transitions. Second operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,664 INFO L87 Difference]: Start difference. First operand 312 states and 441 transitions. Second operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,672 INFO L93 Difference]: Finished difference Result 312 states and 441 transitions. [2022-02-21 04:21:33,673 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 441 transitions. [2022-02-21 04:21:33,674 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:33,674 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:33,674 INFO L74 IsIncluded]: Start isIncluded. First operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 312 states and 441 transitions. [2022-02-21 04:21:33,675 INFO L87 Difference]: Start difference. First operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 312 states and 441 transitions. [2022-02-21 04:21:33,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:33,681 INFO L93 Difference]: Finished difference Result 312 states and 441 transitions. [2022-02-21 04:21:33,682 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 441 transitions. [2022-02-21 04:21:33,682 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:33,683 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:33,683 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:33,683 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:33,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298 states, 298 states have (on average 1.4261744966442953) internal successors, (425), 297 states have internal predecessors, (425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:33,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298 states to 298 states and 425 transitions. [2022-02-21 04:21:33,689 INFO L704 BuchiCegarLoop]: Abstraction has 298 states and 425 transitions. [2022-02-21 04:21:33,689 INFO L587 BuchiCegarLoop]: Abstraction has 298 states and 425 transitions. [2022-02-21 04:21:33,689 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:33,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states and 425 transitions. [2022-02-21 04:21:33,690 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 270 [2022-02-21 04:21:33,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:33,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:33,691 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:33,691 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:33,691 INFO L791 eck$LassoCheckResult]: Stem: 931#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 863#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 864#L222 assume !(1 == ~q_req_up~0); 861#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 862#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 897#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 915#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 913#L275 assume !(0 == ~q_read_ev~0); 914#L275-2 assume !(0 == ~q_write_ev~0); 901#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 902#L65 assume !(1 == ~p_dw_pc~0); 900#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 899#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 857#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 858#L315 assume !(0 != activate_threads_~tmp~1#1); 867#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 868#L84 assume !(1 == ~c_dr_pc~0); 886#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 876#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 877#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 840#L323 assume !(0 != activate_threads_~tmp___0~1#1); 841#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 930#L293 assume !(1 == ~q_read_ev~0); 830#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 831#L298-1 assume { :end_inline_reset_delta_events } true; 865#L419-2 [2022-02-21 04:21:33,691 INFO L793 eck$LassoCheckResult]: Loop: 865#L419-2 assume !false; 866#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 872#L364 assume !false; 903#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 871#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 835#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 880#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 881#L344 assume !(0 != eval_~tmp___1~0#1); 846#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 847#L222-3 assume !(1 == ~q_req_up~0); 907#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1125#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1124#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 1123#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 848#L65-3 assume !(1 == ~p_dw_pc~0); 849#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 926#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 927#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 929#L315-3 assume !(0 != activate_threads_~tmp~1#1); 908#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 836#L84-3 assume !(1 == ~c_dr_pc~0); 837#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 1127#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1126#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1122#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1121#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1105#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1106#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1119#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1117#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1115#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1113#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1111#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1104#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 874#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 875#L436 assume !(0 != start_simulation_~tmp~4#1); 865#L419-2 [2022-02-21 04:21:33,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:33,693 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647375, now seen corresponding path program 1 times [2022-02-21 04:21:33,693 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:33,693 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [228320637] [2022-02-21 04:21:33,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:33,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:33,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:33,725 INFO L290 TraceCheckUtils]: 0: Hoare triple {1755#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {1755#true} is VALID [2022-02-21 04:21:33,726 INFO L290 TraceCheckUtils]: 1: Hoare triple {1755#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,726 INFO L290 TraceCheckUtils]: 2: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,726 INFO L290 TraceCheckUtils]: 3: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(1 == ~q_req_up~0); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,727 INFO L290 TraceCheckUtils]: 4: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,727 INFO L290 TraceCheckUtils]: 5: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,728 INFO L290 TraceCheckUtils]: 6: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,728 INFO L290 TraceCheckUtils]: 7: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,728 INFO L290 TraceCheckUtils]: 8: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(0 == ~q_read_ev~0); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,729 INFO L290 TraceCheckUtils]: 9: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(0 == ~q_write_ev~0); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,729 INFO L290 TraceCheckUtils]: 10: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,729 INFO L290 TraceCheckUtils]: 11: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(1 == ~p_dw_pc~0); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,730 INFO L290 TraceCheckUtils]: 12: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,730 INFO L290 TraceCheckUtils]: 13: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,730 INFO L290 TraceCheckUtils]: 14: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,731 INFO L290 TraceCheckUtils]: 15: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(0 != activate_threads_~tmp~1#1); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,731 INFO L290 TraceCheckUtils]: 16: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,731 INFO L290 TraceCheckUtils]: 17: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(1 == ~c_dr_pc~0); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,732 INFO L290 TraceCheckUtils]: 18: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,732 INFO L290 TraceCheckUtils]: 19: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,732 INFO L290 TraceCheckUtils]: 20: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,733 INFO L290 TraceCheckUtils]: 21: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(0 != activate_threads_~tmp___0~1#1); {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,733 INFO L290 TraceCheckUtils]: 22: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1757#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:33,733 INFO L290 TraceCheckUtils]: 23: Hoare triple {1757#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(1 == ~q_read_ev~0); {1758#(not (= ~q_write_ev~0 1))} is VALID [2022-02-21 04:21:33,734 INFO L290 TraceCheckUtils]: 24: Hoare triple {1758#(not (= ~q_write_ev~0 1))} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {1756#false} is VALID [2022-02-21 04:21:33,734 INFO L290 TraceCheckUtils]: 25: Hoare triple {1756#false} assume { :end_inline_reset_delta_events } true; {1756#false} is VALID [2022-02-21 04:21:33,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:33,734 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:33,734 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [228320637] [2022-02-21 04:21:33,735 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [228320637] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:33,735 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:33,735 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:33,735 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347972096] [2022-02-21 04:21:33,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:33,735 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:33,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:33,736 INFO L85 PathProgramCache]: Analyzing trace with hash -631754702, now seen corresponding path program 2 times [2022-02-21 04:21:33,736 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:33,736 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [19171000] [2022-02-21 04:21:33,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:33,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:33,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:33,770 INFO L290 TraceCheckUtils]: 0: Hoare triple {1759#true} assume !false; {1759#true} is VALID [2022-02-21 04:21:33,771 INFO L290 TraceCheckUtils]: 1: Hoare triple {1759#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {1759#true} is VALID [2022-02-21 04:21:33,771 INFO L290 TraceCheckUtils]: 2: Hoare triple {1759#true} assume !false; {1759#true} is VALID [2022-02-21 04:21:33,771 INFO L290 TraceCheckUtils]: 3: Hoare triple {1759#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1759#true} is VALID [2022-02-21 04:21:33,774 INFO L290 TraceCheckUtils]: 4: Hoare triple {1759#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1761#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:33,777 INFO L290 TraceCheckUtils]: 5: Hoare triple {1761#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1762#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:33,777 INFO L290 TraceCheckUtils]: 6: Hoare triple {1762#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {1763#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:33,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {1763#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {1760#false} is VALID [2022-02-21 04:21:33,778 INFO L290 TraceCheckUtils]: 8: Hoare triple {1760#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1760#false} is VALID [2022-02-21 04:21:33,778 INFO L290 TraceCheckUtils]: 9: Hoare triple {1760#false} assume !(1 == ~q_req_up~0); {1760#false} is VALID [2022-02-21 04:21:33,778 INFO L290 TraceCheckUtils]: 10: Hoare triple {1760#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1760#false} is VALID [2022-02-21 04:21:33,778 INFO L290 TraceCheckUtils]: 11: Hoare triple {1760#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 12: Hoare triple {1760#false} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 13: Hoare triple {1760#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 14: Hoare triple {1760#false} assume !(1 == ~p_dw_pc~0); {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 15: Hoare triple {1760#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 16: Hoare triple {1760#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {1760#false} is VALID [2022-02-21 04:21:33,779 INFO L290 TraceCheckUtils]: 17: Hoare triple {1760#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {1760#false} is VALID [2022-02-21 04:21:33,780 INFO L290 TraceCheckUtils]: 18: Hoare triple {1760#false} assume !(0 != activate_threads_~tmp~1#1); {1760#false} is VALID [2022-02-21 04:21:33,780 INFO L290 TraceCheckUtils]: 19: Hoare triple {1760#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {1760#false} is VALID [2022-02-21 04:21:33,780 INFO L290 TraceCheckUtils]: 20: Hoare triple {1760#false} assume !(1 == ~c_dr_pc~0); {1760#false} is VALID [2022-02-21 04:21:33,780 INFO L290 TraceCheckUtils]: 21: Hoare triple {1760#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {1760#false} is VALID [2022-02-21 04:21:33,780 INFO L290 TraceCheckUtils]: 22: Hoare triple {1760#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {1760#false} is VALID [2022-02-21 04:21:33,787 INFO L290 TraceCheckUtils]: 23: Hoare triple {1760#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1760#false} is VALID [2022-02-21 04:21:33,787 INFO L290 TraceCheckUtils]: 24: Hoare triple {1760#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 25: Hoare triple {1760#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 26: Hoare triple {1760#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 27: Hoare triple {1760#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 28: Hoare triple {1760#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 29: Hoare triple {1760#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1760#false} is VALID [2022-02-21 04:21:33,788 INFO L290 TraceCheckUtils]: 30: Hoare triple {1760#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L290 TraceCheckUtils]: 31: Hoare triple {1760#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L290 TraceCheckUtils]: 32: Hoare triple {1760#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L290 TraceCheckUtils]: 33: Hoare triple {1760#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L290 TraceCheckUtils]: 34: Hoare triple {1760#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L290 TraceCheckUtils]: 35: Hoare triple {1760#false} assume !(0 != start_simulation_~tmp~4#1); {1760#false} is VALID [2022-02-21 04:21:33,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:33,790 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:33,790 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [19171000] [2022-02-21 04:21:33,790 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [19171000] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:33,790 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:33,790 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:33,790 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055468773] [2022-02-21 04:21:33,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:33,791 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:33,791 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:33,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:33,792 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:33,792 INFO L87 Difference]: Start difference. First operand 298 states and 425 transitions. cyclomatic complexity: 129 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,094 INFO L93 Difference]: Finished difference Result 683 states and 947 transitions. [2022-02-21 04:21:34,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:34,094 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,112 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:34,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,138 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-02-21 04:21:34,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 683 states to 683 states and 947 transitions. [2022-02-21 04:21:34,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 683 [2022-02-21 04:21:34,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 683 [2022-02-21 04:21:34,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:34,174 INFO L681 BuchiCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-02-21 04:21:34,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2022-02-21 04:21:34,188 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:34,189 INFO L82 GeneralOperation]: Start isEquivalent. First operand 683 states and 947 transitions. Second operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,190 INFO L74 IsIncluded]: Start isIncluded. First operand 683 states and 947 transitions. Second operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,191 INFO L87 Difference]: Start difference. First operand 683 states and 947 transitions. Second operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,210 INFO L93 Difference]: Finished difference Result 683 states and 947 transitions. [2022-02-21 04:21:34,210 INFO L276 IsEmpty]: Start isEmpty. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,211 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:34,211 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:34,213 INFO L74 IsIncluded]: Start isIncluded. First operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 683 states and 947 transitions. [2022-02-21 04:21:34,214 INFO L87 Difference]: Start difference. First operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 683 states and 947 transitions. [2022-02-21 04:21:34,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,230 INFO L93 Difference]: Finished difference Result 683 states and 947 transitions. [2022-02-21 04:21:34,230 INFO L276 IsEmpty]: Start isEmpty. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,231 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:34,231 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:34,231 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:34,231 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:34,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 683 states have (on average 1.3865300146412884) internal successors, (947), 682 states have internal predecessors, (947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 947 transitions. [2022-02-21 04:21:34,248 INFO L704 BuchiCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-02-21 04:21:34,248 INFO L587 BuchiCegarLoop]: Abstraction has 683 states and 947 transitions. [2022-02-21 04:21:34,248 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:34,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 683 states and 947 transitions. [2022-02-21 04:21:34,251 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2022-02-21 04:21:34,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:34,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:34,251 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:34,252 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:34,252 INFO L791 eck$LassoCheckResult]: Stem: 2565#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 2537#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 2485#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2486#L222 assume !(1 == ~q_req_up~0); 2481#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2482#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 2519#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 2546#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2539#L275 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2540#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 2555#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2596#L65 assume !(1 == ~p_dw_pc~0); 2594#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 2593#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2592#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2591#L315 assume !(0 != activate_threads_~tmp~1#1); 2590#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2589#L84 assume !(1 == ~c_dr_pc~0); 2588#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 2587#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2586#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2585#L323 assume !(0 != activate_threads_~tmp___0~1#1); 2584#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2583#L293 assume !(1 == ~q_read_ev~0); 2582#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 2553#L298-1 assume { :end_inline_reset_delta_events } true; 2554#L419-2 [2022-02-21 04:21:34,252 INFO L793 eck$LassoCheckResult]: Loop: 2554#L419-2 assume !false; 2663#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 2494#L364 assume !false; 2658#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2659#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2644#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2645#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 2633#L344 assume !(0 != eval_~tmp___1~0#1); 2635#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2779#L222-3 assume !(1 == ~q_req_up~0); 2780#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2771#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 2772#L275-5 assume !(0 == ~q_write_ev~0); 2824#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 2821#L65-3 assume 1 == ~p_dw_pc~0; 2818#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 2816#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 2814#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2812#L315-3 assume !(0 != activate_threads_~tmp~1#1); 2810#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 2808#L84-3 assume !(1 == ~c_dr_pc~0); 2806#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 2804#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 2802#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2800#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 2798#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2795#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 2751#L293-5 assume !(1 == ~q_write_ev~0); 2750#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2713#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2712#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2704#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2705#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 2698#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2699#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2693#L436 assume !(0 != start_simulation_~tmp~4#1); 2554#L419-2 [2022-02-21 04:21:34,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:34,253 INFO L85 PathProgramCache]: Analyzing trace with hash 1964845233, now seen corresponding path program 1 times [2022-02-21 04:21:34,253 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:34,253 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209641810] [2022-02-21 04:21:34,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:34,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:34,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:34,271 INFO L290 TraceCheckUtils]: 0: Hoare triple {4502#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {4502#true} is VALID [2022-02-21 04:21:34,272 INFO L290 TraceCheckUtils]: 1: Hoare triple {4502#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,272 INFO L290 TraceCheckUtils]: 2: Hoare triple {4504#(= ~q_read_ev~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,273 INFO L290 TraceCheckUtils]: 3: Hoare triple {4504#(= ~q_read_ev~0 2)} assume !(1 == ~q_req_up~0); {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,273 INFO L290 TraceCheckUtils]: 4: Hoare triple {4504#(= ~q_read_ev~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,273 INFO L290 TraceCheckUtils]: 5: Hoare triple {4504#(= ~q_read_ev~0 2)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,274 INFO L290 TraceCheckUtils]: 6: Hoare triple {4504#(= ~q_read_ev~0 2)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,274 INFO L290 TraceCheckUtils]: 7: Hoare triple {4504#(= ~q_read_ev~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4504#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:34,274 INFO L290 TraceCheckUtils]: 8: Hoare triple {4504#(= ~q_read_ev~0 2)} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 9: Hoare triple {4503#false} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 10: Hoare triple {4503#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 11: Hoare triple {4503#false} assume !(1 == ~p_dw_pc~0); {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 12: Hoare triple {4503#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 13: Hoare triple {4503#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 14: Hoare triple {4503#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 15: Hoare triple {4503#false} assume !(0 != activate_threads_~tmp~1#1); {4503#false} is VALID [2022-02-21 04:21:34,275 INFO L290 TraceCheckUtils]: 16: Hoare triple {4503#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 17: Hoare triple {4503#false} assume !(1 == ~c_dr_pc~0); {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 18: Hoare triple {4503#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 19: Hoare triple {4503#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 20: Hoare triple {4503#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 21: Hoare triple {4503#false} assume !(0 != activate_threads_~tmp___0~1#1); {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 22: Hoare triple {4503#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4503#false} is VALID [2022-02-21 04:21:34,276 INFO L290 TraceCheckUtils]: 23: Hoare triple {4503#false} assume !(1 == ~q_read_ev~0); {4503#false} is VALID [2022-02-21 04:21:34,277 INFO L290 TraceCheckUtils]: 24: Hoare triple {4503#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {4503#false} is VALID [2022-02-21 04:21:34,277 INFO L290 TraceCheckUtils]: 25: Hoare triple {4503#false} assume { :end_inline_reset_delta_events } true; {4503#false} is VALID [2022-02-21 04:21:34,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:34,277 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:34,277 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209641810] [2022-02-21 04:21:34,277 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209641810] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:34,277 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:34,278 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:34,278 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590433481] [2022-02-21 04:21:34,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:34,278 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:34,278 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:34,278 INFO L85 PathProgramCache]: Analyzing trace with hash 27676819, now seen corresponding path program 1 times [2022-02-21 04:21:34,279 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:34,279 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516537819] [2022-02-21 04:21:34,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:34,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:34,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:34,305 INFO L290 TraceCheckUtils]: 0: Hoare triple {4505#true} assume !false; {4505#true} is VALID [2022-02-21 04:21:34,305 INFO L290 TraceCheckUtils]: 1: Hoare triple {4505#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {4505#true} is VALID [2022-02-21 04:21:34,305 INFO L290 TraceCheckUtils]: 2: Hoare triple {4505#true} assume !false; {4505#true} is VALID [2022-02-21 04:21:34,305 INFO L290 TraceCheckUtils]: 3: Hoare triple {4505#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {4505#true} is VALID [2022-02-21 04:21:34,306 INFO L290 TraceCheckUtils]: 4: Hoare triple {4505#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {4507#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:34,306 INFO L290 TraceCheckUtils]: 5: Hoare triple {4507#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {4508#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:34,306 INFO L290 TraceCheckUtils]: 6: Hoare triple {4508#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {4509#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 7: Hoare triple {4509#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {4506#false} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 8: Hoare triple {4506#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4506#false} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 9: Hoare triple {4506#false} assume !(1 == ~q_req_up~0); {4506#false} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 10: Hoare triple {4506#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4506#false} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 11: Hoare triple {4506#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {4506#false} is VALID [2022-02-21 04:21:34,307 INFO L290 TraceCheckUtils]: 12: Hoare triple {4506#false} assume !(0 == ~q_write_ev~0); {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 13: Hoare triple {4506#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 14: Hoare triple {4506#false} assume 1 == ~p_dw_pc~0; {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 15: Hoare triple {4506#false} assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 16: Hoare triple {4506#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 17: Hoare triple {4506#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 18: Hoare triple {4506#false} assume !(0 != activate_threads_~tmp~1#1); {4506#false} is VALID [2022-02-21 04:21:34,308 INFO L290 TraceCheckUtils]: 19: Hoare triple {4506#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 20: Hoare triple {4506#false} assume !(1 == ~c_dr_pc~0); {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 21: Hoare triple {4506#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 22: Hoare triple {4506#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 23: Hoare triple {4506#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 24: Hoare triple {4506#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 25: Hoare triple {4506#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 26: Hoare triple {4506#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {4506#false} is VALID [2022-02-21 04:21:34,309 INFO L290 TraceCheckUtils]: 27: Hoare triple {4506#false} assume !(1 == ~q_write_ev~0); {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 28: Hoare triple {4506#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 29: Hoare triple {4506#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 30: Hoare triple {4506#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 31: Hoare triple {4506#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 32: Hoare triple {4506#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 33: Hoare triple {4506#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4506#false} is VALID [2022-02-21 04:21:34,310 INFO L290 TraceCheckUtils]: 34: Hoare triple {4506#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {4506#false} is VALID [2022-02-21 04:21:34,311 INFO L290 TraceCheckUtils]: 35: Hoare triple {4506#false} assume !(0 != start_simulation_~tmp~4#1); {4506#false} is VALID [2022-02-21 04:21:34,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:34,311 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:34,311 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516537819] [2022-02-21 04:21:34,311 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516537819] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:34,311 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:34,312 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:34,312 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543752344] [2022-02-21 04:21:34,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:34,312 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:34,312 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:34,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:34,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:34,313 INFO L87 Difference]: Start difference. First operand 683 states and 947 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,461 INFO L93 Difference]: Finished difference Result 952 states and 1297 transitions. [2022-02-21 04:21:34,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:34,461 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,480 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:34,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 952 states and 1297 transitions. [2022-02-21 04:21:34,509 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 906 [2022-02-21 04:21:34,535 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 952 states to 952 states and 1297 transitions. [2022-02-21 04:21:34,536 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 952 [2022-02-21 04:21:34,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 952 [2022-02-21 04:21:34,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 952 states and 1297 transitions. [2022-02-21 04:21:34,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:34,537 INFO L681 BuchiCegarLoop]: Abstraction has 952 states and 1297 transitions. [2022-02-21 04:21:34,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 952 states and 1297 transitions. [2022-02-21 04:21:34,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 952 to 680. [2022-02-21 04:21:34,545 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:34,546 INFO L82 GeneralOperation]: Start isEquivalent. First operand 952 states and 1297 transitions. Second operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,547 INFO L74 IsIncluded]: Start isIncluded. First operand 952 states and 1297 transitions. Second operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,548 INFO L87 Difference]: Start difference. First operand 952 states and 1297 transitions. Second operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,573 INFO L93 Difference]: Finished difference Result 952 states and 1297 transitions. [2022-02-21 04:21:34,573 INFO L276 IsEmpty]: Start isEmpty. Operand 952 states and 1297 transitions. [2022-02-21 04:21:34,574 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:34,574 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:34,576 INFO L74 IsIncluded]: Start isIncluded. First operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 952 states and 1297 transitions. [2022-02-21 04:21:34,577 INFO L87 Difference]: Start difference. First operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 952 states and 1297 transitions. [2022-02-21 04:21:34,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,602 INFO L93 Difference]: Finished difference Result 952 states and 1297 transitions. [2022-02-21 04:21:34,602 INFO L276 IsEmpty]: Start isEmpty. Operand 952 states and 1297 transitions. [2022-02-21 04:21:34,604 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:34,604 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:34,604 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:34,604 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:34,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.3661764705882353) internal successors, (929), 679 states have internal predecessors, (929), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 929 transitions. [2022-02-21 04:21:34,619 INFO L704 BuchiCegarLoop]: Abstraction has 680 states and 929 transitions. [2022-02-21 04:21:34,619 INFO L587 BuchiCegarLoop]: Abstraction has 680 states and 929 transitions. [2022-02-21 04:21:34,619 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:34,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 929 transitions. [2022-02-21 04:21:34,622 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 636 [2022-02-21 04:21:34,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:34,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:34,622 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:34,622 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:34,623 INFO L791 eck$LassoCheckResult]: Stem: 5569#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 5544#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 5495#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5496#L222 assume !(1 == ~q_req_up~0); 5493#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5494#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 5530#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 5552#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5548#L275 assume !(0 == ~q_read_ev~0); 5549#L275-2 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 5561#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 5582#L65 assume !(1 == ~p_dw_pc~0); 5532#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 5580#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 5581#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 5559#L315 assume !(0 != activate_threads_~tmp~1#1); 5560#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 5564#L84 assume !(1 == ~c_dr_pc~0); 5565#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 5507#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 5508#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5472#L323 assume !(0 != activate_threads_~tmp___0~1#1); 5473#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5567#L293 assume !(1 == ~q_read_ev~0); 5568#L293-2 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5463#L298-1 assume { :end_inline_reset_delta_events } true; 5497#L419-2 [2022-02-21 04:21:34,623 INFO L793 eck$LassoCheckResult]: Loop: 5497#L419-2 assume !false; 5498#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 5504#L364 assume !false; 5535#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5503#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5467#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5511#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 5512#L344 assume !(0 != eval_~tmp___1~0#1); 5478#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5479#L222-3 assume !(1 == ~q_req_up~0); 5539#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5528#L275-3 assume !(0 == ~q_read_ev~0); 5529#L275-5 assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; 5562#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 6123#L65-3 assume !(1 == ~p_dw_pc~0); 6121#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 6120#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 6119#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6118#L315-3 assume !(0 != activate_threads_~tmp~1#1); 6117#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 6116#L84-3 assume !(1 == ~c_dr_pc~0); 6115#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 6114#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 6113#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6112#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 6111#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6110#L293-3 assume !(1 == ~q_read_ev~0); 6109#L293-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 5477#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 5536#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 5537#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 5464#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 5465#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 5487#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5488#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 5506#L436 assume !(0 != start_simulation_~tmp~4#1); 5497#L419-2 [2022-02-21 04:21:34,623 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:34,623 INFO L85 PathProgramCache]: Analyzing trace with hash -29299473, now seen corresponding path program 1 times [2022-02-21 04:21:34,623 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:34,624 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054173156] [2022-02-21 04:21:34,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:34,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:34,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:34,644 INFO L290 TraceCheckUtils]: 0: Hoare triple {8049#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {8049#true} is VALID [2022-02-21 04:21:34,644 INFO L290 TraceCheckUtils]: 1: Hoare triple {8049#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,645 INFO L290 TraceCheckUtils]: 2: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,645 INFO L290 TraceCheckUtils]: 3: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(1 == ~q_req_up~0); {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,645 INFO L290 TraceCheckUtils]: 4: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,646 INFO L290 TraceCheckUtils]: 5: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,646 INFO L290 TraceCheckUtils]: 6: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,646 INFO L290 TraceCheckUtils]: 7: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8051#(= ~q_write_ev~0 ~q_read_ev~0)} is VALID [2022-02-21 04:21:34,647 INFO L290 TraceCheckUtils]: 8: Hoare triple {8051#(= ~q_write_ev~0 ~q_read_ev~0)} assume !(0 == ~q_read_ev~0); {8052#(not (= ~q_write_ev~0 0))} is VALID [2022-02-21 04:21:34,647 INFO L290 TraceCheckUtils]: 9: Hoare triple {8052#(not (= ~q_write_ev~0 0))} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {8050#false} is VALID [2022-02-21 04:21:34,647 INFO L290 TraceCheckUtils]: 10: Hoare triple {8050#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {8050#false} is VALID [2022-02-21 04:21:34,647 INFO L290 TraceCheckUtils]: 11: Hoare triple {8050#false} assume !(1 == ~p_dw_pc~0); {8050#false} is VALID [2022-02-21 04:21:34,647 INFO L290 TraceCheckUtils]: 12: Hoare triple {8050#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 13: Hoare triple {8050#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 14: Hoare triple {8050#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 15: Hoare triple {8050#false} assume !(0 != activate_threads_~tmp~1#1); {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 16: Hoare triple {8050#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 17: Hoare triple {8050#false} assume !(1 == ~c_dr_pc~0); {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 18: Hoare triple {8050#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {8050#false} is VALID [2022-02-21 04:21:34,648 INFO L290 TraceCheckUtils]: 19: Hoare triple {8050#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 20: Hoare triple {8050#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 21: Hoare triple {8050#false} assume !(0 != activate_threads_~tmp___0~1#1); {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 22: Hoare triple {8050#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 23: Hoare triple {8050#false} assume !(1 == ~q_read_ev~0); {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 24: Hoare triple {8050#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L290 TraceCheckUtils]: 25: Hoare triple {8050#false} assume { :end_inline_reset_delta_events } true; {8050#false} is VALID [2022-02-21 04:21:34,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:34,650 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:34,650 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054173156] [2022-02-21 04:21:34,650 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054173156] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:34,650 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:34,650 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:34,650 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347627371] [2022-02-21 04:21:34,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:34,651 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:34,651 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:34,651 INFO L85 PathProgramCache]: Analyzing trace with hash -884233102, now seen corresponding path program 1 times [2022-02-21 04:21:34,651 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:34,651 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102727221] [2022-02-21 04:21:34,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:34,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:34,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:34,677 INFO L290 TraceCheckUtils]: 0: Hoare triple {8053#true} assume !false; {8053#true} is VALID [2022-02-21 04:21:34,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {8053#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {8053#true} is VALID [2022-02-21 04:21:34,677 INFO L290 TraceCheckUtils]: 2: Hoare triple {8053#true} assume !false; {8053#true} is VALID [2022-02-21 04:21:34,677 INFO L290 TraceCheckUtils]: 3: Hoare triple {8053#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {8053#true} is VALID [2022-02-21 04:21:34,678 INFO L290 TraceCheckUtils]: 4: Hoare triple {8053#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {8055#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:34,678 INFO L290 TraceCheckUtils]: 5: Hoare triple {8055#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {8056#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:34,679 INFO L290 TraceCheckUtils]: 6: Hoare triple {8056#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {8057#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:34,679 INFO L290 TraceCheckUtils]: 7: Hoare triple {8057#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {8054#false} is VALID [2022-02-21 04:21:34,679 INFO L290 TraceCheckUtils]: 8: Hoare triple {8054#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8054#false} is VALID [2022-02-21 04:21:34,679 INFO L290 TraceCheckUtils]: 9: Hoare triple {8054#false} assume !(1 == ~q_req_up~0); {8054#false} is VALID [2022-02-21 04:21:34,679 INFO L290 TraceCheckUtils]: 10: Hoare triple {8054#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 11: Hoare triple {8054#false} assume !(0 == ~q_read_ev~0); {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 12: Hoare triple {8054#false} assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 13: Hoare triple {8054#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 14: Hoare triple {8054#false} assume !(1 == ~p_dw_pc~0); {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 15: Hoare triple {8054#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 16: Hoare triple {8054#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 17: Hoare triple {8054#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {8054#false} is VALID [2022-02-21 04:21:34,680 INFO L290 TraceCheckUtils]: 18: Hoare triple {8054#false} assume !(0 != activate_threads_~tmp~1#1); {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 19: Hoare triple {8054#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 20: Hoare triple {8054#false} assume !(1 == ~c_dr_pc~0); {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 21: Hoare triple {8054#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 22: Hoare triple {8054#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 23: Hoare triple {8054#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 24: Hoare triple {8054#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 25: Hoare triple {8054#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8054#false} is VALID [2022-02-21 04:21:34,681 INFO L290 TraceCheckUtils]: 26: Hoare triple {8054#false} assume !(1 == ~q_read_ev~0); {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 27: Hoare triple {8054#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 28: Hoare triple {8054#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 29: Hoare triple {8054#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 30: Hoare triple {8054#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 31: Hoare triple {8054#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 32: Hoare triple {8054#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 33: Hoare triple {8054#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8054#false} is VALID [2022-02-21 04:21:34,682 INFO L290 TraceCheckUtils]: 34: Hoare triple {8054#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {8054#false} is VALID [2022-02-21 04:21:34,683 INFO L290 TraceCheckUtils]: 35: Hoare triple {8054#false} assume !(0 != start_simulation_~tmp~4#1); {8054#false} is VALID [2022-02-21 04:21:34,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:34,683 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:34,683 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102727221] [2022-02-21 04:21:34,683 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102727221] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:34,683 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:34,683 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:34,684 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27548855] [2022-02-21 04:21:34,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:34,684 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:34,684 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:34,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:34,685 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:34,685 INFO L87 Difference]: Start difference. First operand 680 states and 929 transitions. cyclomatic complexity: 251 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,868 INFO L93 Difference]: Finished difference Result 830 states and 1123 transitions. [2022-02-21 04:21:34,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-02-21 04:21:34,868 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,883 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:34,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1123 transitions. [2022-02-21 04:21:34,907 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 802 [2022-02-21 04:21:34,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1123 transitions. [2022-02-21 04:21:34,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:34,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:34,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1123 transitions. [2022-02-21 04:21:34,949 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:34,949 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1123 transitions. [2022-02-21 04:21:34,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1123 transitions. [2022-02-21 04:21:34,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 608. [2022-02-21 04:21:34,956 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:34,957 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1123 transitions. Second operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,960 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1123 transitions. Second operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,960 INFO L87 Difference]: Start difference. First operand 830 states and 1123 transitions. Second operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:34,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:34,979 INFO L93 Difference]: Finished difference Result 830 states and 1123 transitions. [2022-02-21 04:21:34,979 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1123 transitions. [2022-02-21 04:21:34,980 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:34,980 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:34,981 INFO L74 IsIncluded]: Start isIncluded. First operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1123 transitions. [2022-02-21 04:21:34,982 INFO L87 Difference]: Start difference. First operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1123 transitions. [2022-02-21 04:21:35,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,002 INFO L93 Difference]: Finished difference Result 830 states and 1123 transitions. [2022-02-21 04:21:35,003 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1123 transitions. [2022-02-21 04:21:35,004 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,004 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:35,004 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:35,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 608 states, 608 states have (on average 1.356907894736842) internal successors, (825), 607 states have internal predecessors, (825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 825 transitions. [2022-02-21 04:21:35,017 INFO L704 BuchiCegarLoop]: Abstraction has 608 states and 825 transitions. [2022-02-21 04:21:35,017 INFO L587 BuchiCegarLoop]: Abstraction has 608 states and 825 transitions. [2022-02-21 04:21:35,017 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:35,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 608 states and 825 transitions. [2022-02-21 04:21:35,019 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 580 [2022-02-21 04:21:35,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,020 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,020 INFO L791 eck$LassoCheckResult]: Stem: 8991#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 8970#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8926#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8927#L222 assume !(1 == ~q_req_up~0); 8922#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8923#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8956#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8977#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8972#L275 assume !(0 == ~q_read_ev~0); 8973#L275-2 assume !(0 == ~q_write_ev~0); 8960#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8961#L65 assume !(1 == ~p_dw_pc~0); 8958#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 8966#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8920#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8921#L315 assume !(0 != activate_threads_~tmp~1#1); 8928#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8929#L84 assume !(1 == ~c_dr_pc~0); 8946#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 8938#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8939#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8900#L323 assume !(0 != activate_threads_~tmp___0~1#1); 8901#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8987#L293 assume !(1 == ~q_read_ev~0); 8892#L293-2 assume !(1 == ~q_write_ev~0); 8893#L298-1 assume { :end_inline_reset_delta_events } true; 8984#L419-2 [2022-02-21 04:21:35,020 INFO L793 eck$LassoCheckResult]: Loop: 8984#L419-2 assume !false; 9327#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8933#L364 assume !false; 9323#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9320#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9316#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9313#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9309#L344 assume !(0 != eval_~tmp___1~0#1); 9310#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9409#L222-3 assume !(1 == ~q_req_up~0); 9406#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9403#L275-3 assume !(0 == ~q_read_ev~0); 9400#L275-5 assume !(0 == ~q_write_ev~0); 9397#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9395#L65-3 assume !(1 == ~p_dw_pc~0); 9392#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 9389#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9386#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9383#L315-3 assume !(0 != activate_threads_~tmp~1#1); 9380#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9378#L84-3 assume !(1 == ~c_dr_pc~0); 9375#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 9372#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9371#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9369#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9365#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9361#L293-3 assume !(1 == ~q_read_ev~0); 9357#L293-5 assume !(1 == ~q_write_ev~0); 9353#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9350#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9344#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9341#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9339#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 9335#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9333#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9331#L436 assume !(0 != start_simulation_~tmp~4#1); 8984#L419-2 [2022-02-21 04:21:35,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 1 times [2022-02-21 04:21:35,021 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,021 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319975010] [2022-02-21 04:21:35,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:35,030 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:35,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:35,057 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:35,057 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,057 INFO L85 PathProgramCache]: Analyzing trace with hash -338188238, now seen corresponding path program 1 times [2022-02-21 04:21:35,058 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,058 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716474626] [2022-02-21 04:21:35,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,086 INFO L290 TraceCheckUtils]: 0: Hoare triple {11163#true} assume !false; {11163#true} is VALID [2022-02-21 04:21:35,087 INFO L290 TraceCheckUtils]: 1: Hoare triple {11163#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {11163#true} is VALID [2022-02-21 04:21:35,087 INFO L290 TraceCheckUtils]: 2: Hoare triple {11163#true} assume !false; {11163#true} is VALID [2022-02-21 04:21:35,087 INFO L290 TraceCheckUtils]: 3: Hoare triple {11163#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {11163#true} is VALID [2022-02-21 04:21:35,087 INFO L290 TraceCheckUtils]: 4: Hoare triple {11163#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {11165#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:35,088 INFO L290 TraceCheckUtils]: 5: Hoare triple {11165#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {11166#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:35,088 INFO L290 TraceCheckUtils]: 6: Hoare triple {11166#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {11167#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:35,088 INFO L290 TraceCheckUtils]: 7: Hoare triple {11167#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 8: Hoare triple {11164#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 9: Hoare triple {11164#false} assume !(1 == ~q_req_up~0); {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 10: Hoare triple {11164#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 11: Hoare triple {11164#false} assume !(0 == ~q_read_ev~0); {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 12: Hoare triple {11164#false} assume !(0 == ~q_write_ev~0); {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 13: Hoare triple {11164#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {11164#false} is VALID [2022-02-21 04:21:35,089 INFO L290 TraceCheckUtils]: 14: Hoare triple {11164#false} assume !(1 == ~p_dw_pc~0); {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 15: Hoare triple {11164#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 16: Hoare triple {11164#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 17: Hoare triple {11164#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 18: Hoare triple {11164#false} assume !(0 != activate_threads_~tmp~1#1); {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 19: Hoare triple {11164#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 20: Hoare triple {11164#false} assume !(1 == ~c_dr_pc~0); {11164#false} is VALID [2022-02-21 04:21:35,090 INFO L290 TraceCheckUtils]: 21: Hoare triple {11164#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 22: Hoare triple {11164#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 23: Hoare triple {11164#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 24: Hoare triple {11164#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 25: Hoare triple {11164#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 26: Hoare triple {11164#false} assume !(1 == ~q_read_ev~0); {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 27: Hoare triple {11164#false} assume !(1 == ~q_write_ev~0); {11164#false} is VALID [2022-02-21 04:21:35,091 INFO L290 TraceCheckUtils]: 28: Hoare triple {11164#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 29: Hoare triple {11164#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 30: Hoare triple {11164#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 31: Hoare triple {11164#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 32: Hoare triple {11164#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 33: Hoare triple {11164#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 34: Hoare triple {11164#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {11164#false} is VALID [2022-02-21 04:21:35,092 INFO L290 TraceCheckUtils]: 35: Hoare triple {11164#false} assume !(0 != start_simulation_~tmp~4#1); {11164#false} is VALID [2022-02-21 04:21:35,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,093 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,093 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716474626] [2022-02-21 04:21:35,093 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716474626] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,093 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,094 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:35,094 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766656217] [2022-02-21 04:21:35,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,094 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:35,094 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:35,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:35,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:35,095 INFO L87 Difference]: Start difference. First operand 608 states and 825 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,362 INFO L93 Difference]: Finished difference Result 919 states and 1233 transitions. [2022-02-21 04:21:35,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:21:35,362 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,388 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:35,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 919 states and 1233 transitions. [2022-02-21 04:21:35,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 890 [2022-02-21 04:21:35,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 919 states to 919 states and 1233 transitions. [2022-02-21 04:21:35,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 919 [2022-02-21 04:21:35,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 919 [2022-02-21 04:21:35,456 INFO L73 IsDeterministic]: Start isDeterministic. Operand 919 states and 1233 transitions. [2022-02-21 04:21:35,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:35,457 INFO L681 BuchiCegarLoop]: Abstraction has 919 states and 1233 transitions. [2022-02-21 04:21:35,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 919 states and 1233 transitions. [2022-02-21 04:21:35,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 919 to 635. [2022-02-21 04:21:35,464 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:35,465 INFO L82 GeneralOperation]: Start isEquivalent. First operand 919 states and 1233 transitions. Second operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,466 INFO L74 IsIncluded]: Start isIncluded. First operand 919 states and 1233 transitions. Second operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,467 INFO L87 Difference]: Start difference. First operand 919 states and 1233 transitions. Second operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,497 INFO L93 Difference]: Finished difference Result 919 states and 1233 transitions. [2022-02-21 04:21:35,497 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1233 transitions. [2022-02-21 04:21:35,498 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,498 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,500 INFO L74 IsIncluded]: Start isIncluded. First operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 919 states and 1233 transitions. [2022-02-21 04:21:35,501 INFO L87 Difference]: Start difference. First operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 919 states and 1233 transitions. [2022-02-21 04:21:35,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,547 INFO L93 Difference]: Finished difference Result 919 states and 1233 transitions. [2022-02-21 04:21:35,547 INFO L276 IsEmpty]: Start isEmpty. Operand 919 states and 1233 transitions. [2022-02-21 04:21:35,549 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,549 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,549 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:35,549 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:35,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 635 states, 635 states have (on average 1.3417322834645669) internal successors, (852), 634 states have internal predecessors, (852), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 635 states to 635 states and 852 transitions. [2022-02-21 04:21:35,565 INFO L704 BuchiCegarLoop]: Abstraction has 635 states and 852 transitions. [2022-02-21 04:21:35,565 INFO L587 BuchiCegarLoop]: Abstraction has 635 states and 852 transitions. [2022-02-21 04:21:35,566 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:35,566 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 635 states and 852 transitions. [2022-02-21 04:21:35,568 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 607 [2022-02-21 04:21:35,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,569 INFO L791 eck$LassoCheckResult]: Stem: 12204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 12178#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 12130#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12131#L222 assume !(1 == ~q_req_up~0); 12128#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12129#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 12164#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 12184#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12181#L275 assume !(0 == ~q_read_ev~0); 12182#L275-2 assume !(0 == ~q_write_ev~0); 12167#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12168#L65 assume !(1 == ~p_dw_pc~0); 12166#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 12176#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 12123#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12124#L315 assume !(0 != activate_threads_~tmp~1#1); 12134#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 12135#L84 assume !(1 == ~c_dr_pc~0); 12153#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 12142#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12143#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12106#L323 assume !(0 != activate_threads_~tmp___0~1#1); 12107#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12203#L293 assume !(1 == ~q_read_ev~0); 12095#L293-2 assume !(1 == ~q_write_ev~0); 12096#L298-1 assume { :end_inline_reset_delta_events } true; 12191#L419-2 [2022-02-21 04:21:35,569 INFO L793 eck$LassoCheckResult]: Loop: 12191#L419-2 assume !false; 12623#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 12139#L364 assume !false; 12619#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12618#L255 assume !(0 == ~p_dw_st~0); 12617#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 12615#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12547#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 12548#L344 assume !(0 != eval_~tmp___1~0#1); 12607#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12674#L222-3 assume !(1 == ~q_req_up~0); 12673#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12672#L275-3 assume !(0 == ~q_read_ev~0); 12671#L275-5 assume !(0 == ~q_write_ev~0); 12670#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 12669#L65-3 assume !(1 == ~p_dw_pc~0); 12667#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 12666#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 12665#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12664#L315-3 assume !(0 != activate_threads_~tmp~1#1); 12663#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 12662#L84-3 assume !(1 == ~c_dr_pc~0); 12661#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 12660#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 12659#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12658#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 12657#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12656#L293-3 assume !(1 == ~q_read_ev~0); 12655#L293-5 assume !(1 == ~q_write_ev~0); 12654#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12653#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12636#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12634#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 12632#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 12630#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12628#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 12626#L436 assume !(0 != start_simulation_~tmp~4#1); 12191#L419-2 [2022-02-21 04:21:35,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 2 times [2022-02-21 04:21:35,570 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,570 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803826775] [2022-02-21 04:21:35,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:35,577 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:35,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:35,585 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:35,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,586 INFO L85 PathProgramCache]: Analyzing trace with hash 22665520, now seen corresponding path program 1 times [2022-02-21 04:21:35,586 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,587 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1370912983] [2022-02-21 04:21:35,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,606 INFO L290 TraceCheckUtils]: 0: Hoare triple {14573#true} assume !false; {14573#true} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 1: Hoare triple {14573#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {14573#true} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 2: Hoare triple {14573#true} assume !false; {14573#true} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 3: Hoare triple {14573#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {14573#true} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 4: Hoare triple {14573#true} assume !(0 == ~p_dw_st~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 5: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 6: Hoare triple {14575#(not (= ~p_dw_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 7: Hoare triple {14575#(not (= ~p_dw_st~0 0))} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 8: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(0 != eval_~tmp___1~0#1); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 9: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 10: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(1 == ~q_req_up~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 11: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 12: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(0 == ~q_read_ev~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,611 INFO L290 TraceCheckUtils]: 13: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(0 == ~q_write_ev~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,611 INFO L290 TraceCheckUtils]: 14: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,611 INFO L290 TraceCheckUtils]: 15: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(1 == ~p_dw_pc~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,612 INFO L290 TraceCheckUtils]: 16: Hoare triple {14575#(not (= ~p_dw_st~0 0))} is_do_write_p_triggered_~__retres1~0#1 := 0; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,612 INFO L290 TraceCheckUtils]: 17: Hoare triple {14575#(not (= ~p_dw_st~0 0))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,612 INFO L290 TraceCheckUtils]: 18: Hoare triple {14575#(not (= ~p_dw_st~0 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,613 INFO L290 TraceCheckUtils]: 19: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,613 INFO L290 TraceCheckUtils]: 20: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,613 INFO L290 TraceCheckUtils]: 21: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(1 == ~c_dr_pc~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,614 INFO L290 TraceCheckUtils]: 22: Hoare triple {14575#(not (= ~p_dw_st~0 0))} is_do_read_c_triggered_~__retres1~1#1 := 0; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,614 INFO L290 TraceCheckUtils]: 23: Hoare triple {14575#(not (= ~p_dw_st~0 0))} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,615 INFO L290 TraceCheckUtils]: 24: Hoare triple {14575#(not (= ~p_dw_st~0 0))} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,615 INFO L290 TraceCheckUtils]: 25: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,615 INFO L290 TraceCheckUtils]: 26: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 27: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(1 == ~q_read_ev~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 28: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume !(1 == ~q_write_ev~0); {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 29: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {14575#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 30: Hoare triple {14575#(not (= ~p_dw_st~0 0))} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {14574#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 31: Hoare triple {14574#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {14574#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 32: Hoare triple {14574#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {14574#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 33: Hoare triple {14574#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {14574#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 34: Hoare triple {14574#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14574#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 35: Hoare triple {14574#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {14574#false} is VALID [2022-02-21 04:21:35,618 INFO L290 TraceCheckUtils]: 36: Hoare triple {14574#false} assume !(0 != start_simulation_~tmp~4#1); {14574#false} is VALID [2022-02-21 04:21:35,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,618 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,618 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1370912983] [2022-02-21 04:21:35,618 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1370912983] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,618 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,619 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:35,619 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [69831383] [2022-02-21 04:21:35,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,619 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:35,619 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:35,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:35,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:35,620 INFO L87 Difference]: Start difference. First operand 635 states and 852 transitions. cyclomatic complexity: 219 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,745 INFO L93 Difference]: Finished difference Result 930 states and 1190 transitions. [2022-02-21 04:21:35,745 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:35,746 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,768 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:35,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,791 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-02-21 04:21:35,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 930 states to 930 states and 1190 transitions. [2022-02-21 04:21:35,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 930 [2022-02-21 04:21:35,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 930 [2022-02-21 04:21:35,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:35,815 INFO L681 BuchiCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-02-21 04:21:35,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 930 to 930. [2022-02-21 04:21:35,823 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:35,825 INFO L82 GeneralOperation]: Start isEquivalent. First operand 930 states and 1190 transitions. Second operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,826 INFO L74 IsIncluded]: Start isIncluded. First operand 930 states and 1190 transitions. Second operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,827 INFO L87 Difference]: Start difference. First operand 930 states and 1190 transitions. Second operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,848 INFO L93 Difference]: Finished difference Result 930 states and 1190 transitions. [2022-02-21 04:21:35,848 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,849 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,849 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,851 INFO L74 IsIncluded]: Start isIncluded. First operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 930 states and 1190 transitions. [2022-02-21 04:21:35,852 INFO L87 Difference]: Start difference. First operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 930 states and 1190 transitions. [2022-02-21 04:21:35,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,873 INFO L93 Difference]: Finished difference Result 930 states and 1190 transitions. [2022-02-21 04:21:35,873 INFO L276 IsEmpty]: Start isEmpty. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,874 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,874 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,875 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:35,875 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:35,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 930 states, 930 states have (on average 1.2795698924731183) internal successors, (1190), 929 states have internal predecessors, (1190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 930 states to 930 states and 1190 transitions. [2022-02-21 04:21:35,896 INFO L704 BuchiCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-02-21 04:21:35,897 INFO L587 BuchiCegarLoop]: Abstraction has 930 states and 1190 transitions. [2022-02-21 04:21:35,897 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:35,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 930 states and 1190 transitions. [2022-02-21 04:21:35,899 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-02-21 04:21:35,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,900 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,900 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,900 INFO L791 eck$LassoCheckResult]: Stem: 15631#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 15595#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 15541#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15542#L222 assume !(1 == ~q_req_up~0); 15539#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15540#L237 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 15577#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 15618#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15619#L275 assume !(0 == ~q_read_ev~0); 15620#L275-2 assume !(0 == ~q_write_ev~0); 15621#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 15646#L65 assume !(1 == ~p_dw_pc~0); 15580#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 15644#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 15645#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 15611#L315 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 15545#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 15546#L84 assume !(1 == ~c_dr_pc~0); 15564#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 15565#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 15605#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15606#L323 assume !(0 != activate_threads_~tmp___0~1#1); 15637#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15638#L293 assume !(1 == ~q_read_ev~0); 15506#L293-2 assume !(1 == ~q_write_ev~0); 15507#L298-1 assume { :end_inline_reset_delta_events } true; 15699#L419-2 [2022-02-21 04:21:35,900 INFO L793 eck$LassoCheckResult]: Loop: 15699#L419-2 assume !false; 15698#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 15697#L364 assume !false; 15696#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15694#L255 assume !(0 == ~p_dw_st~0); 15695#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 15734#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15733#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 15732#L344 assume !(0 != eval_~tmp___1~0#1); 15731#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15730#L222-3 assume !(1 == ~q_req_up~0); 15729#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15728#L275-3 assume !(0 == ~q_read_ev~0); 15727#L275-5 assume !(0 == ~q_write_ev~0); 15726#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 15725#L65-3 assume !(1 == ~p_dw_pc~0); 15723#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 15722#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 15721#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 15719#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 15718#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 15717#L84-3 assume !(1 == ~c_dr_pc~0); 15716#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 15714#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 15713#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 15712#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 15711#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15710#L293-3 assume !(1 == ~q_read_ev~0); 15709#L293-5 assume !(1 == ~q_write_ev~0); 15708#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 15706#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 15705#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 15704#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 15703#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 15702#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15701#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 15700#L436 assume !(0 != start_simulation_~tmp~4#1); 15699#L419-2 [2022-02-21 04:21:35,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,901 INFO L85 PathProgramCache]: Analyzing trace with hash -1896010065, now seen corresponding path program 1 times [2022-02-21 04:21:35,901 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,901 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631250165] [2022-02-21 04:21:35,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,915 INFO L290 TraceCheckUtils]: 0: Hoare triple {18299#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {18299#true} is VALID [2022-02-21 04:21:35,916 INFO L290 TraceCheckUtils]: 1: Hoare triple {18299#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {18301#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:35,916 INFO L290 TraceCheckUtils]: 2: Hoare triple {18301#(= ~p_dw_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18301#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:35,917 INFO L290 TraceCheckUtils]: 3: Hoare triple {18301#(= ~p_dw_i~0 1)} assume !(1 == ~q_req_up~0); {18301#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:35,917 INFO L290 TraceCheckUtils]: 4: Hoare triple {18301#(= ~p_dw_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18301#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:35,917 INFO L290 TraceCheckUtils]: 5: Hoare triple {18301#(= ~p_dw_i~0 1)} assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; {18300#false} is VALID [2022-02-21 04:21:35,917 INFO L290 TraceCheckUtils]: 6: Hoare triple {18300#false} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 7: Hoare triple {18300#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 8: Hoare triple {18300#false} assume !(0 == ~q_read_ev~0); {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 9: Hoare triple {18300#false} assume !(0 == ~q_write_ev~0); {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 10: Hoare triple {18300#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 11: Hoare triple {18300#false} assume !(1 == ~p_dw_pc~0); {18300#false} is VALID [2022-02-21 04:21:35,918 INFO L290 TraceCheckUtils]: 12: Hoare triple {18300#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 13: Hoare triple {18300#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 14: Hoare triple {18300#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 15: Hoare triple {18300#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 16: Hoare triple {18300#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 17: Hoare triple {18300#false} assume !(1 == ~c_dr_pc~0); {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 18: Hoare triple {18300#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {18300#false} is VALID [2022-02-21 04:21:35,919 INFO L290 TraceCheckUtils]: 19: Hoare triple {18300#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 20: Hoare triple {18300#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 21: Hoare triple {18300#false} assume !(0 != activate_threads_~tmp___0~1#1); {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 22: Hoare triple {18300#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 23: Hoare triple {18300#false} assume !(1 == ~q_read_ev~0); {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 24: Hoare triple {18300#false} assume !(1 == ~q_write_ev~0); {18300#false} is VALID [2022-02-21 04:21:35,920 INFO L290 TraceCheckUtils]: 25: Hoare triple {18300#false} assume { :end_inline_reset_delta_events } true; {18300#false} is VALID [2022-02-21 04:21:35,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,921 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,921 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631250165] [2022-02-21 04:21:35,921 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631250165] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,921 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,921 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:35,922 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583315125] [2022-02-21 04:21:35,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,922 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:35,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,923 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 1 times [2022-02-21 04:21:35,923 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,923 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573673340] [2022-02-21 04:21:35,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,979 INFO L290 TraceCheckUtils]: 0: Hoare triple {18302#true} assume !false; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 1: Hoare triple {18302#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 2: Hoare triple {18302#true} assume !false; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 3: Hoare triple {18302#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 4: Hoare triple {18302#true} assume !(0 == ~p_dw_st~0); {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 5: Hoare triple {18302#true} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 6: Hoare triple {18302#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {18302#true} is VALID [2022-02-21 04:21:35,980 INFO L290 TraceCheckUtils]: 7: Hoare triple {18302#true} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 8: Hoare triple {18302#true} assume !(0 != eval_~tmp___1~0#1); {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 9: Hoare triple {18302#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 10: Hoare triple {18302#true} assume !(1 == ~q_req_up~0); {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 11: Hoare triple {18302#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 12: Hoare triple {18302#true} assume !(0 == ~q_read_ev~0); {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 13: Hoare triple {18302#true} assume !(0 == ~q_write_ev~0); {18302#true} is VALID [2022-02-21 04:21:35,981 INFO L290 TraceCheckUtils]: 14: Hoare triple {18302#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {18302#true} is VALID [2022-02-21 04:21:35,982 INFO L290 TraceCheckUtils]: 15: Hoare triple {18302#true} assume !(1 == ~p_dw_pc~0); {18302#true} is VALID [2022-02-21 04:21:35,982 INFO L290 TraceCheckUtils]: 16: Hoare triple {18302#true} is_do_write_p_triggered_~__retres1~0#1 := 0; {18304#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:35,983 INFO L290 TraceCheckUtils]: 17: Hoare triple {18304#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {18305#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:35,984 INFO L290 TraceCheckUtils]: 18: Hoare triple {18305#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {18306#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:35,984 INFO L290 TraceCheckUtils]: 19: Hoare triple {18306#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {18303#false} is VALID [2022-02-21 04:21:35,984 INFO L290 TraceCheckUtils]: 20: Hoare triple {18303#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {18303#false} is VALID [2022-02-21 04:21:35,984 INFO L290 TraceCheckUtils]: 21: Hoare triple {18303#false} assume !(1 == ~c_dr_pc~0); {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 22: Hoare triple {18303#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 23: Hoare triple {18303#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 24: Hoare triple {18303#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 25: Hoare triple {18303#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 26: Hoare triple {18303#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 27: Hoare triple {18303#false} assume !(1 == ~q_read_ev~0); {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 28: Hoare triple {18303#false} assume !(1 == ~q_write_ev~0); {18303#false} is VALID [2022-02-21 04:21:35,985 INFO L290 TraceCheckUtils]: 29: Hoare triple {18303#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 30: Hoare triple {18303#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 31: Hoare triple {18303#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 32: Hoare triple {18303#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 33: Hoare triple {18303#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 34: Hoare triple {18303#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 35: Hoare triple {18303#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {18303#false} is VALID [2022-02-21 04:21:35,986 INFO L290 TraceCheckUtils]: 36: Hoare triple {18303#false} assume !(0 != start_simulation_~tmp~4#1); {18303#false} is VALID [2022-02-21 04:21:35,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,987 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,987 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573673340] [2022-02-21 04:21:35,987 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573673340] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,988 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,988 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:35,988 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307129026] [2022-02-21 04:21:35,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:35,988 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:35,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:35,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:35,989 INFO L87 Difference]: Start difference. First operand 930 states and 1190 transitions. cyclomatic complexity: 262 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,101 INFO L93 Difference]: Finished difference Result 909 states and 1165 transitions. [2022-02-21 04:21:36,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:36,101 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,120 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:36,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,161 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-02-21 04:21:36,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 909 states to 909 states and 1165 transitions. [2022-02-21 04:21:36,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 909 [2022-02-21 04:21:36,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 909 [2022-02-21 04:21:36,186 INFO L73 IsDeterministic]: Start isDeterministic. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:36,187 INFO L681 BuchiCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-02-21 04:21:36,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 909. [2022-02-21 04:21:36,200 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:36,203 INFO L82 GeneralOperation]: Start isEquivalent. First operand 909 states and 1165 transitions. Second operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,205 INFO L74 IsIncluded]: Start isIncluded. First operand 909 states and 1165 transitions. Second operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,208 INFO L87 Difference]: Start difference. First operand 909 states and 1165 transitions. Second operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,232 INFO L93 Difference]: Finished difference Result 909 states and 1165 transitions. [2022-02-21 04:21:36,233 INFO L276 IsEmpty]: Start isEmpty. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,234 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:36,234 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:36,236 INFO L74 IsIncluded]: Start isIncluded. First operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 909 states and 1165 transitions. [2022-02-21 04:21:36,237 INFO L87 Difference]: Start difference. First operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 909 states and 1165 transitions. [2022-02-21 04:21:36,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,261 INFO L93 Difference]: Finished difference Result 909 states and 1165 transitions. [2022-02-21 04:21:36,261 INFO L276 IsEmpty]: Start isEmpty. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,262 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:36,263 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:36,263 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:36,263 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:36,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.2816281628162816) internal successors, (1165), 908 states have internal predecessors, (1165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1165 transitions. [2022-02-21 04:21:36,300 INFO L704 BuchiCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-02-21 04:21:36,300 INFO L587 BuchiCegarLoop]: Abstraction has 909 states and 1165 transitions. [2022-02-21 04:21:36,300 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:36,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1165 transitions. [2022-02-21 04:21:36,304 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2022-02-21 04:21:36,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:36,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:36,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:36,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:36,305 INFO L791 eck$LassoCheckResult]: Stem: 19327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 19304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 19253#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19254#L222 assume !(1 == ~q_req_up~0); 19249#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19250#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 19287#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 19310#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19307#L275 assume !(0 == ~q_read_ev~0); 19308#L275-2 assume !(0 == ~q_write_ev~0); 19292#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 19293#L65 assume !(1 == ~p_dw_pc~0); 19289#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 19300#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 19247#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 19248#L315 assume !(0 != activate_threads_~tmp~1#1); 19255#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 19256#L84 assume !(1 == ~c_dr_pc~0); 19274#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 19266#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 19267#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19227#L323 assume !(0 != activate_threads_~tmp___0~1#1); 19228#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19324#L293 assume !(1 == ~q_read_ev~0); 19218#L293-2 assume !(1 == ~q_write_ev~0); 19219#L298-1 assume { :end_inline_reset_delta_events } true; 19319#L419-2 [2022-02-21 04:21:36,306 INFO L793 eck$LassoCheckResult]: Loop: 19319#L419-2 assume !false; 19375#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 19374#L364 assume !false; 19373#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 19371#L255 assume !(0 == ~p_dw_st~0); 19372#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 19411#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 19409#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 19407#L344 assume !(0 != eval_~tmp___1~0#1); 19406#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19405#L222-3 assume !(1 == ~q_req_up~0); 19404#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19403#L275-3 assume !(0 == ~q_read_ev~0); 19402#L275-5 assume !(0 == ~q_write_ev~0); 19401#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 19400#L65-3 assume !(1 == ~p_dw_pc~0); 19398#L65-5 is_do_write_p_triggered_~__retres1~0#1 := 0; 19397#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 19396#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 19394#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 19393#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 19392#L84-3 assume !(1 == ~c_dr_pc~0); 19391#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 19390#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 19389#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 19388#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 19387#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19386#L293-3 assume !(1 == ~q_read_ev~0); 19385#L293-5 assume !(1 == ~q_write_ev~0); 19384#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 19382#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 19381#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 19380#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 19379#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 19378#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19377#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 19376#L436 assume !(0 != start_simulation_~tmp~4#1); 19319#L419-2 [2022-02-21 04:21:36,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:36,306 INFO L85 PathProgramCache]: Analyzing trace with hash -1617647313, now seen corresponding path program 3 times [2022-02-21 04:21:36,306 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:36,307 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142483014] [2022-02-21 04:21:36,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:36,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:36,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:36,315 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:36,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:36,324 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:36,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:36,325 INFO L85 PathProgramCache]: Analyzing trace with hash 2016810226, now seen corresponding path program 2 times [2022-02-21 04:21:36,325 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:36,325 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953548760] [2022-02-21 04:21:36,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:36,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:36,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:36,369 INFO L290 TraceCheckUtils]: 0: Hoare triple {21948#true} assume !false; {21948#true} is VALID [2022-02-21 04:21:36,369 INFO L290 TraceCheckUtils]: 1: Hoare triple {21948#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {21948#true} is VALID [2022-02-21 04:21:36,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {21948#true} assume !false; {21948#true} is VALID [2022-02-21 04:21:36,369 INFO L290 TraceCheckUtils]: 3: Hoare triple {21948#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {21948#true} is VALID [2022-02-21 04:21:36,369 INFO L290 TraceCheckUtils]: 4: Hoare triple {21948#true} assume !(0 == ~p_dw_st~0); {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 5: Hoare triple {21948#true} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 6: Hoare triple {21948#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 7: Hoare triple {21948#true} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 8: Hoare triple {21948#true} assume !(0 != eval_~tmp___1~0#1); {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 9: Hoare triple {21948#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 10: Hoare triple {21948#true} assume !(1 == ~q_req_up~0); {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 11: Hoare triple {21948#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {21948#true} is VALID [2022-02-21 04:21:36,370 INFO L290 TraceCheckUtils]: 12: Hoare triple {21948#true} assume !(0 == ~q_read_ev~0); {21948#true} is VALID [2022-02-21 04:21:36,371 INFO L290 TraceCheckUtils]: 13: Hoare triple {21948#true} assume !(0 == ~q_write_ev~0); {21948#true} is VALID [2022-02-21 04:21:36,371 INFO L290 TraceCheckUtils]: 14: Hoare triple {21948#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {21948#true} is VALID [2022-02-21 04:21:36,371 INFO L290 TraceCheckUtils]: 15: Hoare triple {21948#true} assume !(1 == ~p_dw_pc~0); {21948#true} is VALID [2022-02-21 04:21:36,371 INFO L290 TraceCheckUtils]: 16: Hoare triple {21948#true} is_do_write_p_triggered_~__retres1~0#1 := 0; {21950#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:36,372 INFO L290 TraceCheckUtils]: 17: Hoare triple {21950#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {21951#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:36,372 INFO L290 TraceCheckUtils]: 18: Hoare triple {21951#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {21952#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 19: Hoare triple {21952#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {21949#false} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 20: Hoare triple {21949#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {21949#false} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 21: Hoare triple {21949#false} assume !(1 == ~c_dr_pc~0); {21949#false} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 22: Hoare triple {21949#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {21949#false} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 23: Hoare triple {21949#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {21949#false} is VALID [2022-02-21 04:21:36,373 INFO L290 TraceCheckUtils]: 24: Hoare triple {21949#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 25: Hoare triple {21949#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 26: Hoare triple {21949#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 27: Hoare triple {21949#false} assume !(1 == ~q_read_ev~0); {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 28: Hoare triple {21949#false} assume !(1 == ~q_write_ev~0); {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 29: Hoare triple {21949#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 30: Hoare triple {21949#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {21949#false} is VALID [2022-02-21 04:21:36,374 INFO L290 TraceCheckUtils]: 31: Hoare triple {21949#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L290 TraceCheckUtils]: 32: Hoare triple {21949#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L290 TraceCheckUtils]: 33: Hoare triple {21949#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L290 TraceCheckUtils]: 34: Hoare triple {21949#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L290 TraceCheckUtils]: 35: Hoare triple {21949#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L290 TraceCheckUtils]: 36: Hoare triple {21949#false} assume !(0 != start_simulation_~tmp~4#1); {21949#false} is VALID [2022-02-21 04:21:36,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:36,375 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:36,376 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1953548760] [2022-02-21 04:21:36,376 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1953548760] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:36,376 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:36,376 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:36,376 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393424055] [2022-02-21 04:21:36,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:36,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:36,377 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:36,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:36,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:36,378 INFO L87 Difference]: Start difference. First operand 909 states and 1165 transitions. cyclomatic complexity: 258 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,881 INFO L93 Difference]: Finished difference Result 1550 states and 1986 transitions. [2022-02-21 04:21:36,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:36,881 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,903 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:36,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1550 states and 1986 transitions. [2022-02-21 04:21:36,962 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1506 [2022-02-21 04:21:37,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1550 states to 1550 states and 1986 transitions. [2022-02-21 04:21:37,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1550 [2022-02-21 04:21:37,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1550 [2022-02-21 04:21:37,018 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,019 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:37,019 INFO L681 BuchiCegarLoop]: Abstraction has 1550 states and 1986 transitions. [2022-02-21 04:21:37,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1550 to 860. [2022-02-21 04:21:37,027 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:37,028 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1550 states and 1986 transitions. Second operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,029 INFO L74 IsIncluded]: Start isIncluded. First operand 1550 states and 1986 transitions. Second operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,030 INFO L87 Difference]: Start difference. First operand 1550 states and 1986 transitions. Second operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,085 INFO L93 Difference]: Finished difference Result 1550 states and 1986 transitions. [2022-02-21 04:21:37,085 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,089 INFO L74 IsIncluded]: Start isIncluded. First operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,089 INFO L87 Difference]: Start difference. First operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,144 INFO L93 Difference]: Finished difference Result 1550 states and 1986 transitions. [2022-02-21 04:21:37,144 INFO L276 IsEmpty]: Start isEmpty. Operand 1550 states and 1986 transitions. [2022-02-21 04:21:37,146 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,146 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,146 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:37,146 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:37,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 860 states, 860 states have (on average 1.2732558139534884) internal successors, (1095), 859 states have internal predecessors, (1095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1095 transitions. [2022-02-21 04:21:37,166 INFO L704 BuchiCegarLoop]: Abstraction has 860 states and 1095 transitions. [2022-02-21 04:21:37,166 INFO L587 BuchiCegarLoop]: Abstraction has 860 states and 1095 transitions. [2022-02-21 04:21:37,166 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:37,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 860 states and 1095 transitions. [2022-02-21 04:21:37,168 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 817 [2022-02-21 04:21:37,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:37,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:37,169 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,169 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,169 INFO L791 eck$LassoCheckResult]: Stem: 23622#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 23595#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 23543#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23544#L222 assume !(1 == ~q_req_up~0); 23541#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23542#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 23579#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 23602#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23600#L275 assume !(0 == ~q_read_ev~0); 23601#L275-2 assume !(0 == ~q_write_ev~0); 23582#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 23583#L65 assume !(1 == ~p_dw_pc~0); 23581#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 23592#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 23536#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 23537#L315 assume !(0 != activate_threads_~tmp~1#1); 23547#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 23548#L84 assume !(1 == ~c_dr_pc~0); 23567#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 23557#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 23558#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 23519#L323 assume !(0 != activate_threads_~tmp___0~1#1); 23520#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23621#L293 assume !(1 == ~q_read_ev~0); 23508#L293-2 assume !(1 == ~q_write_ev~0); 23509#L298-1 assume { :end_inline_reset_delta_events } true; 23610#L419-2 assume !false; 24263#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 24262#L364 assume !false; 24186#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24184#L255 assume !(0 == ~p_dw_st~0); 24185#L259 [2022-02-21 04:21:37,169 INFO L793 eck$LassoCheckResult]: Loop: 24185#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 24266#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 24267#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 24258#L344 assume 0 != eval_~tmp___1~0#1; 24255#L344-1 assume !(0 == ~p_dw_st~0); 24253#L349 assume !(0 == ~c_dr_st~0); 23598#L364 assume !false; 24270#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 24269#L255 assume !(0 == ~p_dw_st~0); 24185#L259 [2022-02-21 04:21:37,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 1 times [2022-02-21 04:21:37,170 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,170 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728546379] [2022-02-21 04:21:37,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:37,184 INFO L290 TraceCheckUtils]: 0: Hoare triple {27471#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {27471#true} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 1: Hoare triple {27471#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {27471#true} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 2: Hoare triple {27471#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {27471#true} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 3: Hoare triple {27471#true} assume !(1 == ~q_req_up~0); {27471#true} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 4: Hoare triple {27471#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {27471#true} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 5: Hoare triple {27471#true} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,185 INFO L290 TraceCheckUtils]: 6: Hoare triple {27473#(= ~p_dw_st~0 0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,186 INFO L290 TraceCheckUtils]: 7: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,186 INFO L290 TraceCheckUtils]: 8: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(0 == ~q_read_ev~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,186 INFO L290 TraceCheckUtils]: 9: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(0 == ~q_write_ev~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,187 INFO L290 TraceCheckUtils]: 10: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,187 INFO L290 TraceCheckUtils]: 11: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(1 == ~p_dw_pc~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,187 INFO L290 TraceCheckUtils]: 12: Hoare triple {27473#(= ~p_dw_st~0 0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,187 INFO L290 TraceCheckUtils]: 13: Hoare triple {27473#(= ~p_dw_st~0 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,188 INFO L290 TraceCheckUtils]: 14: Hoare triple {27473#(= ~p_dw_st~0 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,188 INFO L290 TraceCheckUtils]: 15: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,188 INFO L290 TraceCheckUtils]: 16: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,189 INFO L290 TraceCheckUtils]: 17: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(1 == ~c_dr_pc~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,189 INFO L290 TraceCheckUtils]: 18: Hoare triple {27473#(= ~p_dw_st~0 0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,189 INFO L290 TraceCheckUtils]: 19: Hoare triple {27473#(= ~p_dw_st~0 0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,189 INFO L290 TraceCheckUtils]: 20: Hoare triple {27473#(= ~p_dw_st~0 0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,190 INFO L290 TraceCheckUtils]: 21: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(0 != activate_threads_~tmp___0~1#1); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,190 INFO L290 TraceCheckUtils]: 22: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,190 INFO L290 TraceCheckUtils]: 23: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(1 == ~q_read_ev~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,190 INFO L290 TraceCheckUtils]: 24: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(1 == ~q_write_ev~0); {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,191 INFO L290 TraceCheckUtils]: 25: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :end_inline_reset_delta_events } true; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,191 INFO L290 TraceCheckUtils]: 26: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !false; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,191 INFO L290 TraceCheckUtils]: 27: Hoare triple {27473#(= ~p_dw_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,192 INFO L290 TraceCheckUtils]: 28: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !false; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,192 INFO L290 TraceCheckUtils]: 29: Hoare triple {27473#(= ~p_dw_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {27473#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,192 INFO L290 TraceCheckUtils]: 30: Hoare triple {27473#(= ~p_dw_st~0 0)} assume !(0 == ~p_dw_st~0); {27472#false} is VALID [2022-02-21 04:21:37,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:37,193 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:37,193 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728546379] [2022-02-21 04:21:37,193 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728546379] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:37,193 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:37,193 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:37,193 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553889457] [2022-02-21 04:21:37,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:37,193 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:37,194 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,194 INFO L85 PathProgramCache]: Analyzing trace with hash -565706813, now seen corresponding path program 1 times [2022-02-21 04:21:37,194 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,194 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1970298945] [2022-02-21 04:21:37,194 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:37,201 INFO L290 TraceCheckUtils]: 0: Hoare triple {27474#true} assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {27476#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:37,202 INFO L290 TraceCheckUtils]: 1: Hoare triple {27476#(= ~c_dr_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {27476#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:37,202 INFO L290 TraceCheckUtils]: 2: Hoare triple {27476#(= ~c_dr_st~0 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {27476#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:37,202 INFO L290 TraceCheckUtils]: 3: Hoare triple {27476#(= ~c_dr_st~0 0)} assume 0 != eval_~tmp___1~0#1; {27476#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:37,203 INFO L290 TraceCheckUtils]: 4: Hoare triple {27476#(= ~c_dr_st~0 0)} assume !(0 == ~p_dw_st~0); {27476#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:37,203 INFO L290 TraceCheckUtils]: 5: Hoare triple {27476#(= ~c_dr_st~0 0)} assume !(0 == ~c_dr_st~0); {27475#false} is VALID [2022-02-21 04:21:37,203 INFO L290 TraceCheckUtils]: 6: Hoare triple {27475#false} assume !false; {27475#false} is VALID [2022-02-21 04:21:37,203 INFO L290 TraceCheckUtils]: 7: Hoare triple {27475#false} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {27475#false} is VALID [2022-02-21 04:21:37,203 INFO L290 TraceCheckUtils]: 8: Hoare triple {27475#false} assume !(0 == ~p_dw_st~0); {27475#false} is VALID [2022-02-21 04:21:37,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:37,203 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:37,204 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1970298945] [2022-02-21 04:21:37,204 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1970298945] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:37,204 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:37,204 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:37,204 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341152632] [2022-02-21 04:21:37,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:37,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:37,204 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:37,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:37,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:37,205 INFO L87 Difference]: Start difference. First operand 860 states and 1095 transitions. cyclomatic complexity: 237 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,313 INFO L93 Difference]: Finished difference Result 1209 states and 1521 transitions. [2022-02-21 04:21:37,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:37,313 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,318 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 9 edges. 9 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:37,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,355 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-02-21 04:21:37,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1521 transitions. [2022-02-21 04:21:37,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2022-02-21 04:21:37,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2022-02-21 04:21:37,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:37,392 INFO L681 BuchiCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-02-21 04:21:37,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2022-02-21 04:21:37,401 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:37,403 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1209 states and 1521 transitions. Second operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,404 INFO L74 IsIncluded]: Start isIncluded. First operand 1209 states and 1521 transitions. Second operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,405 INFO L87 Difference]: Start difference. First operand 1209 states and 1521 transitions. Second operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,440 INFO L93 Difference]: Finished difference Result 1209 states and 1521 transitions. [2022-02-21 04:21:37,440 INFO L276 IsEmpty]: Start isEmpty. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,441 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,441 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,443 INFO L74 IsIncluded]: Start isIncluded. First operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,444 INFO L87 Difference]: Start difference. First operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,481 INFO L93 Difference]: Finished difference Result 1209 states and 1521 transitions. [2022-02-21 04:21:37,481 INFO L276 IsEmpty]: Start isEmpty. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,482 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,482 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,483 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:37,483 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:37,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.2580645161290323) internal successors, (1521), 1208 states have internal predecessors, (1521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1521 transitions. [2022-02-21 04:21:37,518 INFO L704 BuchiCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-02-21 04:21:37,518 INFO L587 BuchiCegarLoop]: Abstraction has 1209 states and 1521 transitions. [2022-02-21 04:21:37,518 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:21:37,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1521 transitions. [2022-02-21 04:21:37,522 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-02-21 04:21:37,522 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:37,522 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:37,522 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,522 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,523 INFO L791 eck$LassoCheckResult]: Stem: 28789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 28769#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 28720#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28721#L222 assume !(1 == ~q_req_up~0); 28718#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28719#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 28755#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 28776#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28773#L275 assume !(0 == ~q_read_ev~0); 28774#L275-2 assume !(0 == ~q_write_ev~0); 28758#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 28759#L65 assume !(1 == ~p_dw_pc~0); 28757#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 28767#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 28713#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 28714#L315 assume !(0 != activate_threads_~tmp~1#1); 28724#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 28725#L84 assume !(1 == ~c_dr_pc~0); 28743#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 28734#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 28735#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28696#L323 assume !(0 != activate_threads_~tmp___0~1#1); 28697#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28788#L293 assume !(1 == ~q_read_ev~0); 28686#L293-2 assume !(1 == ~q_write_ev~0); 28687#L298-1 assume { :end_inline_reset_delta_events } true; 28783#L419-2 assume !false; 28882#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 28881#L364 assume !false; 28879#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 28877#L255 assume !(0 == ~p_dw_st~0); 28876#L259 [2022-02-21 04:21:37,523 INFO L793 eck$LassoCheckResult]: Loop: 28876#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 28874#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 28872#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 28870#L344 assume 0 != eval_~tmp___1~0#1; 28860#L344-1 assume !(0 == ~p_dw_st~0); 28731#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 28732#L368 assume !(0 != eval_~tmp___0~2#1); 28771#L364 assume !false; 28880#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 28878#L255 assume !(0 == ~p_dw_st~0); 28876#L259 [2022-02-21 04:21:37,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1220673252, now seen corresponding path program 2 times [2022-02-21 04:21:37,523 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,524 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [814738296] [2022-02-21 04:21:37,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:37,537 INFO L290 TraceCheckUtils]: 0: Hoare triple {32316#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {32316#true} is VALID [2022-02-21 04:21:37,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {32316#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {32316#true} is VALID [2022-02-21 04:21:37,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {32316#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {32316#true} is VALID [2022-02-21 04:21:37,538 INFO L290 TraceCheckUtils]: 3: Hoare triple {32316#true} assume !(1 == ~q_req_up~0); {32316#true} is VALID [2022-02-21 04:21:37,538 INFO L290 TraceCheckUtils]: 4: Hoare triple {32316#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {32316#true} is VALID [2022-02-21 04:21:37,538 INFO L290 TraceCheckUtils]: 5: Hoare triple {32316#true} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,539 INFO L290 TraceCheckUtils]: 6: Hoare triple {32318#(= ~p_dw_st~0 0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,539 INFO L290 TraceCheckUtils]: 7: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,539 INFO L290 TraceCheckUtils]: 8: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(0 == ~q_read_ev~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,539 INFO L290 TraceCheckUtils]: 9: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(0 == ~q_write_ev~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,540 INFO L290 TraceCheckUtils]: 10: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,540 INFO L290 TraceCheckUtils]: 11: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(1 == ~p_dw_pc~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,540 INFO L290 TraceCheckUtils]: 12: Hoare triple {32318#(= ~p_dw_st~0 0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,540 INFO L290 TraceCheckUtils]: 13: Hoare triple {32318#(= ~p_dw_st~0 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,541 INFO L290 TraceCheckUtils]: 14: Hoare triple {32318#(= ~p_dw_st~0 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,541 INFO L290 TraceCheckUtils]: 15: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,541 INFO L290 TraceCheckUtils]: 16: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,542 INFO L290 TraceCheckUtils]: 17: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(1 == ~c_dr_pc~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,542 INFO L290 TraceCheckUtils]: 18: Hoare triple {32318#(= ~p_dw_st~0 0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,542 INFO L290 TraceCheckUtils]: 19: Hoare triple {32318#(= ~p_dw_st~0 0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,542 INFO L290 TraceCheckUtils]: 20: Hoare triple {32318#(= ~p_dw_st~0 0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,543 INFO L290 TraceCheckUtils]: 21: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(0 != activate_threads_~tmp___0~1#1); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,543 INFO L290 TraceCheckUtils]: 22: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,543 INFO L290 TraceCheckUtils]: 23: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(1 == ~q_read_ev~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,544 INFO L290 TraceCheckUtils]: 24: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(1 == ~q_write_ev~0); {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,544 INFO L290 TraceCheckUtils]: 25: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :end_inline_reset_delta_events } true; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,544 INFO L290 TraceCheckUtils]: 26: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !false; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,544 INFO L290 TraceCheckUtils]: 27: Hoare triple {32318#(= ~p_dw_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,545 INFO L290 TraceCheckUtils]: 28: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !false; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,545 INFO L290 TraceCheckUtils]: 29: Hoare triple {32318#(= ~p_dw_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {32318#(= ~p_dw_st~0 0)} is VALID [2022-02-21 04:21:37,545 INFO L290 TraceCheckUtils]: 30: Hoare triple {32318#(= ~p_dw_st~0 0)} assume !(0 == ~p_dw_st~0); {32317#false} is VALID [2022-02-21 04:21:37,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:37,546 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:37,546 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [814738296] [2022-02-21 04:21:37,546 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [814738296] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:37,546 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:37,546 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:37,546 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277746059] [2022-02-21 04:21:37,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:37,547 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:37,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,547 INFO L85 PathProgramCache]: Analyzing trace with hash -410340052, now seen corresponding path program 1 times [2022-02-21 04:21:37,547 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,547 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775763275] [2022-02-21 04:21:37,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:37,550 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:37,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:37,552 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:37,618 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:37,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:37,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:37,619 INFO L87 Difference]: Start difference. First operand 1209 states and 1521 transitions. cyclomatic complexity: 314 Second operand has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,783 INFO L93 Difference]: Finished difference Result 1209 states and 1471 transitions. [2022-02-21 04:21:37,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:37,784 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 15.5) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,805 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:37,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:37,867 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-02-21 04:21:37,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1209 states to 1209 states and 1471 transitions. [2022-02-21 04:21:37,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1209 [2022-02-21 04:21:37,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1209 [2022-02-21 04:21:37,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:37,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:37,930 INFO L681 BuchiCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-02-21 04:21:37,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:37,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1209 to 1209. [2022-02-21 04:21:37,948 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:37,949 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1209 states and 1471 transitions. Second operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,951 INFO L74 IsIncluded]: Start isIncluded. First operand 1209 states and 1471 transitions. Second operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,952 INFO L87 Difference]: Start difference. First operand 1209 states and 1471 transitions. Second operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,009 INFO L93 Difference]: Finished difference Result 1209 states and 1471 transitions. [2022-02-21 04:21:38,010 INFO L276 IsEmpty]: Start isEmpty. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:38,011 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:38,012 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:38,014 INFO L74 IsIncluded]: Start isIncluded. First operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1209 states and 1471 transitions. [2022-02-21 04:21:38,015 INFO L87 Difference]: Start difference. First operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1209 states and 1471 transitions. [2022-02-21 04:21:38,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,075 INFO L93 Difference]: Finished difference Result 1209 states and 1471 transitions. [2022-02-21 04:21:38,075 INFO L276 IsEmpty]: Start isEmpty. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:38,077 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:38,077 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:38,077 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:38,077 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:38,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1209 states, 1209 states have (on average 1.216708023159636) internal successors, (1471), 1208 states have internal predecessors, (1471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1209 states to 1209 states and 1471 transitions. [2022-02-21 04:21:38,137 INFO L704 BuchiCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-02-21 04:21:38,137 INFO L587 BuchiCegarLoop]: Abstraction has 1209 states and 1471 transitions. [2022-02-21 04:21:38,137 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:21:38,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1209 states and 1471 transitions. [2022-02-21 04:21:38,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1166 [2022-02-21 04:21:38,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:38,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:38,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:38,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2022-02-21 04:21:38,144 INFO L791 eck$LassoCheckResult]: Stem: 33638#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 33616#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 33566#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33567#L222 assume !(1 == ~q_req_up~0); 33562#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33563#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 33600#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 33621#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33618#L275 assume !(0 == ~q_read_ev~0); 33619#L275-2 assume !(0 == ~q_write_ev~0); 33604#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 33605#L65 assume !(1 == ~p_dw_pc~0); 33602#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 33611#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 33560#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 33561#L315 assume !(0 != activate_threads_~tmp~1#1); 33568#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 33569#L84 assume !(1 == ~c_dr_pc~0); 33587#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 33579#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 33580#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 33540#L323 assume !(0 != activate_threads_~tmp___0~1#1); 33541#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33635#L293 assume !(1 == ~q_read_ev~0); 33532#L293-2 assume !(1 == ~q_write_ev~0); 33533#L298-1 assume { :end_inline_reset_delta_events } true; 33629#L419-2 assume !false; 33688#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 33687#L364 assume !false; 33686#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 33685#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 33684#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 33683#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 33681#L344 assume 0 != eval_~tmp___1~0#1; 33679#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 33677#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 33674#L128 assume !(0 == ~p_dw_pc~0); 33675#L131 assume 1 == ~p_dw_pc~0; 33670#L141 [2022-02-21 04:21:38,144 INFO L793 eck$LassoCheckResult]: Loop: 33670#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 34254#L139-1 assume !false; 34253#L140 assume !(0 == ~q_free~0); 33670#L141 [2022-02-21 04:21:38,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:38,146 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 1 times [2022-02-21 04:21:38,146 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:38,146 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830291822] [2022-02-21 04:21:38,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:38,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:38,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:38,191 INFO L290 TraceCheckUtils]: 0: Hoare triple {37160#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {37160#true} is VALID [2022-02-21 04:21:38,192 INFO L290 TraceCheckUtils]: 1: Hoare triple {37160#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,193 INFO L290 TraceCheckUtils]: 2: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,193 INFO L290 TraceCheckUtils]: 3: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(1 == ~q_req_up~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,194 INFO L290 TraceCheckUtils]: 4: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,194 INFO L290 TraceCheckUtils]: 5: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,194 INFO L290 TraceCheckUtils]: 6: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,195 INFO L290 TraceCheckUtils]: 7: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,195 INFO L290 TraceCheckUtils]: 8: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(0 == ~q_read_ev~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,195 INFO L290 TraceCheckUtils]: 9: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(0 == ~q_write_ev~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,196 INFO L290 TraceCheckUtils]: 10: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,196 INFO L290 TraceCheckUtils]: 11: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(1 == ~p_dw_pc~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,196 INFO L290 TraceCheckUtils]: 12: Hoare triple {37162#(= ~p_dw_pc~0 0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,197 INFO L290 TraceCheckUtils]: 13: Hoare triple {37162#(= ~p_dw_pc~0 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,197 INFO L290 TraceCheckUtils]: 14: Hoare triple {37162#(= ~p_dw_pc~0 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,197 INFO L290 TraceCheckUtils]: 15: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,198 INFO L290 TraceCheckUtils]: 16: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,198 INFO L290 TraceCheckUtils]: 17: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(1 == ~c_dr_pc~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,198 INFO L290 TraceCheckUtils]: 18: Hoare triple {37162#(= ~p_dw_pc~0 0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,199 INFO L290 TraceCheckUtils]: 19: Hoare triple {37162#(= ~p_dw_pc~0 0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,199 INFO L290 TraceCheckUtils]: 20: Hoare triple {37162#(= ~p_dw_pc~0 0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,199 INFO L290 TraceCheckUtils]: 21: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(0 != activate_threads_~tmp___0~1#1); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,200 INFO L290 TraceCheckUtils]: 22: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,200 INFO L290 TraceCheckUtils]: 23: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(1 == ~q_read_ev~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,201 INFO L290 TraceCheckUtils]: 24: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(1 == ~q_write_ev~0); {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,201 INFO L290 TraceCheckUtils]: 25: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :end_inline_reset_delta_events } true; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,201 INFO L290 TraceCheckUtils]: 26: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !false; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,202 INFO L290 TraceCheckUtils]: 27: Hoare triple {37162#(= ~p_dw_pc~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,202 INFO L290 TraceCheckUtils]: 28: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !false; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,202 INFO L290 TraceCheckUtils]: 29: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,203 INFO L290 TraceCheckUtils]: 30: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,203 INFO L290 TraceCheckUtils]: 31: Hoare triple {37162#(= ~p_dw_pc~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,203 INFO L290 TraceCheckUtils]: 32: Hoare triple {37162#(= ~p_dw_pc~0 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,204 INFO L290 TraceCheckUtils]: 33: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 0 != eval_~tmp___1~0#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,204 INFO L290 TraceCheckUtils]: 34: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,204 INFO L290 TraceCheckUtils]: 35: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; {37162#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:38,205 INFO L290 TraceCheckUtils]: 36: Hoare triple {37162#(= ~p_dw_pc~0 0)} assume !(0 == ~p_dw_pc~0); {37161#false} is VALID [2022-02-21 04:21:38,205 INFO L290 TraceCheckUtils]: 37: Hoare triple {37161#false} assume 1 == ~p_dw_pc~0; {37161#false} is VALID [2022-02-21 04:21:38,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:38,205 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:38,205 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830291822] [2022-02-21 04:21:38,206 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830291822] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:38,206 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:38,206 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:38,206 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1786665435] [2022-02-21 04:21:38,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:38,207 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:38,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:38,207 INFO L85 PathProgramCache]: Analyzing trace with hash 220166, now seen corresponding path program 1 times [2022-02-21 04:21:38,207 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:38,207 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343811994] [2022-02-21 04:21:38,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:38,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:38,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:38,218 INFO L290 TraceCheckUtils]: 0: Hoare triple {37163#true} ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; {37165#(= ~q_free~0 0)} is VALID [2022-02-21 04:21:38,219 INFO L290 TraceCheckUtils]: 1: Hoare triple {37165#(= ~q_free~0 0)} assume !false; {37165#(= ~q_free~0 0)} is VALID [2022-02-21 04:21:38,219 INFO L290 TraceCheckUtils]: 2: Hoare triple {37165#(= ~q_free~0 0)} assume !(0 == ~q_free~0); {37164#false} is VALID [2022-02-21 04:21:38,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:38,220 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:38,220 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343811994] [2022-02-21 04:21:38,220 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343811994] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:38,220 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:38,220 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [1] imperfect sequences [] total 1 [2022-02-21 04:21:38,221 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2048343751] [2022-02-21 04:21:38,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:38,222 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:38,222 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:38,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:38,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:38,223 INFO L87 Difference]: Start difference. First operand 1209 states and 1471 transitions. cyclomatic complexity: 264 Second operand has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,464 INFO L93 Difference]: Finished difference Result 2195 states and 2627 transitions. [2022-02-21 04:21:38,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:38,464 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,467 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 3 edges. 3 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:38,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2195 states and 2627 transitions. [2022-02-21 04:21:38,586 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2152 [2022-02-21 04:21:38,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2195 states to 2195 states and 2627 transitions. [2022-02-21 04:21:38,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2195 [2022-02-21 04:21:38,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2195 [2022-02-21 04:21:38,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2195 states and 2627 transitions. [2022-02-21 04:21:38,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:38,709 INFO L681 BuchiCegarLoop]: Abstraction has 2195 states and 2627 transitions. [2022-02-21 04:21:38,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2195 states and 2627 transitions. [2022-02-21 04:21:38,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2195 to 1879. [2022-02-21 04:21:38,725 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:38,727 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2195 states and 2627 transitions. Second operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,729 INFO L74 IsIncluded]: Start isIncluded. First operand 2195 states and 2627 transitions. Second operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,730 INFO L87 Difference]: Start difference. First operand 2195 states and 2627 transitions. Second operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,945 INFO L93 Difference]: Finished difference Result 2195 states and 2627 transitions. [2022-02-21 04:21:38,945 INFO L276 IsEmpty]: Start isEmpty. Operand 2195 states and 2627 transitions. [2022-02-21 04:21:38,954 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:38,954 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:38,973 INFO L74 IsIncluded]: Start isIncluded. First operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2195 states and 2627 transitions. [2022-02-21 04:21:38,974 INFO L87 Difference]: Start difference. First operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2195 states and 2627 transitions. [2022-02-21 04:21:39,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:39,205 INFO L93 Difference]: Finished difference Result 2195 states and 2627 transitions. [2022-02-21 04:21:39,205 INFO L276 IsEmpty]: Start isEmpty. Operand 2195 states and 2627 transitions. [2022-02-21 04:21:39,207 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:39,208 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:39,208 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:39,208 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:39,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1879 states, 1879 states have (on average 1.204364023416711) internal successors, (2263), 1878 states have internal predecessors, (2263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1879 states to 1879 states and 2263 transitions. [2022-02-21 04:21:39,396 INFO L704 BuchiCegarLoop]: Abstraction has 1879 states and 2263 transitions. [2022-02-21 04:21:39,396 INFO L587 BuchiCegarLoop]: Abstraction has 1879 states and 2263 transitions. [2022-02-21 04:21:39,396 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:21:39,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1879 states and 2263 transitions. [2022-02-21 04:21:39,418 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2022-02-21 04:21:39,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:39,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:39,419 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:39,419 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:39,419 INFO L791 eck$LassoCheckResult]: Stem: 39464#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 39441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 39394#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39395#L222 assume !(1 == ~q_req_up~0); 39392#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39393#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 39427#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 39449#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39446#L275 assume !(0 == ~q_read_ev~0); 39447#L275-2 assume !(0 == ~q_write_ev~0); 39430#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 39431#L65 assume !(1 == ~p_dw_pc~0); 39429#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 39439#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 39388#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39389#L315 assume !(0 != activate_threads_~tmp~1#1); 39398#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 39399#L84 assume !(1 == ~c_dr_pc~0); 39416#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 39407#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 39408#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 39371#L323 assume !(0 != activate_threads_~tmp___0~1#1); 39372#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39463#L293 assume !(1 == ~q_read_ev~0); 39361#L293-2 assume !(1 == ~q_write_ev~0); 39362#L298-1 assume { :end_inline_reset_delta_events } true; 39455#L419-2 assume !false; 39537#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 39536#L364 assume !false; 39535#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 39534#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 39533#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 39532#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 39530#L344 assume 0 != eval_~tmp___1~0#1; 39528#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 39526#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 39523#L128 assume !(0 == ~p_dw_pc~0); 39524#L131 assume 1 == ~p_dw_pc~0; 39453#L141 [2022-02-21 04:21:39,423 INFO L793 eck$LassoCheckResult]: Loop: 39453#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 39384#L139-1 assume !false; 39385#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 39400#L158 assume { :end_inline_do_write_p } true; 39401#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 39557#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 40438#L169 assume 0 == ~c_dr_pc~0; 39473#L198-1 assume !false; 40430#L181 assume !(1 == ~q_free~0); 39480#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 39373#L198 assume ~p_last_write~0 == ~c_last_read~0; 39374#L199 assume ~p_num_write~0 == ~c_num_read~0; 40108#L198-1 assume !false; 40106#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 40101#L212 assume { :end_inline_do_read_c } true; 40097#L364 assume !false; 40095#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 40093#L255 assume !(0 == ~p_dw_st~0); 40090#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 40089#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 40087#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 40083#L344 assume !(0 != eval_~tmp___1~0#1); 40081#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40078#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 40074#L35-3 assume !(0 == ~q_free~0); 40036#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 40031#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 39986#L48-1 assume { :end_inline_update_fifo_q } true; 39984#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39982#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 39979#L275-5 assume !(0 == ~q_write_ev~0); 39977#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 39975#L65-3 assume 1 == ~p_dw_pc~0; 39971#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 39969#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 39967#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 39963#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 39961#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 39949#L84-3 assume !(1 == ~c_dr_pc~0); 39817#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 39814#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 39811#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 39808#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 39422#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39423#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 39375#L293-5 assume !(1 == ~q_write_ev~0); 39376#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 41239#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 41238#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 41237#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 41236#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 41235#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41234#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 39438#L436 assume !(0 != start_simulation_~tmp~4#1); 39396#L419-2 assume !false; 39397#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 39435#L364 assume !false; 39432#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 39402#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 39403#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 39411#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 39412#L344 assume 0 != eval_~tmp___1~0#1; 39421#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 39448#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 41220#L128 assume !(0 == ~p_dw_pc~0); 41221#L131 assume 1 == ~p_dw_pc~0; 39453#L141 [2022-02-21 04:21:39,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:39,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1071076411, now seen corresponding path program 2 times [2022-02-21 04:21:39,427 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:39,427 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930363913] [2022-02-21 04:21:39,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:39,427 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:39,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:39,461 INFO L290 TraceCheckUtils]: 0: Hoare triple {45633#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {45633#true} is VALID [2022-02-21 04:21:39,461 INFO L290 TraceCheckUtils]: 1: Hoare triple {45633#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,461 INFO L290 TraceCheckUtils]: 2: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,462 INFO L290 TraceCheckUtils]: 3: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(1 == ~q_req_up~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,462 INFO L290 TraceCheckUtils]: 4: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,462 INFO L290 TraceCheckUtils]: 5: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,463 INFO L290 TraceCheckUtils]: 6: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,463 INFO L290 TraceCheckUtils]: 7: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,463 INFO L290 TraceCheckUtils]: 8: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(0 == ~q_read_ev~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,463 INFO L290 TraceCheckUtils]: 9: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(0 == ~q_write_ev~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,464 INFO L290 TraceCheckUtils]: 10: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,464 INFO L290 TraceCheckUtils]: 11: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(1 == ~p_dw_pc~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,464 INFO L290 TraceCheckUtils]: 12: Hoare triple {45635#(= ~p_dw_pc~0 0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,464 INFO L290 TraceCheckUtils]: 13: Hoare triple {45635#(= ~p_dw_pc~0 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,465 INFO L290 TraceCheckUtils]: 14: Hoare triple {45635#(= ~p_dw_pc~0 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,465 INFO L290 TraceCheckUtils]: 15: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,465 INFO L290 TraceCheckUtils]: 16: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,466 INFO L290 TraceCheckUtils]: 17: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(1 == ~c_dr_pc~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,466 INFO L290 TraceCheckUtils]: 18: Hoare triple {45635#(= ~p_dw_pc~0 0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,466 INFO L290 TraceCheckUtils]: 19: Hoare triple {45635#(= ~p_dw_pc~0 0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,466 INFO L290 TraceCheckUtils]: 20: Hoare triple {45635#(= ~p_dw_pc~0 0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,474 INFO L290 TraceCheckUtils]: 21: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(0 != activate_threads_~tmp___0~1#1); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,474 INFO L290 TraceCheckUtils]: 22: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,474 INFO L290 TraceCheckUtils]: 23: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(1 == ~q_read_ev~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,475 INFO L290 TraceCheckUtils]: 24: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(1 == ~q_write_ev~0); {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,475 INFO L290 TraceCheckUtils]: 25: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :end_inline_reset_delta_events } true; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,475 INFO L290 TraceCheckUtils]: 26: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !false; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,476 INFO L290 TraceCheckUtils]: 27: Hoare triple {45635#(= ~p_dw_pc~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,476 INFO L290 TraceCheckUtils]: 28: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !false; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,476 INFO L290 TraceCheckUtils]: 29: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,476 INFO L290 TraceCheckUtils]: 30: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,477 INFO L290 TraceCheckUtils]: 31: Hoare triple {45635#(= ~p_dw_pc~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,477 INFO L290 TraceCheckUtils]: 32: Hoare triple {45635#(= ~p_dw_pc~0 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,477 INFO L290 TraceCheckUtils]: 33: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 0 != eval_~tmp___1~0#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,477 INFO L290 TraceCheckUtils]: 34: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,478 INFO L290 TraceCheckUtils]: 35: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; {45635#(= ~p_dw_pc~0 0)} is VALID [2022-02-21 04:21:39,478 INFO L290 TraceCheckUtils]: 36: Hoare triple {45635#(= ~p_dw_pc~0 0)} assume !(0 == ~p_dw_pc~0); {45634#false} is VALID [2022-02-21 04:21:39,478 INFO L290 TraceCheckUtils]: 37: Hoare triple {45634#false} assume 1 == ~p_dw_pc~0; {45634#false} is VALID [2022-02-21 04:21:39,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:39,478 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:39,478 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930363913] [2022-02-21 04:21:39,478 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930363913] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:39,478 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:39,479 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:39,479 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597233841] [2022-02-21 04:21:39,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:39,479 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:39,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:39,479 INFO L85 PathProgramCache]: Analyzing trace with hash -1533797676, now seen corresponding path program 1 times [2022-02-21 04:21:39,479 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:39,480 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096427062] [2022-02-21 04:21:39,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:39,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:39,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:39,511 INFO L290 TraceCheckUtils]: 0: Hoare triple {45636#true} ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; {45636#true} is VALID [2022-02-21 04:21:39,511 INFO L290 TraceCheckUtils]: 1: Hoare triple {45636#true} assume !false; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 2: Hoare triple {45636#true} assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 3: Hoare triple {45636#true} assume { :end_inline_do_write_p } true; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 4: Hoare triple {45636#true} assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 5: Hoare triple {45636#true} assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 6: Hoare triple {45636#true} assume 0 == ~c_dr_pc~0; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 7: Hoare triple {45636#true} assume !false; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 8: Hoare triple {45636#true} assume !(1 == ~q_free~0); {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 9: Hoare triple {45636#true} do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 10: Hoare triple {45636#true} assume ~p_last_write~0 == ~c_last_read~0; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 11: Hoare triple {45636#true} assume ~p_num_write~0 == ~c_num_read~0; {45636#true} is VALID [2022-02-21 04:21:39,512 INFO L290 TraceCheckUtils]: 12: Hoare triple {45636#true} assume !false; {45636#true} is VALID [2022-02-21 04:21:39,513 INFO L290 TraceCheckUtils]: 13: Hoare triple {45636#true} assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,513 INFO L290 TraceCheckUtils]: 14: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_do_read_c } true; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,526 INFO L290 TraceCheckUtils]: 15: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !false; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,526 INFO L290 TraceCheckUtils]: 16: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,526 INFO L290 TraceCheckUtils]: 17: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~p_dw_st~0); {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,527 INFO L290 TraceCheckUtils]: 18: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,527 INFO L290 TraceCheckUtils]: 19: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,527 INFO L290 TraceCheckUtils]: 20: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,527 INFO L290 TraceCheckUtils]: 21: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 != eval_~tmp___1~0#1); {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,528 INFO L290 TraceCheckUtils]: 22: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,528 INFO L290 TraceCheckUtils]: 23: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,528 INFO L290 TraceCheckUtils]: 24: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~q_free~0); {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,528 INFO L290 TraceCheckUtils]: 25: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_free~0;~q_read_ev~0 := 0; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,529 INFO L290 TraceCheckUtils]: 26: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} ~q_ev~0 := 0;~q_req_up~0 := 0; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,529 INFO L290 TraceCheckUtils]: 27: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_update_fifo_q } true; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,529 INFO L290 TraceCheckUtils]: 28: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,530 INFO L290 TraceCheckUtils]: 29: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,530 INFO L290 TraceCheckUtils]: 30: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~q_write_ev~0); {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,530 INFO L290 TraceCheckUtils]: 31: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,530 INFO L290 TraceCheckUtils]: 32: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~p_dw_pc~0; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,531 INFO L290 TraceCheckUtils]: 33: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,531 INFO L290 TraceCheckUtils]: 34: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,531 INFO L290 TraceCheckUtils]: 35: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,531 INFO L290 TraceCheckUtils]: 36: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 37: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 38: Hoare triple {45638#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(1 == ~c_dr_pc~0); {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 39: Hoare triple {45637#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 40: Hoare triple {45637#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 41: Hoare triple {45637#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 42: Hoare triple {45637#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 43: Hoare triple {45637#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 44: Hoare triple {45637#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 45: Hoare triple {45637#false} assume !(1 == ~q_write_ev~0); {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 46: Hoare triple {45637#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 47: Hoare triple {45637#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 48: Hoare triple {45637#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 49: Hoare triple {45637#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {45637#false} is VALID [2022-02-21 04:21:39,532 INFO L290 TraceCheckUtils]: 50: Hoare triple {45637#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 51: Hoare triple {45637#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 52: Hoare triple {45637#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 53: Hoare triple {45637#false} assume !(0 != start_simulation_~tmp~4#1); {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 54: Hoare triple {45637#false} assume !false; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 55: Hoare triple {45637#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 56: Hoare triple {45637#false} assume !false; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 57: Hoare triple {45637#false} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 58: Hoare triple {45637#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 59: Hoare triple {45637#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 60: Hoare triple {45637#false} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 61: Hoare triple {45637#false} assume 0 != eval_~tmp___1~0#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 62: Hoare triple {45637#false} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 63: Hoare triple {45637#false} assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 64: Hoare triple {45637#false} assume !(0 == ~p_dw_pc~0); {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L290 TraceCheckUtils]: 65: Hoare triple {45637#false} assume 1 == ~p_dw_pc~0; {45637#false} is VALID [2022-02-21 04:21:39,533 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-02-21 04:21:39,534 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:39,534 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096427062] [2022-02-21 04:21:39,534 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096427062] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:39,534 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:39,534 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:39,534 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704665922] [2022-02-21 04:21:39,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:39,534 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:39,534 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:39,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:39,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:39,535 INFO L87 Difference]: Start difference. First operand 1879 states and 2263 transitions. cyclomatic complexity: 386 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:39,804 INFO L93 Difference]: Finished difference Result 1933 states and 2326 transitions. [2022-02-21 04:21:39,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:39,804 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,842 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:39,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1933 states and 2326 transitions. [2022-02-21 04:21:39,950 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1892 [2022-02-21 04:21:40,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1933 states to 1933 states and 2326 transitions. [2022-02-21 04:21:40,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1933 [2022-02-21 04:21:40,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1933 [2022-02-21 04:21:40,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:40,061 INFO L681 BuchiCegarLoop]: Abstraction has 1933 states and 2326 transitions. [2022-02-21 04:21:40,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1933 to 1877. [2022-02-21 04:21:40,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:40,082 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1933 states and 2326 transitions. Second operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,084 INFO L74 IsIncluded]: Start isIncluded. First operand 1933 states and 2326 transitions. Second operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,085 INFO L87 Difference]: Start difference. First operand 1933 states and 2326 transitions. Second operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:40,176 INFO L93 Difference]: Finished difference Result 1933 states and 2326 transitions. [2022-02-21 04:21:40,176 INFO L276 IsEmpty]: Start isEmpty. Operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,179 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:40,179 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:40,182 INFO L74 IsIncluded]: Start isIncluded. First operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,184 INFO L87 Difference]: Start difference. First operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:40,315 INFO L93 Difference]: Finished difference Result 1933 states and 2326 transitions. [2022-02-21 04:21:40,315 INFO L276 IsEmpty]: Start isEmpty. Operand 1933 states and 2326 transitions. [2022-02-21 04:21:40,319 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:40,319 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:40,319 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:40,319 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:40,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1877 states have (on average 1.202983484283431) internal successors, (2258), 1876 states have internal predecessors, (2258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2258 transitions. [2022-02-21 04:21:40,443 INFO L704 BuchiCegarLoop]: Abstraction has 1877 states and 2258 transitions. [2022-02-21 04:21:40,443 INFO L587 BuchiCegarLoop]: Abstraction has 1877 states and 2258 transitions. [2022-02-21 04:21:40,443 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:21:40,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1877 states and 2258 transitions. [2022-02-21 04:21:40,461 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1836 [2022-02-21 04:21:40,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:40,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:40,463 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,463 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,463 INFO L791 eck$LassoCheckResult]: Stem: 47679#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 47653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 47605#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47606#L222 assume !(1 == ~q_req_up~0); 47603#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47604#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 47640#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 47661#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47658#L275 assume !(0 == ~q_read_ev~0); 47659#L275-2 assume !(0 == ~q_write_ev~0); 47641#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 47642#L65 assume !(1 == ~p_dw_pc~0); 47650#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 47651#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 47599#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 47600#L315 assume !(0 != activate_threads_~tmp~1#1); 47609#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 47610#L84 assume !(1 == ~c_dr_pc~0); 47629#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 47618#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 47619#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 47582#L323 assume !(0 != activate_threads_~tmp___0~1#1); 47583#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47678#L293 assume !(1 == ~q_read_ev~0); 47572#L293-2 assume !(1 == ~q_write_ev~0); 47573#L298-1 assume { :end_inline_reset_delta_events } true; 47669#L419-2 assume !false; 47735#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 47734#L364 assume !false; 47733#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 47732#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 47731#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 47730#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 47728#L344 assume 0 != eval_~tmp___1~0#1; 47726#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 47724#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 47722#L128 assume 0 == ~p_dw_pc~0; 47720#L139-1 assume !false; 47717#L140 assume !(0 == ~q_free~0); 47718#L141 [2022-02-21 04:21:40,464 INFO L793 eck$LassoCheckResult]: Loop: 47718#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 48822#L139-1 assume !false; 47812#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 47809#L158 assume { :end_inline_do_write_p } true; 47810#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 48074#L368 assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; 47705#L169 assume 0 == ~c_dr_pc~0; 47702#L198-1 assume !false; 47630#L181 assume !(1 == ~q_free~0); 47631#L182-1 do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; 47584#L198 assume ~p_last_write~0 == ~c_last_read~0; 47585#L199 assume ~p_num_write~0 == ~c_num_read~0; 47944#L198-1 assume !false; 47940#L181 assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; 47936#L212 assume { :end_inline_do_read_c } true; 47930#L364 assume !false; 47928#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 47926#L255 assume !(0 == ~p_dw_st~0); 47923#L259 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 47920#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 47918#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 47915#L344 assume !(0 != eval_~tmp___1~0#1); 47897#L380 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47898#L222-3 assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; 48013#L35-3 assume !(0 == ~q_free~0); 48399#L35-5 assume 1 == ~q_free~0;~q_read_ev~0 := 0; 48400#L40-3 ~q_ev~0 := 0;~q_req_up~0 := 0; 48453#L48-1 assume { :end_inline_update_fifo_q } true; 48451#L222-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48448#L275-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 48443#L275-5 assume !(0 == ~q_write_ev~0); 48440#L280-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 48437#L65-3 assume 1 == ~p_dw_pc~0; 48432#L66-1 assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 48406#L76-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 48407#L77-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 48917#L315-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 48911#L315-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 48912#L84-3 assume !(1 == ~c_dr_pc~0); 49026#L84-5 is_do_read_c_triggered_~__retres1~1#1 := 0; 48909#L95-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 48910#L96-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 48902#L323-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 48903#L323-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48893#L293-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 48894#L293-5 assume !(1 == ~q_write_ev~0); 48883#L298-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 48884#L255-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 48875#L267-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 48876#L268-1 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 48868#L394 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 48869#L401 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48862#L402 start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 48863#L436 assume !(0 != start_simulation_~tmp~4#1); 48856#L419-2 assume !false; 48857#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 48850#L364 assume !false; 48851#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 48844#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 48845#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 48838#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 48839#L344 assume 0 != eval_~tmp___1~0#1; 48832#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 48833#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 48824#L128 assume !(0 == ~p_dw_pc~0); 48826#L131 assume 1 == ~p_dw_pc~0; 47718#L141 [2022-02-21 04:21:40,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,464 INFO L85 PathProgramCache]: Analyzing trace with hash 1156368236, now seen corresponding path program 1 times [2022-02-21 04:21:40,465 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,465 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [946190572] [2022-02-21 04:21:40,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,475 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:40,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,488 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:40,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1533797676, now seen corresponding path program 2 times [2022-02-21 04:21:40,490 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,490 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036492927] [2022-02-21 04:21:40,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:40,525 INFO L290 TraceCheckUtils]: 0: Hoare triple {53320#true} ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; {53320#true} is VALID [2022-02-21 04:21:40,525 INFO L290 TraceCheckUtils]: 1: Hoare triple {53320#true} assume !false; {53320#true} is VALID [2022-02-21 04:21:40,525 INFO L290 TraceCheckUtils]: 2: Hoare triple {53320#true} assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; {53320#true} is VALID [2022-02-21 04:21:40,525 INFO L290 TraceCheckUtils]: 3: Hoare triple {53320#true} assume { :end_inline_do_write_p } true; {53320#true} is VALID [2022-02-21 04:21:40,525 INFO L290 TraceCheckUtils]: 4: Hoare triple {53320#true} assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 5: Hoare triple {53320#true} assume 0 != eval_~tmp___0~2#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1; {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 6: Hoare triple {53320#true} assume 0 == ~c_dr_pc~0; {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 7: Hoare triple {53320#true} assume !false; {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 8: Hoare triple {53320#true} assume !(1 == ~q_free~0); {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 9: Hoare triple {53320#true} do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_req_up~0 := 1; {53320#true} is VALID [2022-02-21 04:21:40,526 INFO L290 TraceCheckUtils]: 10: Hoare triple {53320#true} assume ~p_last_write~0 == ~c_last_read~0; {53320#true} is VALID [2022-02-21 04:21:40,527 INFO L290 TraceCheckUtils]: 11: Hoare triple {53320#true} assume ~p_num_write~0 == ~c_num_read~0; {53320#true} is VALID [2022-02-21 04:21:40,527 INFO L290 TraceCheckUtils]: 12: Hoare triple {53320#true} assume !false; {53320#true} is VALID [2022-02-21 04:21:40,535 INFO L290 TraceCheckUtils]: 13: Hoare triple {53320#true} assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,536 INFO L290 TraceCheckUtils]: 14: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_do_read_c } true; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,537 INFO L290 TraceCheckUtils]: 15: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !false; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,537 INFO L290 TraceCheckUtils]: 16: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,537 INFO L290 TraceCheckUtils]: 17: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~p_dw_st~0); {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,538 INFO L290 TraceCheckUtils]: 18: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,538 INFO L290 TraceCheckUtils]: 19: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,539 INFO L290 TraceCheckUtils]: 20: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,539 INFO L290 TraceCheckUtils]: 21: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 != eval_~tmp___1~0#1); {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,540 INFO L290 TraceCheckUtils]: 22: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,540 INFO L290 TraceCheckUtils]: 23: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_req_up~0;assume { :begin_inline_update_fifo_q } true; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,541 INFO L290 TraceCheckUtils]: 24: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~q_free~0); {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,541 INFO L290 TraceCheckUtils]: 25: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_free~0;~q_read_ev~0 := 0; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,541 INFO L290 TraceCheckUtils]: 26: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} ~q_ev~0 := 0;~q_req_up~0 := 0; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,542 INFO L290 TraceCheckUtils]: 27: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_update_fifo_q } true; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,542 INFO L290 TraceCheckUtils]: 28: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,543 INFO L290 TraceCheckUtils]: 29: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,543 INFO L290 TraceCheckUtils]: 30: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(0 == ~q_write_ev~0); {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,544 INFO L290 TraceCheckUtils]: 31: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,544 INFO L290 TraceCheckUtils]: 32: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~p_dw_pc~0; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,544 INFO L290 TraceCheckUtils]: 33: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,545 INFO L290 TraceCheckUtils]: 34: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,545 INFO L290 TraceCheckUtils]: 35: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,546 INFO L290 TraceCheckUtils]: 36: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,546 INFO L290 TraceCheckUtils]: 37: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 38: Hoare triple {53322#(= (+ (- 1) ~c_dr_pc~0) 0)} assume !(1 == ~c_dr_pc~0); {53321#false} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 39: Hoare triple {53321#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {53321#false} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 40: Hoare triple {53321#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {53321#false} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 41: Hoare triple {53321#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {53321#false} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 42: Hoare triple {53321#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {53321#false} is VALID [2022-02-21 04:21:40,547 INFO L290 TraceCheckUtils]: 43: Hoare triple {53321#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 44: Hoare triple {53321#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 45: Hoare triple {53321#false} assume !(1 == ~q_write_ev~0); {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 46: Hoare triple {53321#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 47: Hoare triple {53321#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 48: Hoare triple {53321#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 49: Hoare triple {53321#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {53321#false} is VALID [2022-02-21 04:21:40,548 INFO L290 TraceCheckUtils]: 50: Hoare triple {53321#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 51: Hoare triple {53321#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 52: Hoare triple {53321#false} start_simulation_#t~ret13#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 53: Hoare triple {53321#false} assume !(0 != start_simulation_~tmp~4#1); {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 54: Hoare triple {53321#false} assume !false; {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 55: Hoare triple {53321#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {53321#false} is VALID [2022-02-21 04:21:40,549 INFO L290 TraceCheckUtils]: 56: Hoare triple {53321#false} assume !false; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 57: Hoare triple {53321#false} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 58: Hoare triple {53321#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 59: Hoare triple {53321#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 60: Hoare triple {53321#false} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 61: Hoare triple {53321#false} assume 0 != eval_~tmp___1~0#1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 62: Hoare triple {53321#false} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {53321#false} is VALID [2022-02-21 04:21:40,550 INFO L290 TraceCheckUtils]: 63: Hoare triple {53321#false} assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; {53321#false} is VALID [2022-02-21 04:21:40,551 INFO L290 TraceCheckUtils]: 64: Hoare triple {53321#false} assume !(0 == ~p_dw_pc~0); {53321#false} is VALID [2022-02-21 04:21:40,551 INFO L290 TraceCheckUtils]: 65: Hoare triple {53321#false} assume 1 == ~p_dw_pc~0; {53321#false} is VALID [2022-02-21 04:21:40,551 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-02-21 04:21:40,551 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:40,552 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036492927] [2022-02-21 04:21:40,552 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036492927] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:40,552 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:40,552 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:40,552 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097331016] [2022-02-21 04:21:40,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:40,553 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:40,553 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:40,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:40,554 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:40,554 INFO L87 Difference]: Start difference. First operand 1877 states and 2258 transitions. cyclomatic complexity: 383 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:40,682 INFO L93 Difference]: Finished difference Result 995 states and 1175 transitions. [2022-02-21 04:21:40,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:40,682 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,725 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:40,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 995 states and 1175 transitions. [2022-02-21 04:21:40,763 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 946 [2022-02-21 04:21:40,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 995 states to 995 states and 1175 transitions. [2022-02-21 04:21:40,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 995 [2022-02-21 04:21:40,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 995 [2022-02-21 04:21:40,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 995 states and 1175 transitions. [2022-02-21 04:21:40,804 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:40,805 INFO L681 BuchiCegarLoop]: Abstraction has 995 states and 1175 transitions. [2022-02-21 04:21:40,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 995 states and 1175 transitions. [2022-02-21 04:21:40,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 995 to 844. [2022-02-21 04:21:40,814 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:40,815 INFO L82 GeneralOperation]: Start isEquivalent. First operand 995 states and 1175 transitions. Second operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,816 INFO L74 IsIncluded]: Start isIncluded. First operand 995 states and 1175 transitions. Second operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,817 INFO L87 Difference]: Start difference. First operand 995 states and 1175 transitions. Second operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:40,842 INFO L93 Difference]: Finished difference Result 995 states and 1175 transitions. [2022-02-21 04:21:40,842 INFO L276 IsEmpty]: Start isEmpty. Operand 995 states and 1175 transitions. [2022-02-21 04:21:40,843 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:40,843 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:40,844 INFO L74 IsIncluded]: Start isIncluded. First operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 995 states and 1175 transitions. [2022-02-21 04:21:40,845 INFO L87 Difference]: Start difference. First operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 995 states and 1175 transitions. [2022-02-21 04:21:40,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:40,867 INFO L93 Difference]: Finished difference Result 995 states and 1175 transitions. [2022-02-21 04:21:40,867 INFO L276 IsEmpty]: Start isEmpty. Operand 995 states and 1175 transitions. [2022-02-21 04:21:40,868 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:40,868 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:40,868 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:40,868 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:40,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 844 states, 844 states have (on average 1.1919431279620853) internal successors, (1006), 843 states have internal predecessors, (1006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 844 states to 844 states and 1006 transitions. [2022-02-21 04:21:40,893 INFO L704 BuchiCegarLoop]: Abstraction has 844 states and 1006 transitions. [2022-02-21 04:21:40,893 INFO L587 BuchiCegarLoop]: Abstraction has 844 states and 1006 transitions. [2022-02-21 04:21:40,893 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:21:40,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 844 states and 1006 transitions. [2022-02-21 04:21:40,895 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 795 [2022-02-21 04:21:40,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:40,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:40,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,896 INFO L791 eck$LassoCheckResult]: Stem: 54417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 54397#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 54351#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54352#L222 assume !(1 == ~q_req_up~0); 54349#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54350#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 54384#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 54405#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54402#L275 assume !(0 == ~q_read_ev~0); 54403#L275-2 assume !(0 == ~q_write_ev~0); 54385#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 54386#L65 assume !(1 == ~p_dw_pc~0); 54394#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 54395#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 54345#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 54346#L315 assume !(0 != activate_threads_~tmp~1#1); 54355#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 54356#L84 assume !(1 == ~c_dr_pc~0); 54373#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 54364#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 54365#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 54328#L323 assume !(0 != activate_threads_~tmp___0~1#1); 54329#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54416#L293 assume !(1 == ~q_read_ev~0); 54318#L293-2 assume !(1 == ~q_write_ev~0); 54319#L298-1 assume { :end_inline_reset_delta_events } true; 54412#L419-2 assume !false; 54467#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 54466#L364 assume !false; 54465#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 54464#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 54463#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 54462#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 54459#L344 assume 0 != eval_~tmp___1~0#1; 54456#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 54453#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 54450#L128 assume 0 == ~p_dw_pc~0; 54446#L139-1 assume !false; 54441#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 54437#L158 assume { :end_inline_do_write_p } true; 54435#L349 [2022-02-21 04:21:40,897 INFO L793 eck$LassoCheckResult]: Loop: 54435#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 54431#L368 assume !(0 != eval_~tmp___0~2#1); 54432#L364 assume !false; 54460#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 54457#L255 assume !(0 == ~p_dw_st~0); 54454#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 54451#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 54447#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 54443#L344 assume 0 != eval_~tmp___1~0#1; 54438#L344-1 assume !(0 == ~p_dw_st~0); 54435#L349 [2022-02-21 04:21:40,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,897 INFO L85 PathProgramCache]: Analyzing trace with hash 1487677052, now seen corresponding path program 1 times [2022-02-21 04:21:40,897 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,898 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395156930] [2022-02-21 04:21:40,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:40,933 INFO L290 TraceCheckUtils]: 0: Hoare triple {57155#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; {57157#(= ~q_req_up~0 0)} is VALID [2022-02-21 04:21:40,933 INFO L290 TraceCheckUtils]: 1: Hoare triple {57157#(= ~q_req_up~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {57158#(and (= ~q_free~0 1) (= ~q_req_up~0 0))} is VALID [2022-02-21 04:21:40,934 INFO L290 TraceCheckUtils]: 2: Hoare triple {57158#(and (= ~q_free~0 1) (= ~q_req_up~0 0))} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {57158#(and (= ~q_free~0 1) (= ~q_req_up~0 0))} is VALID [2022-02-21 04:21:40,934 INFO L290 TraceCheckUtils]: 3: Hoare triple {57158#(and (= ~q_free~0 1) (= ~q_req_up~0 0))} assume !(1 == ~q_req_up~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,934 INFO L290 TraceCheckUtils]: 4: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,935 INFO L290 TraceCheckUtils]: 5: Hoare triple {57159#(not (= ~q_free~0 0))} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,935 INFO L290 TraceCheckUtils]: 6: Hoare triple {57159#(not (= ~q_free~0 0))} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,935 INFO L290 TraceCheckUtils]: 7: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,935 INFO L290 TraceCheckUtils]: 8: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(0 == ~q_read_ev~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,936 INFO L290 TraceCheckUtils]: 9: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(0 == ~q_write_ev~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,936 INFO L290 TraceCheckUtils]: 10: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,936 INFO L290 TraceCheckUtils]: 11: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(1 == ~p_dw_pc~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,936 INFO L290 TraceCheckUtils]: 12: Hoare triple {57159#(not (= ~q_free~0 0))} is_do_write_p_triggered_~__retres1~0#1 := 0; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,937 INFO L290 TraceCheckUtils]: 13: Hoare triple {57159#(not (= ~q_free~0 0))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,937 INFO L290 TraceCheckUtils]: 14: Hoare triple {57159#(not (= ~q_free~0 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,937 INFO L290 TraceCheckUtils]: 15: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(0 != activate_threads_~tmp~1#1); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,938 INFO L290 TraceCheckUtils]: 16: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,938 INFO L290 TraceCheckUtils]: 17: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(1 == ~c_dr_pc~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,938 INFO L290 TraceCheckUtils]: 18: Hoare triple {57159#(not (= ~q_free~0 0))} is_do_read_c_triggered_~__retres1~1#1 := 0; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,938 INFO L290 TraceCheckUtils]: 19: Hoare triple {57159#(not (= ~q_free~0 0))} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,939 INFO L290 TraceCheckUtils]: 20: Hoare triple {57159#(not (= ~q_free~0 0))} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,939 INFO L290 TraceCheckUtils]: 21: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(0 != activate_threads_~tmp___0~1#1); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,939 INFO L290 TraceCheckUtils]: 22: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,940 INFO L290 TraceCheckUtils]: 23: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(1 == ~q_read_ev~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,940 INFO L290 TraceCheckUtils]: 24: Hoare triple {57159#(not (= ~q_free~0 0))} assume !(1 == ~q_write_ev~0); {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,940 INFO L290 TraceCheckUtils]: 25: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :end_inline_reset_delta_events } true; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,940 INFO L290 TraceCheckUtils]: 26: Hoare triple {57159#(not (= ~q_free~0 0))} assume !false; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,941 INFO L290 TraceCheckUtils]: 27: Hoare triple {57159#(not (= ~q_free~0 0))} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,941 INFO L290 TraceCheckUtils]: 28: Hoare triple {57159#(not (= ~q_free~0 0))} assume !false; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,941 INFO L290 TraceCheckUtils]: 29: Hoare triple {57159#(not (= ~q_free~0 0))} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,942 INFO L290 TraceCheckUtils]: 30: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,942 INFO L290 TraceCheckUtils]: 31: Hoare triple {57159#(not (= ~q_free~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,942 INFO L290 TraceCheckUtils]: 32: Hoare triple {57159#(not (= ~q_free~0 0))} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,943 INFO L290 TraceCheckUtils]: 33: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 != eval_~tmp___1~0#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,943 INFO L290 TraceCheckUtils]: 34: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,944 INFO L290 TraceCheckUtils]: 35: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,944 INFO L290 TraceCheckUtils]: 36: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 == ~p_dw_pc~0; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,944 INFO L290 TraceCheckUtils]: 37: Hoare triple {57159#(not (= ~q_free~0 0))} assume !false; {57159#(not (= ~q_free~0 0))} is VALID [2022-02-21 04:21:40,945 INFO L290 TraceCheckUtils]: 38: Hoare triple {57159#(not (= ~q_free~0 0))} assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; {57156#false} is VALID [2022-02-21 04:21:40,945 INFO L290 TraceCheckUtils]: 39: Hoare triple {57156#false} assume { :end_inline_do_write_p } true; {57156#false} is VALID [2022-02-21 04:21:40,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:40,945 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:40,945 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395156930] [2022-02-21 04:21:40,946 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395156930] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:40,946 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:40,946 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:40,946 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165830520] [2022-02-21 04:21:40,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:40,947 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:40,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1964822518, now seen corresponding path program 2 times [2022-02-21 04:21:40,947 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,948 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306917294] [2022-02-21 04:21:40,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,951 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:40,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,954 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:40,998 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:40,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:40,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:40,999 INFO L87 Difference]: Start difference. First operand 844 states and 1006 transitions. cyclomatic complexity: 165 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:41,353 INFO L93 Difference]: Finished difference Result 1152 states and 1340 transitions. [2022-02-21 04:21:41,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:41,353 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,378 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:41,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,416 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1105 [2022-02-21 04:21:41,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1152 states to 1152 states and 1340 transitions. [2022-02-21 04:21:41,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1152 [2022-02-21 04:21:41,468 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1152 [2022-02-21 04:21:41,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:41,469 INFO L681 BuchiCegarLoop]: Abstraction has 1152 states and 1340 transitions. [2022-02-21 04:21:41,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1152 to 777. [2022-02-21 04:21:41,480 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:41,481 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1152 states and 1340 transitions. Second operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,482 INFO L74 IsIncluded]: Start isIncluded. First operand 1152 states and 1340 transitions. Second operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,483 INFO L87 Difference]: Start difference. First operand 1152 states and 1340 transitions. Second operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:41,530 INFO L93 Difference]: Finished difference Result 1152 states and 1340 transitions. [2022-02-21 04:21:41,530 INFO L276 IsEmpty]: Start isEmpty. Operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,531 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:41,532 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:41,533 INFO L74 IsIncluded]: Start isIncluded. First operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,534 INFO L87 Difference]: Start difference. First operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:41,582 INFO L93 Difference]: Finished difference Result 1152 states and 1340 transitions. [2022-02-21 04:21:41,582 INFO L276 IsEmpty]: Start isEmpty. Operand 1152 states and 1340 transitions. [2022-02-21 04:21:41,583 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:41,583 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:41,584 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:41,584 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:41,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 777 states, 777 states have (on average 1.1853281853281854) internal successors, (921), 776 states have internal predecessors, (921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 777 states to 777 states and 921 transitions. [2022-02-21 04:21:41,608 INFO L704 BuchiCegarLoop]: Abstraction has 777 states and 921 transitions. [2022-02-21 04:21:41,608 INFO L587 BuchiCegarLoop]: Abstraction has 777 states and 921 transitions. [2022-02-21 04:21:41,608 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:21:41,609 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 777 states and 921 transitions. [2022-02-21 04:21:41,611 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 730 [2022-02-21 04:21:41,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:41,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:41,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:41,612 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:41,612 INFO L791 eck$LassoCheckResult]: Stem: 58417#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0; 58399#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 58351#L462 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 58352#L222 assume !(1 == ~q_req_up~0); 58347#L222-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58348#L237 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 58383#L237-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 58405#L242-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58402#L275 assume !(0 == ~q_read_ev~0); 58403#L275-2 assume !(0 == ~q_write_ev~0); 58385#L280-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 58386#L65 assume !(1 == ~p_dw_pc~0); 58394#L65-2 is_do_write_p_triggered_~__retres1~0#1 := 0; 58395#L76 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 58345#L77 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 58346#L315 assume !(0 != activate_threads_~tmp~1#1); 58353#L315-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 58354#L84 assume !(1 == ~c_dr_pc~0); 58371#L84-2 is_do_read_c_triggered_~__retres1~1#1 := 0; 58364#L95 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 58365#L96 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 58326#L323 assume !(0 != activate_threads_~tmp___0~1#1); 58327#L323-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58415#L293 assume !(1 == ~q_read_ev~0); 58318#L293-2 assume !(1 == ~q_write_ev~0); 58319#L298-1 assume { :end_inline_reset_delta_events } true; 58411#L419-2 assume !false; 58455#L420 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 58454#L364 assume !false; 58453#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 58452#L255 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 58451#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 58450#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 58449#L344 assume 0 != eval_~tmp___1~0#1; 58448#L344-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 58447#L353 assume 0 != eval_~tmp~2#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1; 58445#L128 assume 0 == ~p_dw_pc~0; 58443#L139-1 assume !false; 58441#L140 assume !(0 == ~q_free~0); 58439#L141 ~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_req_up~0 := 1; 58437#L139-1 assume !false; 58435#L140 assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1; 58433#L158 assume { :end_inline_do_write_p } true; 58432#L349 [2022-02-21 04:21:41,612 INFO L793 eck$LassoCheckResult]: Loop: 58432#L349 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 58430#L368 assume !(0 != eval_~tmp___0~2#1); 58431#L364 assume !false; 58446#L340 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 58444#L255 assume !(0 == ~p_dw_st~0); 58442#L259 assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 58440#L267 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 58438#L268 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 58436#L344 assume 0 != eval_~tmp___1~0#1; 58434#L344-1 assume !(0 == ~p_dw_st~0); 58432#L349 [2022-02-21 04:21:41,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:41,613 INFO L85 PathProgramCache]: Analyzing trace with hash -377667827, now seen corresponding path program 1 times [2022-02-21 04:21:41,613 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:41,613 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981785667] [2022-02-21 04:21:41,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:41,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:41,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,621 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:41,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,630 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:41,631 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:41,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1964822518, now seen corresponding path program 3 times [2022-02-21 04:21:41,631 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:41,631 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998272609] [2022-02-21 04:21:41,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:41,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:41,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,634 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:41,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,636 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:41,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:41,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1458589694, now seen corresponding path program 1 times [2022-02-21 04:21:41,637 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:41,637 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862501817] [2022-02-21 04:21:41,637 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:41,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:41,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,649 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:41,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:41,658 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:42,585 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:21:42 BoogieIcfgContainer [2022-02-21 04:21:42,585 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:21:42,586 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:21:42,586 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:21:42,586 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:21:42,587 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:32" (3/4) ... [2022-02-21 04:21:42,589 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:21:42,634 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:21:42,634 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:21:42,636 INFO L158 Benchmark]: Toolchain (without parser) took 11252.96ms. Allocated memory was 90.2MB in the beginning and 226.5MB in the end (delta: 136.3MB). Free memory was 48.4MB in the beginning and 99.2MB in the end (delta: -50.9MB). Peak memory consumption was 87.9MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,636 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 90.2MB. Free memory was 65.2MB in the beginning and 65.2MB in the end (delta: 44.5kB). There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:21:42,636 INFO L158 Benchmark]: CACSL2BoogieTranslator took 275.30ms. Allocated memory was 90.2MB in the beginning and 119.5MB in the end (delta: 29.4MB). Free memory was 48.1MB in the beginning and 86.8MB in the end (delta: -38.7MB). Peak memory consumption was 6.2MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,636 INFO L158 Benchmark]: Boogie Procedure Inliner took 52.83ms. Allocated memory is still 119.5MB. Free memory was 86.8MB in the beginning and 83.9MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,637 INFO L158 Benchmark]: Boogie Preprocessor took 58.24ms. Allocated memory is still 119.5MB. Free memory was 83.9MB in the beginning and 82.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,637 INFO L158 Benchmark]: RCFGBuilder took 498.02ms. Allocated memory is still 119.5MB. Free memory was 82.2MB in the beginning and 83.5MB in the end (delta: -1.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,637 INFO L158 Benchmark]: BuchiAutomizer took 10313.90ms. Allocated memory was 119.5MB in the beginning and 226.5MB in the end (delta: 107.0MB). Free memory was 83.3MB in the beginning and 102.5MB in the end (delta: -19.2MB). Peak memory consumption was 88.4MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,638 INFO L158 Benchmark]: Witness Printer took 48.57ms. Allocated memory is still 226.5MB. Free memory was 102.5MB in the beginning and 99.2MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:21:42,639 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 90.2MB. Free memory was 65.2MB in the beginning and 65.2MB in the end (delta: 44.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 275.30ms. Allocated memory was 90.2MB in the beginning and 119.5MB in the end (delta: 29.4MB). Free memory was 48.1MB in the beginning and 86.8MB in the end (delta: -38.7MB). Peak memory consumption was 6.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 52.83ms. Allocated memory is still 119.5MB. Free memory was 86.8MB in the beginning and 83.9MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 58.24ms. Allocated memory is still 119.5MB. Free memory was 83.9MB in the beginning and 82.2MB in the end (delta: 1.7MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 498.02ms. Allocated memory is still 119.5MB. Free memory was 82.2MB in the beginning and 83.5MB in the end (delta: -1.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 10313.90ms. Allocated memory was 119.5MB in the beginning and 226.5MB in the end (delta: 107.0MB). Free memory was 83.3MB in the beginning and 102.5MB in the end (delta: -19.2MB). Peak memory consumption was 88.4MB. Max. memory is 16.1GB. * Witness Printer took 48.57ms. Allocated memory is still 226.5MB. Free memory was 102.5MB in the beginning and 99.2MB in the end (delta: 3.3MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 777 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.2s and 16 iterations. TraceHistogramMax:2. Analysis of lassos took 2.4s. Construction of modules took 0.2s. Büchi inclusion checks took 3.6s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 2.4s AutomataMinimizationTime, 15 MinimizatonAttempts, 2380 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 1.2s Buchi closure took 0.0s. Biggest automaton had 1879 states and ocurred in iteration 12. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2426 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2426 mSDsluCounter, 4424 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2294 mSDsCounter, 92 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 314 IncrementalHoareTripleChecker+Invalid, 406 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 92 mSolverCounterUnsat, 2130 mSDtfsCounter, 314 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc0 concLT0 SILN2 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 364]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=4, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@14a7de19=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@72bd2240=0, q_read_ev=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39092057=0, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c339ba2=0, q_req_up=1, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@39cffc1d=0, p_dw_pc=1, __retres1=1, q_free=0, \result=0, p_dw_st=2, __retres1=0, q_ev=0, tmp___0=0, tmp=5, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@79ab5369=0, kernel_st=1, p_num_write=1, q_buf_0=4, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5b1e5758=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) [L280] COND FALSE !((int )q_write_ev == 0) [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; [L65] COND FALSE !((int )p_dw_pc == 1) [L75] __retres1 = 0 [L77] return (__retres1); [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; [L84] COND FALSE !((int )c_dr_pc == 1) [L94] __retres1 = 0 [L96] return (__retres1); [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) [L298] COND FALSE !((int )q_write_ev == 1) [L416] RET reset_delta_events() [L419] COND TRUE 1 [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND TRUE \read(tmp) [L355] p_dw_st = 1 [L356] CALL do_write_p() [L128] COND TRUE (int )p_dw_pc == 0 [L139] COND TRUE 1 [L141] COND FALSE !((int )q_free == 0) [L151] q_buf_0 = __VERIFIER_nondet_int() [L152] p_last_write = q_buf_0 [L153] p_num_write += 1 [L154] q_free = 0 [L155] q_req_up = 1 [L139] COND TRUE 1 [L141] COND TRUE (int )q_free == 0 [L142] p_dw_st = 2 [L143] p_dw_pc = 1 [L356] RET do_write_p() Loop: [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND FALSE !((int )p_dw_st == 0) [L259] COND TRUE (int )c_dr_st == 0 [L260] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND FALSE !((int )p_dw_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:21:42,698 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)