./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:33,702 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:33,704 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:33,725 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:33,725 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:33,732 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:33,733 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:33,737 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:33,738 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:33,740 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:33,740 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:33,741 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:33,742 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:33,744 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:33,745 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:33,747 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:33,748 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:33,752 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:33,753 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:33,754 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:33,758 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:33,759 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:33,760 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:33,760 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:33,762 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:33,765 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:33,765 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:33,766 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:33,766 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:33,767 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:33,768 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:33,768 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:33,769 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:33,770 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:33,770 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:33,771 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:33,772 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:33,772 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:33,772 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:33,773 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:33,773 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:33,774 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:33,799 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:33,800 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:33,800 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:33,801 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:33,802 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:33,802 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:33,802 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:33,802 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:33,802 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:33,802 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:33,803 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:33,803 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:33,803 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:33,803 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:33,804 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:33,805 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:33,806 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:33,806 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:33,806 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:33,806 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:33,806 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:33,807 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:33,807 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2022-02-21 04:21:33,993 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:34,012 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:34,014 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:34,015 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:34,015 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:34,016 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-02-21 04:21:34,063 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/535444e91/c9cafade8528413882183b259a215224/FLAG8e3b274f7 [2022-02-21 04:21:34,445 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:34,445 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2022-02-21 04:21:34,453 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/535444e91/c9cafade8528413882183b259a215224/FLAG8e3b274f7 [2022-02-21 04:21:34,464 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/535444e91/c9cafade8528413882183b259a215224 [2022-02-21 04:21:34,466 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:34,467 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:34,469 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:34,469 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:34,471 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:34,472 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,472 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3688c4f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34, skipping insertion in model container [2022-02-21 04:21:34,473 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,477 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:34,496 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:34,629 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-02-21 04:21:34,694 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:34,701 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:34,707 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c[640,653] [2022-02-21 04:21:34,725 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:34,737 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:34,738 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34 WrapperNode [2022-02-21 04:21:34,738 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:34,739 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:34,739 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:34,739 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:34,744 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,749 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,780 INFO L137 Inliner]: procedures = 31, calls = 35, calls flagged for inlining = 30, calls inlined = 33, statements flattened = 406 [2022-02-21 04:21:34,781 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:34,781 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:34,781 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:34,782 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:34,786 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,786 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,788 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,788 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,797 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,813 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,814 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,816 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:34,817 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:34,817 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:34,817 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:34,818 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (1/1) ... [2022-02-21 04:21:34,823 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:34,831 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:34,839 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:34,848 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:34,871 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:34,871 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:34,871 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:34,871 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:34,917 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:34,918 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:35,231 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##104: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2022-02-21 04:21:35,231 INFO L766 $ProcedureCfgBuilder]: dead code at ProgramPoint $Ultimate##105: assume !(1 == ~q_free~0); [2022-02-21 04:21:35,231 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:35,236 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:35,236 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-02-21 04:21:35,238 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:35 BoogieIcfgContainer [2022-02-21 04:21:35,238 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:35,239 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:35,239 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:35,241 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:35,241 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:35,242 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:34" (1/3) ... [2022-02-21 04:21:35,242 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18c6ebcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:35, skipping insertion in model container [2022-02-21 04:21:35,242 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:35,242 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:34" (2/3) ... [2022-02-21 04:21:35,243 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@18c6ebcb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:35, skipping insertion in model container [2022-02-21 04:21:35,243 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:35,243 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:35" (3/3) ... [2022-02-21 04:21:35,244 INFO L388 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2022-02-21 04:21:35,278 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:35,278 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:35,278 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:35,279 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:35,279 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:35,279 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:35,279 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:35,279 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:35,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-02-21 04:21:35,348 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,348 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,353 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,354 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,354 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:35,355 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,367 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2022-02-21 04:21:35,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,369 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,370 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,373 INFO L791 eck$LassoCheckResult]: Stem: 131#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 39#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 29#L551true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31#L258true assume !(1 == ~q_req_up~0); 68#L258-2true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60#L273true assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 109#L273-2true assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; 97#L278-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48#L311true assume !(0 == ~q_read_ev~0); 98#L311-2true assume !(0 == ~q_write_ev~0); 76#L316-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 35#L66true assume 1 == ~p_dw_pc~0; 130#L67true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 55#L87true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 90#L88true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 53#L387true assume !(0 != activate_threads_~tmp~1#1); 103#L387-2true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 82#L95true assume 1 == ~c_dr_pc~0; 116#L96true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 27#L116true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 7#L117true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 77#L395true assume !(0 != activate_threads_~tmp___0~1#1); 14#L395-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33#L329true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 56#L329-2true assume !(1 == ~q_write_ev~0); 37#L334-1true assume { :end_inline_reset_delta_events } true; 127#L491-2true [2022-02-21 04:21:35,374 INFO L793 eck$LassoCheckResult]: Loop: 127#L491-2true assume !false; 128#L492true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 94#L435true assume !true; 144#L451true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59#L258-3true assume !(1 == ~q_req_up~0); 106#L258-5true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132#L311-3true assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 110#L311-5true assume !(0 == ~q_write_ev~0); 69#L316-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 108#L66-3true assume 1 == ~p_dw_pc~0; 91#L67-1true assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 11#L87-1true is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 126#L88-1true activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 121#L387-3true assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 36#L387-5true assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 124#L95-3true assume 1 == ~c_dr_pc~0; 64#L96-1true assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 100#L116-1true is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 95#L117-1true activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 133#L395-3true assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 20#L395-5true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44#L329-3true assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 85#L329-5true assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 140#L334-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 51#L291-1true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 101#L303-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 102#L304-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 78#L510true assume !(0 == start_simulation_~tmp~4#1); 8#L510-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 73#L291-2true assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 89#L303-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 93#L304-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 141#L465true assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 34#L472true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 137#L473true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 75#L523true assume !(0 != start_simulation_~tmp___0~3#1); 127#L491-2true [2022-02-21 04:21:35,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,378 INFO L85 PathProgramCache]: Analyzing trace with hash 854607455, now seen corresponding path program 1 times [2022-02-21 04:21:35,387 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,388 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [911739833] [2022-02-21 04:21:35,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,551 INFO L290 TraceCheckUtils]: 0: Hoare triple {146#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {146#true} is VALID [2022-02-21 04:21:35,553 INFO L290 TraceCheckUtils]: 1: Hoare triple {146#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {148#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:35,554 INFO L290 TraceCheckUtils]: 2: Hoare triple {148#(= 1 ~c_dr_i~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {148#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:35,555 INFO L290 TraceCheckUtils]: 3: Hoare triple {148#(= 1 ~c_dr_i~0)} assume !(1 == ~q_req_up~0); {148#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:35,556 INFO L290 TraceCheckUtils]: 4: Hoare triple {148#(= 1 ~c_dr_i~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {148#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:35,557 INFO L290 TraceCheckUtils]: 5: Hoare triple {148#(= 1 ~c_dr_i~0)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {148#(= 1 ~c_dr_i~0)} is VALID [2022-02-21 04:21:35,558 INFO L290 TraceCheckUtils]: 6: Hoare triple {148#(= 1 ~c_dr_i~0)} assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2; {147#false} is VALID [2022-02-21 04:21:35,558 INFO L290 TraceCheckUtils]: 7: Hoare triple {147#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {147#false} is VALID [2022-02-21 04:21:35,559 INFO L290 TraceCheckUtils]: 8: Hoare triple {147#false} assume !(0 == ~q_read_ev~0); {147#false} is VALID [2022-02-21 04:21:35,559 INFO L290 TraceCheckUtils]: 9: Hoare triple {147#false} assume !(0 == ~q_write_ev~0); {147#false} is VALID [2022-02-21 04:21:35,559 INFO L290 TraceCheckUtils]: 10: Hoare triple {147#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {147#false} is VALID [2022-02-21 04:21:35,559 INFO L290 TraceCheckUtils]: 11: Hoare triple {147#false} assume 1 == ~p_dw_pc~0; {147#false} is VALID [2022-02-21 04:21:35,559 INFO L290 TraceCheckUtils]: 12: Hoare triple {147#false} assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {147#false} is VALID [2022-02-21 04:21:35,560 INFO L290 TraceCheckUtils]: 13: Hoare triple {147#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {147#false} is VALID [2022-02-21 04:21:35,560 INFO L290 TraceCheckUtils]: 14: Hoare triple {147#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {147#false} is VALID [2022-02-21 04:21:35,560 INFO L290 TraceCheckUtils]: 15: Hoare triple {147#false} assume !(0 != activate_threads_~tmp~1#1); {147#false} is VALID [2022-02-21 04:21:35,560 INFO L290 TraceCheckUtils]: 16: Hoare triple {147#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {147#false} is VALID [2022-02-21 04:21:35,560 INFO L290 TraceCheckUtils]: 17: Hoare triple {147#false} assume 1 == ~c_dr_pc~0; {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 18: Hoare triple {147#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 19: Hoare triple {147#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 20: Hoare triple {147#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 21: Hoare triple {147#false} assume !(0 != activate_threads_~tmp___0~1#1); {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 22: Hoare triple {147#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {147#false} is VALID [2022-02-21 04:21:35,561 INFO L290 TraceCheckUtils]: 23: Hoare triple {147#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {147#false} is VALID [2022-02-21 04:21:35,562 INFO L290 TraceCheckUtils]: 24: Hoare triple {147#false} assume !(1 == ~q_write_ev~0); {147#false} is VALID [2022-02-21 04:21:35,562 INFO L290 TraceCheckUtils]: 25: Hoare triple {147#false} assume { :end_inline_reset_delta_events } true; {147#false} is VALID [2022-02-21 04:21:35,563 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,564 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,564 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [911739833] [2022-02-21 04:21:35,565 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [911739833] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,565 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,565 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:35,566 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977634174] [2022-02-21 04:21:35,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,569 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:35,571 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,572 INFO L85 PathProgramCache]: Analyzing trace with hash 784504738, now seen corresponding path program 1 times [2022-02-21 04:21:35,572 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,572 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393670482] [2022-02-21 04:21:35,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:35,605 INFO L290 TraceCheckUtils]: 0: Hoare triple {149#true} assume !false; {149#true} is VALID [2022-02-21 04:21:35,606 INFO L290 TraceCheckUtils]: 1: Hoare triple {149#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {149#true} is VALID [2022-02-21 04:21:35,606 INFO L290 TraceCheckUtils]: 2: Hoare triple {149#true} assume !true; {150#false} is VALID [2022-02-21 04:21:35,606 INFO L290 TraceCheckUtils]: 3: Hoare triple {150#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {150#false} is VALID [2022-02-21 04:21:35,606 INFO L290 TraceCheckUtils]: 4: Hoare triple {150#false} assume !(1 == ~q_req_up~0); {150#false} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 5: Hoare triple {150#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {150#false} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 6: Hoare triple {150#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {150#false} is VALID [2022-02-21 04:21:35,607 INFO L290 TraceCheckUtils]: 7: Hoare triple {150#false} assume !(0 == ~q_write_ev~0); {150#false} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 8: Hoare triple {150#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {150#false} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 9: Hoare triple {150#false} assume 1 == ~p_dw_pc~0; {150#false} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 10: Hoare triple {150#false} assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {150#false} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 11: Hoare triple {150#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {150#false} is VALID [2022-02-21 04:21:35,608 INFO L290 TraceCheckUtils]: 12: Hoare triple {150#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {150#false} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 13: Hoare triple {150#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {150#false} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 14: Hoare triple {150#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {150#false} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 15: Hoare triple {150#false} assume 1 == ~c_dr_pc~0; {150#false} is VALID [2022-02-21 04:21:35,609 INFO L290 TraceCheckUtils]: 16: Hoare triple {150#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {150#false} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 17: Hoare triple {150#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {150#false} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 18: Hoare triple {150#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {150#false} is VALID [2022-02-21 04:21:35,610 INFO L290 TraceCheckUtils]: 19: Hoare triple {150#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {150#false} is VALID [2022-02-21 04:21:35,611 INFO L290 TraceCheckUtils]: 20: Hoare triple {150#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {150#false} is VALID [2022-02-21 04:21:35,612 INFO L290 TraceCheckUtils]: 21: Hoare triple {150#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {150#false} is VALID [2022-02-21 04:21:35,613 INFO L290 TraceCheckUtils]: 22: Hoare triple {150#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {150#false} is VALID [2022-02-21 04:21:35,613 INFO L290 TraceCheckUtils]: 23: Hoare triple {150#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {150#false} is VALID [2022-02-21 04:21:35,615 INFO L290 TraceCheckUtils]: 24: Hoare triple {150#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {150#false} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 25: Hoare triple {150#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {150#false} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 26: Hoare triple {150#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {150#false} is VALID [2022-02-21 04:21:35,616 INFO L290 TraceCheckUtils]: 27: Hoare triple {150#false} assume !(0 == start_simulation_~tmp~4#1); {150#false} is VALID [2022-02-21 04:21:35,617 INFO L290 TraceCheckUtils]: 28: Hoare triple {150#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {150#false} is VALID [2022-02-21 04:21:35,618 INFO L290 TraceCheckUtils]: 29: Hoare triple {150#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {150#false} is VALID [2022-02-21 04:21:35,618 INFO L290 TraceCheckUtils]: 30: Hoare triple {150#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {150#false} is VALID [2022-02-21 04:21:35,619 INFO L290 TraceCheckUtils]: 31: Hoare triple {150#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {150#false} is VALID [2022-02-21 04:21:35,619 INFO L290 TraceCheckUtils]: 32: Hoare triple {150#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {150#false} is VALID [2022-02-21 04:21:35,619 INFO L290 TraceCheckUtils]: 33: Hoare triple {150#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {150#false} is VALID [2022-02-21 04:21:35,619 INFO L290 TraceCheckUtils]: 34: Hoare triple {150#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {150#false} is VALID [2022-02-21 04:21:35,619 INFO L290 TraceCheckUtils]: 35: Hoare triple {150#false} assume !(0 != start_simulation_~tmp___0~3#1); {150#false} is VALID [2022-02-21 04:21:35,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:35,620 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:35,621 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393670482] [2022-02-21 04:21:35,621 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393670482] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:35,621 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:35,621 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:35,621 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947581477] [2022-02-21 04:21:35,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:35,623 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:35,624 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:35,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:35,645 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:35,649 INFO L87 Difference]: Start difference. First operand has 142 states, 141 states have (on average 1.5602836879432624) internal successors, (220), 141 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,833 INFO L93 Difference]: Finished difference Result 140 states and 207 transitions. [2022-02-21 04:21:35,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:35,835 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,853 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:35,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 140 states and 207 transitions. [2022-02-21 04:21:35,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-02-21 04:21:35,879 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 140 states to 134 states and 201 transitions. [2022-02-21 04:21:35,879 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 134 [2022-02-21 04:21:35,880 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 134 [2022-02-21 04:21:35,880 INFO L73 IsDeterministic]: Start isDeterministic. Operand 134 states and 201 transitions. [2022-02-21 04:21:35,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:35,880 INFO L681 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-02-21 04:21:35,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states and 201 transitions. [2022-02-21 04:21:35,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2022-02-21 04:21:35,906 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:35,909 INFO L82 GeneralOperation]: Start isEquivalent. First operand 134 states and 201 transitions. Second operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,910 INFO L74 IsIncluded]: Start isIncluded. First operand 134 states and 201 transitions. Second operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,912 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. Second operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,916 INFO L93 Difference]: Finished difference Result 134 states and 201 transitions. [2022-02-21 04:21:35,916 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 201 transitions. [2022-02-21 04:21:35,917 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,917 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,917 INFO L74 IsIncluded]: Start isIncluded. First operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 134 states and 201 transitions. [2022-02-21 04:21:35,917 INFO L87 Difference]: Start difference. First operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 134 states and 201 transitions. [2022-02-21 04:21:35,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:35,920 INFO L93 Difference]: Finished difference Result 134 states and 201 transitions. [2022-02-21 04:21:35,920 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 201 transitions. [2022-02-21 04:21:35,921 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:35,921 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:35,921 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:35,921 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:35,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.5) internal successors, (201), 133 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:35,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 201 transitions. [2022-02-21 04:21:35,925 INFO L704 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-02-21 04:21:35,925 INFO L587 BuchiCegarLoop]: Abstraction has 134 states and 201 transitions. [2022-02-21 04:21:35,925 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:35,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 201 transitions. [2022-02-21 04:21:35,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2022-02-21 04:21:35,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:35,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:35,927 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,927 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:35,927 INFO L791 eck$LassoCheckResult]: Stem: 424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 336#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 337#L258 assume !(1 == ~q_req_up~0); 341#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 387#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 410#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 365#L311 assume !(0 == ~q_read_ev~0); 366#L311-2 assume !(0 == ~q_write_ev~0); 396#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 345#L66 assume 1 == ~p_dw_pc~0; 347#L67 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 379#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 380#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 375#L387 assume !(0 != activate_threads_~tmp~1#1); 376#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 400#L95 assume 1 == ~c_dr_pc~0; 402#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 333#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 298#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 299#L395 assume !(0 != activate_threads_~tmp___0~1#1); 311#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 312#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 344#L329-2 assume !(1 == ~q_write_ev~0); 350#L334-1 assume { :end_inline_reset_delta_events } true; 351#L491-2 [2022-02-21 04:21:35,934 INFO L793 eck$LassoCheckResult]: Loop: 351#L491-2 assume !false; 423#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 352#L435 assume !false; 381#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 382#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 297#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 411#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 412#L415 assume !(0 != eval_~tmp___1~0#1); 420#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#L258-3 assume !(1 == ~q_req_up~0); 385#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 415#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 418#L311-5 assume !(0 == ~q_write_ev~0); 393#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 394#L66-3 assume 1 == ~p_dw_pc~0; 406#L67-1 assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; 303#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 308#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 422#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 348#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 349#L95-3 assume 1 == ~c_dr_pc~0; 389#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 390#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 408#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 409#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 318#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 361#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 403#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 372#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 373#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 413#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 397#L510 assume !(0 == start_simulation_~tmp~4#1); 300#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 301#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 335#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 405#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 407#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 342#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 343#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 395#L523 assume !(0 != start_simulation_~tmp___0~3#1); 351#L491-2 [2022-02-21 04:21:35,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:35,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1672255905, now seen corresponding path program 1 times [2022-02-21 04:21:35,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:35,940 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285105627] [2022-02-21 04:21:35,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:35,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:35,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:36,010 INFO L290 TraceCheckUtils]: 0: Hoare triple {696#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {698#(= ~q_req_up~0 0)} is VALID [2022-02-21 04:21:36,011 INFO L290 TraceCheckUtils]: 1: Hoare triple {698#(= ~q_req_up~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {699#(= ~q_req_up~0 ~p_dw_pc~0)} is VALID [2022-02-21 04:21:36,012 INFO L290 TraceCheckUtils]: 2: Hoare triple {699#(= ~q_req_up~0 ~p_dw_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {699#(= ~q_req_up~0 ~p_dw_pc~0)} is VALID [2022-02-21 04:21:36,012 INFO L290 TraceCheckUtils]: 3: Hoare triple {699#(= ~q_req_up~0 ~p_dw_pc~0)} assume !(1 == ~q_req_up~0); {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,013 INFO L290 TraceCheckUtils]: 4: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,013 INFO L290 TraceCheckUtils]: 5: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,013 INFO L290 TraceCheckUtils]: 6: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,014 INFO L290 TraceCheckUtils]: 7: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,014 INFO L290 TraceCheckUtils]: 8: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume !(0 == ~q_read_ev~0); {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,015 INFO L290 TraceCheckUtils]: 9: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume !(0 == ~q_write_ev~0); {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,015 INFO L290 TraceCheckUtils]: 10: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {700#(not (= ~p_dw_pc~0 1))} is VALID [2022-02-21 04:21:36,015 INFO L290 TraceCheckUtils]: 11: Hoare triple {700#(not (= ~p_dw_pc~0 1))} assume 1 == ~p_dw_pc~0; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 12: Hoare triple {697#false} assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 13: Hoare triple {697#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 14: Hoare triple {697#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 15: Hoare triple {697#false} assume !(0 != activate_threads_~tmp~1#1); {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 16: Hoare triple {697#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 17: Hoare triple {697#false} assume 1 == ~c_dr_pc~0; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 18: Hoare triple {697#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {697#false} is VALID [2022-02-21 04:21:36,016 INFO L290 TraceCheckUtils]: 19: Hoare triple {697#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 20: Hoare triple {697#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 21: Hoare triple {697#false} assume !(0 != activate_threads_~tmp___0~1#1); {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 22: Hoare triple {697#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 23: Hoare triple {697#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 24: Hoare triple {697#false} assume !(1 == ~q_write_ev~0); {697#false} is VALID [2022-02-21 04:21:36,017 INFO L290 TraceCheckUtils]: 25: Hoare triple {697#false} assume { :end_inline_reset_delta_events } true; {697#false} is VALID [2022-02-21 04:21:36,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:36,018 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:36,018 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285105627] [2022-02-21 04:21:36,018 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285105627] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:36,018 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:36,018 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:36,018 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643840988] [2022-02-21 04:21:36,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:36,019 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:36,019 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:36,019 INFO L85 PathProgramCache]: Analyzing trace with hash 2119142840, now seen corresponding path program 1 times [2022-02-21 04:21:36,019 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:36,019 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221930018] [2022-02-21 04:21:36,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:36,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:36,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:36,063 INFO L290 TraceCheckUtils]: 0: Hoare triple {701#true} assume !false; {701#true} is VALID [2022-02-21 04:21:36,063 INFO L290 TraceCheckUtils]: 1: Hoare triple {701#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {701#true} is VALID [2022-02-21 04:21:36,063 INFO L290 TraceCheckUtils]: 2: Hoare triple {701#true} assume !false; {701#true} is VALID [2022-02-21 04:21:36,063 INFO L290 TraceCheckUtils]: 3: Hoare triple {701#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {701#true} is VALID [2022-02-21 04:21:36,064 INFO L290 TraceCheckUtils]: 4: Hoare triple {701#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {703#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:36,064 INFO L290 TraceCheckUtils]: 5: Hoare triple {703#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {704#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:36,065 INFO L290 TraceCheckUtils]: 6: Hoare triple {704#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {705#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:36,065 INFO L290 TraceCheckUtils]: 7: Hoare triple {705#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {702#false} is VALID [2022-02-21 04:21:36,065 INFO L290 TraceCheckUtils]: 8: Hoare triple {702#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {702#false} is VALID [2022-02-21 04:21:36,066 INFO L290 TraceCheckUtils]: 9: Hoare triple {702#false} assume !(1 == ~q_req_up~0); {702#false} is VALID [2022-02-21 04:21:36,066 INFO L290 TraceCheckUtils]: 10: Hoare triple {702#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {702#false} is VALID [2022-02-21 04:21:36,066 INFO L290 TraceCheckUtils]: 11: Hoare triple {702#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 12: Hoare triple {702#false} assume !(0 == ~q_write_ev~0); {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 13: Hoare triple {702#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 14: Hoare triple {702#false} assume 1 == ~p_dw_pc~0; {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 15: Hoare triple {702#false} assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1; {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 16: Hoare triple {702#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {702#false} is VALID [2022-02-21 04:21:36,067 INFO L290 TraceCheckUtils]: 17: Hoare triple {702#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 18: Hoare triple {702#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 19: Hoare triple {702#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 20: Hoare triple {702#false} assume 1 == ~c_dr_pc~0; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 21: Hoare triple {702#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 22: Hoare triple {702#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 23: Hoare triple {702#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 24: Hoare triple {702#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:36,068 INFO L290 TraceCheckUtils]: 25: Hoare triple {702#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {702#false} is VALID [2022-02-21 04:21:36,069 INFO L290 TraceCheckUtils]: 26: Hoare triple {702#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {702#false} is VALID [2022-02-21 04:21:36,069 INFO L290 TraceCheckUtils]: 27: Hoare triple {702#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {702#false} is VALID [2022-02-21 04:21:36,069 INFO L290 TraceCheckUtils]: 28: Hoare triple {702#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:36,069 INFO L290 TraceCheckUtils]: 29: Hoare triple {702#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {702#false} is VALID [2022-02-21 04:21:36,069 INFO L290 TraceCheckUtils]: 30: Hoare triple {702#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 31: Hoare triple {702#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 32: Hoare triple {702#false} assume !(0 == start_simulation_~tmp~4#1); {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 33: Hoare triple {702#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 34: Hoare triple {702#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 35: Hoare triple {702#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 36: Hoare triple {702#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {702#false} is VALID [2022-02-21 04:21:36,070 INFO L290 TraceCheckUtils]: 37: Hoare triple {702#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {702#false} is VALID [2022-02-21 04:21:36,071 INFO L290 TraceCheckUtils]: 38: Hoare triple {702#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {702#false} is VALID [2022-02-21 04:21:36,071 INFO L290 TraceCheckUtils]: 39: Hoare triple {702#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {702#false} is VALID [2022-02-21 04:21:36,071 INFO L290 TraceCheckUtils]: 40: Hoare triple {702#false} assume !(0 != start_simulation_~tmp___0~3#1); {702#false} is VALID [2022-02-21 04:21:36,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:36,071 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:36,072 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221930018] [2022-02-21 04:21:36,072 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221930018] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:36,072 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:36,072 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:36,072 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684356482] [2022-02-21 04:21:36,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:36,072 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:36,073 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:36,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:36,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:36,073 INFO L87 Difference]: Start difference. First operand 134 states and 201 transitions. cyclomatic complexity: 68 Second operand has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,757 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2022-02-21 04:21:36,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:36,757 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 5.2) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,773 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:36,774 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 696 transitions. [2022-02-21 04:21:36,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 446 [2022-02-21 04:21:36,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 696 transitions. [2022-02-21 04:21:36,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2022-02-21 04:21:36,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2022-02-21 04:21:36,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 696 transitions. [2022-02-21 04:21:36,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:36,818 INFO L681 BuchiCegarLoop]: Abstraction has 479 states and 696 transitions. [2022-02-21 04:21:36,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 696 transitions. [2022-02-21 04:21:36,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 466. [2022-02-21 04:21:36,833 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:36,835 INFO L82 GeneralOperation]: Start isEquivalent. First operand 479 states and 696 transitions. Second operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,836 INFO L74 IsIncluded]: Start isIncluded. First operand 479 states and 696 transitions. Second operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,837 INFO L87 Difference]: Start difference. First operand 479 states and 696 transitions. Second operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,852 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2022-02-21 04:21:36,852 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 696 transitions. [2022-02-21 04:21:36,854 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:36,854 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:36,855 INFO L74 IsIncluded]: Start isIncluded. First operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 479 states and 696 transitions. [2022-02-21 04:21:36,856 INFO L87 Difference]: Start difference. First operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 479 states and 696 transitions. [2022-02-21 04:21:36,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:36,872 INFO L93 Difference]: Finished difference Result 479 states and 696 transitions. [2022-02-21 04:21:36,872 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 696 transitions. [2022-02-21 04:21:36,874 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:36,874 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:36,874 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:36,874 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:36,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 466 states, 466 states have (on average 1.4656652360515021) internal successors, (683), 465 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:36,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 683 transitions. [2022-02-21 04:21:36,889 INFO L704 BuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-02-21 04:21:36,889 INFO L587 BuchiCegarLoop]: Abstraction has 466 states and 683 transitions. [2022-02-21 04:21:36,889 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:36,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 466 states and 683 transitions. [2022-02-21 04:21:36,892 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 435 [2022-02-21 04:21:36,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:36,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:36,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:36,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:36,893 INFO L791 eck$LassoCheckResult]: Stem: 1336#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 1253#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 1237#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1238#L258 assume !(1 == ~q_req_up~0); 1241#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1284#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 1285#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 1317#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1265#L311 assume !(0 == ~q_read_ev~0); 1266#L311-2 assume !(0 == ~q_write_ev~0); 1296#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1245#L66 assume !(1 == ~p_dw_pc~0); 1246#L66-2 assume !(2 == ~p_dw_pc~0); 1257#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 1278#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1279#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1274#L387 assume !(0 != activate_threads_~tmp~1#1); 1275#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1302#L95 assume 1 == ~c_dr_pc~0; 1304#L96 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1234#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1196#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1197#L395 assume !(0 != activate_threads_~tmp___0~1#1); 1209#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1210#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1244#L329-2 assume !(1 == ~q_write_ev~0); 1249#L334-1 assume { :end_inline_reset_delta_events } true; 1250#L491-2 [2022-02-21 04:21:36,893 INFO L793 eck$LassoCheckResult]: Loop: 1250#L491-2 assume !false; 1335#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 1251#L435 assume !false; 1280#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1281#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1195#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1319#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1320#L415 assume !(0 != eval_~tmp___1~0#1); 1327#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1282#L258-3 assume !(1 == ~q_req_up~0); 1283#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1322#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 1325#L311-5 assume !(0 == ~q_write_ev~0); 1291#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 1292#L66-3 assume !(1 == ~p_dw_pc~0); 1270#L66-5 assume !(2 == ~p_dw_pc~0); 1200#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 1201#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 1206#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1332#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 1247#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 1248#L95-3 assume 1 == ~c_dr_pc~0; 1287#L96-1 assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; 1288#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 1315#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1316#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 1218#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1219#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 1256#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 1308#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1271#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1272#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1318#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1297#L510 assume !(0 == start_simulation_~tmp~4#1); 1198#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1199#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1236#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1310#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1314#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 1242#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1243#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1295#L523 assume !(0 != start_simulation_~tmp___0~3#1); 1250#L491-2 [2022-02-21 04:21:36,893 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:36,894 INFO L85 PathProgramCache]: Analyzing trace with hash -841270075, now seen corresponding path program 1 times [2022-02-21 04:21:36,894 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:36,894 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209203823] [2022-02-21 04:21:36,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:36,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:36,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:36,926 INFO L290 TraceCheckUtils]: 0: Hoare triple {2616#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {2618#(= ~q_req_up~0 0)} is VALID [2022-02-21 04:21:36,927 INFO L290 TraceCheckUtils]: 1: Hoare triple {2618#(= ~q_req_up~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {2619#(= ~c_dr_pc~0 ~q_req_up~0)} is VALID [2022-02-21 04:21:36,928 INFO L290 TraceCheckUtils]: 2: Hoare triple {2619#(= ~c_dr_pc~0 ~q_req_up~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2619#(= ~c_dr_pc~0 ~q_req_up~0)} is VALID [2022-02-21 04:21:36,928 INFO L290 TraceCheckUtils]: 3: Hoare triple {2619#(= ~c_dr_pc~0 ~q_req_up~0)} assume !(1 == ~q_req_up~0); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,928 INFO L290 TraceCheckUtils]: 4: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,929 INFO L290 TraceCheckUtils]: 5: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,929 INFO L290 TraceCheckUtils]: 6: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,929 INFO L290 TraceCheckUtils]: 7: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,930 INFO L290 TraceCheckUtils]: 8: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume !(0 == ~q_read_ev~0); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,930 INFO L290 TraceCheckUtils]: 9: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume !(0 == ~q_write_ev~0); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,930 INFO L290 TraceCheckUtils]: 10: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,931 INFO L290 TraceCheckUtils]: 11: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume !(1 == ~p_dw_pc~0); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,931 INFO L290 TraceCheckUtils]: 12: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume !(2 == ~p_dw_pc~0); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,931 INFO L290 TraceCheckUtils]: 13: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} is_do_write_p_triggered_~__retres1~0#1 := 0; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,932 INFO L290 TraceCheckUtils]: 14: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,932 INFO L290 TraceCheckUtils]: 15: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,932 INFO L290 TraceCheckUtils]: 16: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 17: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {2620#(not (= ~c_dr_pc~0 1))} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 18: Hoare triple {2620#(not (= ~c_dr_pc~0 1))} assume 1 == ~c_dr_pc~0; {2617#false} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 19: Hoare triple {2617#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {2617#false} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 20: Hoare triple {2617#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {2617#false} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 21: Hoare triple {2617#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {2617#false} is VALID [2022-02-21 04:21:36,933 INFO L290 TraceCheckUtils]: 22: Hoare triple {2617#false} assume !(0 != activate_threads_~tmp___0~1#1); {2617#false} is VALID [2022-02-21 04:21:36,934 INFO L290 TraceCheckUtils]: 23: Hoare triple {2617#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2617#false} is VALID [2022-02-21 04:21:36,934 INFO L290 TraceCheckUtils]: 24: Hoare triple {2617#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {2617#false} is VALID [2022-02-21 04:21:36,934 INFO L290 TraceCheckUtils]: 25: Hoare triple {2617#false} assume !(1 == ~q_write_ev~0); {2617#false} is VALID [2022-02-21 04:21:36,934 INFO L290 TraceCheckUtils]: 26: Hoare triple {2617#false} assume { :end_inline_reset_delta_events } true; {2617#false} is VALID [2022-02-21 04:21:36,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:36,934 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:36,934 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209203823] [2022-02-21 04:21:36,934 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209203823] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:36,935 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:36,935 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-02-21 04:21:36,935 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496236165] [2022-02-21 04:21:36,935 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:36,935 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:36,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:36,936 INFO L85 PathProgramCache]: Analyzing trace with hash 1851475893, now seen corresponding path program 1 times [2022-02-21 04:21:36,936 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:36,936 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331161112] [2022-02-21 04:21:36,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:36,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:36,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:36,967 INFO L290 TraceCheckUtils]: 0: Hoare triple {2621#true} assume !false; {2621#true} is VALID [2022-02-21 04:21:36,967 INFO L290 TraceCheckUtils]: 1: Hoare triple {2621#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {2621#true} is VALID [2022-02-21 04:21:36,967 INFO L290 TraceCheckUtils]: 2: Hoare triple {2621#true} assume !false; {2621#true} is VALID [2022-02-21 04:21:36,967 INFO L290 TraceCheckUtils]: 3: Hoare triple {2621#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {2621#true} is VALID [2022-02-21 04:21:36,968 INFO L290 TraceCheckUtils]: 4: Hoare triple {2621#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {2623#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:36,968 INFO L290 TraceCheckUtils]: 5: Hoare triple {2623#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {2624#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:36,969 INFO L290 TraceCheckUtils]: 6: Hoare triple {2624#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {2625#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:36,969 INFO L290 TraceCheckUtils]: 7: Hoare triple {2625#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 8: Hoare triple {2622#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 9: Hoare triple {2622#false} assume !(1 == ~q_req_up~0); {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 10: Hoare triple {2622#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 11: Hoare triple {2622#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 12: Hoare triple {2622#false} assume !(0 == ~q_write_ev~0); {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 13: Hoare triple {2622#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 14: Hoare triple {2622#false} assume !(1 == ~p_dw_pc~0); {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 15: Hoare triple {2622#false} assume !(2 == ~p_dw_pc~0); {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 16: Hoare triple {2622#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 17: Hoare triple {2622#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {2622#false} is VALID [2022-02-21 04:21:36,970 INFO L290 TraceCheckUtils]: 18: Hoare triple {2622#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {2622#false} is VALID [2022-02-21 04:21:36,971 INFO L290 TraceCheckUtils]: 19: Hoare triple {2622#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {2622#false} is VALID [2022-02-21 04:21:36,971 INFO L290 TraceCheckUtils]: 20: Hoare triple {2622#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {2622#false} is VALID [2022-02-21 04:21:36,971 INFO L290 TraceCheckUtils]: 21: Hoare triple {2622#false} assume 1 == ~c_dr_pc~0; {2622#false} is VALID [2022-02-21 04:21:36,972 INFO L290 TraceCheckUtils]: 22: Hoare triple {2622#false} assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1; {2622#false} is VALID [2022-02-21 04:21:36,972 INFO L290 TraceCheckUtils]: 23: Hoare triple {2622#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {2622#false} is VALID [2022-02-21 04:21:36,972 INFO L290 TraceCheckUtils]: 24: Hoare triple {2622#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 25: Hoare triple {2622#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 26: Hoare triple {2622#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 27: Hoare triple {2622#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 28: Hoare triple {2622#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 29: Hoare triple {2622#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 30: Hoare triple {2622#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {2622#false} is VALID [2022-02-21 04:21:36,974 INFO L290 TraceCheckUtils]: 31: Hoare triple {2622#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {2622#false} is VALID [2022-02-21 04:21:36,975 INFO L290 TraceCheckUtils]: 32: Hoare triple {2622#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {2622#false} is VALID [2022-02-21 04:21:36,975 INFO L290 TraceCheckUtils]: 33: Hoare triple {2622#false} assume !(0 == start_simulation_~tmp~4#1); {2622#false} is VALID [2022-02-21 04:21:36,975 INFO L290 TraceCheckUtils]: 34: Hoare triple {2622#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {2622#false} is VALID [2022-02-21 04:21:36,975 INFO L290 TraceCheckUtils]: 35: Hoare triple {2622#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 36: Hoare triple {2622#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 37: Hoare triple {2622#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 38: Hoare triple {2622#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 39: Hoare triple {2622#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 40: Hoare triple {2622#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {2622#false} is VALID [2022-02-21 04:21:36,976 INFO L290 TraceCheckUtils]: 41: Hoare triple {2622#false} assume !(0 != start_simulation_~tmp___0~3#1); {2622#false} is VALID [2022-02-21 04:21:36,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:36,977 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:36,977 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331161112] [2022-02-21 04:21:36,977 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331161112] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:36,977 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:36,978 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:36,978 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058425277] [2022-02-21 04:21:36,978 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:36,978 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:36,979 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:36,979 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:36,979 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:36,980 INFO L87 Difference]: Start difference. First operand 466 states and 683 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,499 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2022-02-21 04:21:37,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:37,500 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 5.4) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,524 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:37,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,564 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1070 [2022-02-21 04:21:37,595 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1105 states to 1105 states and 1581 transitions. [2022-02-21 04:21:37,595 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1105 [2022-02-21 04:21:37,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1105 [2022-02-21 04:21:37,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:37,597 INFO L681 BuchiCegarLoop]: Abstraction has 1105 states and 1581 transitions. [2022-02-21 04:21:37,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1105 to 1072. [2022-02-21 04:21:37,609 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:37,610 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1105 states and 1581 transitions. Second operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,612 INFO L74 IsIncluded]: Start isIncluded. First operand 1105 states and 1581 transitions. Second operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,613 INFO L87 Difference]: Start difference. First operand 1105 states and 1581 transitions. Second operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,642 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2022-02-21 04:21:37,642 INFO L276 IsEmpty]: Start isEmpty. Operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,644 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,644 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,645 INFO L74 IsIncluded]: Start isIncluded. First operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,647 INFO L87 Difference]: Start difference. First operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:37,676 INFO L93 Difference]: Finished difference Result 1105 states and 1581 transitions. [2022-02-21 04:21:37,677 INFO L276 IsEmpty]: Start isEmpty. Operand 1105 states and 1581 transitions. [2022-02-21 04:21:37,678 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:37,678 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:37,678 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:37,678 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:37,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1072 states, 1072 states have (on average 1.4347014925373134) internal successors, (1538), 1071 states have internal predecessors, (1538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:37,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1072 states to 1072 states and 1538 transitions. [2022-02-21 04:21:37,707 INFO L704 BuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-02-21 04:21:37,707 INFO L587 BuchiCegarLoop]: Abstraction has 1072 states and 1538 transitions. [2022-02-21 04:21:37,707 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:37,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1072 states and 1538 transitions. [2022-02-21 04:21:37,711 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1038 [2022-02-21 04:21:37,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:37,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:37,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,711 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:37,712 INFO L791 eck$LassoCheckResult]: Stem: 3890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 3799#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 3783#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3784#L258 assume !(1 == ~q_req_up~0); 3787#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3830#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 3831#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 3868#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3808#L311 assume !(0 == ~q_read_ev~0); 3809#L311-2 assume !(0 == ~q_write_ev~0); 3843#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3791#L66 assume !(1 == ~p_dw_pc~0); 3792#L66-2 assume !(2 == ~p_dw_pc~0); 3803#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 3823#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3824#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3819#L387 assume !(0 != activate_threads_~tmp~1#1); 3820#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3851#L95 assume !(1 == ~c_dr_pc~0); 3852#L95-2 assume !(2 == ~c_dr_pc~0); 3832#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 3780#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3741#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3742#L395 assume !(0 != activate_threads_~tmp___0~1#1); 3754#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3755#L329 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 3788#L329-2 assume !(1 == ~q_write_ev~0); 3795#L334-1 assume { :end_inline_reset_delta_events } true; 3796#L491-2 [2022-02-21 04:21:37,712 INFO L793 eck$LassoCheckResult]: Loop: 3796#L491-2 assume !false; 3889#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 3797#L435 assume !false; 3825#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3826#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3740#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3892#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3878#L415 assume !(0 != eval_~tmp___1~0#1); 3879#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3828#L258-3 assume !(1 == ~q_req_up~0); 3829#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3873#L311-3 assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; 3876#L311-5 assume !(0 == ~q_write_ev~0); 3839#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 3840#L66-3 assume !(1 == ~p_dw_pc~0); 3812#L66-5 assume !(2 == ~p_dw_pc~0); 3745#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 3746#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 3750#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3887#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 3793#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 3794#L95-3 assume !(1 == ~c_dr_pc~0); 3735#L95-5 assume !(2 == ~c_dr_pc~0); 3736#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 3871#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 3864#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3865#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 3763#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3764#L329-3 assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; 3804#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 3856#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3813#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3814#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3872#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3844#L510 assume !(0 == start_simulation_~tmp~4#1); 3743#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3744#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3782#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3859#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3863#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 3789#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3790#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3842#L523 assume !(0 != start_simulation_~tmp___0~3#1); 3796#L491-2 [2022-02-21 04:21:37,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,713 INFO L85 PathProgramCache]: Analyzing trace with hash 156116973, now seen corresponding path program 1 times [2022-02-21 04:21:37,713 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,713 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675165311] [2022-02-21 04:21:37,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:37,746 INFO L290 TraceCheckUtils]: 0: Hoare triple {7020#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {7020#true} is VALID [2022-02-21 04:21:37,747 INFO L290 TraceCheckUtils]: 1: Hoare triple {7020#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,747 INFO L290 TraceCheckUtils]: 2: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,748 INFO L290 TraceCheckUtils]: 3: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(1 == ~q_req_up~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,748 INFO L290 TraceCheckUtils]: 4: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,748 INFO L290 TraceCheckUtils]: 5: Hoare triple {7022#(= ~q_read_ev~0 2)} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,749 INFO L290 TraceCheckUtils]: 6: Hoare triple {7022#(= ~q_read_ev~0 2)} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,749 INFO L290 TraceCheckUtils]: 7: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,749 INFO L290 TraceCheckUtils]: 8: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(0 == ~q_read_ev~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,750 INFO L290 TraceCheckUtils]: 9: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(0 == ~q_write_ev~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,750 INFO L290 TraceCheckUtils]: 10: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,750 INFO L290 TraceCheckUtils]: 11: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(1 == ~p_dw_pc~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,751 INFO L290 TraceCheckUtils]: 12: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(2 == ~p_dw_pc~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,751 INFO L290 TraceCheckUtils]: 13: Hoare triple {7022#(= ~q_read_ev~0 2)} is_do_write_p_triggered_~__retres1~0#1 := 0; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,751 INFO L290 TraceCheckUtils]: 14: Hoare triple {7022#(= ~q_read_ev~0 2)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,751 INFO L290 TraceCheckUtils]: 15: Hoare triple {7022#(= ~q_read_ev~0 2)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,752 INFO L290 TraceCheckUtils]: 16: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(0 != activate_threads_~tmp~1#1); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,752 INFO L290 TraceCheckUtils]: 17: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,752 INFO L290 TraceCheckUtils]: 18: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(1 == ~c_dr_pc~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,753 INFO L290 TraceCheckUtils]: 19: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(2 == ~c_dr_pc~0); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,753 INFO L290 TraceCheckUtils]: 20: Hoare triple {7022#(= ~q_read_ev~0 2)} is_do_read_c_triggered_~__retres1~1#1 := 0; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,753 INFO L290 TraceCheckUtils]: 21: Hoare triple {7022#(= ~q_read_ev~0 2)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,754 INFO L290 TraceCheckUtils]: 22: Hoare triple {7022#(= ~q_read_ev~0 2)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,754 INFO L290 TraceCheckUtils]: 23: Hoare triple {7022#(= ~q_read_ev~0 2)} assume !(0 != activate_threads_~tmp___0~1#1); {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,754 INFO L290 TraceCheckUtils]: 24: Hoare triple {7022#(= ~q_read_ev~0 2)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7022#(= ~q_read_ev~0 2)} is VALID [2022-02-21 04:21:37,755 INFO L290 TraceCheckUtils]: 25: Hoare triple {7022#(= ~q_read_ev~0 2)} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {7021#false} is VALID [2022-02-21 04:21:37,755 INFO L290 TraceCheckUtils]: 26: Hoare triple {7021#false} assume !(1 == ~q_write_ev~0); {7021#false} is VALID [2022-02-21 04:21:37,755 INFO L290 TraceCheckUtils]: 27: Hoare triple {7021#false} assume { :end_inline_reset_delta_events } true; {7021#false} is VALID [2022-02-21 04:21:37,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:37,755 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:37,755 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675165311] [2022-02-21 04:21:37,756 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675165311] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:37,756 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:37,756 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:37,756 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1161420358] [2022-02-21 04:21:37,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:37,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:37,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:37,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1021819368, now seen corresponding path program 1 times [2022-02-21 04:21:37,756 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:37,757 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848224560] [2022-02-21 04:21:37,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:37,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:37,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:37,785 INFO L290 TraceCheckUtils]: 0: Hoare triple {7023#true} assume !false; {7023#true} is VALID [2022-02-21 04:21:37,785 INFO L290 TraceCheckUtils]: 1: Hoare triple {7023#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {7023#true} is VALID [2022-02-21 04:21:37,785 INFO L290 TraceCheckUtils]: 2: Hoare triple {7023#true} assume !false; {7023#true} is VALID [2022-02-21 04:21:37,785 INFO L290 TraceCheckUtils]: 3: Hoare triple {7023#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7023#true} is VALID [2022-02-21 04:21:37,786 INFO L290 TraceCheckUtils]: 4: Hoare triple {7023#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7025#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:37,786 INFO L290 TraceCheckUtils]: 5: Hoare triple {7025#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7026#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 6: Hoare triple {7026#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {7027#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 7: Hoare triple {7027#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {7024#false} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 8: Hoare triple {7024#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7024#false} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 9: Hoare triple {7024#false} assume !(1 == ~q_req_up~0); {7024#false} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 10: Hoare triple {7024#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7024#false} is VALID [2022-02-21 04:21:37,787 INFO L290 TraceCheckUtils]: 11: Hoare triple {7024#false} assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 12: Hoare triple {7024#false} assume !(0 == ~q_write_ev~0); {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 13: Hoare triple {7024#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 14: Hoare triple {7024#false} assume !(1 == ~p_dw_pc~0); {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 15: Hoare triple {7024#false} assume !(2 == ~p_dw_pc~0); {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 16: Hoare triple {7024#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 17: Hoare triple {7024#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 18: Hoare triple {7024#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 19: Hoare triple {7024#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 20: Hoare triple {7024#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 21: Hoare triple {7024#false} assume !(1 == ~c_dr_pc~0); {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 22: Hoare triple {7024#false} assume !(2 == ~c_dr_pc~0); {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 23: Hoare triple {7024#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {7024#false} is VALID [2022-02-21 04:21:37,788 INFO L290 TraceCheckUtils]: 24: Hoare triple {7024#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 25: Hoare triple {7024#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 26: Hoare triple {7024#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 27: Hoare triple {7024#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 28: Hoare triple {7024#false} assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 29: Hoare triple {7024#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 30: Hoare triple {7024#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7024#false} is VALID [2022-02-21 04:21:37,789 INFO L290 TraceCheckUtils]: 31: Hoare triple {7024#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7024#false} is VALID [2022-02-21 04:21:37,792 INFO L290 TraceCheckUtils]: 32: Hoare triple {7024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7024#false} is VALID [2022-02-21 04:21:37,792 INFO L290 TraceCheckUtils]: 33: Hoare triple {7024#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {7024#false} is VALID [2022-02-21 04:21:37,792 INFO L290 TraceCheckUtils]: 34: Hoare triple {7024#false} assume !(0 == start_simulation_~tmp~4#1); {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 35: Hoare triple {7024#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 36: Hoare triple {7024#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 37: Hoare triple {7024#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 38: Hoare triple {7024#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 39: Hoare triple {7024#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 40: Hoare triple {7024#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 41: Hoare triple {7024#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L290 TraceCheckUtils]: 42: Hoare triple {7024#false} assume !(0 != start_simulation_~tmp___0~3#1); {7024#false} is VALID [2022-02-21 04:21:37,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:37,793 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:37,794 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848224560] [2022-02-21 04:21:37,794 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848224560] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:37,794 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:37,794 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:37,794 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277866963] [2022-02-21 04:21:37,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:37,794 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:37,794 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:37,795 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:37,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:37,795 INFO L87 Difference]: Start difference. First operand 1072 states and 1538 transitions. cyclomatic complexity: 470 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,017 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2022-02-21 04:21:38,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:38,017 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,056 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 28 edges. 28 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:38,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,138 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-02-21 04:21:38,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-02-21 04:21:38,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1742 [2022-02-21 04:21:38,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1742 [2022-02-21 04:21:38,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:38,211 INFO L681 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-02-21 04:21:38,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1742 to 1742. [2022-02-21 04:21:38,232 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:38,234 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1742 states and 2482 transitions. Second operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,236 INFO L74 IsIncluded]: Start isIncluded. First operand 1742 states and 2482 transitions. Second operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,239 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. Second operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,307 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2022-02-21 04:21:38,307 INFO L276 IsEmpty]: Start isEmpty. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,309 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:38,309 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:38,312 INFO L74 IsIncluded]: Start isIncluded. First operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,314 INFO L87 Difference]: Start difference. First operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:38,381 INFO L93 Difference]: Finished difference Result 1742 states and 2482 transitions. [2022-02-21 04:21:38,381 INFO L276 IsEmpty]: Start isEmpty. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,383 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:38,383 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:38,383 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:38,383 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:38,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1742 states, 1742 states have (on average 1.4247990815154994) internal successors, (2482), 1741 states have internal predecessors, (2482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:38,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1742 states to 1742 states and 2482 transitions. [2022-02-21 04:21:38,474 INFO L704 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-02-21 04:21:38,474 INFO L587 BuchiCegarLoop]: Abstraction has 1742 states and 2482 transitions. [2022-02-21 04:21:38,474 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:38,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1742 states and 2482 transitions. [2022-02-21 04:21:38,478 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1708 [2022-02-21 04:21:38,478 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:38,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:38,479 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:38,479 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:38,483 INFO L791 eck$LassoCheckResult]: Stem: 8940#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 8837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 8822#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8823#L258 assume !(1 == ~q_req_up~0); 8824#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8873#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 8874#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 8915#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8852#L311 assume !(0 == ~q_read_ev~0); 8853#L311-2 assume !(0 == ~q_write_ev~0); 8888#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 8830#L66 assume !(1 == ~p_dw_pc~0); 8831#L66-2 assume !(2 == ~p_dw_pc~0); 8843#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 8868#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 8869#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8862#L387 assume !(0 != activate_threads_~tmp~1#1); 8863#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 8899#L95 assume !(1 == ~c_dr_pc~0); 8900#L95-2 assume !(2 == ~c_dr_pc~0); 8875#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 8817#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 8777#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8778#L395 assume !(0 != activate_threads_~tmp___0~1#1); 8793#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8794#L329 assume !(1 == ~q_read_ev~0); 8827#L329-2 assume !(1 == ~q_write_ev~0); 8835#L334-1 assume { :end_inline_reset_delta_events } true; 8836#L491-2 [2022-02-21 04:21:38,484 INFO L793 eck$LassoCheckResult]: Loop: 8836#L491-2 assume !false; 9090#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 8833#L435 assume !false; 9084#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9080#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9076#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9071#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 9067#L415 assume !(0 != eval_~tmp___1~0#1); 9068#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9254#L258-3 assume !(1 == ~q_req_up~0); 9252#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9247#L311-3 assume !(0 == ~q_read_ev~0); 9242#L311-5 assume !(0 == ~q_write_ev~0); 9237#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 9232#L66-3 assume !(1 == ~p_dw_pc~0); 9227#L66-5 assume !(2 == ~p_dw_pc~0); 9223#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 9217#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 9212#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 9211#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 9210#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 9208#L95-3 assume !(1 == ~c_dr_pc~0); 9205#L95-5 assume !(2 == ~c_dr_pc~0); 9204#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 9202#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 9198#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9196#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 9194#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9192#L329-3 assume !(1 == ~q_read_ev~0); 9190#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 9188#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9186#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9147#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9141#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 9134#L510 assume !(0 == start_simulation_~tmp~4#1); 9127#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9121#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9115#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9111#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 9106#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 9103#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9099#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 9096#L523 assume !(0 != start_simulation_~tmp___0~3#1); 8836#L491-2 [2022-02-21 04:21:38,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:38,484 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 1 times [2022-02-21 04:21:38,485 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:38,485 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221299325] [2022-02-21 04:21:38,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:38,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:38,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:38,500 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:38,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:38,535 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:38,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:38,536 INFO L85 PathProgramCache]: Analyzing trace with hash 16715304, now seen corresponding path program 1 times [2022-02-21 04:21:38,536 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:38,536 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159369000] [2022-02-21 04:21:38,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:38,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:38,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:38,583 INFO L290 TraceCheckUtils]: 0: Hoare triple {14001#true} assume !false; {14001#true} is VALID [2022-02-21 04:21:38,584 INFO L290 TraceCheckUtils]: 1: Hoare triple {14001#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {14001#true} is VALID [2022-02-21 04:21:38,584 INFO L290 TraceCheckUtils]: 2: Hoare triple {14001#true} assume !false; {14001#true} is VALID [2022-02-21 04:21:38,584 INFO L290 TraceCheckUtils]: 3: Hoare triple {14001#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {14001#true} is VALID [2022-02-21 04:21:38,584 INFO L290 TraceCheckUtils]: 4: Hoare triple {14001#true} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {14003#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:38,585 INFO L290 TraceCheckUtils]: 5: Hoare triple {14003#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {14004#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:38,585 INFO L290 TraceCheckUtils]: 6: Hoare triple {14004#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {14005#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} is VALID [2022-02-21 04:21:38,585 INFO L290 TraceCheckUtils]: 7: Hoare triple {14005#(<= 1 |ULTIMATE.start_eval_~tmp___1~0#1|)} assume !(0 != eval_~tmp___1~0#1); {14002#false} is VALID [2022-02-21 04:21:38,585 INFO L290 TraceCheckUtils]: 8: Hoare triple {14002#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14002#false} is VALID [2022-02-21 04:21:38,585 INFO L290 TraceCheckUtils]: 9: Hoare triple {14002#false} assume !(1 == ~q_req_up~0); {14002#false} is VALID [2022-02-21 04:21:38,586 INFO L290 TraceCheckUtils]: 10: Hoare triple {14002#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14002#false} is VALID [2022-02-21 04:21:38,586 INFO L290 TraceCheckUtils]: 11: Hoare triple {14002#false} assume !(0 == ~q_read_ev~0); {14002#false} is VALID [2022-02-21 04:21:38,586 INFO L290 TraceCheckUtils]: 12: Hoare triple {14002#false} assume !(0 == ~q_write_ev~0); {14002#false} is VALID [2022-02-21 04:21:38,586 INFO L290 TraceCheckUtils]: 13: Hoare triple {14002#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 14: Hoare triple {14002#false} assume !(1 == ~p_dw_pc~0); {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 15: Hoare triple {14002#false} assume !(2 == ~p_dw_pc~0); {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 16: Hoare triple {14002#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 17: Hoare triple {14002#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 18: Hoare triple {14002#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 19: Hoare triple {14002#false} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 20: Hoare triple {14002#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {14002#false} is VALID [2022-02-21 04:21:38,587 INFO L290 TraceCheckUtils]: 21: Hoare triple {14002#false} assume !(1 == ~c_dr_pc~0); {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 22: Hoare triple {14002#false} assume !(2 == ~c_dr_pc~0); {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 23: Hoare triple {14002#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 24: Hoare triple {14002#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 25: Hoare triple {14002#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 26: Hoare triple {14002#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 27: Hoare triple {14002#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 28: Hoare triple {14002#false} assume !(1 == ~q_read_ev~0); {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 29: Hoare triple {14002#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {14002#false} is VALID [2022-02-21 04:21:38,588 INFO L290 TraceCheckUtils]: 30: Hoare triple {14002#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {14002#false} is VALID [2022-02-21 04:21:38,589 INFO L290 TraceCheckUtils]: 31: Hoare triple {14002#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {14002#false} is VALID [2022-02-21 04:21:38,589 INFO L290 TraceCheckUtils]: 32: Hoare triple {14002#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {14002#false} is VALID [2022-02-21 04:21:38,589 INFO L290 TraceCheckUtils]: 33: Hoare triple {14002#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {14002#false} is VALID [2022-02-21 04:21:38,589 INFO L290 TraceCheckUtils]: 34: Hoare triple {14002#false} assume !(0 == start_simulation_~tmp~4#1); {14002#false} is VALID [2022-02-21 04:21:38,589 INFO L290 TraceCheckUtils]: 35: Hoare triple {14002#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {14002#false} is VALID [2022-02-21 04:21:38,590 INFO L290 TraceCheckUtils]: 36: Hoare triple {14002#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {14002#false} is VALID [2022-02-21 04:21:38,590 INFO L290 TraceCheckUtils]: 37: Hoare triple {14002#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {14002#false} is VALID [2022-02-21 04:21:38,590 INFO L290 TraceCheckUtils]: 38: Hoare triple {14002#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {14002#false} is VALID [2022-02-21 04:21:38,591 INFO L290 TraceCheckUtils]: 39: Hoare triple {14002#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {14002#false} is VALID [2022-02-21 04:21:38,591 INFO L290 TraceCheckUtils]: 40: Hoare triple {14002#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14002#false} is VALID [2022-02-21 04:21:38,591 INFO L290 TraceCheckUtils]: 41: Hoare triple {14002#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {14002#false} is VALID [2022-02-21 04:21:38,591 INFO L290 TraceCheckUtils]: 42: Hoare triple {14002#false} assume !(0 != start_simulation_~tmp___0~3#1); {14002#false} is VALID [2022-02-21 04:21:38,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:38,591 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:38,591 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159369000] [2022-02-21 04:21:38,592 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159369000] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:38,592 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:38,592 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:38,592 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834606817] [2022-02-21 04:21:38,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:38,592 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:38,592 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:38,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:38,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:38,593 INFO L87 Difference]: Start difference. First operand 1742 states and 2482 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:39,096 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2022-02-21 04:21:39,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:21:39,096 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,120 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:39,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,331 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2907 [2022-02-21 04:21:39,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2947 states to 2947 states and 4108 transitions. [2022-02-21 04:21:39,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2947 [2022-02-21 04:21:39,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2947 [2022-02-21 04:21:39,549 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:39,551 INFO L681 BuchiCegarLoop]: Abstraction has 2947 states and 4108 transitions. [2022-02-21 04:21:39,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2947 to 1805. [2022-02-21 04:21:39,581 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:39,583 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2947 states and 4108 transitions. Second operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,585 INFO L74 IsIncluded]: Start isIncluded. First operand 2947 states and 4108 transitions. Second operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,587 INFO L87 Difference]: Start difference. First operand 2947 states and 4108 transitions. Second operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:39,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:39,767 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2022-02-21 04:21:39,767 INFO L276 IsEmpty]: Start isEmpty. Operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,770 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:39,770 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:39,773 INFO L74 IsIncluded]: Start isIncluded. First operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,774 INFO L87 Difference]: Start difference. First operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:39,963 INFO L93 Difference]: Finished difference Result 2947 states and 4108 transitions. [2022-02-21 04:21:39,963 INFO L276 IsEmpty]: Start isEmpty. Operand 2947 states and 4108 transitions. [2022-02-21 04:21:39,966 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:39,966 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:39,966 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:39,966 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:39,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4099722991689752) internal successors, (2545), 1804 states have internal predecessors, (2545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:40,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2545 transitions. [2022-02-21 04:21:40,046 INFO L704 BuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-02-21 04:21:40,046 INFO L587 BuchiCegarLoop]: Abstraction has 1805 states and 2545 transitions. [2022-02-21 04:21:40,046 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:40,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2545 transitions. [2022-02-21 04:21:40,052 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1771 [2022-02-21 04:21:40,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:40,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:40,052 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,052 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:40,053 INFO L791 eck$LassoCheckResult]: Stem: 17130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 17029#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 17015#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17016#L258 assume !(1 == ~q_req_up~0); 17017#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17059#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 17060#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 17099#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17038#L311 assume !(0 == ~q_read_ev~0); 17039#L311-2 assume !(0 == ~q_write_ev~0); 17076#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 17023#L66 assume !(1 == ~p_dw_pc~0); 17024#L66-2 assume !(2 == ~p_dw_pc~0); 17034#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 17054#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 17055#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 17048#L387 assume !(0 != activate_threads_~tmp~1#1); 17049#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 17084#L95 assume !(1 == ~c_dr_pc~0); 17085#L95-2 assume !(2 == ~c_dr_pc~0); 17061#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 17010#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 16968#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 16969#L395 assume !(0 != activate_threads_~tmp___0~1#1); 16984#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16985#L329 assume !(1 == ~q_read_ev~0); 17020#L329-2 assume !(1 == ~q_write_ev~0); 17027#L334-1 assume { :end_inline_reset_delta_events } true; 17028#L491-2 [2022-02-21 04:21:40,053 INFO L793 eck$LassoCheckResult]: Loop: 17028#L491-2 assume !false; 17469#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 17468#L435 assume !false; 17467#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 17466#L291 assume !(0 == ~p_dw_st~0); 17465#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 17463#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 17461#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 17458#L415 assume !(0 != eval_~tmp___1~0#1); 17459#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17512#L258-3 assume !(1 == ~q_req_up~0); 17511#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17510#L311-3 assume !(0 == ~q_read_ev~0); 17509#L311-5 assume !(0 == ~q_write_ev~0); 17508#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 17507#L66-3 assume !(1 == ~p_dw_pc~0); 17506#L66-5 assume !(2 == ~p_dw_pc~0); 17505#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 17504#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 17503#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 17502#L387-3 assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; 17501#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 17500#L95-3 assume !(1 == ~c_dr_pc~0); 17499#L95-5 assume !(2 == ~c_dr_pc~0); 17498#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 17497#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 17496#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17495#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 17494#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17493#L329-3 assume !(1 == ~q_read_ev~0); 17492#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 17491#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 17490#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 17487#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 17485#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 17482#L510 assume !(0 == start_simulation_~tmp~4#1); 17480#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 17479#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 17477#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 17476#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 17475#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 17474#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17473#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 17472#L523 assume !(0 != start_simulation_~tmp___0~3#1); 17028#L491-2 [2022-02-21 04:21:40,053 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,053 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 2 times [2022-02-21 04:21:40,053 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,053 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183697883] [2022-02-21 04:21:40,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,059 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:40,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:40,065 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:40,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:40,065 INFO L85 PathProgramCache]: Analyzing trace with hash 526545300, now seen corresponding path program 1 times [2022-02-21 04:21:40,065 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:40,065 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878182404] [2022-02-21 04:21:40,065 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:40,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:40,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 0: Hoare triple {24665#true} assume !false; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 1: Hoare triple {24665#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 2: Hoare triple {24665#true} assume !false; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 3: Hoare triple {24665#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 4: Hoare triple {24665#true} assume !(0 == ~p_dw_st~0); {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 5: Hoare triple {24665#true} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 6: Hoare triple {24665#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 7: Hoare triple {24665#true} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 8: Hoare triple {24665#true} assume !(0 != eval_~tmp___1~0#1); {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 9: Hoare triple {24665#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 10: Hoare triple {24665#true} assume !(1 == ~q_req_up~0); {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 11: Hoare triple {24665#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24665#true} is VALID [2022-02-21 04:21:40,120 INFO L290 TraceCheckUtils]: 12: Hoare triple {24665#true} assume !(0 == ~q_read_ev~0); {24665#true} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 13: Hoare triple {24665#true} assume !(0 == ~q_write_ev~0); {24665#true} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 14: Hoare triple {24665#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {24665#true} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 15: Hoare triple {24665#true} assume !(1 == ~p_dw_pc~0); {24665#true} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 16: Hoare triple {24665#true} assume !(2 == ~p_dw_pc~0); {24665#true} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 17: Hoare triple {24665#true} is_do_write_p_triggered_~__retres1~0#1 := 0; {24667#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:40,121 INFO L290 TraceCheckUtils]: 18: Hoare triple {24667#(and (<= |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_do_write_p_triggered_~__retres1~0#1|))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {24668#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:40,122 INFO L290 TraceCheckUtils]: 19: Hoare triple {24668#(and (<= 0 |ULTIMATE.start_is_do_write_p_triggered_#res#1|) (<= |ULTIMATE.start_is_do_write_p_triggered_#res#1| 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {24669#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 20: Hoare triple {24669#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0; {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 21: Hoare triple {24666#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 22: Hoare triple {24666#false} assume !(1 == ~c_dr_pc~0); {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 23: Hoare triple {24666#false} assume !(2 == ~c_dr_pc~0); {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 24: Hoare triple {24666#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 25: Hoare triple {24666#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {24666#false} is VALID [2022-02-21 04:21:40,123 INFO L290 TraceCheckUtils]: 26: Hoare triple {24666#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 27: Hoare triple {24666#false} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 28: Hoare triple {24666#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 29: Hoare triple {24666#false} assume !(1 == ~q_read_ev~0); {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 30: Hoare triple {24666#false} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 31: Hoare triple {24666#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 32: Hoare triple {24666#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 33: Hoare triple {24666#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {24666#false} is VALID [2022-02-21 04:21:40,124 INFO L290 TraceCheckUtils]: 34: Hoare triple {24666#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 35: Hoare triple {24666#false} assume !(0 == start_simulation_~tmp~4#1); {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 36: Hoare triple {24666#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 37: Hoare triple {24666#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 38: Hoare triple {24666#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 39: Hoare triple {24666#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 40: Hoare triple {24666#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 41: Hoare triple {24666#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 42: Hoare triple {24666#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {24666#false} is VALID [2022-02-21 04:21:40,128 INFO L290 TraceCheckUtils]: 43: Hoare triple {24666#false} assume !(0 != start_simulation_~tmp___0~3#1); {24666#false} is VALID [2022-02-21 04:21:40,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:40,129 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:40,129 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1878182404] [2022-02-21 04:21:40,129 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1878182404] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:40,129 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:40,129 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:40,129 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169393612] [2022-02-21 04:21:40,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:40,130 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:40,130 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:40,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:40,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:40,130 INFO L87 Difference]: Start difference. First operand 1805 states and 2545 transitions. cyclomatic complexity: 744 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:41,018 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2022-02-21 04:21:41,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:41,018 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,041 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:41,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4219 states and 5928 transitions. [2022-02-21 04:21:41,468 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4181 [2022-02-21 04:21:41,892 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4219 states to 4219 states and 5928 transitions. [2022-02-21 04:21:41,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4219 [2022-02-21 04:21:41,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4219 [2022-02-21 04:21:41,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4219 states and 5928 transitions. [2022-02-21 04:21:41,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:41,898 INFO L681 BuchiCegarLoop]: Abstraction has 4219 states and 5928 transitions. [2022-02-21 04:21:41,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4219 states and 5928 transitions. [2022-02-21 04:21:41,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4219 to 1883. [2022-02-21 04:21:41,934 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:41,936 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4219 states and 5928 transitions. Second operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,938 INFO L74 IsIncluded]: Start isIncluded. First operand 4219 states and 5928 transitions. Second operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:41,939 INFO L87 Difference]: Start difference. First operand 4219 states and 5928 transitions. Second operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:42,342 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2022-02-21 04:21:42,343 INFO L276 IsEmpty]: Start isEmpty. Operand 4219 states and 5928 transitions. [2022-02-21 04:21:42,348 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:42,348 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:42,350 INFO L74 IsIncluded]: Start isIncluded. First operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4219 states and 5928 transitions. [2022-02-21 04:21:42,351 INFO L87 Difference]: Start difference. First operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4219 states and 5928 transitions. [2022-02-21 04:21:42,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:42,757 INFO L93 Difference]: Finished difference Result 4219 states and 5928 transitions. [2022-02-21 04:21:42,757 INFO L276 IsEmpty]: Start isEmpty. Operand 4219 states and 5928 transitions. [2022-02-21 04:21:42,761 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:42,761 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:42,761 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:42,761 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:42,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1883 states, 1883 states have (on average 1.3839617631439194) internal successors, (2606), 1882 states have internal predecessors, (2606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1883 states to 1883 states and 2606 transitions. [2022-02-21 04:21:42,849 INFO L704 BuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-02-21 04:21:42,849 INFO L587 BuchiCegarLoop]: Abstraction has 1883 states and 2606 transitions. [2022-02-21 04:21:42,849 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:42,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1883 states and 2606 transitions. [2022-02-21 04:21:42,854 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1849 [2022-02-21 04:21:42,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:42,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:42,854 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,854 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,855 INFO L791 eck$LassoCheckResult]: Stem: 29054#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 28959#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 28943#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28944#L258 assume !(1 == ~q_req_up~0); 28947#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28994#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 28995#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 29032#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28972#L311 assume !(0 == ~q_read_ev~0); 28973#L311-2 assume !(0 == ~q_write_ev~0); 29010#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 28951#L66 assume !(1 == ~p_dw_pc~0); 28952#L66-2 assume !(2 == ~p_dw_pc~0); 28963#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 28988#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 28989#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 28984#L387 assume !(0 != activate_threads_~tmp~1#1); 28985#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 29018#L95 assume !(1 == ~c_dr_pc~0); 29019#L95-2 assume !(2 == ~c_dr_pc~0); 28996#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 28940#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 28902#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28903#L395 assume !(0 != activate_threads_~tmp___0~1#1); 28916#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28917#L329 assume !(1 == ~q_read_ev~0); 28948#L329-2 assume !(1 == ~q_write_ev~0); 28955#L334-1 assume { :end_inline_reset_delta_events } true; 28956#L491-2 [2022-02-21 04:21:42,855 INFO L793 eck$LassoCheckResult]: Loop: 28956#L491-2 assume !false; 29250#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 29144#L435 assume !false; 29248#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 29237#L291 assume !(0 == ~p_dw_st~0); 29238#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 29239#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29233#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 29234#L415 assume !(0 != eval_~tmp___1~0#1); 29294#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29293#L258-3 assume !(1 == ~q_req_up~0); 29292#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29291#L311-3 assume !(0 == ~q_read_ev~0); 29290#L311-5 assume !(0 == ~q_write_ev~0); 29289#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 29288#L66-3 assume !(1 == ~p_dw_pc~0); 28976#L66-5 assume !(2 == ~p_dw_pc~0); 28977#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 29263#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 29262#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 29259#L387-3 assume !(0 != activate_threads_~tmp~1#1); 29257#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 29255#L95-3 assume !(1 == ~c_dr_pc~0); 29240#L95-5 assume !(2 == ~c_dr_pc~0); 29099#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 29092#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 29091#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 29090#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 29089#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29088#L329-3 assume !(1 == ~q_read_ev~0); 29087#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 29085#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 29086#L291-1 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 29081#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29080#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 29077#L510 assume !(0 == start_simulation_~tmp~4#1); 29078#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 29261#L291-2 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 29258#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 29256#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 29254#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 29253#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29252#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 29251#L523 assume !(0 != start_simulation_~tmp___0~3#1); 28956#L491-2 [2022-02-21 04:21:42,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,855 INFO L85 PathProgramCache]: Analyzing trace with hash 156118895, now seen corresponding path program 3 times [2022-02-21 04:21:42,855 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,858 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756142781] [2022-02-21 04:21:42,858 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:42,866 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:42,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:42,881 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:42,881 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,881 INFO L85 PathProgramCache]: Analyzing trace with hash 392531794, now seen corresponding path program 1 times [2022-02-21 04:21:42,882 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,882 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145112702] [2022-02-21 04:21:42,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:42,918 INFO L290 TraceCheckUtils]: 0: Hoare triple {39220#true} assume !false; {39220#true} is VALID [2022-02-21 04:21:42,918 INFO L290 TraceCheckUtils]: 1: Hoare triple {39220#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {39220#true} is VALID [2022-02-21 04:21:42,919 INFO L290 TraceCheckUtils]: 2: Hoare triple {39220#true} assume !false; {39220#true} is VALID [2022-02-21 04:21:42,919 INFO L290 TraceCheckUtils]: 3: Hoare triple {39220#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {39220#true} is VALID [2022-02-21 04:21:42,919 INFO L290 TraceCheckUtils]: 4: Hoare triple {39220#true} assume !(0 == ~p_dw_st~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,919 INFO L290 TraceCheckUtils]: 5: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,920 INFO L290 TraceCheckUtils]: 6: Hoare triple {39222#(not (= ~p_dw_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,920 INFO L290 TraceCheckUtils]: 7: Hoare triple {39222#(not (= ~p_dw_st~0 0))} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,920 INFO L290 TraceCheckUtils]: 8: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(0 != eval_~tmp___1~0#1); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,920 INFO L290 TraceCheckUtils]: 9: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,921 INFO L290 TraceCheckUtils]: 10: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(1 == ~q_req_up~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,921 INFO L290 TraceCheckUtils]: 11: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,921 INFO L290 TraceCheckUtils]: 12: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(0 == ~q_read_ev~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,921 INFO L290 TraceCheckUtils]: 13: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(0 == ~q_write_ev~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,922 INFO L290 TraceCheckUtils]: 14: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,922 INFO L290 TraceCheckUtils]: 15: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(1 == ~p_dw_pc~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,922 INFO L290 TraceCheckUtils]: 16: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(2 == ~p_dw_pc~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,923 INFO L290 TraceCheckUtils]: 17: Hoare triple {39222#(not (= ~p_dw_st~0 0))} is_do_write_p_triggered_~__retres1~0#1 := 0; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,923 INFO L290 TraceCheckUtils]: 18: Hoare triple {39222#(not (= ~p_dw_st~0 0))} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,923 INFO L290 TraceCheckUtils]: 19: Hoare triple {39222#(not (= ~p_dw_st~0 0))} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,923 INFO L290 TraceCheckUtils]: 20: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,924 INFO L290 TraceCheckUtils]: 21: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,924 INFO L290 TraceCheckUtils]: 22: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(1 == ~c_dr_pc~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,924 INFO L290 TraceCheckUtils]: 23: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(2 == ~c_dr_pc~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,925 INFO L290 TraceCheckUtils]: 24: Hoare triple {39222#(not (= ~p_dw_st~0 0))} is_do_read_c_triggered_~__retres1~1#1 := 0; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,925 INFO L290 TraceCheckUtils]: 25: Hoare triple {39222#(not (= ~p_dw_st~0 0))} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,925 INFO L290 TraceCheckUtils]: 26: Hoare triple {39222#(not (= ~p_dw_st~0 0))} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,925 INFO L290 TraceCheckUtils]: 27: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,926 INFO L290 TraceCheckUtils]: 28: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,926 INFO L290 TraceCheckUtils]: 29: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume !(1 == ~q_read_ev~0); {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,926 INFO L290 TraceCheckUtils]: 30: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 31: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {39222#(not (= ~p_dw_st~0 0))} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 32: Hoare triple {39222#(not (= ~p_dw_st~0 0))} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {39221#false} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 33: Hoare triple {39221#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {39221#false} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 34: Hoare triple {39221#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {39221#false} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 35: Hoare triple {39221#false} assume !(0 == start_simulation_~tmp~4#1); {39221#false} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 36: Hoare triple {39221#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {39221#false} is VALID [2022-02-21 04:21:42,927 INFO L290 TraceCheckUtils]: 37: Hoare triple {39221#false} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 38: Hoare triple {39221#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 39: Hoare triple {39221#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 40: Hoare triple {39221#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 41: Hoare triple {39221#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 42: Hoare triple {39221#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L290 TraceCheckUtils]: 43: Hoare triple {39221#false} assume !(0 != start_simulation_~tmp___0~3#1); {39221#false} is VALID [2022-02-21 04:21:42,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:42,928 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:42,929 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145112702] [2022-02-21 04:21:42,929 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145112702] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:42,929 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:42,929 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:42,929 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022010066] [2022-02-21 04:21:42,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:42,929 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:42,930 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:42,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:42,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:42,932 INFO L87 Difference]: Start difference. First operand 1883 states and 2606 transitions. cyclomatic complexity: 727 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,239 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2022-02-21 04:21:43,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:43,239 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,263 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:43,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:43,483 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-02-21 04:21:43,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-02-21 04:21:43,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2972 [2022-02-21 04:21:43,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2972 [2022-02-21 04:21:43,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:43,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:43,689 INFO L681 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-02-21 04:21:43,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:43,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2972. [2022-02-21 04:21:43,712 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:43,715 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2972 states and 4013 transitions. Second operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,717 INFO L74 IsIncluded]: Start isIncluded. First operand 2972 states and 4013 transitions. Second operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,719 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. Second operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,910 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2022-02-21 04:21:43,910 INFO L276 IsEmpty]: Start isEmpty. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:43,913 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,913 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,916 INFO L74 IsIncluded]: Start isIncluded. First operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2972 states and 4013 transitions. [2022-02-21 04:21:43,918 INFO L87 Difference]: Start difference. First operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2972 states and 4013 transitions. [2022-02-21 04:21:44,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,116 INFO L93 Difference]: Finished difference Result 2972 states and 4013 transitions. [2022-02-21 04:21:44,116 INFO L276 IsEmpty]: Start isEmpty. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:44,118 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,118 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,118 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:44,118 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:44,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2972 states, 2972 states have (on average 1.3502691790040378) internal successors, (4013), 2971 states have internal predecessors, (4013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2972 states to 2972 states and 4013 transitions. [2022-02-21 04:21:44,322 INFO L704 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-02-21 04:21:44,322 INFO L587 BuchiCegarLoop]: Abstraction has 2972 states and 4013 transitions. [2022-02-21 04:21:44,322 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:44,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2972 states and 4013 transitions. [2022-02-21 04:21:44,328 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-02-21 04:21:44,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,329 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,329 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,329 INFO L791 eck$LassoCheckResult]: Stem: 42371#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 42261#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 42246#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42247#L258 assume !(1 == ~q_req_up~0); 42248#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42296#L273 assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; 42297#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 42338#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42339#L311 assume !(0 == ~q_read_ev~0); 42345#L311-2 assume !(0 == ~q_write_ev~0); 42346#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 42255#L66 assume !(1 == ~p_dw_pc~0); 42256#L66-2 assume !(2 == ~p_dw_pc~0); 42367#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 42368#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 42333#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42334#L387 assume !(0 != activate_threads_~tmp~1#1); 42347#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 42348#L95 assume !(1 == ~c_dr_pc~0); 42349#L95-2 assume !(2 == ~c_dr_pc~0); 42350#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 42240#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 42241#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 42314#L395 assume !(0 != activate_threads_~tmp___0~1#1); 42315#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42251#L329 assume !(1 == ~q_read_ev~0); 42252#L329-2 assume !(1 == ~q_write_ev~0); 42259#L334-1 assume { :end_inline_reset_delta_events } true; 42260#L491-2 [2022-02-21 04:21:44,329 INFO L793 eck$LassoCheckResult]: Loop: 42260#L491-2 assume !false; 42476#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 42450#L435 assume !false; 42471#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 42469#L291 assume !(0 == ~p_dw_st~0); 42467#L295 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 42465#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 42462#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 42458#L415 assume !(0 != eval_~tmp___1~0#1); 42459#L451 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42532#L258-3 assume !(1 == ~q_req_up~0); 42531#L258-5 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42530#L311-3 assume !(0 == ~q_read_ev~0); 42529#L311-5 assume !(0 == ~q_write_ev~0); 42528#L316-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 42527#L66-3 assume !(1 == ~p_dw_pc~0); 42526#L66-5 assume !(2 == ~p_dw_pc~0); 42525#L76-3 is_do_write_p_triggered_~__retres1~0#1 := 0; 42524#L87-1 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 42523#L88-1 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 42521#L387-3 assume !(0 != activate_threads_~tmp~1#1); 42519#L387-5 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 42517#L95-3 assume !(1 == ~c_dr_pc~0); 42515#L95-5 assume !(2 == ~c_dr_pc~0); 42513#L105-3 is_do_read_c_triggered_~__retres1~1#1 := 0; 42511#L116-1 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 42509#L117-1 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 42507#L395-3 assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; 42505#L395-5 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42503#L329-3 assume !(1 == ~q_read_ev~0); 42501#L329-5 assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; 42499#L334-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 42497#L291-1 assume !(0 == ~p_dw_st~0); 42495#L295-1 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 42493#L303-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 42491#L304-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 42488#L510 assume !(0 == start_simulation_~tmp~4#1); 42486#L510-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 42485#L291-2 assume !(0 == ~p_dw_st~0); 42484#L295-2 assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 42483#L303-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 42482#L304-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 42481#L465 assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; 42480#L472 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42479#L473 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 42478#L523 assume !(0 != start_simulation_~tmp___0~3#1); 42260#L491-2 [2022-02-21 04:21:44,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,330 INFO L85 PathProgramCache]: Analyzing trace with hash -1649319439, now seen corresponding path program 1 times [2022-02-21 04:21:44,330 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,330 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417019969] [2022-02-21 04:21:44,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,342 INFO L290 TraceCheckUtils]: 0: Hoare triple {51114#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {51114#true} is VALID [2022-02-21 04:21:44,342 INFO L290 TraceCheckUtils]: 1: Hoare triple {51114#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {51116#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 2: Hoare triple {51116#(= ~p_dw_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {51116#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 3: Hoare triple {51116#(= ~p_dw_i~0 1)} assume !(1 == ~q_req_up~0); {51116#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 4: Hoare triple {51116#(= ~p_dw_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {51116#(= ~p_dw_i~0 1)} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 5: Hoare triple {51116#(= ~p_dw_i~0 1)} assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2; {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 6: Hoare triple {51115#false} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 7: Hoare triple {51115#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 8: Hoare triple {51115#false} assume !(0 == ~q_read_ev~0); {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 9: Hoare triple {51115#false} assume !(0 == ~q_write_ev~0); {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 10: Hoare triple {51115#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 11: Hoare triple {51115#false} assume !(1 == ~p_dw_pc~0); {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 12: Hoare triple {51115#false} assume !(2 == ~p_dw_pc~0); {51115#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 13: Hoare triple {51115#false} is_do_write_p_triggered_~__retres1~0#1 := 0; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 14: Hoare triple {51115#false} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 15: Hoare triple {51115#false} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 16: Hoare triple {51115#false} assume !(0 != activate_threads_~tmp~1#1); {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 17: Hoare triple {51115#false} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 18: Hoare triple {51115#false} assume !(1 == ~c_dr_pc~0); {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 19: Hoare triple {51115#false} assume !(2 == ~c_dr_pc~0); {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 20: Hoare triple {51115#false} is_do_read_c_triggered_~__retres1~1#1 := 0; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 21: Hoare triple {51115#false} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {51115#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 22: Hoare triple {51115#false} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 23: Hoare triple {51115#false} assume !(0 != activate_threads_~tmp___0~1#1); {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 24: Hoare triple {51115#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 25: Hoare triple {51115#false} assume !(1 == ~q_read_ev~0); {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 26: Hoare triple {51115#false} assume !(1 == ~q_write_ev~0); {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 27: Hoare triple {51115#false} assume { :end_inline_reset_delta_events } true; {51115#false} is VALID [2022-02-21 04:21:44,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,346 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,346 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417019969] [2022-02-21 04:21:44,347 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417019969] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,347 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,347 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:44,347 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581974158] [2022-02-21 04:21:44,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,347 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:44,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,348 INFO L85 PathProgramCache]: Analyzing trace with hash 2092921140, now seen corresponding path program 1 times [2022-02-21 04:21:44,348 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,348 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [625678835] [2022-02-21 04:21:44,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,359 INFO L290 TraceCheckUtils]: 0: Hoare triple {51117#true} assume !false; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 1: Hoare triple {51117#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 2: Hoare triple {51117#true} assume !false; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 3: Hoare triple {51117#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 4: Hoare triple {51117#true} assume !(0 == ~p_dw_st~0); {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 5: Hoare triple {51117#true} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 6: Hoare triple {51117#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 7: Hoare triple {51117#true} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {51117#true} is VALID [2022-02-21 04:21:44,360 INFO L290 TraceCheckUtils]: 8: Hoare triple {51117#true} assume !(0 != eval_~tmp___1~0#1); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 9: Hoare triple {51117#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 10: Hoare triple {51117#true} assume !(1 == ~q_req_up~0); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 11: Hoare triple {51117#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 12: Hoare triple {51117#true} assume !(0 == ~q_read_ev~0); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 13: Hoare triple {51117#true} assume !(0 == ~q_write_ev~0); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 14: Hoare triple {51117#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 15: Hoare triple {51117#true} assume !(1 == ~p_dw_pc~0); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 16: Hoare triple {51117#true} assume !(2 == ~p_dw_pc~0); {51117#true} is VALID [2022-02-21 04:21:44,361 INFO L290 TraceCheckUtils]: 17: Hoare triple {51117#true} is_do_write_p_triggered_~__retres1~0#1 := 0; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 18: Hoare triple {51117#true} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 19: Hoare triple {51117#true} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 20: Hoare triple {51117#true} assume !(0 != activate_threads_~tmp~1#1); {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 21: Hoare triple {51117#true} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 22: Hoare triple {51117#true} assume !(1 == ~c_dr_pc~0); {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 23: Hoare triple {51117#true} assume !(2 == ~c_dr_pc~0); {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 24: Hoare triple {51117#true} is_do_read_c_triggered_~__retres1~1#1 := 0; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 25: Hoare triple {51117#true} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {51117#true} is VALID [2022-02-21 04:21:44,362 INFO L290 TraceCheckUtils]: 26: Hoare triple {51117#true} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {51117#true} is VALID [2022-02-21 04:21:44,363 INFO L290 TraceCheckUtils]: 27: Hoare triple {51117#true} assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0; {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,363 INFO L290 TraceCheckUtils]: 28: Hoare triple {51119#(= ~c_dr_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,363 INFO L290 TraceCheckUtils]: 29: Hoare triple {51119#(= ~c_dr_st~0 0)} assume !(1 == ~q_read_ev~0); {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,364 INFO L290 TraceCheckUtils]: 30: Hoare triple {51119#(= ~c_dr_st~0 0)} assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2; {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,364 INFO L290 TraceCheckUtils]: 31: Hoare triple {51119#(= ~c_dr_st~0 0)} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,364 INFO L290 TraceCheckUtils]: 32: Hoare triple {51119#(= ~c_dr_st~0 0)} assume !(0 == ~p_dw_st~0); {51119#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:44,364 INFO L290 TraceCheckUtils]: 33: Hoare triple {51119#(= ~c_dr_st~0 0)} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {51118#false} is VALID [2022-02-21 04:21:44,364 INFO L290 TraceCheckUtils]: 34: Hoare triple {51118#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 35: Hoare triple {51118#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 36: Hoare triple {51118#false} assume !(0 == start_simulation_~tmp~4#1); {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 37: Hoare triple {51118#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 38: Hoare triple {51118#false} assume !(0 == ~p_dw_st~0); {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 39: Hoare triple {51118#false} assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 40: Hoare triple {51118#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 41: Hoare triple {51118#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 42: Hoare triple {51118#false} assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0; {51118#false} is VALID [2022-02-21 04:21:44,365 INFO L290 TraceCheckUtils]: 43: Hoare triple {51118#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {51118#false} is VALID [2022-02-21 04:21:44,366 INFO L290 TraceCheckUtils]: 44: Hoare triple {51118#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {51118#false} is VALID [2022-02-21 04:21:44,366 INFO L290 TraceCheckUtils]: 45: Hoare triple {51118#false} assume !(0 != start_simulation_~tmp___0~3#1); {51118#false} is VALID [2022-02-21 04:21:44,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,366 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,366 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [625678835] [2022-02-21 04:21:44,366 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [625678835] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,366 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,366 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:44,367 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [87103533] [2022-02-21 04:21:44,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,367 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:44,367 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:44,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:44,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:44,368 INFO L87 Difference]: Start difference. First operand 2972 states and 4013 transitions. cyclomatic complexity: 1048 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,642 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2022-02-21 04:21:44,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:44,642 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,658 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 28 edges. 28 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:44,659 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:44,837 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-02-21 04:21:45,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-02-21 04:21:45,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2950 [2022-02-21 04:21:45,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2950 [2022-02-21 04:21:45,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:45,019 INFO L681 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-02-21 04:21:45,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2950 to 2950. [2022-02-21 04:21:45,043 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:45,046 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2950 states and 3987 transitions. Second operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,048 INFO L74 IsIncluded]: Start isIncluded. First operand 2950 states and 3987 transitions. Second operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,050 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. Second operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,223 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2022-02-21 04:21:45,223 INFO L276 IsEmpty]: Start isEmpty. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,225 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,225 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,229 INFO L74 IsIncluded]: Start isIncluded. First operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,231 INFO L87 Difference]: Start difference. First operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,407 INFO L93 Difference]: Finished difference Result 2950 states and 3987 transitions. [2022-02-21 04:21:45,407 INFO L276 IsEmpty]: Start isEmpty. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,409 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,409 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,409 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:45,409 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:45,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2950 states, 2950 states have (on average 1.3515254237288135) internal successors, (3987), 2949 states have internal predecessors, (3987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2950 states to 2950 states and 3987 transitions. [2022-02-21 04:21:45,591 INFO L704 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-02-21 04:21:45,591 INFO L587 BuchiCegarLoop]: Abstraction has 2950 states and 3987 transitions. [2022-02-21 04:21:45,591 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:45,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2950 states and 3987 transitions. [2022-02-21 04:21:45,601 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2910 [2022-02-21 04:21:45,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,615 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,615 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,615 INFO L791 eck$LassoCheckResult]: Stem: 54231#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 54134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 54120#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54121#L258 assume !(1 == ~q_req_up~0); 54122#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54164#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 54165#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 54204#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54144#L311 assume !(0 == ~q_read_ev~0); 54145#L311-2 assume !(0 == ~q_write_ev~0); 54184#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 54128#L66 assume !(1 == ~p_dw_pc~0); 54129#L66-2 assume !(2 == ~p_dw_pc~0); 54138#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 54159#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 54160#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 54153#L387 assume !(0 != activate_threads_~tmp~1#1); 54154#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 54192#L95 assume !(1 == ~c_dr_pc~0); 54193#L95-2 assume !(2 == ~c_dr_pc~0); 54166#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 54115#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 54077#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 54078#L395 assume !(0 != activate_threads_~tmp___0~1#1); 54092#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54093#L329 assume !(1 == ~q_read_ev~0); 54125#L329-2 assume !(1 == ~q_write_ev~0); 54132#L334-1 assume { :end_inline_reset_delta_events } true; 54133#L491-2 assume !false; 54325#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 54324#L435 [2022-02-21 04:21:45,618 INFO L793 eck$LassoCheckResult]: Loop: 54324#L435 assume !false; 54322#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 54320#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 54318#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 54315#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 54312#L415 assume 0 != eval_~tmp___1~0#1; 54308#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 54304#L424 assume !(0 != eval_~tmp~2#1); 54305#L420 assume !(0 == ~c_dr_st~0); 54324#L435 [2022-02-21 04:21:45,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,618 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 1 times [2022-02-21 04:21:45,618 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,618 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342642506] [2022-02-21 04:21:45,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,623 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:45,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,629 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:45,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,629 INFO L85 PathProgramCache]: Analyzing trace with hash 1094877037, now seen corresponding path program 1 times [2022-02-21 04:21:45,629 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,629 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351930277] [2022-02-21 04:21:45,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,631 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:45,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,633 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:45,633 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,633 INFO L85 PathProgramCache]: Analyzing trace with hash -1470124195, now seen corresponding path program 1 times [2022-02-21 04:21:45,634 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,634 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404457870] [2022-02-21 04:21:45,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 0: Hoare triple {62927#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; {62927#true} is VALID [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 1: Hoare triple {62927#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; {62927#true} is VALID [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 2: Hoare triple {62927#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {62927#true} is VALID [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 3: Hoare triple {62927#true} assume !(1 == ~q_req_up~0); {62927#true} is VALID [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 4: Hoare triple {62927#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {62927#true} is VALID [2022-02-21 04:21:45,652 INFO L290 TraceCheckUtils]: 5: Hoare triple {62927#true} assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; {62927#true} is VALID [2022-02-21 04:21:45,653 INFO L290 TraceCheckUtils]: 6: Hoare triple {62927#true} assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,653 INFO L290 TraceCheckUtils]: 7: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,653 INFO L290 TraceCheckUtils]: 8: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 == ~q_read_ev~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,653 INFO L290 TraceCheckUtils]: 9: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 == ~q_write_ev~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,654 INFO L290 TraceCheckUtils]: 10: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,654 INFO L290 TraceCheckUtils]: 11: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(1 == ~p_dw_pc~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,654 INFO L290 TraceCheckUtils]: 12: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(2 == ~p_dw_pc~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,654 INFO L290 TraceCheckUtils]: 13: Hoare triple {62929#(= ~c_dr_st~0 0)} is_do_write_p_triggered_~__retres1~0#1 := 0; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,654 INFO L290 TraceCheckUtils]: 14: Hoare triple {62929#(= ~c_dr_st~0 0)} is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,655 INFO L290 TraceCheckUtils]: 15: Hoare triple {62929#(= ~c_dr_st~0 0)} activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,655 INFO L290 TraceCheckUtils]: 16: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,655 INFO L290 TraceCheckUtils]: 17: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,655 INFO L290 TraceCheckUtils]: 18: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(1 == ~c_dr_pc~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,656 INFO L290 TraceCheckUtils]: 19: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(2 == ~c_dr_pc~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,656 INFO L290 TraceCheckUtils]: 20: Hoare triple {62929#(= ~c_dr_st~0 0)} is_do_read_c_triggered_~__retres1~1#1 := 0; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,656 INFO L290 TraceCheckUtils]: 21: Hoare triple {62929#(= ~c_dr_st~0 0)} is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,656 INFO L290 TraceCheckUtils]: 22: Hoare triple {62929#(= ~c_dr_st~0 0)} activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,657 INFO L290 TraceCheckUtils]: 23: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 != activate_threads_~tmp___0~1#1); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,657 INFO L290 TraceCheckUtils]: 24: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,657 INFO L290 TraceCheckUtils]: 25: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(1 == ~q_read_ev~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,657 INFO L290 TraceCheckUtils]: 26: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(1 == ~q_write_ev~0); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,658 INFO L290 TraceCheckUtils]: 27: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :end_inline_reset_delta_events } true; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,658 INFO L290 TraceCheckUtils]: 28: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !false; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,663 INFO L290 TraceCheckUtils]: 29: Hoare triple {62929#(= ~c_dr_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,663 INFO L290 TraceCheckUtils]: 30: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !false; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,664 INFO L290 TraceCheckUtils]: 31: Hoare triple {62929#(= ~c_dr_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,665 INFO L290 TraceCheckUtils]: 32: Hoare triple {62929#(= ~c_dr_st~0 0)} assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,666 INFO L290 TraceCheckUtils]: 33: Hoare triple {62929#(= ~c_dr_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,666 INFO L290 TraceCheckUtils]: 34: Hoare triple {62929#(= ~c_dr_st~0 0)} eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,666 INFO L290 TraceCheckUtils]: 35: Hoare triple {62929#(= ~c_dr_st~0 0)} assume 0 != eval_~tmp___1~0#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,667 INFO L290 TraceCheckUtils]: 36: Hoare triple {62929#(= ~c_dr_st~0 0)} assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,668 INFO L290 TraceCheckUtils]: 37: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 != eval_~tmp~2#1); {62929#(= ~c_dr_st~0 0)} is VALID [2022-02-21 04:21:45,669 INFO L290 TraceCheckUtils]: 38: Hoare triple {62929#(= ~c_dr_st~0 0)} assume !(0 == ~c_dr_st~0); {62928#false} is VALID [2022-02-21 04:21:45,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,670 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,670 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1404457870] [2022-02-21 04:21:45,670 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1404457870] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,670 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,670 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:45,670 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114601545] [2022-02-21 04:21:45,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,735 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:45,736 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:45,736 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:45,736 INFO L87 Difference]: Start difference. First operand 2950 states and 3987 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,349 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2022-02-21 04:21:46,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:46,349 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,376 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4412 states and 5918 transitions. [2022-02-21 04:21:46,830 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 4373 [2022-02-21 04:21:47,302 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4412 states to 4412 states and 5918 transitions. [2022-02-21 04:21:47,302 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4412 [2022-02-21 04:21:47,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4412 [2022-02-21 04:21:47,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4412 states and 5918 transitions. [2022-02-21 04:21:47,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:47,307 INFO L681 BuchiCegarLoop]: Abstraction has 4412 states and 5918 transitions. [2022-02-21 04:21:47,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4412 states and 5918 transitions. [2022-02-21 04:21:47,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4412 to 3868. [2022-02-21 04:21:47,374 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:47,376 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4412 states and 5918 transitions. Second operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,378 INFO L74 IsIncluded]: Start isIncluded. First operand 4412 states and 5918 transitions. Second operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,380 INFO L87 Difference]: Start difference. First operand 4412 states and 5918 transitions. Second operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,809 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2022-02-21 04:21:47,809 INFO L276 IsEmpty]: Start isEmpty. Operand 4412 states and 5918 transitions. [2022-02-21 04:21:47,813 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,813 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,817 INFO L74 IsIncluded]: Start isIncluded. First operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4412 states and 5918 transitions. [2022-02-21 04:21:47,819 INFO L87 Difference]: Start difference. First operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4412 states and 5918 transitions. [2022-02-21 04:21:48,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,218 INFO L93 Difference]: Finished difference Result 4412 states and 5918 transitions. [2022-02-21 04:21:48,218 INFO L276 IsEmpty]: Start isEmpty. Operand 4412 states and 5918 transitions. [2022-02-21 04:21:48,222 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,222 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,222 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,222 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3868 states, 3868 states have (on average 1.3495346432264737) internal successors, (5220), 3867 states have internal predecessors, (5220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3868 states to 3868 states and 5220 transitions. [2022-02-21 04:21:48,541 INFO L704 BuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-02-21 04:21:48,541 INFO L587 BuchiCegarLoop]: Abstraction has 3868 states and 5220 transitions. [2022-02-21 04:21:48,541 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:48,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3868 states and 5220 transitions. [2022-02-21 04:21:48,549 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 3829 [2022-02-21 04:21:48,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,550 INFO L791 eck$LassoCheckResult]: Stem: 67502#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0; 67406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1; 67393#L551 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67394#L258 assume !(1 == ~q_req_up~0); 67395#L258-2 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67440#L273 assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0; 67441#L273-2 assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0; 67477#L278-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67417#L311 assume !(0 == ~q_read_ev~0); 67418#L311-2 assume !(0 == ~q_write_ev~0); 67456#L316-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1; 67401#L66 assume !(1 == ~p_dw_pc~0); 67402#L66-2 assume !(2 == ~p_dw_pc~0); 67412#L76-1 is_do_write_p_triggered_~__retres1~0#1 := 0; 67434#L87 is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1; 67435#L88 activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 67428#L387 assume !(0 != activate_threads_~tmp~1#1); 67429#L387-2 assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1; 67464#L95 assume !(1 == ~c_dr_pc~0); 67465#L95-2 assume !(2 == ~c_dr_pc~0); 67442#L105-1 is_do_read_c_triggered_~__retres1~1#1 := 0; 67388#L116 is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1; 67349#L117 activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 67350#L395 assume !(0 != activate_threads_~tmp___0~1#1); 67364#L395-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67365#L329 assume !(1 == ~q_read_ev~0); 67398#L329-2 assume !(1 == ~q_write_ev~0); 67404#L334-1 assume { :end_inline_reset_delta_events } true; 67405#L491-2 assume !false; 67661#L492 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1; 67640#L435 [2022-02-21 04:21:48,550 INFO L793 eck$LassoCheckResult]: Loop: 67640#L435 assume !false; 67659#L411 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 67655#L291 assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 67653#L303 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 67652#L304 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 67650#L415 assume 0 != eval_~tmp___1~0#1; 67647#L415-1 assume 0 == ~p_dw_st~0;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 67644#L424 assume !(0 != eval_~tmp~2#1); 67642#L420 assume 0 == ~c_dr_st~0;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 67639#L439 assume !(0 != eval_~tmp___0~2#1); 67640#L435 [2022-02-21 04:21:48,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,551 INFO L85 PathProgramCache]: Analyzing trace with hash -293592559, now seen corresponding path program 2 times [2022-02-21 04:21:48,551 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,551 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130980636] [2022-02-21 04:21:48,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,557 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:48,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,562 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:48,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,562 INFO L85 PathProgramCache]: Analyzing trace with hash -418551849, now seen corresponding path program 1 times [2022-02-21 04:21:48,562 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,562 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721466571] [2022-02-21 04:21:48,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,565 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:48,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,567 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:48,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1670788583, now seen corresponding path program 1 times [2022-02-21 04:21:48,567 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,567 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1807605024] [2022-02-21 04:21:48,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,572 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:48,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,577 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:49,286 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:21:49 BoogieIcfgContainer [2022-02-21 04:21:49,286 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:21:49,287 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:21:49,287 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:21:49,287 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:21:49,287 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:35" (3/4) ... [2022-02-21 04:21:49,290 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:21:49,338 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:21:49,338 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:21:49,339 INFO L158 Benchmark]: Toolchain (without parser) took 14871.77ms. Allocated memory was 104.9MB in the beginning and 226.5MB in the end (delta: 121.6MB). Free memory was 74.8MB in the beginning and 99.0MB in the end (delta: -24.2MB). Peak memory consumption was 96.8MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,340 INFO L158 Benchmark]: CDTParser took 0.17ms. Allocated memory is still 104.9MB. Free memory is still 60.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:21:49,340 INFO L158 Benchmark]: CACSL2BoogieTranslator took 269.73ms. Allocated memory is still 104.9MB. Free memory was 74.5MB in the beginning and 78.0MB in the end (delta: -3.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,340 INFO L158 Benchmark]: Boogie Procedure Inliner took 41.82ms. Allocated memory is still 104.9MB. Free memory was 78.0MB in the beginning and 75.1MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,340 INFO L158 Benchmark]: Boogie Preprocessor took 35.08ms. Allocated memory is still 104.9MB. Free memory was 75.1MB in the beginning and 73.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,341 INFO L158 Benchmark]: RCFGBuilder took 421.08ms. Allocated memory is still 104.9MB. Free memory was 73.0MB in the beginning and 52.0MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,341 INFO L158 Benchmark]: BuchiAutomizer took 14047.69ms. Allocated memory was 104.9MB in the beginning and 226.5MB in the end (delta: 121.6MB). Free memory was 51.6MB in the beginning and 103.2MB in the end (delta: -51.6MB). Peak memory consumption was 97.7MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,341 INFO L158 Benchmark]: Witness Printer took 51.68ms. Allocated memory is still 226.5MB. Free memory was 102.1MB in the beginning and 99.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:49,342 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17ms. Allocated memory is still 104.9MB. Free memory is still 60.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 269.73ms. Allocated memory is still 104.9MB. Free memory was 74.5MB in the beginning and 78.0MB in the end (delta: -3.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 41.82ms. Allocated memory is still 104.9MB. Free memory was 78.0MB in the beginning and 75.1MB in the end (delta: 2.9MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 35.08ms. Allocated memory is still 104.9MB. Free memory was 75.1MB in the beginning and 73.0MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 421.08ms. Allocated memory is still 104.9MB. Free memory was 73.0MB in the beginning and 52.0MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 14047.69ms. Allocated memory was 104.9MB in the beginning and 226.5MB in the end (delta: 121.6MB). Free memory was 51.6MB in the beginning and 103.2MB in the end (delta: -51.6MB). Peak memory consumption was 97.7MB. Max. memory is 16.1GB. * Witness Printer took 51.68ms. Allocated memory is still 226.5MB. Free memory was 102.1MB in the beginning and 99.0MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 3868 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 13.9s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.2s. Büchi inclusion checks took 4.2s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 4.4s AutomataMinimizationTime, 9 MinimizatonAttempts, 4068 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 3.2s Buchi closure took 0.0s. Biggest automaton had 3868 states and ocurred in iteration 9. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3109 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3109 mSDsluCounter, 4252 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2626 mSDsCounter, 105 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 261 IncrementalHoareTripleChecker+Invalid, 366 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 105 mSolverCounterUnsat, 1626 mSDtfsCounter, 261 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {p_last_write=0, c_dr_i=1, c_dr_pc=0, a_t=0, NULL=0, \result=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33a34af5=0, __retres1=0, c_num_read=0, c_dr_st=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@200afa2a=0, q_read_ev=2, p_dw_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@61c298b9=0, q_req_up=0, q_write_ev=2, tmp___0=0, tmp___1=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7eb10ef0=0, t=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4559bab3=0, p_dw_pc=0, q_free=1, __retres1=1, fast_clk_edge=2, \result=0, p_dw_st=0, __retres1=0, q_ev=0, tmp___0=0, slow_clk_edge=2, tmp=0, c_last_read=0, NULL=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6e925005=0, kernel_st=1, p_num_write=0, q_buf_0=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6b475a2a=0, __retres1=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) [L316] COND FALSE !((int )q_write_ev == 0) [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; [L66] COND FALSE !((int )p_dw_pc == 1) [L76] COND FALSE !((int )p_dw_pc == 2) [L86] __retres1 = 0 [L88] return (__retres1); [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; [L95] COND FALSE !((int )c_dr_pc == 1) [L105] COND FALSE !((int )c_dr_pc == 2) [L115] __retres1 = 0 [L117] return (__retres1); [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) [L334] COND FALSE !((int )q_write_ev == 1) [L488] RET reset_delta_events() [L491] COND TRUE 1 [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:21:49,395 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)