./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.01.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.01.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:40,317 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:40,319 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:40,355 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:40,356 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:40,358 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:40,359 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:40,361 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:40,363 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:40,368 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:40,368 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:40,369 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:40,370 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:40,372 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:40,373 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:40,376 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:40,377 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:40,378 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:40,379 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:40,384 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:40,385 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:40,386 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:40,387 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:40,388 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:40,390 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:40,390 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:40,390 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:40,391 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:40,392 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:40,392 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:40,392 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:40,393 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:40,394 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:40,395 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:40,396 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:40,396 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:40,396 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:40,397 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:40,397 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:40,397 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:40,398 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:40,398 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:40,423 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:40,424 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:40,424 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:40,424 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:40,425 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:40,425 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:40,425 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:40,425 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:40,426 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:40,426 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:40,426 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:40,427 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:40,427 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:40,428 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:40,429 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:40,429 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:40,429 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:40,429 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:40,429 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:40,429 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:40,430 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:40,430 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b0a21004c99a1cc1588d43a2481960a2ce9f2cdf68e9a363306433e7d24bd30 [2022-02-21 04:21:40,636 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:40,655 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:40,656 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:40,658 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:40,658 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:40,659 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2022-02-21 04:21:40,713 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0865a0f16/23159382995b425bb4077354a75b572c/FLAGcb3d71f66 [2022-02-21 04:21:41,084 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:41,085 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c [2022-02-21 04:21:41,090 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0865a0f16/23159382995b425bb4077354a75b572c/FLAGcb3d71f66 [2022-02-21 04:21:41,099 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0865a0f16/23159382995b425bb4077354a75b572c [2022-02-21 04:21:41,102 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:41,103 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:41,111 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:41,111 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:41,114 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:41,115 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,116 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@36b5ae9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41, skipping insertion in model container [2022-02-21 04:21:41,116 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,120 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:41,154 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:41,256 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2022-02-21 04:21:41,301 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:41,308 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:41,315 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.01.cil-1.c[671,684] [2022-02-21 04:21:41,334 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:41,359 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:41,359 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41 WrapperNode [2022-02-21 04:21:41,359 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:41,360 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:41,360 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:41,360 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:41,365 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,379 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,421 INFO L137 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 38, statements flattened = 405 [2022-02-21 04:21:41,421 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:41,422 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:41,422 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:41,422 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:41,429 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,429 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,431 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,438 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,442 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,449 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,450 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,452 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:41,453 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:41,453 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:41,453 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:41,453 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (1/1) ... [2022-02-21 04:21:41,459 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:41,467 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:41,475 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:41,478 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:41,502 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:41,502 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:41,502 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:41,502 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:41,548 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:41,550 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:41,877 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:41,896 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:41,896 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-02-21 04:21:41,898 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:41 BoogieIcfgContainer [2022-02-21 04:21:41,898 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:41,899 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:41,899 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:41,901 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:41,902 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:41,902 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:41" (1/3) ... [2022-02-21 04:21:41,902 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5bbbde65 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:41, skipping insertion in model container [2022-02-21 04:21:41,903 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:41,903 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:41" (2/3) ... [2022-02-21 04:21:41,903 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5bbbde65 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:41, skipping insertion in model container [2022-02-21 04:21:41,903 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:41,903 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:41" (3/3) ... [2022-02-21 04:21:41,904 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.01.cil-1.c [2022-02-21 04:21:41,932 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:41,932 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:41,932 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:41,932 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:41,932 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:41,933 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:41,933 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:41,933 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:41,953 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,006 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2022-02-21 04:21:42,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:42,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:42,012 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,012 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,012 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:42,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,027 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 117 [2022-02-21 04:21:42,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:42,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:42,028 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,028 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,035 INFO L791 eck$LassoCheckResult]: Stem: 140#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 49#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 98#L391true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60#L163true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77#L170true assume !(1 == ~m_i~0);~m_st~0 := 2; 57#L170-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 141#L175-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79#L259true assume !(0 == ~M_E~0); 136#L259-2true assume !(0 == ~T1_E~0); 96#L264-1true assume !(0 == ~E_M~0); 114#L269-1true assume !(0 == ~E_1~0); 89#L274-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L124true assume 1 == ~m_pc~0; 100#L125true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 127#L135true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20#L136true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 154#L319true assume !(0 != activate_threads_~tmp~1#1); 21#L319-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119#L143true assume 1 == ~t1_pc~0; 8#L144true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 104#L154true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56#L155true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28#L327true assume !(0 != activate_threads_~tmp___0~0#1); 43#L327-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74#L287true assume !(1 == ~M_E~0); 106#L287-2true assume !(1 == ~T1_E~0); 39#L292-1true assume !(1 == ~E_M~0); 42#L297-1true assume !(1 == ~E_1~0); 29#L302-1true assume { :end_inline_reset_delta_events } true; 54#L428-2true [2022-02-21 04:21:42,036 INFO L793 eck$LassoCheckResult]: Loop: 54#L428-2true assume !false; 93#L429true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 80#L234true assume false; 6#L249true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26#L163-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L259-3true assume 0 == ~M_E~0;~M_E~0 := 1; 138#L259-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 113#L264-3true assume 0 == ~E_M~0;~E_M~0 := 1; 18#L269-3true assume 0 == ~E_1~0;~E_1~0 := 1; 67#L274-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14#L124-9true assume 1 == ~m_pc~0; 33#L125-3true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 72#L135-3true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25#L136-3true activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 90#L319-9true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51#L319-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65#L143-9true assume !(1 == ~t1_pc~0); 27#L143-11true is_transmit1_triggered_~__retres1~1#1 := 0; 66#L154-3true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17#L155-3true activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 116#L327-9true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 153#L327-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 142#L287-3true assume !(1 == ~M_E~0); 75#L287-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 87#L297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 7#L302-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 130#L188-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 31#L200-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 111#L201-1true start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 38#L447true assume !(0 == start_simulation_~tmp~3#1); 108#L447-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9#L188-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 99#L200-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 134#L201-2true stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 101#L402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 144#L409true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118#L410true start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 68#L460true assume !(0 != start_simulation_~tmp___0~1#1); 54#L428-2true [2022-02-21 04:21:42,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,063 INFO L85 PathProgramCache]: Analyzing trace with hash -704910459, now seen corresponding path program 1 times [2022-02-21 04:21:42,070 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,071 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025967895] [2022-02-21 04:21:42,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:42,239 INFO L290 TraceCheckUtils]: 0: Hoare triple {156#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {156#true} is VALID [2022-02-21 04:21:42,240 INFO L290 TraceCheckUtils]: 1: Hoare triple {156#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {158#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:42,241 INFO L290 TraceCheckUtils]: 2: Hoare triple {158#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {158#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:42,242 INFO L290 TraceCheckUtils]: 3: Hoare triple {158#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {158#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:42,242 INFO L290 TraceCheckUtils]: 4: Hoare triple {158#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {157#false} is VALID [2022-02-21 04:21:42,242 INFO L290 TraceCheckUtils]: 5: Hoare triple {157#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {157#false} is VALID [2022-02-21 04:21:42,243 INFO L290 TraceCheckUtils]: 6: Hoare triple {157#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {157#false} is VALID [2022-02-21 04:21:42,243 INFO L290 TraceCheckUtils]: 7: Hoare triple {157#false} assume !(0 == ~M_E~0); {157#false} is VALID [2022-02-21 04:21:42,244 INFO L290 TraceCheckUtils]: 8: Hoare triple {157#false} assume !(0 == ~T1_E~0); {157#false} is VALID [2022-02-21 04:21:42,244 INFO L290 TraceCheckUtils]: 9: Hoare triple {157#false} assume !(0 == ~E_M~0); {157#false} is VALID [2022-02-21 04:21:42,244 INFO L290 TraceCheckUtils]: 10: Hoare triple {157#false} assume !(0 == ~E_1~0); {157#false} is VALID [2022-02-21 04:21:42,244 INFO L290 TraceCheckUtils]: 11: Hoare triple {157#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {157#false} is VALID [2022-02-21 04:21:42,245 INFO L290 TraceCheckUtils]: 12: Hoare triple {157#false} assume 1 == ~m_pc~0; {157#false} is VALID [2022-02-21 04:21:42,245 INFO L290 TraceCheckUtils]: 13: Hoare triple {157#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {157#false} is VALID [2022-02-21 04:21:42,245 INFO L290 TraceCheckUtils]: 14: Hoare triple {157#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {157#false} is VALID [2022-02-21 04:21:42,245 INFO L290 TraceCheckUtils]: 15: Hoare triple {157#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {157#false} is VALID [2022-02-21 04:21:42,246 INFO L290 TraceCheckUtils]: 16: Hoare triple {157#false} assume !(0 != activate_threads_~tmp~1#1); {157#false} is VALID [2022-02-21 04:21:42,246 INFO L290 TraceCheckUtils]: 17: Hoare triple {157#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {157#false} is VALID [2022-02-21 04:21:42,246 INFO L290 TraceCheckUtils]: 18: Hoare triple {157#false} assume 1 == ~t1_pc~0; {157#false} is VALID [2022-02-21 04:21:42,246 INFO L290 TraceCheckUtils]: 19: Hoare triple {157#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {157#false} is VALID [2022-02-21 04:21:42,247 INFO L290 TraceCheckUtils]: 20: Hoare triple {157#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {157#false} is VALID [2022-02-21 04:21:42,247 INFO L290 TraceCheckUtils]: 21: Hoare triple {157#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {157#false} is VALID [2022-02-21 04:21:42,248 INFO L290 TraceCheckUtils]: 22: Hoare triple {157#false} assume !(0 != activate_threads_~tmp___0~0#1); {157#false} is VALID [2022-02-21 04:21:42,248 INFO L290 TraceCheckUtils]: 23: Hoare triple {157#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {157#false} is VALID [2022-02-21 04:21:42,248 INFO L290 TraceCheckUtils]: 24: Hoare triple {157#false} assume !(1 == ~M_E~0); {157#false} is VALID [2022-02-21 04:21:42,248 INFO L290 TraceCheckUtils]: 25: Hoare triple {157#false} assume !(1 == ~T1_E~0); {157#false} is VALID [2022-02-21 04:21:42,248 INFO L290 TraceCheckUtils]: 26: Hoare triple {157#false} assume !(1 == ~E_M~0); {157#false} is VALID [2022-02-21 04:21:42,249 INFO L290 TraceCheckUtils]: 27: Hoare triple {157#false} assume !(1 == ~E_1~0); {157#false} is VALID [2022-02-21 04:21:42,249 INFO L290 TraceCheckUtils]: 28: Hoare triple {157#false} assume { :end_inline_reset_delta_events } true; {157#false} is VALID [2022-02-21 04:21:42,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:42,251 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:42,251 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025967895] [2022-02-21 04:21:42,252 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025967895] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:42,252 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:42,252 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:42,255 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [645603692] [2022-02-21 04:21:42,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:42,260 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:42,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,263 INFO L85 PathProgramCache]: Analyzing trace with hash 180057256, now seen corresponding path program 1 times [2022-02-21 04:21:42,263 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,264 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078424563] [2022-02-21 04:21:42,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:42,304 INFO L290 TraceCheckUtils]: 0: Hoare triple {159#true} assume !false; {159#true} is VALID [2022-02-21 04:21:42,305 INFO L290 TraceCheckUtils]: 1: Hoare triple {159#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {159#true} is VALID [2022-02-21 04:21:42,306 INFO L290 TraceCheckUtils]: 2: Hoare triple {159#true} assume false; {160#false} is VALID [2022-02-21 04:21:42,306 INFO L290 TraceCheckUtils]: 3: Hoare triple {160#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {160#false} is VALID [2022-02-21 04:21:42,307 INFO L290 TraceCheckUtils]: 4: Hoare triple {160#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {160#false} is VALID [2022-02-21 04:21:42,307 INFO L290 TraceCheckUtils]: 5: Hoare triple {160#false} assume 0 == ~M_E~0;~M_E~0 := 1; {160#false} is VALID [2022-02-21 04:21:42,307 INFO L290 TraceCheckUtils]: 6: Hoare triple {160#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {160#false} is VALID [2022-02-21 04:21:42,307 INFO L290 TraceCheckUtils]: 7: Hoare triple {160#false} assume 0 == ~E_M~0;~E_M~0 := 1; {160#false} is VALID [2022-02-21 04:21:42,308 INFO L290 TraceCheckUtils]: 8: Hoare triple {160#false} assume 0 == ~E_1~0;~E_1~0 := 1; {160#false} is VALID [2022-02-21 04:21:42,308 INFO L290 TraceCheckUtils]: 9: Hoare triple {160#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {160#false} is VALID [2022-02-21 04:21:42,308 INFO L290 TraceCheckUtils]: 10: Hoare triple {160#false} assume 1 == ~m_pc~0; {160#false} is VALID [2022-02-21 04:21:42,308 INFO L290 TraceCheckUtils]: 11: Hoare triple {160#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {160#false} is VALID [2022-02-21 04:21:42,309 INFO L290 TraceCheckUtils]: 12: Hoare triple {160#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {160#false} is VALID [2022-02-21 04:21:42,309 INFO L290 TraceCheckUtils]: 13: Hoare triple {160#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {160#false} is VALID [2022-02-21 04:21:42,309 INFO L290 TraceCheckUtils]: 14: Hoare triple {160#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {160#false} is VALID [2022-02-21 04:21:42,309 INFO L290 TraceCheckUtils]: 15: Hoare triple {160#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {160#false} is VALID [2022-02-21 04:21:42,309 INFO L290 TraceCheckUtils]: 16: Hoare triple {160#false} assume !(1 == ~t1_pc~0); {160#false} is VALID [2022-02-21 04:21:42,310 INFO L290 TraceCheckUtils]: 17: Hoare triple {160#false} is_transmit1_triggered_~__retres1~1#1 := 0; {160#false} is VALID [2022-02-21 04:21:42,310 INFO L290 TraceCheckUtils]: 18: Hoare triple {160#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {160#false} is VALID [2022-02-21 04:21:42,310 INFO L290 TraceCheckUtils]: 19: Hoare triple {160#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {160#false} is VALID [2022-02-21 04:21:42,311 INFO L290 TraceCheckUtils]: 20: Hoare triple {160#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {160#false} is VALID [2022-02-21 04:21:42,313 INFO L290 TraceCheckUtils]: 21: Hoare triple {160#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {160#false} is VALID [2022-02-21 04:21:42,314 INFO L290 TraceCheckUtils]: 22: Hoare triple {160#false} assume !(1 == ~M_E~0); {160#false} is VALID [2022-02-21 04:21:42,314 INFO L290 TraceCheckUtils]: 23: Hoare triple {160#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {160#false} is VALID [2022-02-21 04:21:42,314 INFO L290 TraceCheckUtils]: 24: Hoare triple {160#false} assume 1 == ~E_M~0;~E_M~0 := 2; {160#false} is VALID [2022-02-21 04:21:42,315 INFO L290 TraceCheckUtils]: 25: Hoare triple {160#false} assume 1 == ~E_1~0;~E_1~0 := 2; {160#false} is VALID [2022-02-21 04:21:42,315 INFO L290 TraceCheckUtils]: 26: Hoare triple {160#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {160#false} is VALID [2022-02-21 04:21:42,315 INFO L290 TraceCheckUtils]: 27: Hoare triple {160#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {160#false} is VALID [2022-02-21 04:21:42,316 INFO L290 TraceCheckUtils]: 28: Hoare triple {160#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {160#false} is VALID [2022-02-21 04:21:42,316 INFO L290 TraceCheckUtils]: 29: Hoare triple {160#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {160#false} is VALID [2022-02-21 04:21:42,316 INFO L290 TraceCheckUtils]: 30: Hoare triple {160#false} assume !(0 == start_simulation_~tmp~3#1); {160#false} is VALID [2022-02-21 04:21:42,317 INFO L290 TraceCheckUtils]: 31: Hoare triple {160#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {160#false} is VALID [2022-02-21 04:21:42,317 INFO L290 TraceCheckUtils]: 32: Hoare triple {160#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {160#false} is VALID [2022-02-21 04:21:42,317 INFO L290 TraceCheckUtils]: 33: Hoare triple {160#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {160#false} is VALID [2022-02-21 04:21:42,317 INFO L290 TraceCheckUtils]: 34: Hoare triple {160#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {160#false} is VALID [2022-02-21 04:21:42,318 INFO L290 TraceCheckUtils]: 35: Hoare triple {160#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {160#false} is VALID [2022-02-21 04:21:42,318 INFO L290 TraceCheckUtils]: 36: Hoare triple {160#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {160#false} is VALID [2022-02-21 04:21:42,318 INFO L290 TraceCheckUtils]: 37: Hoare triple {160#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {160#false} is VALID [2022-02-21 04:21:42,318 INFO L290 TraceCheckUtils]: 38: Hoare triple {160#false} assume !(0 != start_simulation_~tmp___0~1#1); {160#false} is VALID [2022-02-21 04:21:42,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:42,319 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:42,320 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078424563] [2022-02-21 04:21:42,320 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078424563] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:42,320 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:42,320 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:42,320 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395584834] [2022-02-21 04:21:42,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:42,321 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:42,322 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:42,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:42,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:42,343 INFO L87 Difference]: Start difference. First operand has 152 states, 151 states have (on average 1.5231788079470199) internal successors, (230), 151 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:42,527 INFO L93 Difference]: Finished difference Result 151 states and 219 transitions. [2022-02-21 04:21:42,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:42,528 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,569 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:42,573 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 219 transitions. [2022-02-21 04:21:42,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2022-02-21 04:21:42,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 146 states and 214 transitions. [2022-02-21 04:21:42,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146 [2022-02-21 04:21:42,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146 [2022-02-21 04:21:42,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 146 states and 214 transitions. [2022-02-21 04:21:42,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:42,588 INFO L681 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-02-21 04:21:42,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states and 214 transitions. [2022-02-21 04:21:42,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2022-02-21 04:21:42,634 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:42,635 INFO L82 GeneralOperation]: Start isEquivalent. First operand 146 states and 214 transitions. Second operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,636 INFO L74 IsIncluded]: Start isIncluded. First operand 146 states and 214 transitions. Second operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,637 INFO L87 Difference]: Start difference. First operand 146 states and 214 transitions. Second operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:42,642 INFO L93 Difference]: Finished difference Result 146 states and 214 transitions. [2022-02-21 04:21:42,642 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 214 transitions. [2022-02-21 04:21:42,643 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:42,643 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:42,644 INFO L74 IsIncluded]: Start isIncluded. First operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 146 states and 214 transitions. [2022-02-21 04:21:42,644 INFO L87 Difference]: Start difference. First operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 146 states and 214 transitions. [2022-02-21 04:21:42,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:42,648 INFO L93 Difference]: Finished difference Result 146 states and 214 transitions. [2022-02-21 04:21:42,648 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 214 transitions. [2022-02-21 04:21:42,649 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:42,649 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:42,649 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:42,649 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:42,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.4657534246575343) internal successors, (214), 145 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:42,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 214 transitions. [2022-02-21 04:21:42,662 INFO L704 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-02-21 04:21:42,662 INFO L587 BuchiCegarLoop]: Abstraction has 146 states and 214 transitions. [2022-02-21 04:21:42,662 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:42,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 214 transitions. [2022-02-21 04:21:42,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 115 [2022-02-21 04:21:42,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:42,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:42,665 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,665 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:42,665 INFO L791 eck$LassoCheckResult]: Stem: 456#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 396#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 408#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 409#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 404#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 424#L259 assume !(0 == ~M_E~0); 425#L259-2 assume !(0 == ~T1_E~0); 441#L264-1 assume !(0 == ~E_M~0); 442#L269-1 assume !(0 == ~E_1~0); 435#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 436#L124 assume 1 == ~m_pc~0; 437#L125 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 416#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 345#L319 assume !(0 != activate_threads_~tmp~1#1); 346#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 347#L143 assume 1 == ~t1_pc~0; 326#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 403#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 360#L327 assume !(0 != activate_threads_~tmp___0~0#1); 361#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 384#L287 assume !(1 == ~M_E~0); 423#L287-2 assume !(1 == ~T1_E~0); 379#L292-1 assume !(1 == ~E_M~0); 380#L297-1 assume !(1 == ~E_1~0); 362#L302-1 assume { :end_inline_reset_delta_events } true; 363#L428-2 [2022-02-21 04:21:42,665 INFO L793 eck$LassoCheckResult]: Loop: 363#L428-2 assume !false; 401#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L234 assume !false; 426#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 348#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 349#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 417#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 418#L215 assume !(0 != eval_~tmp~0#1); 319#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 320#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 355#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 455#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 447#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 342#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 343#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 332#L124-9 assume 1 == ~m_pc~0; 333#L125-3 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 368#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 353#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 354#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 397#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 398#L143-9 assume !(1 == ~t1_pc~0); 356#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 357#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 338#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 449#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457#L287-3 assume !(1 == ~M_E~0); 421#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 422#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 432#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 317#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 318#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 358#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 359#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 376#L447 assume !(0 == start_simulation_~tmp~3#1); 377#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 321#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 322#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 443#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 444#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 445#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 450#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 414#L460 assume !(0 != start_simulation_~tmp___0~1#1); 363#L428-2 [2022-02-21 04:21:42,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,669 INFO L85 PathProgramCache]: Analyzing trace with hash -845459069, now seen corresponding path program 1 times [2022-02-21 04:21:42,670 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,670 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906738940] [2022-02-21 04:21:42,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:42,723 INFO L290 TraceCheckUtils]: 0: Hoare triple {753#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,723 INFO L290 TraceCheckUtils]: 1: Hoare triple {755#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,723 INFO L290 TraceCheckUtils]: 2: Hoare triple {755#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,724 INFO L290 TraceCheckUtils]: 3: Hoare triple {755#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,724 INFO L290 TraceCheckUtils]: 4: Hoare triple {755#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,724 INFO L290 TraceCheckUtils]: 5: Hoare triple {755#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,725 INFO L290 TraceCheckUtils]: 6: Hoare triple {755#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,727 INFO L290 TraceCheckUtils]: 7: Hoare triple {755#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,727 INFO L290 TraceCheckUtils]: 8: Hoare triple {755#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,728 INFO L290 TraceCheckUtils]: 9: Hoare triple {755#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,728 INFO L290 TraceCheckUtils]: 10: Hoare triple {755#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,728 INFO L290 TraceCheckUtils]: 11: Hoare triple {755#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {755#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:42,729 INFO L290 TraceCheckUtils]: 12: Hoare triple {755#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {754#false} is VALID [2022-02-21 04:21:42,729 INFO L290 TraceCheckUtils]: 13: Hoare triple {754#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {754#false} is VALID [2022-02-21 04:21:42,729 INFO L290 TraceCheckUtils]: 14: Hoare triple {754#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {754#false} is VALID [2022-02-21 04:21:42,729 INFO L290 TraceCheckUtils]: 15: Hoare triple {754#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 16: Hoare triple {754#false} assume !(0 != activate_threads_~tmp~1#1); {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 17: Hoare triple {754#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 18: Hoare triple {754#false} assume 1 == ~t1_pc~0; {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 19: Hoare triple {754#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 20: Hoare triple {754#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {754#false} is VALID [2022-02-21 04:21:42,731 INFO L290 TraceCheckUtils]: 21: Hoare triple {754#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 22: Hoare triple {754#false} assume !(0 != activate_threads_~tmp___0~0#1); {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 23: Hoare triple {754#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 24: Hoare triple {754#false} assume !(1 == ~M_E~0); {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 25: Hoare triple {754#false} assume !(1 == ~T1_E~0); {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 26: Hoare triple {754#false} assume !(1 == ~E_M~0); {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 27: Hoare triple {754#false} assume !(1 == ~E_1~0); {754#false} is VALID [2022-02-21 04:21:42,732 INFO L290 TraceCheckUtils]: 28: Hoare triple {754#false} assume { :end_inline_reset_delta_events } true; {754#false} is VALID [2022-02-21 04:21:42,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:42,733 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:42,733 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906738940] [2022-02-21 04:21:42,733 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906738940] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:42,733 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:42,733 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:42,733 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987556239] [2022-02-21 04:21:42,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:42,734 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:42,740 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:42,740 INFO L85 PathProgramCache]: Analyzing trace with hash -1897027051, now seen corresponding path program 1 times [2022-02-21 04:21:42,740 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:42,741 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390543298] [2022-02-21 04:21:42,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:42,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:42,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:42,787 INFO L290 TraceCheckUtils]: 0: Hoare triple {756#true} assume !false; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 1: Hoare triple {756#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 2: Hoare triple {756#true} assume !false; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 3: Hoare triple {756#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 4: Hoare triple {756#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 5: Hoare triple {756#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {756#true} is VALID [2022-02-21 04:21:42,788 INFO L290 TraceCheckUtils]: 6: Hoare triple {756#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {756#true} is VALID [2022-02-21 04:21:42,792 INFO L290 TraceCheckUtils]: 7: Hoare triple {756#true} assume !(0 != eval_~tmp~0#1); {756#true} is VALID [2022-02-21 04:21:42,793 INFO L290 TraceCheckUtils]: 8: Hoare triple {756#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {756#true} is VALID [2022-02-21 04:21:42,794 INFO L290 TraceCheckUtils]: 9: Hoare triple {756#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {756#true} is VALID [2022-02-21 04:21:42,794 INFO L290 TraceCheckUtils]: 10: Hoare triple {756#true} assume 0 == ~M_E~0;~M_E~0 := 1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,794 INFO L290 TraceCheckUtils]: 11: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,795 INFO L290 TraceCheckUtils]: 12: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,795 INFO L290 TraceCheckUtils]: 13: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,796 INFO L290 TraceCheckUtils]: 14: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,797 INFO L290 TraceCheckUtils]: 15: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~m_pc~0; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,797 INFO L290 TraceCheckUtils]: 16: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,798 INFO L290 TraceCheckUtils]: 17: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,798 INFO L290 TraceCheckUtils]: 18: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,805 INFO L290 TraceCheckUtils]: 19: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,805 INFO L290 TraceCheckUtils]: 20: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,806 INFO L290 TraceCheckUtils]: 21: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,808 INFO L290 TraceCheckUtils]: 22: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,808 INFO L290 TraceCheckUtils]: 23: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,808 INFO L290 TraceCheckUtils]: 24: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,809 INFO L290 TraceCheckUtils]: 25: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,809 INFO L290 TraceCheckUtils]: 26: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {758#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:42,809 INFO L290 TraceCheckUtils]: 27: Hoare triple {758#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {757#false} is VALID [2022-02-21 04:21:42,809 INFO L290 TraceCheckUtils]: 28: Hoare triple {757#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 29: Hoare triple {757#false} assume 1 == ~E_M~0;~E_M~0 := 2; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 30: Hoare triple {757#false} assume 1 == ~E_1~0;~E_1~0 := 2; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 31: Hoare triple {757#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 32: Hoare triple {757#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 33: Hoare triple {757#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 34: Hoare triple {757#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 35: Hoare triple {757#false} assume !(0 == start_simulation_~tmp~3#1); {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 36: Hoare triple {757#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 37: Hoare triple {757#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 38: Hoare triple {757#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 39: Hoare triple {757#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 40: Hoare triple {757#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {757#false} is VALID [2022-02-21 04:21:42,810 INFO L290 TraceCheckUtils]: 41: Hoare triple {757#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {757#false} is VALID [2022-02-21 04:21:42,811 INFO L290 TraceCheckUtils]: 42: Hoare triple {757#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {757#false} is VALID [2022-02-21 04:21:42,811 INFO L290 TraceCheckUtils]: 43: Hoare triple {757#false} assume !(0 != start_simulation_~tmp___0~1#1); {757#false} is VALID [2022-02-21 04:21:42,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:42,811 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:42,811 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [390543298] [2022-02-21 04:21:42,811 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [390543298] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:42,811 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:42,811 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:42,812 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300622801] [2022-02-21 04:21:42,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:42,812 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:42,812 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:42,812 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:42,812 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:42,813 INFO L87 Difference]: Start difference. First operand 146 states and 214 transitions. cyclomatic complexity: 69 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,042 INFO L93 Difference]: Finished difference Result 253 states and 362 transitions. [2022-02-21 04:21:43,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:43,043 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,063 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:43,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 253 states and 362 transitions. [2022-02-21 04:21:43,078 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 222 [2022-02-21 04:21:43,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 253 states to 253 states and 362 transitions. [2022-02-21 04:21:43,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 253 [2022-02-21 04:21:43,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 253 [2022-02-21 04:21:43,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 253 states and 362 transitions. [2022-02-21 04:21:43,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:43,084 INFO L681 BuchiCegarLoop]: Abstraction has 253 states and 362 transitions. [2022-02-21 04:21:43,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states and 362 transitions. [2022-02-21 04:21:43,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 240. [2022-02-21 04:21:43,091 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:43,091 INFO L82 GeneralOperation]: Start isEquivalent. First operand 253 states and 362 transitions. Second operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,092 INFO L74 IsIncluded]: Start isIncluded. First operand 253 states and 362 transitions. Second operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,092 INFO L87 Difference]: Start difference. First operand 253 states and 362 transitions. Second operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,097 INFO L93 Difference]: Finished difference Result 253 states and 362 transitions. [2022-02-21 04:21:43,097 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 362 transitions. [2022-02-21 04:21:43,098 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,098 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,098 INFO L74 IsIncluded]: Start isIncluded. First operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 253 states and 362 transitions. [2022-02-21 04:21:43,099 INFO L87 Difference]: Start difference. First operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 253 states and 362 transitions. [2022-02-21 04:21:43,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,103 INFO L93 Difference]: Finished difference Result 253 states and 362 transitions. [2022-02-21 04:21:43,103 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 362 transitions. [2022-02-21 04:21:43,104 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,104 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,104 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:43,104 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:43,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 240 states, 240 states have (on average 1.4375) internal successors, (345), 239 states have internal predecessors, (345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 345 transitions. [2022-02-21 04:21:43,109 INFO L704 BuchiCegarLoop]: Abstraction has 240 states and 345 transitions. [2022-02-21 04:21:43,109 INFO L587 BuchiCegarLoop]: Abstraction has 240 states and 345 transitions. [2022-02-21 04:21:43,109 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:43,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 240 states and 345 transitions. [2022-02-21 04:21:43,110 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 209 [2022-02-21 04:21:43,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:43,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:43,110 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:43,111 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:43,111 INFO L791 eck$LassoCheckResult]: Stem: 1167#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 1096#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1097#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1111#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1112#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 1107#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1108#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1128#L259 assume !(0 == ~M_E~0); 1129#L259-2 assume !(0 == ~T1_E~0); 1144#L264-1 assume !(0 == ~E_M~0); 1145#L269-1 assume !(0 == ~E_1~0); 1140#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1141#L124 assume !(1 == ~m_pc~0); 1118#L124-2 is_master_triggered_~__retres1~0#1 := 0; 1119#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1044#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1045#L319 assume !(0 != activate_threads_~tmp~1#1); 1046#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1047#L143 assume 1 == ~t1_pc~0; 1021#L144 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1022#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1106#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1058#L327 assume !(0 != activate_threads_~tmp___0~0#1); 1059#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1086#L287 assume !(1 == ~M_E~0); 1125#L287-2 assume !(1 == ~T1_E~0); 1081#L292-1 assume !(1 == ~E_M~0); 1082#L297-1 assume !(1 == ~E_1~0); 1060#L302-1 assume { :end_inline_reset_delta_events } true; 1061#L428-2 [2022-02-21 04:21:43,111 INFO L793 eck$LassoCheckResult]: Loop: 1061#L428-2 assume !false; 1104#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1130#L234 assume !false; 1131#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1048#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1049#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1120#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1121#L215 assume !(0 != eval_~tmp~0#1); 1017#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1018#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1055#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1166#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1152#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1041#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1042#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1033#L124-9 assume !(1 == ~m_pc~0); 1034#L124-11 is_master_triggered_~__retres1~0#1 := 0; 1251#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1250#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1249#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1239#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1238#L143-9 assume !(1 == ~t1_pc~0); 1236#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 1235#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1234#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1154#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1155#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1168#L287-3 assume !(1 == ~M_E~0); 1126#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1127#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1137#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1019#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1020#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1064#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1065#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1078#L447 assume !(0 == start_simulation_~tmp~3#1); 1079#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1024#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1025#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1146#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 1147#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1148#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1156#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1117#L460 assume !(0 != start_simulation_~tmp___0~1#1); 1061#L428-2 [2022-02-21 04:21:43,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:43,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1269536452, now seen corresponding path program 1 times [2022-02-21 04:21:43,111 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:43,112 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596267298] [2022-02-21 04:21:43,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:43,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:43,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:43,137 INFO L290 TraceCheckUtils]: 0: Hoare triple {1761#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,138 INFO L290 TraceCheckUtils]: 1: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,138 INFO L290 TraceCheckUtils]: 2: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,138 INFO L290 TraceCheckUtils]: 3: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,139 INFO L290 TraceCheckUtils]: 4: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,139 INFO L290 TraceCheckUtils]: 5: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,139 INFO L290 TraceCheckUtils]: 6: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,140 INFO L290 TraceCheckUtils]: 7: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,140 INFO L290 TraceCheckUtils]: 8: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,140 INFO L290 TraceCheckUtils]: 9: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,141 INFO L290 TraceCheckUtils]: 10: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1763#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:43,141 INFO L290 TraceCheckUtils]: 12: Hoare triple {1763#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,141 INFO L290 TraceCheckUtils]: 13: Hoare triple {1764#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {1764#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,143 INFO L290 TraceCheckUtils]: 15: Hoare triple {1764#(not (= ~t1_pc~0 1))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 16: Hoare triple {1764#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 17: Hoare triple {1764#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1764#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 18: Hoare triple {1764#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {1762#false} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 19: Hoare triple {1762#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {1762#false} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 20: Hoare triple {1762#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1762#false} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 21: Hoare triple {1762#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1762#false} is VALID [2022-02-21 04:21:43,144 INFO L290 TraceCheckUtils]: 22: Hoare triple {1762#false} assume !(0 != activate_threads_~tmp___0~0#1); {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 23: Hoare triple {1762#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 24: Hoare triple {1762#false} assume !(1 == ~M_E~0); {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 25: Hoare triple {1762#false} assume !(1 == ~T1_E~0); {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 26: Hoare triple {1762#false} assume !(1 == ~E_M~0); {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 27: Hoare triple {1762#false} assume !(1 == ~E_1~0); {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L290 TraceCheckUtils]: 28: Hoare triple {1762#false} assume { :end_inline_reset_delta_events } true; {1762#false} is VALID [2022-02-21 04:21:43,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:43,145 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:43,145 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596267298] [2022-02-21 04:21:43,145 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596267298] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:43,145 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:43,145 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:43,146 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148614934] [2022-02-21 04:21:43,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:43,146 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:43,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:43,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 1 times [2022-02-21 04:21:43,146 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:43,146 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1695908464] [2022-02-21 04:21:43,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:43,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:43,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:43,168 INFO L290 TraceCheckUtils]: 0: Hoare triple {1765#true} assume !false; {1765#true} is VALID [2022-02-21 04:21:43,168 INFO L290 TraceCheckUtils]: 1: Hoare triple {1765#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1765#true} is VALID [2022-02-21 04:21:43,168 INFO L290 TraceCheckUtils]: 2: Hoare triple {1765#true} assume !false; {1765#true} is VALID [2022-02-21 04:21:43,168 INFO L290 TraceCheckUtils]: 3: Hoare triple {1765#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 4: Hoare triple {1765#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 5: Hoare triple {1765#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 6: Hoare triple {1765#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 7: Hoare triple {1765#true} assume !(0 != eval_~tmp~0#1); {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 8: Hoare triple {1765#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1765#true} is VALID [2022-02-21 04:21:43,169 INFO L290 TraceCheckUtils]: 9: Hoare triple {1765#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1765#true} is VALID [2022-02-21 04:21:43,170 INFO L290 TraceCheckUtils]: 10: Hoare triple {1765#true} assume 0 == ~M_E~0;~M_E~0 := 1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,170 INFO L290 TraceCheckUtils]: 11: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,170 INFO L290 TraceCheckUtils]: 12: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,171 INFO L290 TraceCheckUtils]: 13: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,171 INFO L290 TraceCheckUtils]: 14: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,171 INFO L290 TraceCheckUtils]: 15: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,171 INFO L290 TraceCheckUtils]: 16: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,172 INFO L290 TraceCheckUtils]: 17: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,172 INFO L290 TraceCheckUtils]: 18: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,172 INFO L290 TraceCheckUtils]: 19: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,173 INFO L290 TraceCheckUtils]: 20: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,173 INFO L290 TraceCheckUtils]: 21: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,173 INFO L290 TraceCheckUtils]: 22: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,174 INFO L290 TraceCheckUtils]: 23: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,174 INFO L290 TraceCheckUtils]: 24: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,174 INFO L290 TraceCheckUtils]: 25: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,174 INFO L290 TraceCheckUtils]: 26: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1767#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 27: Hoare triple {1767#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {1766#false} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 28: Hoare triple {1766#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1766#false} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 29: Hoare triple {1766#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1766#false} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 30: Hoare triple {1766#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1766#false} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 31: Hoare triple {1766#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1766#false} is VALID [2022-02-21 04:21:43,175 INFO L290 TraceCheckUtils]: 32: Hoare triple {1766#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 33: Hoare triple {1766#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 34: Hoare triple {1766#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 35: Hoare triple {1766#false} assume !(0 == start_simulation_~tmp~3#1); {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 36: Hoare triple {1766#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 37: Hoare triple {1766#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 38: Hoare triple {1766#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {1766#false} is VALID [2022-02-21 04:21:43,176 INFO L290 TraceCheckUtils]: 39: Hoare triple {1766#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {1766#false} is VALID [2022-02-21 04:21:43,177 INFO L290 TraceCheckUtils]: 40: Hoare triple {1766#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1766#false} is VALID [2022-02-21 04:21:43,177 INFO L290 TraceCheckUtils]: 41: Hoare triple {1766#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1766#false} is VALID [2022-02-21 04:21:43,177 INFO L290 TraceCheckUtils]: 42: Hoare triple {1766#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {1766#false} is VALID [2022-02-21 04:21:43,177 INFO L290 TraceCheckUtils]: 43: Hoare triple {1766#false} assume !(0 != start_simulation_~tmp___0~1#1); {1766#false} is VALID [2022-02-21 04:21:43,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:43,177 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:43,178 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1695908464] [2022-02-21 04:21:43,178 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1695908464] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:43,178 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:43,178 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:43,178 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [547004951] [2022-02-21 04:21:43,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:43,178 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:43,179 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:43,179 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:43,180 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:43,180 INFO L87 Difference]: Start difference. First operand 240 states and 345 transitions. cyclomatic complexity: 107 Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,583 INFO L93 Difference]: Finished difference Result 512 states and 719 transitions. [2022-02-21 04:21:43,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:43,584 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 7.25) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,601 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:43,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 719 transitions. [2022-02-21 04:21:43,616 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 461 [2022-02-21 04:21:43,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 719 transitions. [2022-02-21 04:21:43,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2022-02-21 04:21:43,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2022-02-21 04:21:43,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 719 transitions. [2022-02-21 04:21:43,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:43,629 INFO L681 BuchiCegarLoop]: Abstraction has 512 states and 719 transitions. [2022-02-21 04:21:43,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 719 transitions. [2022-02-21 04:21:43,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 407. [2022-02-21 04:21:43,638 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:43,638 INFO L82 GeneralOperation]: Start isEquivalent. First operand 512 states and 719 transitions. Second operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,639 INFO L74 IsIncluded]: Start isIncluded. First operand 512 states and 719 transitions. Second operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,640 INFO L87 Difference]: Start difference. First operand 512 states and 719 transitions. Second operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,650 INFO L93 Difference]: Finished difference Result 512 states and 719 transitions. [2022-02-21 04:21:43,650 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 719 transitions. [2022-02-21 04:21:43,651 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,651 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,651 INFO L74 IsIncluded]: Start isIncluded. First operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 512 states and 719 transitions. [2022-02-21 04:21:43,652 INFO L87 Difference]: Start difference. First operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 512 states and 719 transitions. [2022-02-21 04:21:43,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,662 INFO L93 Difference]: Finished difference Result 512 states and 719 transitions. [2022-02-21 04:21:43,662 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 719 transitions. [2022-02-21 04:21:43,663 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,663 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,663 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:43,663 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:43,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.425061425061425) internal successors, (580), 406 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 580 transitions. [2022-02-21 04:21:43,670 INFO L704 BuchiCegarLoop]: Abstraction has 407 states and 580 transitions. [2022-02-21 04:21:43,670 INFO L587 BuchiCegarLoop]: Abstraction has 407 states and 580 transitions. [2022-02-21 04:21:43,670 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:43,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 580 transitions. [2022-02-21 04:21:43,671 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-02-21 04:21:43,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:43,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:43,672 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:43,672 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:43,672 INFO L791 eck$LassoCheckResult]: Stem: 2443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 2366#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2367#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2381#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2382#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 2377#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2378#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2398#L259 assume !(0 == ~M_E~0); 2399#L259-2 assume !(0 == ~T1_E~0); 2420#L264-1 assume !(0 == ~E_M~0); 2421#L269-1 assume !(0 == ~E_1~0); 2414#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2415#L124 assume !(1 == ~m_pc~0); 2388#L124-2 is_master_triggered_~__retres1~0#1 := 0; 2389#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2313#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2314#L319 assume !(0 != activate_threads_~tmp~1#1); 2315#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2316#L143 assume !(1 == ~t1_pc~0); 2299#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2300#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2376#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2331#L327 assume !(0 != activate_threads_~tmp___0~0#1); 2332#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2353#L287 assume !(1 == ~M_E~0); 2397#L287-2 assume !(1 == ~T1_E~0); 2348#L292-1 assume !(1 == ~E_M~0); 2349#L297-1 assume !(1 == ~E_1~0); 2333#L302-1 assume { :end_inline_reset_delta_events } true; 2334#L428-2 [2022-02-21 04:21:43,672 INFO L793 eck$LassoCheckResult]: Loop: 2334#L428-2 assume !false; 2374#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2394#L234 assume !false; 2403#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2317#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2318#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2391#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2392#L215 assume !(0 != eval_~tmp~0#1); 2445#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2676#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2675#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2674#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2673#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2672#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2671#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2670#L124-9 assume !(1 == ~m_pc~0); 2425#L124-11 is_master_triggered_~__retres1~0#1 := 0; 2390#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2322#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2323#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2370#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2371#L143-9 assume !(1 == ~t1_pc~0); 2325#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 2326#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2306#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2307#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2428#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2444#L287-3 assume !(1 == ~M_E~0); 2395#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2396#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2406#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2287#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2288#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2327#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2328#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2345#L447 assume !(0 == start_simulation_~tmp~3#1); 2346#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2291#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2292#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2422#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 2423#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2424#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2430#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2387#L460 assume !(0 != start_simulation_~tmp___0~1#1); 2334#L428-2 [2022-02-21 04:21:43,683 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:43,683 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 1 times [2022-02-21 04:21:43,683 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:43,684 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115522766] [2022-02-21 04:21:43,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:43,684 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:43,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:43,691 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:43,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:43,716 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:43,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:43,716 INFO L85 PathProgramCache]: Analyzing trace with hash 1426265558, now seen corresponding path program 2 times [2022-02-21 04:21:43,717 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:43,717 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504084864] [2022-02-21 04:21:43,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:43,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:43,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 0: Hoare triple {3718#true} assume !false; {3718#true} is VALID [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 1: Hoare triple {3718#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3718#true} is VALID [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 2: Hoare triple {3718#true} assume !false; {3718#true} is VALID [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 3: Hoare triple {3718#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3718#true} is VALID [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 4: Hoare triple {3718#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {3718#true} is VALID [2022-02-21 04:21:43,745 INFO L290 TraceCheckUtils]: 5: Hoare triple {3718#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3718#true} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 6: Hoare triple {3718#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {3718#true} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 7: Hoare triple {3718#true} assume !(0 != eval_~tmp~0#1); {3718#true} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 8: Hoare triple {3718#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3718#true} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 9: Hoare triple {3718#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3718#true} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 10: Hoare triple {3718#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,746 INFO L290 TraceCheckUtils]: 11: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,747 INFO L290 TraceCheckUtils]: 12: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,747 INFO L290 TraceCheckUtils]: 13: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,747 INFO L290 TraceCheckUtils]: 14: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,748 INFO L290 TraceCheckUtils]: 15: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~m_pc~0); {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,748 INFO L290 TraceCheckUtils]: 16: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,748 INFO L290 TraceCheckUtils]: 17: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,748 INFO L290 TraceCheckUtils]: 18: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,749 INFO L290 TraceCheckUtils]: 19: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,749 INFO L290 TraceCheckUtils]: 20: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,749 INFO L290 TraceCheckUtils]: 21: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~t1_pc~0); {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,750 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,750 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,750 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,750 INFO L290 TraceCheckUtils]: 25: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,754 INFO L290 TraceCheckUtils]: 26: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3720#(= (+ (- 1) ~M_E~0) 0)} is VALID [2022-02-21 04:21:43,755 INFO L290 TraceCheckUtils]: 27: Hoare triple {3720#(= (+ (- 1) ~M_E~0) 0)} assume !(1 == ~M_E~0); {3719#false} is VALID [2022-02-21 04:21:43,756 INFO L290 TraceCheckUtils]: 28: Hoare triple {3719#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3719#false} is VALID [2022-02-21 04:21:43,757 INFO L290 TraceCheckUtils]: 29: Hoare triple {3719#false} assume 1 == ~E_M~0;~E_M~0 := 2; {3719#false} is VALID [2022-02-21 04:21:43,757 INFO L290 TraceCheckUtils]: 30: Hoare triple {3719#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3719#false} is VALID [2022-02-21 04:21:43,757 INFO L290 TraceCheckUtils]: 31: Hoare triple {3719#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3719#false} is VALID [2022-02-21 04:21:43,757 INFO L290 TraceCheckUtils]: 32: Hoare triple {3719#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {3719#false} is VALID [2022-02-21 04:21:43,757 INFO L290 TraceCheckUtils]: 33: Hoare triple {3719#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 34: Hoare triple {3719#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 35: Hoare triple {3719#false} assume !(0 == start_simulation_~tmp~3#1); {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 36: Hoare triple {3719#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 37: Hoare triple {3719#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 38: Hoare triple {3719#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 39: Hoare triple {3719#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 40: Hoare triple {3719#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 41: Hoare triple {3719#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 42: Hoare triple {3719#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L290 TraceCheckUtils]: 43: Hoare triple {3719#false} assume !(0 != start_simulation_~tmp___0~1#1); {3719#false} is VALID [2022-02-21 04:21:43,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:43,758 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:43,759 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504084864] [2022-02-21 04:21:43,759 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504084864] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:43,759 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:43,759 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:43,759 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503006627] [2022-02-21 04:21:43,759 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:43,759 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:43,759 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:43,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:43,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:43,760 INFO L87 Difference]: Start difference. First operand 407 states and 580 transitions. cyclomatic complexity: 175 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,903 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2022-02-21 04:21:43,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:43,903 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,940 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:43,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 496 states and 698 transitions. [2022-02-21 04:21:43,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2022-02-21 04:21:43,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 496 states to 496 states and 698 transitions. [2022-02-21 04:21:43,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 496 [2022-02-21 04:21:43,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 496 [2022-02-21 04:21:43,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 496 states and 698 transitions. [2022-02-21 04:21:43,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:43,968 INFO L681 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-02-21 04:21:43,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states and 698 transitions. [2022-02-21 04:21:43,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 496. [2022-02-21 04:21:43,981 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:43,982 INFO L82 GeneralOperation]: Start isEquivalent. First operand 496 states and 698 transitions. Second operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,984 INFO L74 IsIncluded]: Start isIncluded. First operand 496 states and 698 transitions. Second operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,985 INFO L87 Difference]: Start difference. First operand 496 states and 698 transitions. Second operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:43,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:43,995 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2022-02-21 04:21:43,995 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 698 transitions. [2022-02-21 04:21:43,996 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:43,996 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:43,997 INFO L74 IsIncluded]: Start isIncluded. First operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 496 states and 698 transitions. [2022-02-21 04:21:43,997 INFO L87 Difference]: Start difference. First operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 496 states and 698 transitions. [2022-02-21 04:21:44,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,007 INFO L93 Difference]: Finished difference Result 496 states and 698 transitions. [2022-02-21 04:21:44,007 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 698 transitions. [2022-02-21 04:21:44,007 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,007 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,008 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:44,008 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:44,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 496 states have (on average 1.407258064516129) internal successors, (698), 495 states have internal predecessors, (698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 698 transitions. [2022-02-21 04:21:44,017 INFO L704 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-02-21 04:21:44,017 INFO L587 BuchiCegarLoop]: Abstraction has 496 states and 698 transitions. [2022-02-21 04:21:44,017 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:44,017 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 698 transitions. [2022-02-21 04:21:44,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 448 [2022-02-21 04:21:44,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,022 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,022 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,022 INFO L791 eck$LassoCheckResult]: Stem: 4380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 4300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4301#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4316#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4317#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 4312#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4313#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4332#L259 assume 0 == ~M_E~0;~M_E~0 := 1; 4333#L259-2 assume !(0 == ~T1_E~0); 4356#L264-1 assume !(0 == ~E_M~0); 4357#L269-1 assume !(0 == ~E_1~0); 4350#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4351#L124 assume !(1 == ~m_pc~0); 4352#L124-2 is_master_triggered_~__retres1~0#1 := 0; 4455#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4453#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4451#L319 assume !(0 != activate_threads_~tmp~1#1); 4449#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4447#L143 assume !(1 == ~t1_pc~0); 4445#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4437#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4432#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4426#L327 assume !(0 != activate_threads_~tmp___0~0#1); 4287#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4288#L287 assume 1 == ~M_E~0;~M_E~0 := 2; 4331#L287-2 assume !(1 == ~T1_E~0); 4282#L292-1 assume !(1 == ~E_M~0); 4283#L297-1 assume !(1 == ~E_1~0); 4265#L302-1 assume { :end_inline_reset_delta_events } true; 4266#L428-2 [2022-02-21 04:21:44,024 INFO L793 eck$LassoCheckResult]: Loop: 4266#L428-2 assume !false; 4652#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4328#L234 assume !false; 4651#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4251#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4252#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4324#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4325#L215 assume !(0 != eval_~tmp~0#1); 4224#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4225#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4258#L259-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4378#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4362#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4245#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4246#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4236#L124-9 assume !(1 == ~m_pc~0); 4237#L124-11 is_master_triggered_~__retres1~0#1 := 0; 4326#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4256#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4257#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4304#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4305#L143-9 assume !(1 == ~t1_pc~0); 4259#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 4260#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4240#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4241#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4364#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4381#L287-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4329#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4330#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4342#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4222#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4223#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4261#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4262#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 4279#L447 assume !(0 == start_simulation_~tmp~3#1); 4280#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 4669#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 4666#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 4664#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 4661#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4659#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4657#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4655#L460 assume !(0 != start_simulation_~tmp___0~1#1); 4266#L428-2 [2022-02-21 04:21:44,024 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,024 INFO L85 PathProgramCache]: Analyzing trace with hash 175996037, now seen corresponding path program 1 times [2022-02-21 04:21:44,024 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,024 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2064073153] [2022-02-21 04:21:44,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,071 INFO L290 TraceCheckUtils]: 0: Hoare triple {5708#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,071 INFO L290 TraceCheckUtils]: 1: Hoare triple {5710#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,072 INFO L290 TraceCheckUtils]: 2: Hoare triple {5710#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,072 INFO L290 TraceCheckUtils]: 3: Hoare triple {5710#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,072 INFO L290 TraceCheckUtils]: 4: Hoare triple {5710#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,073 INFO L290 TraceCheckUtils]: 5: Hoare triple {5710#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,073 INFO L290 TraceCheckUtils]: 6: Hoare triple {5710#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5710#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 7: Hoare triple {5710#(= ~M_E~0 2)} assume 0 == ~M_E~0;~M_E~0 := 1; {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 8: Hoare triple {5709#false} assume !(0 == ~T1_E~0); {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 9: Hoare triple {5709#false} assume !(0 == ~E_M~0); {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 10: Hoare triple {5709#false} assume !(0 == ~E_1~0); {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 11: Hoare triple {5709#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 12: Hoare triple {5709#false} assume !(1 == ~m_pc~0); {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 13: Hoare triple {5709#false} is_master_triggered_~__retres1~0#1 := 0; {5709#false} is VALID [2022-02-21 04:21:44,074 INFO L290 TraceCheckUtils]: 14: Hoare triple {5709#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5709#false} is VALID [2022-02-21 04:21:44,075 INFO L290 TraceCheckUtils]: 15: Hoare triple {5709#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {5709#false} is VALID [2022-02-21 04:21:44,075 INFO L290 TraceCheckUtils]: 16: Hoare triple {5709#false} assume !(0 != activate_threads_~tmp~1#1); {5709#false} is VALID [2022-02-21 04:21:44,075 INFO L290 TraceCheckUtils]: 17: Hoare triple {5709#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5709#false} is VALID [2022-02-21 04:21:44,075 INFO L290 TraceCheckUtils]: 18: Hoare triple {5709#false} assume !(1 == ~t1_pc~0); {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 19: Hoare triple {5709#false} is_transmit1_triggered_~__retres1~1#1 := 0; {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 20: Hoare triple {5709#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 21: Hoare triple {5709#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 22: Hoare triple {5709#false} assume !(0 != activate_threads_~tmp___0~0#1); {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 23: Hoare triple {5709#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 24: Hoare triple {5709#false} assume 1 == ~M_E~0;~M_E~0 := 2; {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 25: Hoare triple {5709#false} assume !(1 == ~T1_E~0); {5709#false} is VALID [2022-02-21 04:21:44,076 INFO L290 TraceCheckUtils]: 26: Hoare triple {5709#false} assume !(1 == ~E_M~0); {5709#false} is VALID [2022-02-21 04:21:44,077 INFO L290 TraceCheckUtils]: 27: Hoare triple {5709#false} assume !(1 == ~E_1~0); {5709#false} is VALID [2022-02-21 04:21:44,077 INFO L290 TraceCheckUtils]: 28: Hoare triple {5709#false} assume { :end_inline_reset_delta_events } true; {5709#false} is VALID [2022-02-21 04:21:44,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,078 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,079 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2064073153] [2022-02-21 04:21:44,079 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2064073153] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,079 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,079 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:44,079 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659165824] [2022-02-21 04:21:44,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,079 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:44,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1280353836, now seen corresponding path program 1 times [2022-02-21 04:21:44,080 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,080 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464463171] [2022-02-21 04:21:44,080 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,124 INFO L290 TraceCheckUtils]: 0: Hoare triple {5711#true} assume !false; {5711#true} is VALID [2022-02-21 04:21:44,124 INFO L290 TraceCheckUtils]: 1: Hoare triple {5711#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5711#true} is VALID [2022-02-21 04:21:44,124 INFO L290 TraceCheckUtils]: 2: Hoare triple {5711#true} assume !false; {5711#true} is VALID [2022-02-21 04:21:44,124 INFO L290 TraceCheckUtils]: 3: Hoare triple {5711#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5711#true} is VALID [2022-02-21 04:21:44,125 INFO L290 TraceCheckUtils]: 4: Hoare triple {5711#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {5713#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:44,125 INFO L290 TraceCheckUtils]: 5: Hoare triple {5713#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5714#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:44,125 INFO L290 TraceCheckUtils]: 6: Hoare triple {5714#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {5715#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 7: Hoare triple {5715#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 8: Hoare triple {5712#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 9: Hoare triple {5712#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 10: Hoare triple {5712#false} assume 0 == ~M_E~0;~M_E~0 := 1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 11: Hoare triple {5712#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 12: Hoare triple {5712#false} assume 0 == ~E_M~0;~E_M~0 := 1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 13: Hoare triple {5712#false} assume 0 == ~E_1~0;~E_1~0 := 1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 14: Hoare triple {5712#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 15: Hoare triple {5712#false} assume !(1 == ~m_pc~0); {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 16: Hoare triple {5712#false} is_master_triggered_~__retres1~0#1 := 0; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 17: Hoare triple {5712#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 18: Hoare triple {5712#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 19: Hoare triple {5712#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 20: Hoare triple {5712#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 21: Hoare triple {5712#false} assume !(1 == ~t1_pc~0); {5712#false} is VALID [2022-02-21 04:21:44,126 INFO L290 TraceCheckUtils]: 22: Hoare triple {5712#false} is_transmit1_triggered_~__retres1~1#1 := 0; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 23: Hoare triple {5712#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 24: Hoare triple {5712#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 25: Hoare triple {5712#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 26: Hoare triple {5712#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 27: Hoare triple {5712#false} assume 1 == ~M_E~0;~M_E~0 := 2; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 28: Hoare triple {5712#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 29: Hoare triple {5712#false} assume 1 == ~E_M~0;~E_M~0 := 2; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 30: Hoare triple {5712#false} assume 1 == ~E_1~0;~E_1~0 := 2; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 31: Hoare triple {5712#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 32: Hoare triple {5712#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 33: Hoare triple {5712#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 34: Hoare triple {5712#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 35: Hoare triple {5712#false} assume !(0 == start_simulation_~tmp~3#1); {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 36: Hoare triple {5712#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 37: Hoare triple {5712#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 38: Hoare triple {5712#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {5712#false} is VALID [2022-02-21 04:21:44,127 INFO L290 TraceCheckUtils]: 39: Hoare triple {5712#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {5712#false} is VALID [2022-02-21 04:21:44,128 INFO L290 TraceCheckUtils]: 40: Hoare triple {5712#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5712#false} is VALID [2022-02-21 04:21:44,128 INFO L290 TraceCheckUtils]: 41: Hoare triple {5712#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5712#false} is VALID [2022-02-21 04:21:44,128 INFO L290 TraceCheckUtils]: 42: Hoare triple {5712#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {5712#false} is VALID [2022-02-21 04:21:44,128 INFO L290 TraceCheckUtils]: 43: Hoare triple {5712#false} assume !(0 != start_simulation_~tmp___0~1#1); {5712#false} is VALID [2022-02-21 04:21:44,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,128 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,128 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464463171] [2022-02-21 04:21:44,128 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464463171] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,128 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,128 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:44,128 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766375591] [2022-02-21 04:21:44,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,129 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:44,129 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:44,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:44,129 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:44,129 INFO L87 Difference]: Start difference. First operand 496 states and 698 transitions. cyclomatic complexity: 204 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,239 INFO L93 Difference]: Finished difference Result 407 states and 566 transitions. [2022-02-21 04:21:44,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:44,239 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 2 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,260 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:44,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-02-21 04:21:44,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 407 states to 407 states and 566 transitions. [2022-02-21 04:21:44,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 407 [2022-02-21 04:21:44,291 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 407 [2022-02-21 04:21:44,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:44,291 INFO L681 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-02-21 04:21:44,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 407. [2022-02-21 04:21:44,295 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:44,295 INFO L82 GeneralOperation]: Start isEquivalent. First operand 407 states and 566 transitions. Second operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,296 INFO L74 IsIncluded]: Start isIncluded. First operand 407 states and 566 transitions. Second operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,296 INFO L87 Difference]: Start difference. First operand 407 states and 566 transitions. Second operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,302 INFO L93 Difference]: Finished difference Result 407 states and 566 transitions. [2022-02-21 04:21:44,302 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,303 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,303 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,304 INFO L74 IsIncluded]: Start isIncluded. First operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 407 states and 566 transitions. [2022-02-21 04:21:44,304 INFO L87 Difference]: Start difference. First operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 407 states and 566 transitions. [2022-02-21 04:21:44,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,310 INFO L93 Difference]: Finished difference Result 407 states and 566 transitions. [2022-02-21 04:21:44,310 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,311 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,311 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,311 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:44,311 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:44,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 407 states have (on average 1.3906633906633907) internal successors, (566), 406 states have internal predecessors, (566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 566 transitions. [2022-02-21 04:21:44,317 INFO L704 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-02-21 04:21:44,317 INFO L587 BuchiCegarLoop]: Abstraction has 407 states and 566 transitions. [2022-02-21 04:21:44,317 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:44,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407 states and 566 transitions. [2022-02-21 04:21:44,318 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 376 [2022-02-21 04:21:44,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,319 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,319 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,319 INFO L791 eck$LassoCheckResult]: Stem: 6284#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 6206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6207#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6221#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6222#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 6217#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6218#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6241#L259 assume !(0 == ~M_E~0); 6242#L259-2 assume !(0 == ~T1_E~0); 6259#L264-1 assume !(0 == ~E_M~0); 6260#L269-1 assume !(0 == ~E_1~0); 6255#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6256#L124 assume !(1 == ~m_pc~0); 6231#L124-2 is_master_triggered_~__retres1~0#1 := 0; 6232#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6154#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6155#L319 assume !(0 != activate_threads_~tmp~1#1); 6156#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6157#L143 assume !(1 == ~t1_pc~0); 6140#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6141#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6216#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6168#L327 assume !(0 != activate_threads_~tmp___0~0#1); 6169#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6193#L287 assume !(1 == ~M_E~0); 6238#L287-2 assume !(1 == ~T1_E~0); 6188#L292-1 assume !(1 == ~E_M~0); 6189#L297-1 assume !(1 == ~E_1~0); 6170#L302-1 assume { :end_inline_reset_delta_events } true; 6171#L428-2 [2022-02-21 04:21:44,319 INFO L793 eck$LassoCheckResult]: Loop: 6171#L428-2 assume !false; 6214#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6237#L234 assume !false; 6243#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6158#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6159#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6233#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6234#L215 assume !(0 != eval_~tmp~0#1); 6287#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6529#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6528#L259-3 assume !(0 == ~M_E~0); 6527#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6526#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6524#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6523#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6522#L124-9 assume !(1 == ~m_pc~0); 6511#L124-11 is_master_triggered_~__retres1~0#1 := 0; 6235#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6163#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6164#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6210#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6211#L143-9 assume !(1 == ~t1_pc~0); 6228#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 6229#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6149#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6150#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6267#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6285#L287-3 assume !(1 == ~M_E~0); 6239#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6240#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6249#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6130#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6131#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6174#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6175#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 6185#L447 assume !(0 == start_simulation_~tmp~3#1); 6186#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6132#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6133#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6261#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 6262#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6263#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6270#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 6230#L460 assume !(0 != start_simulation_~tmp___0~1#1); 6171#L428-2 [2022-02-21 04:21:44,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,335 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 2 times [2022-02-21 04:21:44,335 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,335 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792001693] [2022-02-21 04:21:44,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:44,341 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:44,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:44,358 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:44,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,360 INFO L85 PathProgramCache]: Analyzing trace with hash -817717740, now seen corresponding path program 1 times [2022-02-21 04:21:44,360 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,361 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124333988] [2022-02-21 04:21:44,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,385 INFO L290 TraceCheckUtils]: 0: Hoare triple {7349#true} assume !false; {7349#true} is VALID [2022-02-21 04:21:44,385 INFO L290 TraceCheckUtils]: 1: Hoare triple {7349#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7349#true} is VALID [2022-02-21 04:21:44,385 INFO L290 TraceCheckUtils]: 2: Hoare triple {7349#true} assume !false; {7349#true} is VALID [2022-02-21 04:21:44,385 INFO L290 TraceCheckUtils]: 3: Hoare triple {7349#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7349#true} is VALID [2022-02-21 04:21:44,386 INFO L290 TraceCheckUtils]: 4: Hoare triple {7349#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7351#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} is VALID [2022-02-21 04:21:44,386 INFO L290 TraceCheckUtils]: 5: Hoare triple {7351#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~2#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7352#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:44,386 INFO L290 TraceCheckUtils]: 6: Hoare triple {7352#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {7353#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 7: Hoare triple {7353#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 8: Hoare triple {7350#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 9: Hoare triple {7350#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 10: Hoare triple {7350#false} assume !(0 == ~M_E~0); {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 11: Hoare triple {7350#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 12: Hoare triple {7350#false} assume 0 == ~E_M~0;~E_M~0 := 1; {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 13: Hoare triple {7350#false} assume 0 == ~E_1~0;~E_1~0 := 1; {7350#false} is VALID [2022-02-21 04:21:44,387 INFO L290 TraceCheckUtils]: 14: Hoare triple {7350#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 15: Hoare triple {7350#false} assume !(1 == ~m_pc~0); {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 16: Hoare triple {7350#false} is_master_triggered_~__retres1~0#1 := 0; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 17: Hoare triple {7350#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 18: Hoare triple {7350#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 19: Hoare triple {7350#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 20: Hoare triple {7350#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 21: Hoare triple {7350#false} assume !(1 == ~t1_pc~0); {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 22: Hoare triple {7350#false} is_transmit1_triggered_~__retres1~1#1 := 0; {7350#false} is VALID [2022-02-21 04:21:44,388 INFO L290 TraceCheckUtils]: 23: Hoare triple {7350#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 24: Hoare triple {7350#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 25: Hoare triple {7350#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 26: Hoare triple {7350#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 27: Hoare triple {7350#false} assume !(1 == ~M_E~0); {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 28: Hoare triple {7350#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 29: Hoare triple {7350#false} assume 1 == ~E_M~0;~E_M~0 := 2; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 30: Hoare triple {7350#false} assume 1 == ~E_1~0;~E_1~0 := 2; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 31: Hoare triple {7350#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7350#false} is VALID [2022-02-21 04:21:44,389 INFO L290 TraceCheckUtils]: 32: Hoare triple {7350#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 33: Hoare triple {7350#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 34: Hoare triple {7350#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 35: Hoare triple {7350#false} assume !(0 == start_simulation_~tmp~3#1); {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 36: Hoare triple {7350#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 37: Hoare triple {7350#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 38: Hoare triple {7350#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 39: Hoare triple {7350#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {7350#false} is VALID [2022-02-21 04:21:44,390 INFO L290 TraceCheckUtils]: 40: Hoare triple {7350#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {7350#false} is VALID [2022-02-21 04:21:44,391 INFO L290 TraceCheckUtils]: 41: Hoare triple {7350#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7350#false} is VALID [2022-02-21 04:21:44,391 INFO L290 TraceCheckUtils]: 42: Hoare triple {7350#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {7350#false} is VALID [2022-02-21 04:21:44,391 INFO L290 TraceCheckUtils]: 43: Hoare triple {7350#false} assume !(0 != start_simulation_~tmp___0~1#1); {7350#false} is VALID [2022-02-21 04:21:44,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,395 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,395 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124333988] [2022-02-21 04:21:44,395 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124333988] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,395 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,396 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:44,396 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318836461] [2022-02-21 04:21:44,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,396 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:44,396 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:44,397 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:44,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:44,397 INFO L87 Difference]: Start difference. First operand 407 states and 566 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,773 INFO L93 Difference]: Finished difference Result 693 states and 942 transitions. [2022-02-21 04:21:44,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:21:44,773 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,796 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:44,797 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 942 transitions. [2022-02-21 04:21:44,813 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 660 [2022-02-21 04:21:44,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 942 transitions. [2022-02-21 04:21:44,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2022-02-21 04:21:44,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2022-02-21 04:21:44,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 942 transitions. [2022-02-21 04:21:44,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:44,828 INFO L681 BuchiCegarLoop]: Abstraction has 693 states and 942 transitions. [2022-02-21 04:21:44,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 942 transitions. [2022-02-21 04:21:44,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 419. [2022-02-21 04:21:44,833 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:44,834 INFO L82 GeneralOperation]: Start isEquivalent. First operand 693 states and 942 transitions. Second operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,834 INFO L74 IsIncluded]: Start isIncluded. First operand 693 states and 942 transitions. Second operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,835 INFO L87 Difference]: Start difference. First operand 693 states and 942 transitions. Second operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,848 INFO L93 Difference]: Finished difference Result 693 states and 942 transitions. [2022-02-21 04:21:44,848 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 942 transitions. [2022-02-21 04:21:44,849 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,849 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,849 INFO L74 IsIncluded]: Start isIncluded. First operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 693 states and 942 transitions. [2022-02-21 04:21:44,850 INFO L87 Difference]: Start difference. First operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 693 states and 942 transitions. [2022-02-21 04:21:44,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,883 INFO L93 Difference]: Finished difference Result 693 states and 942 transitions. [2022-02-21 04:21:44,883 INFO L276 IsEmpty]: Start isEmpty. Operand 693 states and 942 transitions. [2022-02-21 04:21:44,884 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,884 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,884 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:44,884 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:44,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 419 states have (on average 1.3794749403341289) internal successors, (578), 418 states have internal predecessors, (578), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 578 transitions. [2022-02-21 04:21:44,891 INFO L704 BuchiCegarLoop]: Abstraction has 419 states and 578 transitions. [2022-02-21 04:21:44,891 INFO L587 BuchiCegarLoop]: Abstraction has 419 states and 578 transitions. [2022-02-21 04:21:44,891 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:44,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 578 transitions. [2022-02-21 04:21:44,892 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2022-02-21 04:21:44,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,893 INFO L791 eck$LassoCheckResult]: Stem: 8224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 8138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8139#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8154#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8155#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 8150#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8151#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8174#L259 assume !(0 == ~M_E~0); 8175#L259-2 assume !(0 == ~T1_E~0); 8195#L264-1 assume !(0 == ~E_M~0); 8196#L269-1 assume !(0 == ~E_1~0); 8189#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8190#L124 assume !(1 == ~m_pc~0); 8162#L124-2 is_master_triggered_~__retres1~0#1 := 0; 8163#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8085#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8086#L319 assume !(0 != activate_threads_~tmp~1#1); 8087#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8088#L143 assume !(1 == ~t1_pc~0); 8072#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8073#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8149#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8099#L327 assume !(0 != activate_threads_~tmp___0~0#1); 8100#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8125#L287 assume !(1 == ~M_E~0); 8170#L287-2 assume !(1 == ~T1_E~0); 8120#L292-1 assume !(1 == ~E_M~0); 8121#L297-1 assume !(1 == ~E_1~0); 8101#L302-1 assume { :end_inline_reset_delta_events } true; 8102#L428-2 [2022-02-21 04:21:44,894 INFO L793 eck$LassoCheckResult]: Loop: 8102#L428-2 assume !false; 8147#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8169#L234 assume !false; 8176#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8089#L188 assume !(0 == ~m_st~0); 8091#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 8202#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8412#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8410#L215 assume !(0 != eval_~tmp~0#1); 8060#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8061#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8096#L259-3 assume !(0 == ~M_E~0); 8223#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8205#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8206#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8282#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8280#L124-9 assume !(1 == ~m_pc~0); 8281#L124-11 is_master_triggered_~__retres1~0#1 := 0; 8257#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8258#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8244#L319-9 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8245#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8159#L143-9 assume !(1 == ~t1_pc~0); 8097#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 8098#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8160#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 8207#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8208#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8225#L287-3 assume !(1 == ~M_E~0); 8171#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8172#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8182#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8062#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8063#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8105#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8106#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 8117#L447 assume !(0 == start_simulation_~tmp~3#1); 8118#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 8064#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 8065#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 8419#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 8418#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8413#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8210#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 8161#L460 assume !(0 != start_simulation_~tmp___0~1#1); 8102#L428-2 [2022-02-21 04:21:44,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,894 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 3 times [2022-02-21 04:21:44,894 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,898 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [526019537] [2022-02-21 04:21:44,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:44,913 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:44,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:44,935 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:44,936 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,936 INFO L85 PathProgramCache]: Analyzing trace with hash 56440981, now seen corresponding path program 1 times [2022-02-21 04:21:44,936 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,936 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453773672] [2022-02-21 04:21:44,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,013 INFO L290 TraceCheckUtils]: 0: Hoare triple {9865#true} assume !false; {9865#true} is VALID [2022-02-21 04:21:45,013 INFO L290 TraceCheckUtils]: 1: Hoare triple {9865#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {9865#true} is VALID [2022-02-21 04:21:45,014 INFO L290 TraceCheckUtils]: 2: Hoare triple {9865#true} assume !false; {9865#true} is VALID [2022-02-21 04:21:45,014 INFO L290 TraceCheckUtils]: 3: Hoare triple {9865#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {9865#true} is VALID [2022-02-21 04:21:45,014 INFO L290 TraceCheckUtils]: 4: Hoare triple {9865#true} assume !(0 == ~m_st~0); {9865#true} is VALID [2022-02-21 04:21:45,014 INFO L290 TraceCheckUtils]: 5: Hoare triple {9865#true} assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {9865#true} is VALID [2022-02-21 04:21:45,015 INFO L290 TraceCheckUtils]: 6: Hoare triple {9865#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {9865#true} is VALID [2022-02-21 04:21:45,015 INFO L290 TraceCheckUtils]: 7: Hoare triple {9865#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {9865#true} is VALID [2022-02-21 04:21:45,017 INFO L290 TraceCheckUtils]: 8: Hoare triple {9865#true} assume !(0 != eval_~tmp~0#1); {9865#true} is VALID [2022-02-21 04:21:45,017 INFO L290 TraceCheckUtils]: 9: Hoare triple {9865#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {9865#true} is VALID [2022-02-21 04:21:45,017 INFO L290 TraceCheckUtils]: 10: Hoare triple {9865#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {9865#true} is VALID [2022-02-21 04:21:45,017 INFO L290 TraceCheckUtils]: 11: Hoare triple {9865#true} assume !(0 == ~M_E~0); {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 12: Hoare triple {9865#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 13: Hoare triple {9865#true} assume 0 == ~E_M~0;~E_M~0 := 1; {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 14: Hoare triple {9865#true} assume 0 == ~E_1~0;~E_1~0 := 1; {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 15: Hoare triple {9865#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 16: Hoare triple {9865#true} assume !(1 == ~m_pc~0); {9865#true} is VALID [2022-02-21 04:21:45,018 INFO L290 TraceCheckUtils]: 17: Hoare triple {9865#true} is_master_triggered_~__retres1~0#1 := 0; {9867#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:45,019 INFO L290 TraceCheckUtils]: 18: Hoare triple {9867#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {9868#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:45,019 INFO L290 TraceCheckUtils]: 19: Hoare triple {9868#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {9869#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 20: Hoare triple {9869#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 21: Hoare triple {9866#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 22: Hoare triple {9866#false} assume !(1 == ~t1_pc~0); {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 23: Hoare triple {9866#false} is_transmit1_triggered_~__retres1~1#1 := 0; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 24: Hoare triple {9866#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 25: Hoare triple {9866#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 26: Hoare triple {9866#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 27: Hoare triple {9866#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 28: Hoare triple {9866#false} assume !(1 == ~M_E~0); {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 29: Hoare triple {9866#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 30: Hoare triple {9866#false} assume 1 == ~E_M~0;~E_M~0 := 2; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 31: Hoare triple {9866#false} assume 1 == ~E_1~0;~E_1~0 := 2; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 32: Hoare triple {9866#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {9866#false} is VALID [2022-02-21 04:21:45,020 INFO L290 TraceCheckUtils]: 33: Hoare triple {9866#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 34: Hoare triple {9866#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 35: Hoare triple {9866#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 36: Hoare triple {9866#false} assume !(0 == start_simulation_~tmp~3#1); {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 37: Hoare triple {9866#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 38: Hoare triple {9866#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 39: Hoare triple {9866#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 40: Hoare triple {9866#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 41: Hoare triple {9866#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 42: Hoare triple {9866#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 43: Hoare triple {9866#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {9866#false} is VALID [2022-02-21 04:21:45,021 INFO L290 TraceCheckUtils]: 44: Hoare triple {9866#false} assume !(0 != start_simulation_~tmp___0~1#1); {9866#false} is VALID [2022-02-21 04:21:45,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,022 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,022 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [453773672] [2022-02-21 04:21:45,022 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [453773672] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,022 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,022 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:45,022 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [699410520] [2022-02-21 04:21:45,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,023 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:45,023 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:45,023 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:45,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:45,024 INFO L87 Difference]: Start difference. First operand 419 states and 578 transitions. cyclomatic complexity: 161 Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,597 INFO L93 Difference]: Finished difference Result 792 states and 1077 transitions. [2022-02-21 04:21:45,597 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:45,597 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,621 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:45,621 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 792 states and 1077 transitions. [2022-02-21 04:21:45,640 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 761 [2022-02-21 04:21:45,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 792 states to 792 states and 1077 transitions. [2022-02-21 04:21:45,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 792 [2022-02-21 04:21:45,663 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 792 [2022-02-21 04:21:45,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 792 states and 1077 transitions. [2022-02-21 04:21:45,664 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:45,664 INFO L681 BuchiCegarLoop]: Abstraction has 792 states and 1077 transitions. [2022-02-21 04:21:45,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 792 states and 1077 transitions. [2022-02-21 04:21:45,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 792 to 440. [2022-02-21 04:21:45,669 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:45,669 INFO L82 GeneralOperation]: Start isEquivalent. First operand 792 states and 1077 transitions. Second operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,670 INFO L74 IsIncluded]: Start isIncluded. First operand 792 states and 1077 transitions. Second operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,671 INFO L87 Difference]: Start difference. First operand 792 states and 1077 transitions. Second operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,686 INFO L93 Difference]: Finished difference Result 792 states and 1077 transitions. [2022-02-21 04:21:45,687 INFO L276 IsEmpty]: Start isEmpty. Operand 792 states and 1077 transitions. [2022-02-21 04:21:45,687 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,687 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,688 INFO L74 IsIncluded]: Start isIncluded. First operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 792 states and 1077 transitions. [2022-02-21 04:21:45,689 INFO L87 Difference]: Start difference. First operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 792 states and 1077 transitions. [2022-02-21 04:21:45,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,705 INFO L93 Difference]: Finished difference Result 792 states and 1077 transitions. [2022-02-21 04:21:45,705 INFO L276 IsEmpty]: Start isEmpty. Operand 792 states and 1077 transitions. [2022-02-21 04:21:45,706 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,706 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,706 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:45,706 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:45,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 440 states, 440 states have (on average 1.3477272727272727) internal successors, (593), 439 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 593 transitions. [2022-02-21 04:21:45,713 INFO L704 BuchiCegarLoop]: Abstraction has 440 states and 593 transitions. [2022-02-21 04:21:45,713 INFO L587 BuchiCegarLoop]: Abstraction has 440 states and 593 transitions. [2022-02-21 04:21:45,713 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:45,713 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 440 states and 593 transitions. [2022-02-21 04:21:45,714 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 409 [2022-02-21 04:21:45,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,715 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,715 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,715 INFO L791 eck$LassoCheckResult]: Stem: 10838#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 10756#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10757#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10773#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10774#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 10767#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10768#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10793#L259 assume !(0 == ~M_E~0); 10794#L259-2 assume !(0 == ~T1_E~0); 10812#L264-1 assume !(0 == ~E_M~0); 10813#L269-1 assume !(0 == ~E_1~0); 10806#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10807#L124 assume !(1 == ~m_pc~0); 10782#L124-2 is_master_triggered_~__retres1~0#1 := 0; 10783#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10698#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10699#L319 assume !(0 != activate_threads_~tmp~1#1); 10700#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10701#L143 assume !(1 == ~t1_pc~0); 10684#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10685#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10766#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10714#L327 assume !(0 != activate_threads_~tmp___0~0#1); 10715#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10740#L287 assume !(1 == ~M_E~0); 10791#L287-2 assume !(1 == ~T1_E~0); 10734#L292-1 assume !(1 == ~E_M~0); 10735#L297-1 assume !(1 == ~E_1~0); 10716#L302-1 assume { :end_inline_reset_delta_events } true; 10717#L428-2 [2022-02-21 04:21:45,715 INFO L793 eck$LassoCheckResult]: Loop: 10717#L428-2 assume !false; 10886#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10887#L234 assume !false; 10882#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10883#L188 assume !(0 == ~m_st~0); 10876#L192 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10878#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10872#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10873#L215 assume !(0 != eval_~tmp~0#1); 10867#L249 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10868#L163-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10863#L259-3 assume !(0 == ~M_E~0); 10864#L259-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10859#L264-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10860#L269-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10779#L274-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10780#L124-9 assume !(1 == ~m_pc~0); 11009#L124-11 is_master_triggered_~__retres1~0#1 := 0; 11006#L135-3 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11003#L136-3 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11000#L319-9 assume !(0 != activate_threads_~tmp~1#1); 10997#L319-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10994#L143-9 assume !(1 == ~t1_pc~0); 10991#L143-11 is_transmit1_triggered_~__retres1~1#1 := 0; 10989#L154-3 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10987#L155-3 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10985#L327-9 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10983#L327-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10967#L287-3 assume !(1 == ~M_E~0); 10968#L287-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10959#L292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10960#L297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10951#L302-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10952#L188-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10942#L200-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10943#L201-1 start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 10935#L447 assume !(0 == start_simulation_~tmp~3#1); 10934#L447-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10930#L188-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10929#L200-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10924#L201-2 stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; 10925#L402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10920#L409 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10921#L410 start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 10917#L460 assume !(0 != start_simulation_~tmp___0~1#1); 10717#L428-2 [2022-02-21 04:21:45,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,718 INFO L85 PathProgramCache]: Analyzing trace with hash 396697797, now seen corresponding path program 4 times [2022-02-21 04:21:45,718 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,718 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457247627] [2022-02-21 04:21:45,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,723 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:45,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:45,728 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:45,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,728 INFO L85 PathProgramCache]: Analyzing trace with hash 196989591, now seen corresponding path program 1 times [2022-02-21 04:21:45,728 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,728 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490504947] [2022-02-21 04:21:45,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,746 INFO L290 TraceCheckUtils]: 0: Hoare triple {12696#true} assume !false; {12696#true} is VALID [2022-02-21 04:21:45,746 INFO L290 TraceCheckUtils]: 1: Hoare triple {12696#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {12696#true} is VALID [2022-02-21 04:21:45,746 INFO L290 TraceCheckUtils]: 2: Hoare triple {12696#true} assume !false; {12696#true} is VALID [2022-02-21 04:21:45,746 INFO L290 TraceCheckUtils]: 3: Hoare triple {12696#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {12696#true} is VALID [2022-02-21 04:21:45,746 INFO L290 TraceCheckUtils]: 4: Hoare triple {12696#true} assume !(0 == ~m_st~0); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,747 INFO L290 TraceCheckUtils]: 5: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,747 INFO L290 TraceCheckUtils]: 6: Hoare triple {12698#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,747 INFO L290 TraceCheckUtils]: 7: Hoare triple {12698#(not (= ~m_st~0 0))} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,747 INFO L290 TraceCheckUtils]: 8: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,747 INFO L290 TraceCheckUtils]: 9: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,748 INFO L290 TraceCheckUtils]: 10: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,748 INFO L290 TraceCheckUtils]: 11: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(0 == ~M_E~0); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,748 INFO L290 TraceCheckUtils]: 12: Hoare triple {12698#(not (= ~m_st~0 0))} assume 0 == ~T1_E~0;~T1_E~0 := 1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,748 INFO L290 TraceCheckUtils]: 13: Hoare triple {12698#(not (= ~m_st~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,749 INFO L290 TraceCheckUtils]: 14: Hoare triple {12698#(not (= ~m_st~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,749 INFO L290 TraceCheckUtils]: 15: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,749 INFO L290 TraceCheckUtils]: 16: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,749 INFO L290 TraceCheckUtils]: 17: Hoare triple {12698#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,750 INFO L290 TraceCheckUtils]: 18: Hoare triple {12698#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,750 INFO L290 TraceCheckUtils]: 19: Hoare triple {12698#(not (= ~m_st~0 0))} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,750 INFO L290 TraceCheckUtils]: 20: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,750 INFO L290 TraceCheckUtils]: 21: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,750 INFO L290 TraceCheckUtils]: 22: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,751 INFO L290 TraceCheckUtils]: 23: Hoare triple {12698#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,751 INFO L290 TraceCheckUtils]: 24: Hoare triple {12698#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,751 INFO L290 TraceCheckUtils]: 25: Hoare triple {12698#(not (= ~m_st~0 0))} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,751 INFO L290 TraceCheckUtils]: 26: Hoare triple {12698#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,752 INFO L290 TraceCheckUtils]: 27: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,752 INFO L290 TraceCheckUtils]: 28: Hoare triple {12698#(not (= ~m_st~0 0))} assume !(1 == ~M_E~0); {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,752 INFO L290 TraceCheckUtils]: 29: Hoare triple {12698#(not (= ~m_st~0 0))} assume 1 == ~T1_E~0;~T1_E~0 := 2; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,752 INFO L290 TraceCheckUtils]: 30: Hoare triple {12698#(not (= ~m_st~0 0))} assume 1 == ~E_M~0;~E_M~0 := 2; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,752 INFO L290 TraceCheckUtils]: 31: Hoare triple {12698#(not (= ~m_st~0 0))} assume 1 == ~E_1~0;~E_1~0 := 2; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 32: Hoare triple {12698#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {12698#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 33: Hoare triple {12698#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {12697#false} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 34: Hoare triple {12697#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {12697#false} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 35: Hoare triple {12697#false} start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; {12697#false} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 36: Hoare triple {12697#false} assume !(0 == start_simulation_~tmp~3#1); {12697#false} is VALID [2022-02-21 04:21:45,753 INFO L290 TraceCheckUtils]: 37: Hoare triple {12697#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 38: Hoare triple {12697#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 39: Hoare triple {12697#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 40: Hoare triple {12697#false} stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 41: Hoare triple {12697#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 42: Hoare triple {12697#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 43: Hoare triple {12697#false} start_simulation_#t~ret12#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L290 TraceCheckUtils]: 44: Hoare triple {12697#false} assume !(0 != start_simulation_~tmp___0~1#1); {12697#false} is VALID [2022-02-21 04:21:45,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,754 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,754 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490504947] [2022-02-21 04:21:45,754 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490504947] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,754 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,755 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:45,756 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280391855] [2022-02-21 04:21:45,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,756 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:45,756 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:45,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:45,757 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:45,757 INFO L87 Difference]: Start difference. First operand 440 states and 593 transitions. cyclomatic complexity: 155 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,901 INFO L93 Difference]: Finished difference Result 641 states and 847 transitions. [2022-02-21 04:21:45,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:45,902 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,926 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:45,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 641 states and 847 transitions. [2022-02-21 04:21:45,941 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 606 [2022-02-21 04:21:45,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 641 states to 641 states and 847 transitions. [2022-02-21 04:21:45,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 641 [2022-02-21 04:21:45,954 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 641 [2022-02-21 04:21:45,954 INFO L73 IsDeterministic]: Start isDeterministic. Operand 641 states and 847 transitions. [2022-02-21 04:21:45,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:45,955 INFO L681 BuchiCegarLoop]: Abstraction has 641 states and 847 transitions. [2022-02-21 04:21:45,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 641 states and 847 transitions. [2022-02-21 04:21:45,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 641 to 624. [2022-02-21 04:21:45,960 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:45,961 INFO L82 GeneralOperation]: Start isEquivalent. First operand 641 states and 847 transitions. Second operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,962 INFO L74 IsIncluded]: Start isIncluded. First operand 641 states and 847 transitions. Second operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,963 INFO L87 Difference]: Start difference. First operand 641 states and 847 transitions. Second operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,974 INFO L93 Difference]: Finished difference Result 641 states and 847 transitions. [2022-02-21 04:21:45,974 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 847 transitions. [2022-02-21 04:21:45,975 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,975 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,975 INFO L74 IsIncluded]: Start isIncluded. First operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 641 states and 847 transitions. [2022-02-21 04:21:45,976 INFO L87 Difference]: Start difference. First operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 641 states and 847 transitions. [2022-02-21 04:21:45,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,987 INFO L93 Difference]: Finished difference Result 641 states and 847 transitions. [2022-02-21 04:21:45,987 INFO L276 IsEmpty]: Start isEmpty. Operand 641 states and 847 transitions. [2022-02-21 04:21:45,988 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,988 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,988 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:45,988 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:45,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 624 states have (on average 1.3237179487179487) internal successors, (826), 623 states have internal predecessors, (826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 826 transitions. [2022-02-21 04:21:46,000 INFO L704 BuchiCegarLoop]: Abstraction has 624 states and 826 transitions. [2022-02-21 04:21:46,000 INFO L587 BuchiCegarLoop]: Abstraction has 624 states and 826 transitions. [2022-02-21 04:21:46,000 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:46,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 624 states and 826 transitions. [2022-02-21 04:21:46,002 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 589 [2022-02-21 04:21:46,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:46,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:46,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,002 INFO L791 eck$LassoCheckResult]: Stem: 13516#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 13422#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 13423#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13438#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13439#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 13434#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13435#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13457#L259 assume !(0 == ~M_E~0); 13458#L259-2 assume !(0 == ~T1_E~0); 13482#L264-1 assume !(0 == ~E_M~0); 13483#L269-1 assume !(0 == ~E_1~0); 13476#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13477#L124 assume !(1 == ~m_pc~0); 13445#L124-2 is_master_triggered_~__retres1~0#1 := 0; 13446#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13368#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13369#L319 assume !(0 != activate_threads_~tmp~1#1); 13370#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13371#L143 assume !(1 == ~t1_pc~0); 13355#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13356#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13433#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13381#L327 assume !(0 != activate_threads_~tmp___0~0#1); 13382#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13408#L287 assume !(1 == ~M_E~0); 13452#L287-2 assume !(1 == ~T1_E~0); 13403#L292-1 assume !(1 == ~E_M~0); 13404#L297-1 assume !(1 == ~E_1~0); 13383#L302-1 assume { :end_inline_reset_delta_events } true; 13384#L428-2 assume !false; 13909#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13723#L234 [2022-02-21 04:21:46,002 INFO L793 eck$LassoCheckResult]: Loop: 13723#L234 assume !false; 13908#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13907#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13905#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13893#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13520#L215 assume 0 != eval_~tmp~0#1; 13521#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 13455#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 13456#L220 assume !(0 == ~t1_st~0); 13723#L234 [2022-02-21 04:21:46,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,003 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 1 times [2022-02-21 04:21:46,004 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,004 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123697088] [2022-02-21 04:21:46,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,010 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,028 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:46,029 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,029 INFO L85 PathProgramCache]: Analyzing trace with hash 2078330545, now seen corresponding path program 1 times [2022-02-21 04:21:46,029 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,029 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12511358] [2022-02-21 04:21:46,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,034 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,041 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:46,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1188516331, now seen corresponding path program 1 times [2022-02-21 04:21:46,041 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,042 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286979276] [2022-02-21 04:21:46,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 0: Hoare triple {15253#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {15253#true} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 1: Hoare triple {15253#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {15253#true} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 2: Hoare triple {15253#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {15253#true} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 3: Hoare triple {15253#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {15253#true} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 4: Hoare triple {15253#true} assume 1 == ~m_i~0;~m_st~0 := 0; {15253#true} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 5: Hoare triple {15253#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,076 INFO L290 TraceCheckUtils]: 6: Hoare triple {15255#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,077 INFO L290 TraceCheckUtils]: 7: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,077 INFO L290 TraceCheckUtils]: 8: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,077 INFO L290 TraceCheckUtils]: 9: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 == ~E_M~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,077 INFO L290 TraceCheckUtils]: 10: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,078 INFO L290 TraceCheckUtils]: 11: Hoare triple {15255#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,078 INFO L290 TraceCheckUtils]: 12: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,078 INFO L290 TraceCheckUtils]: 13: Hoare triple {15255#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,078 INFO L290 TraceCheckUtils]: 14: Hoare triple {15255#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,078 INFO L290 TraceCheckUtils]: 15: Hoare triple {15255#(= ~t1_st~0 0)} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,079 INFO L290 TraceCheckUtils]: 16: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,079 INFO L290 TraceCheckUtils]: 17: Hoare triple {15255#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,079 INFO L290 TraceCheckUtils]: 18: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,079 INFO L290 TraceCheckUtils]: 19: Hoare triple {15255#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,080 INFO L290 TraceCheckUtils]: 20: Hoare triple {15255#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,080 INFO L290 TraceCheckUtils]: 21: Hoare triple {15255#(= ~t1_st~0 0)} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,080 INFO L290 TraceCheckUtils]: 22: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,080 INFO L290 TraceCheckUtils]: 23: Hoare triple {15255#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,081 INFO L290 TraceCheckUtils]: 24: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,081 INFO L290 TraceCheckUtils]: 25: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,081 INFO L290 TraceCheckUtils]: 26: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~E_M~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,081 INFO L290 TraceCheckUtils]: 27: Hoare triple {15255#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,081 INFO L290 TraceCheckUtils]: 28: Hoare triple {15255#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,082 INFO L290 TraceCheckUtils]: 29: Hoare triple {15255#(= ~t1_st~0 0)} assume !false; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,082 INFO L290 TraceCheckUtils]: 30: Hoare triple {15255#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,083 INFO L290 TraceCheckUtils]: 31: Hoare triple {15255#(= ~t1_st~0 0)} assume !false; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,084 INFO L290 TraceCheckUtils]: 32: Hoare triple {15255#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,084 INFO L290 TraceCheckUtils]: 33: Hoare triple {15255#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,085 INFO L290 TraceCheckUtils]: 34: Hoare triple {15255#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,086 INFO L290 TraceCheckUtils]: 35: Hoare triple {15255#(= ~t1_st~0 0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,088 INFO L290 TraceCheckUtils]: 36: Hoare triple {15255#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,088 INFO L290 TraceCheckUtils]: 37: Hoare triple {15255#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,088 INFO L290 TraceCheckUtils]: 38: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {15255#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:46,088 INFO L290 TraceCheckUtils]: 39: Hoare triple {15255#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {15254#false} is VALID [2022-02-21 04:21:46,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,089 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,089 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [286979276] [2022-02-21 04:21:46,089 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [286979276] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,089 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,089 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:46,089 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532316453] [2022-02-21 04:21:46,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,146 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:46,147 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:46,147 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:46,147 INFO L87 Difference]: Start difference. First operand 624 states and 826 transitions. cyclomatic complexity: 206 Second operand has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,339 INFO L93 Difference]: Finished difference Result 1035 states and 1346 transitions. [2022-02-21 04:21:46,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:46,339 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 20.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,360 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,361 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,387 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 973 [2022-02-21 04:21:46,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1035 states to 1035 states and 1346 transitions. [2022-02-21 04:21:46,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1035 [2022-02-21 04:21:46,413 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1035 [2022-02-21 04:21:46,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:46,414 INFO L681 BuchiCegarLoop]: Abstraction has 1035 states and 1346 transitions. [2022-02-21 04:21:46,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1035 to 1019. [2022-02-21 04:21:46,424 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:46,425 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1035 states and 1346 transitions. Second operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,426 INFO L74 IsIncluded]: Start isIncluded. First operand 1035 states and 1346 transitions. Second operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,428 INFO L87 Difference]: Start difference. First operand 1035 states and 1346 transitions. Second operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,454 INFO L93 Difference]: Finished difference Result 1035 states and 1346 transitions. [2022-02-21 04:21:46,454 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,455 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,455 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,457 INFO L74 IsIncluded]: Start isIncluded. First operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,459 INFO L87 Difference]: Start difference. First operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,484 INFO L93 Difference]: Finished difference Result 1035 states and 1346 transitions. [2022-02-21 04:21:46,484 INFO L276 IsEmpty]: Start isEmpty. Operand 1035 states and 1346 transitions. [2022-02-21 04:21:46,486 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,486 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,486 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:46,486 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:46,487 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1019 states, 1019 states have (on average 1.3052011776251227) internal successors, (1330), 1018 states have internal predecessors, (1330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1019 states to 1019 states and 1330 transitions. [2022-02-21 04:21:46,511 INFO L704 BuchiCegarLoop]: Abstraction has 1019 states and 1330 transitions. [2022-02-21 04:21:46,511 INFO L587 BuchiCegarLoop]: Abstraction has 1019 states and 1330 transitions. [2022-02-21 04:21:46,511 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:46,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1019 states and 1330 transitions. [2022-02-21 04:21:46,514 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 957 [2022-02-21 04:21:46,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:46,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:46,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,515 INFO L791 eck$LassoCheckResult]: Stem: 16475#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 16375#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 16376#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16395#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16396#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 16390#L170-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 16391#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17200#L259 assume !(0 == ~M_E~0); 17199#L259-2 assume !(0 == ~T1_E~0); 17198#L264-1 assume !(0 == ~E_M~0); 17197#L269-1 assume !(0 == ~E_1~0); 17196#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17195#L124 assume !(1 == ~m_pc~0); 17194#L124-2 is_master_triggered_~__retres1~0#1 := 0; 17193#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17192#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 17191#L319 assume !(0 != activate_threads_~tmp~1#1); 17190#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17189#L143 assume !(1 == ~t1_pc~0); 17188#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17187#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17186#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 16334#L327 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16335#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17133#L287 assume !(1 == ~M_E~0); 16447#L287-2 assume !(1 == ~T1_E~0); 16357#L292-1 assume !(1 == ~E_M~0); 16358#L297-1 assume !(1 == ~E_1~0); 16337#L302-1 assume { :end_inline_reset_delta_events } true; 16338#L428-2 assume !false; 17264#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16462#L234 [2022-02-21 04:21:46,515 INFO L793 eck$LassoCheckResult]: Loop: 16462#L234 assume !false; 17260#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 17257#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 17258#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 17274#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17273#L215 assume 0 != eval_~tmp~0#1; 17272#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 16415#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 16410#L220 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 16411#L237 assume !(0 != eval_~tmp_ndt_2~0#1); 16462#L234 [2022-02-21 04:21:46,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,516 INFO L85 PathProgramCache]: Analyzing trace with hash -1643521085, now seen corresponding path program 1 times [2022-02-21 04:21:46,516 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,516 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266991935] [2022-02-21 04:21:46,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,531 INFO L290 TraceCheckUtils]: 0: Hoare triple {19383#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; {19383#true} is VALID [2022-02-21 04:21:46,532 INFO L290 TraceCheckUtils]: 1: Hoare triple {19383#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; {19385#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:46,532 INFO L290 TraceCheckUtils]: 2: Hoare triple {19385#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {19385#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:46,532 INFO L290 TraceCheckUtils]: 3: Hoare triple {19385#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {19385#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:46,532 INFO L290 TraceCheckUtils]: 4: Hoare triple {19385#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {19385#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 5: Hoare triple {19385#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 6: Hoare triple {19384#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 7: Hoare triple {19384#false} assume !(0 == ~M_E~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 8: Hoare triple {19384#false} assume !(0 == ~T1_E~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 9: Hoare triple {19384#false} assume !(0 == ~E_M~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 10: Hoare triple {19384#false} assume !(0 == ~E_1~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 11: Hoare triple {19384#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 12: Hoare triple {19384#false} assume !(1 == ~m_pc~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 13: Hoare triple {19384#false} is_master_triggered_~__retres1~0#1 := 0; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 14: Hoare triple {19384#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 15: Hoare triple {19384#false} activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 16: Hoare triple {19384#false} assume !(0 != activate_threads_~tmp~1#1); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 17: Hoare triple {19384#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 18: Hoare triple {19384#false} assume !(1 == ~t1_pc~0); {19384#false} is VALID [2022-02-21 04:21:46,533 INFO L290 TraceCheckUtils]: 19: Hoare triple {19384#false} is_transmit1_triggered_~__retres1~1#1 := 0; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 20: Hoare triple {19384#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 21: Hoare triple {19384#false} activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 22: Hoare triple {19384#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 23: Hoare triple {19384#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 24: Hoare triple {19384#false} assume !(1 == ~M_E~0); {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 25: Hoare triple {19384#false} assume !(1 == ~T1_E~0); {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 26: Hoare triple {19384#false} assume !(1 == ~E_M~0); {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 27: Hoare triple {19384#false} assume !(1 == ~E_1~0); {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 28: Hoare triple {19384#false} assume { :end_inline_reset_delta_events } true; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 29: Hoare triple {19384#false} assume !false; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L290 TraceCheckUtils]: 30: Hoare triple {19384#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {19384#false} is VALID [2022-02-21 04:21:46,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,534 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,534 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266991935] [2022-02-21 04:21:46,534 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266991935] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,534 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,534 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:46,535 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [124918397] [2022-02-21 04:21:46,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,535 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:46,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,536 INFO L85 PathProgramCache]: Analyzing trace with hash 3735164, now seen corresponding path program 1 times [2022-02-21 04:21:46,536 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,536 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348478484] [2022-02-21 04:21:46,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,541 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,545 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:46,603 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:46,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:46,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:46,604 INFO L87 Difference]: Start difference. First operand 1019 states and 1330 transitions. cyclomatic complexity: 316 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,721 INFO L93 Difference]: Finished difference Result 984 states and 1283 transitions. [2022-02-21 04:21:46,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:46,721 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,736 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,761 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 948 [2022-02-21 04:21:46,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 984 states to 984 states and 1283 transitions. [2022-02-21 04:21:46,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 984 [2022-02-21 04:21:46,785 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 984 [2022-02-21 04:21:46,785 INFO L73 IsDeterministic]: Start isDeterministic. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:46,786 INFO L681 BuchiCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-02-21 04:21:46,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,794 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 984 to 984. [2022-02-21 04:21:46,794 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:46,795 INFO L82 GeneralOperation]: Start isEquivalent. First operand 984 states and 1283 transitions. Second operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,796 INFO L74 IsIncluded]: Start isIncluded. First operand 984 states and 1283 transitions. Second operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,797 INFO L87 Difference]: Start difference. First operand 984 states and 1283 transitions. Second operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,821 INFO L93 Difference]: Finished difference Result 984 states and 1283 transitions. [2022-02-21 04:21:46,821 INFO L276 IsEmpty]: Start isEmpty. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,822 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,822 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,823 INFO L74 IsIncluded]: Start isIncluded. First operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 984 states and 1283 transitions. [2022-02-21 04:21:46,825 INFO L87 Difference]: Start difference. First operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 984 states and 1283 transitions. [2022-02-21 04:21:46,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,848 INFO L93 Difference]: Finished difference Result 984 states and 1283 transitions. [2022-02-21 04:21:46,848 INFO L276 IsEmpty]: Start isEmpty. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,850 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,850 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,850 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:46,850 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:46,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 984 states, 984 states have (on average 1.3038617886178863) internal successors, (1283), 983 states have internal predecessors, (1283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 984 states to 984 states and 1283 transitions. [2022-02-21 04:21:46,874 INFO L704 BuchiCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-02-21 04:21:46,874 INFO L587 BuchiCegarLoop]: Abstraction has 984 states and 1283 transitions. [2022-02-21 04:21:46,874 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:21:46,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 984 states and 1283 transitions. [2022-02-21 04:21:46,877 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 948 [2022-02-21 04:21:46,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:46,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:46,877 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,877 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,877 INFO L791 eck$LassoCheckResult]: Stem: 20548#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~token~0 := 0;~local~0 := 0; 20454#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 20455#L391 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20471#L163 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20472#L170 assume 1 == ~m_i~0;~m_st~0 := 0; 20467#L170-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20468#L175-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20491#L259 assume !(0 == ~M_E~0); 20492#L259-2 assume !(0 == ~T1_E~0); 20515#L264-1 assume !(0 == ~E_M~0); 20516#L269-1 assume !(0 == ~E_1~0); 20508#L274-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20509#L124 assume !(1 == ~m_pc~0); 20479#L124-2 is_master_triggered_~__retres1~0#1 := 0; 20480#L135 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20400#L136 activate_threads_#t~ret8#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 20401#L319 assume !(0 != activate_threads_~tmp~1#1); 20402#L319-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20403#L143 assume !(1 == ~t1_pc~0); 20387#L143-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20388#L154 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20466#L155 activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20413#L327 assume !(0 != activate_threads_~tmp___0~0#1); 20414#L327-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20441#L287 assume !(1 == ~M_E~0); 20485#L287-2 assume !(1 == ~T1_E~0); 20435#L292-1 assume !(1 == ~E_M~0); 20436#L297-1 assume !(1 == ~E_1~0); 20415#L302-1 assume { :end_inline_reset_delta_events } true; 20416#L428-2 assume !false; 20714#L429 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20713#L234 [2022-02-21 04:21:46,877 INFO L793 eck$LassoCheckResult]: Loop: 20713#L234 assume !false; 20710#L211 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 20707#L188 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 20705#L200 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 20702#L201 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20700#L215 assume 0 != eval_~tmp~0#1; 20698#L215-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 20695#L223 assume !(0 != eval_~tmp_ndt_1~0#1); 20696#L220 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 20715#L237 assume !(0 != eval_~tmp_ndt_2~0#1); 20713#L234 [2022-02-21 04:21:46,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,878 INFO L85 PathProgramCache]: Analyzing trace with hash -1025502329, now seen corresponding path program 2 times [2022-02-21 04:21:46,878 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,878 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623319643] [2022-02-21 04:21:46,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,888 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,896 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:46,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,896 INFO L85 PathProgramCache]: Analyzing trace with hash 3735164, now seen corresponding path program 2 times [2022-02-21 04:21:46,897 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,897 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713393880] [2022-02-21 04:21:46,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,899 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,901 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:46,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1810701694, now seen corresponding path program 1 times [2022-02-21 04:21:46,902 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,902 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80507690] [2022-02-21 04:21:46,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,907 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:46,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:46,912 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:47,411 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:21:47 BoogieIcfgContainer [2022-02-21 04:21:47,411 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:21:47,412 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:21:47,412 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:21:47,412 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:21:47,412 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:41" (3/4) ... [2022-02-21 04:21:47,415 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:21:47,447 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:21:47,447 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:21:47,448 INFO L158 Benchmark]: Toolchain (without parser) took 6344.89ms. Allocated memory was 104.9MB in the beginning and 159.4MB in the end (delta: 54.5MB). Free memory was 64.8MB in the beginning and 73.0MB in the end (delta: -8.2MB). Peak memory consumption was 46.3MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,448 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 104.9MB. Free memory is still 81.1MB. There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:21:47,449 INFO L158 Benchmark]: CACSL2BoogieTranslator took 248.49ms. Allocated memory is still 104.9MB. Free memory was 64.6MB in the beginning and 75.8MB in the end (delta: -11.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,449 INFO L158 Benchmark]: Boogie Procedure Inliner took 61.21ms. Allocated memory is still 104.9MB. Free memory was 75.8MB in the beginning and 72.8MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,449 INFO L158 Benchmark]: Boogie Preprocessor took 30.13ms. Allocated memory is still 104.9MB. Free memory was 72.8MB in the beginning and 70.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,449 INFO L158 Benchmark]: RCFGBuilder took 445.41ms. Allocated memory is still 104.9MB. Free memory was 70.7MB in the beginning and 49.7MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,450 INFO L158 Benchmark]: BuchiAutomizer took 5512.76ms. Allocated memory was 104.9MB in the beginning and 159.4MB in the end (delta: 54.5MB). Free memory was 49.7MB in the beginning and 76.2MB in the end (delta: -26.5MB). Peak memory consumption was 29.5MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,450 INFO L158 Benchmark]: Witness Printer took 35.69ms. Allocated memory is still 159.4MB. Free memory was 76.2MB in the beginning and 73.0MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:21:47,451 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 104.9MB. Free memory is still 81.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 248.49ms. Allocated memory is still 104.9MB. Free memory was 64.6MB in the beginning and 75.8MB in the end (delta: -11.2MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 61.21ms. Allocated memory is still 104.9MB. Free memory was 75.8MB in the beginning and 72.8MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 30.13ms. Allocated memory is still 104.9MB. Free memory was 72.8MB in the beginning and 70.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 445.41ms. Allocated memory is still 104.9MB. Free memory was 70.7MB in the beginning and 49.7MB in the end (delta: 21.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 5512.76ms. Allocated memory was 104.9MB in the beginning and 159.4MB in the end (delta: 54.5MB). Free memory was 49.7MB in the beginning and 76.2MB in the end (delta: -26.5MB). Peak memory consumption was 29.5MB. Max. memory is 16.1GB. * Witness Printer took 35.69ms. Allocated memory is still 159.4MB. Free memory was 76.2MB in the beginning and 73.0MB in the end (delta: 3.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.10 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 984 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.4s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.1s. Büchi inclusion checks took 2.5s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.5s AutomataMinimizationTime, 10 MinimizatonAttempts, 777 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had 1019 states and ocurred in iteration 9. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2356 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2356 mSDsluCounter, 4359 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2303 mSDsCounter, 80 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 223 IncrementalHoareTripleChecker+Invalid, 303 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 80 mSolverCounterUnsat, 2056 mSDtfsCounter, 223 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 210]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32613988=0, token=0, NULL=1, \result=0, tmp=0, __retres1=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@580d8eb7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@60450705=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1e443e8b=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51a8ee5=0, t1_pc=0, tmp_ndt_2=0, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@213b7947=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ceaa1c4=0, E_1=2, __retres1=0, M_E=2, tmp_ndt_1=0, __retres1=1, tmp=1, \result=0, m_i=1, t1_st=0, __retres1=0, local=0, m_st=0, E_M=2, NULL=0, kernel_st=1, tmp___0=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 210]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int m_st ; [L27] int t1_st ; [L28] int m_i ; [L29] int t1_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int E_M = 2; [L33] int E_1 = 2; [L37] int token ; [L39] int local ; [L473] int __retres1 ; [L477] CALL init_model() [L388] m_i = 1 [L389] t1_i = 1 [L477] RET init_model() [L478] CALL start_simulation() [L414] int kernel_st ; [L415] int tmp ; [L416] int tmp___0 ; [L420] kernel_st = 0 [L421] FCALL update_channels() [L422] CALL init_threads() [L170] COND TRUE m_i == 1 [L171] m_st = 0 [L175] COND TRUE t1_i == 1 [L176] t1_st = 0 [L422] RET init_threads() [L423] CALL fire_delta_events() [L259] COND FALSE !(M_E == 0) [L264] COND FALSE !(T1_E == 0) [L269] COND FALSE !(E_M == 0) [L274] COND FALSE !(E_1 == 0) [L423] RET fire_delta_events() [L424] CALL activate_threads() [L312] int tmp ; [L313] int tmp___0 ; [L317] CALL, EXPR is_master_triggered() [L121] int __retres1 ; [L124] COND FALSE !(m_pc == 1) [L134] __retres1 = 0 [L136] return (__retres1); [L317] RET, EXPR is_master_triggered() [L317] tmp = is_master_triggered() [L319] COND FALSE !(\read(tmp)) [L325] CALL, EXPR is_transmit1_triggered() [L140] int __retres1 ; [L143] COND FALSE !(t1_pc == 1) [L153] __retres1 = 0 [L155] return (__retres1); [L325] RET, EXPR is_transmit1_triggered() [L325] tmp___0 = is_transmit1_triggered() [L327] COND FALSE !(\read(tmp___0)) [L424] RET activate_threads() [L425] CALL reset_delta_events() [L287] COND FALSE !(M_E == 1) [L292] COND FALSE !(T1_E == 1) [L297] COND FALSE !(E_M == 1) [L302] COND FALSE !(E_1 == 1) [L425] RET reset_delta_events() [L428] COND TRUE 1 [L431] kernel_st = 1 [L432] CALL eval() [L206] int tmp ; Loop: [L210] COND TRUE 1 [L213] CALL, EXPR exists_runnable_thread() [L185] int __retres1 ; [L188] COND TRUE m_st == 0 [L189] __retres1 = 1 [L201] return (__retres1); [L213] RET, EXPR exists_runnable_thread() [L213] tmp = exists_runnable_thread() [L215] COND TRUE \read(tmp) [L220] COND TRUE m_st == 0 [L221] int tmp_ndt_1; [L222] tmp_ndt_1 = __VERIFIER_nondet_int() [L223] COND FALSE !(\read(tmp_ndt_1)) [L234] COND TRUE t1_st == 0 [L235] int tmp_ndt_2; [L236] tmp_ndt_2 = __VERIFIER_nondet_int() [L237] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:21:47,496 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)