./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.02.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:41,542 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:41,547 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:41,583 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:41,583 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:41,586 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:41,587 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:41,590 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:41,591 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:41,595 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:41,595 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:41,596 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:41,597 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:41,598 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:41,600 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:41,602 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:41,602 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:41,603 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:41,605 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:41,609 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:41,610 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:41,611 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:41,612 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:41,612 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:41,617 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:41,617 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:41,618 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:41,619 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:41,619 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:41,620 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:41,620 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:41,621 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:41,622 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:41,623 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:41,623 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:41,624 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:41,624 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:41,624 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:41,624 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:41,625 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:41,625 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:41,626 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:41,651 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:41,652 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:41,652 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:41,652 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:41,654 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:41,654 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:41,654 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:41,654 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:41,654 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:41,654 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:41,655 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:41,655 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:41,655 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:41,656 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:41,656 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:41,657 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:41,657 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:41,657 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:41,657 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:41,658 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:41,658 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:41,658 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:41,659 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:41,659 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:41,659 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:41,659 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:41,660 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:41,660 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 44ef362a593e25f5681bc4a034b065cd86559bd3dd750386bca2a1f270891ccd [2022-02-21 04:21:41,884 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:41,920 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:41,922 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:41,923 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:41,923 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:41,924 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2022-02-21 04:21:41,974 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06bdc3a45/3ee079e6c1154b76adcbbc96965588a9/FLAG64a880685 [2022-02-21 04:21:42,345 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:42,345 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c [2022-02-21 04:21:42,351 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06bdc3a45/3ee079e6c1154b76adcbbc96965588a9/FLAG64a880685 [2022-02-21 04:21:42,768 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/06bdc3a45/3ee079e6c1154b76adcbbc96965588a9 [2022-02-21 04:21:42,770 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:42,771 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:42,772 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:42,772 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:42,779 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:42,780 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:42" (1/1) ... [2022-02-21 04:21:42,781 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3802b6fb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:42, skipping insertion in model container [2022-02-21 04:21:42,781 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:42" (1/1) ... [2022-02-21 04:21:42,791 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:42,832 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:42,962 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2022-02-21 04:21:43,035 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:43,042 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:43,049 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.02.cil-1.c[671,684] [2022-02-21 04:21:43,067 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:43,078 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:43,078 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43 WrapperNode [2022-02-21 04:21:43,079 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:43,080 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:43,080 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:43,080 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:43,084 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,091 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,134 INFO L137 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 49, statements flattened = 594 [2022-02-21 04:21:43,135 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:43,135 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:43,135 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:43,135 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:43,140 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,140 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,143 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,146 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,157 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,164 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,167 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,171 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:43,172 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:43,180 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:43,180 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:43,183 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (1/1) ... [2022-02-21 04:21:43,190 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:43,197 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:43,206 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:43,240 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:43,250 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:43,251 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:43,251 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:43,251 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:43,299 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:43,300 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:43,825 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:43,834 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:43,835 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-02-21 04:21:43,836 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:43 BoogieIcfgContainer [2022-02-21 04:21:43,836 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:43,837 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:43,837 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:43,853 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:43,853 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:43,853 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:42" (1/3) ... [2022-02-21 04:21:43,854 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@639bcbd4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:43, skipping insertion in model container [2022-02-21 04:21:43,854 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:43,855 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:43" (2/3) ... [2022-02-21 04:21:43,855 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@639bcbd4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:43, skipping insertion in model container [2022-02-21 04:21:43,855 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:43,855 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:43" (3/3) ... [2022-02-21 04:21:43,856 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.02.cil-1.c [2022-02-21 04:21:43,891 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:43,892 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:43,892 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:43,892 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:43,892 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:43,892 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:43,892 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:43,892 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:43,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2022-02-21 04:21:44,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,016 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,016 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,016 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:44,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 184 [2022-02-21 04:21:44,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,046 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,054 INFO L791 eck$LassoCheckResult]: Stem: 220#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 161#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 189#L516true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186#L224true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77#L231true assume !(1 == ~m_i~0);~m_st~0 := 2; 4#L231-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 129#L236-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 126#L241-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29#L344true assume !(0 == ~M_E~0); 182#L344-2true assume !(0 == ~T1_E~0); 156#L349-1true assume !(0 == ~T2_E~0); 38#L354-1true assume 0 == ~E_M~0;~E_M~0 := 1; 193#L359-1true assume !(0 == ~E_1~0); 36#L364-1true assume !(0 == ~E_2~0); 164#L369-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L166true assume 1 == ~m_pc~0; 151#L167true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 167#L177true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28#L178true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 210#L425true assume !(0 != activate_threads_~tmp~1#1); 226#L425-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 101#L185true assume !(1 == ~t1_pc~0); 41#L185-2true is_transmit1_triggered_~__retres1~1#1 := 0; 61#L196true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70#L197true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 66#L433true assume !(0 != activate_threads_~tmp___0~0#1); 165#L433-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111#L204true assume 1 == ~t2_pc~0; 71#L205true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 130#L215true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 208#L216true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19#L441true assume !(0 != activate_threads_~tmp___1~0#1); 95#L441-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116#L382true assume !(1 == ~M_E~0); 13#L382-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 83#L387-1true assume !(1 == ~T2_E~0); 190#L392-1true assume !(1 == ~E_M~0); 106#L397-1true assume !(1 == ~E_1~0); 135#L402-1true assume !(1 == ~E_2~0); 96#L407-1true assume { :end_inline_reset_delta_events } true; 178#L553-2true [2022-02-21 04:21:44,057 INFO L793 eck$LassoCheckResult]: Loop: 178#L553-2true assume !false; 231#L554true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232#L319true assume !true; 32#L334true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 221#L224-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 196#L344-3true assume !(0 == ~M_E~0); 3#L344-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 78#L349-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 31#L354-3true assume 0 == ~E_M~0;~E_M~0 := 1; 103#L359-3true assume 0 == ~E_1~0;~E_1~0 := 1; 76#L364-3true assume 0 == ~E_2~0;~E_2~0 := 1; 74#L369-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59#L166-12true assume !(1 == ~m_pc~0); 172#L166-14true is_master_triggered_~__retres1~0#1 := 0; 44#L177-4true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82#L178-4true activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 56#L425-12true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119#L425-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 204#L185-12true assume !(1 == ~t1_pc~0); 34#L185-14true is_transmit1_triggered_~__retres1~1#1 := 0; 146#L196-4true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 200#L197-4true activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 197#L433-12true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136#L433-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 199#L204-12true assume !(1 == ~t2_pc~0); 49#L204-14true is_transmit2_triggered_~__retres1~2#1 := 0; 104#L215-4true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42#L216-4true activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 93#L441-12true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69#L441-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30#L382-3true assume 1 == ~M_E~0;~M_E~0 := 2; 79#L382-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 115#L387-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 143#L392-3true assume 1 == ~E_M~0;~E_M~0 := 2; 9#L397-3true assume 1 == ~E_1~0;~E_1~0 := 2; 122#L402-3true assume 1 == ~E_2~0;~E_2~0 := 2; 15#L407-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 8#L254-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 20#L271-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 133#L272-1true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 108#L572true assume !(0 == start_simulation_~tmp~3#1); 150#L572-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 27#L254-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 80#L271-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18#L272-2true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 198#L527true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87#L534true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191#L535true start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 184#L585true assume !(0 != start_simulation_~tmp___0~1#1); 178#L553-2true [2022-02-21 04:21:44,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,067 INFO L85 PathProgramCache]: Analyzing trace with hash 332551043, now seen corresponding path program 1 times [2022-02-21 04:21:44,073 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,074 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428375111] [2022-02-21 04:21:44,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,262 INFO L290 TraceCheckUtils]: 0: Hoare triple {235#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {235#true} is VALID [2022-02-21 04:21:44,263 INFO L290 TraceCheckUtils]: 1: Hoare triple {235#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {237#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:44,264 INFO L290 TraceCheckUtils]: 2: Hoare triple {237#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {237#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:44,264 INFO L290 TraceCheckUtils]: 3: Hoare triple {237#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {237#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:44,265 INFO L290 TraceCheckUtils]: 4: Hoare triple {237#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {236#false} is VALID [2022-02-21 04:21:44,265 INFO L290 TraceCheckUtils]: 5: Hoare triple {236#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {236#false} is VALID [2022-02-21 04:21:44,266 INFO L290 TraceCheckUtils]: 6: Hoare triple {236#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {236#false} is VALID [2022-02-21 04:21:44,266 INFO L290 TraceCheckUtils]: 7: Hoare triple {236#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {236#false} is VALID [2022-02-21 04:21:44,266 INFO L290 TraceCheckUtils]: 8: Hoare triple {236#false} assume !(0 == ~M_E~0); {236#false} is VALID [2022-02-21 04:21:44,266 INFO L290 TraceCheckUtils]: 9: Hoare triple {236#false} assume !(0 == ~T1_E~0); {236#false} is VALID [2022-02-21 04:21:44,267 INFO L290 TraceCheckUtils]: 10: Hoare triple {236#false} assume !(0 == ~T2_E~0); {236#false} is VALID [2022-02-21 04:21:44,267 INFO L290 TraceCheckUtils]: 11: Hoare triple {236#false} assume 0 == ~E_M~0;~E_M~0 := 1; {236#false} is VALID [2022-02-21 04:21:44,267 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#false} assume !(0 == ~E_1~0); {236#false} is VALID [2022-02-21 04:21:44,268 INFO L290 TraceCheckUtils]: 13: Hoare triple {236#false} assume !(0 == ~E_2~0); {236#false} is VALID [2022-02-21 04:21:44,268 INFO L290 TraceCheckUtils]: 14: Hoare triple {236#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {236#false} is VALID [2022-02-21 04:21:44,268 INFO L290 TraceCheckUtils]: 15: Hoare triple {236#false} assume 1 == ~m_pc~0; {236#false} is VALID [2022-02-21 04:21:44,268 INFO L290 TraceCheckUtils]: 16: Hoare triple {236#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {236#false} is VALID [2022-02-21 04:21:44,268 INFO L290 TraceCheckUtils]: 17: Hoare triple {236#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 18: Hoare triple {236#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 19: Hoare triple {236#false} assume !(0 != activate_threads_~tmp~1#1); {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 20: Hoare triple {236#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 21: Hoare triple {236#false} assume !(1 == ~t1_pc~0); {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 22: Hoare triple {236#false} is_transmit1_triggered_~__retres1~1#1 := 0; {236#false} is VALID [2022-02-21 04:21:44,269 INFO L290 TraceCheckUtils]: 23: Hoare triple {236#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {236#false} is VALID [2022-02-21 04:21:44,270 INFO L290 TraceCheckUtils]: 24: Hoare triple {236#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {236#false} is VALID [2022-02-21 04:21:44,270 INFO L290 TraceCheckUtils]: 25: Hoare triple {236#false} assume !(0 != activate_threads_~tmp___0~0#1); {236#false} is VALID [2022-02-21 04:21:44,270 INFO L290 TraceCheckUtils]: 26: Hoare triple {236#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {236#false} is VALID [2022-02-21 04:21:44,271 INFO L290 TraceCheckUtils]: 27: Hoare triple {236#false} assume 1 == ~t2_pc~0; {236#false} is VALID [2022-02-21 04:21:44,272 INFO L290 TraceCheckUtils]: 28: Hoare triple {236#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {236#false} is VALID [2022-02-21 04:21:44,272 INFO L290 TraceCheckUtils]: 29: Hoare triple {236#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {236#false} is VALID [2022-02-21 04:21:44,272 INFO L290 TraceCheckUtils]: 30: Hoare triple {236#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {236#false} is VALID [2022-02-21 04:21:44,272 INFO L290 TraceCheckUtils]: 31: Hoare triple {236#false} assume !(0 != activate_threads_~tmp___1~0#1); {236#false} is VALID [2022-02-21 04:21:44,272 INFO L290 TraceCheckUtils]: 32: Hoare triple {236#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {236#false} is VALID [2022-02-21 04:21:44,273 INFO L290 TraceCheckUtils]: 33: Hoare triple {236#false} assume !(1 == ~M_E~0); {236#false} is VALID [2022-02-21 04:21:44,273 INFO L290 TraceCheckUtils]: 34: Hoare triple {236#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {236#false} is VALID [2022-02-21 04:21:44,273 INFO L290 TraceCheckUtils]: 35: Hoare triple {236#false} assume !(1 == ~T2_E~0); {236#false} is VALID [2022-02-21 04:21:44,273 INFO L290 TraceCheckUtils]: 36: Hoare triple {236#false} assume !(1 == ~E_M~0); {236#false} is VALID [2022-02-21 04:21:44,273 INFO L290 TraceCheckUtils]: 37: Hoare triple {236#false} assume !(1 == ~E_1~0); {236#false} is VALID [2022-02-21 04:21:44,274 INFO L290 TraceCheckUtils]: 38: Hoare triple {236#false} assume !(1 == ~E_2~0); {236#false} is VALID [2022-02-21 04:21:44,274 INFO L290 TraceCheckUtils]: 39: Hoare triple {236#false} assume { :end_inline_reset_delta_events } true; {236#false} is VALID [2022-02-21 04:21:44,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,275 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,276 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428375111] [2022-02-21 04:21:44,277 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428375111] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,277 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,277 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:44,278 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032056119] [2022-02-21 04:21:44,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,283 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:44,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,285 INFO L85 PathProgramCache]: Analyzing trace with hash -152738315, now seen corresponding path program 1 times [2022-02-21 04:21:44,285 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,285 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779849195] [2022-02-21 04:21:44,286 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,329 INFO L290 TraceCheckUtils]: 0: Hoare triple {238#true} assume !false; {238#true} is VALID [2022-02-21 04:21:44,330 INFO L290 TraceCheckUtils]: 1: Hoare triple {238#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {238#true} is VALID [2022-02-21 04:21:44,331 INFO L290 TraceCheckUtils]: 2: Hoare triple {238#true} assume !true; {239#false} is VALID [2022-02-21 04:21:44,331 INFO L290 TraceCheckUtils]: 3: Hoare triple {239#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {239#false} is VALID [2022-02-21 04:21:44,331 INFO L290 TraceCheckUtils]: 4: Hoare triple {239#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {239#false} is VALID [2022-02-21 04:21:44,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {239#false} assume !(0 == ~M_E~0); {239#false} is VALID [2022-02-21 04:21:44,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {239#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {239#false} is VALID [2022-02-21 04:21:44,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {239#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {239#false} is VALID [2022-02-21 04:21:44,333 INFO L290 TraceCheckUtils]: 8: Hoare triple {239#false} assume 0 == ~E_M~0;~E_M~0 := 1; {239#false} is VALID [2022-02-21 04:21:44,334 INFO L290 TraceCheckUtils]: 9: Hoare triple {239#false} assume 0 == ~E_1~0;~E_1~0 := 1; {239#false} is VALID [2022-02-21 04:21:44,334 INFO L290 TraceCheckUtils]: 10: Hoare triple {239#false} assume 0 == ~E_2~0;~E_2~0 := 1; {239#false} is VALID [2022-02-21 04:21:44,337 INFO L290 TraceCheckUtils]: 11: Hoare triple {239#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {239#false} is VALID [2022-02-21 04:21:44,337 INFO L290 TraceCheckUtils]: 12: Hoare triple {239#false} assume !(1 == ~m_pc~0); {239#false} is VALID [2022-02-21 04:21:44,338 INFO L290 TraceCheckUtils]: 13: Hoare triple {239#false} is_master_triggered_~__retres1~0#1 := 0; {239#false} is VALID [2022-02-21 04:21:44,338 INFO L290 TraceCheckUtils]: 14: Hoare triple {239#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {239#false} is VALID [2022-02-21 04:21:44,338 INFO L290 TraceCheckUtils]: 15: Hoare triple {239#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {239#false} is VALID [2022-02-21 04:21:44,339 INFO L290 TraceCheckUtils]: 16: Hoare triple {239#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {239#false} is VALID [2022-02-21 04:21:44,339 INFO L290 TraceCheckUtils]: 17: Hoare triple {239#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {239#false} is VALID [2022-02-21 04:21:44,340 INFO L290 TraceCheckUtils]: 18: Hoare triple {239#false} assume !(1 == ~t1_pc~0); {239#false} is VALID [2022-02-21 04:21:44,341 INFO L290 TraceCheckUtils]: 19: Hoare triple {239#false} is_transmit1_triggered_~__retres1~1#1 := 0; {239#false} is VALID [2022-02-21 04:21:44,342 INFO L290 TraceCheckUtils]: 20: Hoare triple {239#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {239#false} is VALID [2022-02-21 04:21:44,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {239#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {239#false} is VALID [2022-02-21 04:21:44,342 INFO L290 TraceCheckUtils]: 22: Hoare triple {239#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {239#false} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 23: Hoare triple {239#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {239#false} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 24: Hoare triple {239#false} assume !(1 == ~t2_pc~0); {239#false} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 25: Hoare triple {239#false} is_transmit2_triggered_~__retres1~2#1 := 0; {239#false} is VALID [2022-02-21 04:21:44,343 INFO L290 TraceCheckUtils]: 26: Hoare triple {239#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {239#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 27: Hoare triple {239#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {239#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 28: Hoare triple {239#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {239#false} is VALID [2022-02-21 04:21:44,344 INFO L290 TraceCheckUtils]: 29: Hoare triple {239#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {239#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 30: Hoare triple {239#false} assume 1 == ~M_E~0;~M_E~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 31: Hoare triple {239#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 32: Hoare triple {239#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 33: Hoare triple {239#false} assume 1 == ~E_M~0;~E_M~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,345 INFO L290 TraceCheckUtils]: 34: Hoare triple {239#false} assume 1 == ~E_1~0;~E_1~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 35: Hoare triple {239#false} assume 1 == ~E_2~0;~E_2~0 := 2; {239#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 36: Hoare triple {239#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {239#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 37: Hoare triple {239#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {239#false} is VALID [2022-02-21 04:21:44,346 INFO L290 TraceCheckUtils]: 38: Hoare triple {239#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {239#false} is VALID [2022-02-21 04:21:44,347 INFO L290 TraceCheckUtils]: 39: Hoare triple {239#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {239#false} is VALID [2022-02-21 04:21:44,347 INFO L290 TraceCheckUtils]: 40: Hoare triple {239#false} assume !(0 == start_simulation_~tmp~3#1); {239#false} is VALID [2022-02-21 04:21:44,347 INFO L290 TraceCheckUtils]: 41: Hoare triple {239#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {239#false} is VALID [2022-02-21 04:21:44,347 INFO L290 TraceCheckUtils]: 42: Hoare triple {239#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {239#false} is VALID [2022-02-21 04:21:44,347 INFO L290 TraceCheckUtils]: 43: Hoare triple {239#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {239#false} is VALID [2022-02-21 04:21:44,348 INFO L290 TraceCheckUtils]: 44: Hoare triple {239#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {239#false} is VALID [2022-02-21 04:21:44,348 INFO L290 TraceCheckUtils]: 45: Hoare triple {239#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {239#false} is VALID [2022-02-21 04:21:44,348 INFO L290 TraceCheckUtils]: 46: Hoare triple {239#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {239#false} is VALID [2022-02-21 04:21:44,348 INFO L290 TraceCheckUtils]: 47: Hoare triple {239#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {239#false} is VALID [2022-02-21 04:21:44,348 INFO L290 TraceCheckUtils]: 48: Hoare triple {239#false} assume !(0 != start_simulation_~tmp___0~1#1); {239#false} is VALID [2022-02-21 04:21:44,349 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,350 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,350 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779849195] [2022-02-21 04:21:44,350 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779849195] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,350 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,350 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:44,351 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403687784] [2022-02-21 04:21:44,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,352 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:44,353 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:44,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:44,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:44,380 INFO L87 Difference]: Start difference. First operand has 231 states, 230 states have (on average 1.5347826086956522) internal successors, (353), 230 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,670 INFO L93 Difference]: Finished difference Result 230 states and 340 transitions. [2022-02-21 04:21:44,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:44,671 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,714 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:44,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 340 transitions. [2022-02-21 04:21:44,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-02-21 04:21:44,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 225 states and 335 transitions. [2022-02-21 04:21:44,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-02-21 04:21:44,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-02-21 04:21:44,739 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 335 transitions. [2022-02-21 04:21:44,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:44,740 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-02-21 04:21:44,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 335 transitions. [2022-02-21 04:21:44,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2022-02-21 04:21:44,764 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:44,766 INFO L82 GeneralOperation]: Start isEquivalent. First operand 225 states and 335 transitions. Second operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,767 INFO L74 IsIncluded]: Start isIncluded. First operand 225 states and 335 transitions. Second operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,768 INFO L87 Difference]: Start difference. First operand 225 states and 335 transitions. Second operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,775 INFO L93 Difference]: Finished difference Result 225 states and 335 transitions. [2022-02-21 04:21:44,775 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 335 transitions. [2022-02-21 04:21:44,776 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,776 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,777 INFO L74 IsIncluded]: Start isIncluded. First operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 225 states and 335 transitions. [2022-02-21 04:21:44,778 INFO L87 Difference]: Start difference. First operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 225 states and 335 transitions. [2022-02-21 04:21:44,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:44,784 INFO L93 Difference]: Finished difference Result 225 states and 335 transitions. [2022-02-21 04:21:44,784 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 335 transitions. [2022-02-21 04:21:44,803 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:44,804 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:44,804 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:44,804 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:44,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.488888888888889) internal successors, (335), 224 states have internal predecessors, (335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:44,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 335 transitions. [2022-02-21 04:21:44,810 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-02-21 04:21:44,810 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 335 transitions. [2022-02-21 04:21:44,810 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:44,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 335 transitions. [2022-02-21 04:21:44,811 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-02-21 04:21:44,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:44,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:44,812 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,812 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:44,813 INFO L791 eck$LassoCheckResult]: Stem: 694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 673#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 600#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 472#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473#L236-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 648#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 520#L344 assume !(0 == ~M_E~0); 521#L344-2 assume !(0 == ~T1_E~0); 669#L349-1 assume !(0 == ~T2_E~0); 539#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 540#L359-1 assume !(0 == ~E_1~0); 534#L364-1 assume !(0 == ~E_2~0); 535#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 613#L166 assume 1 == ~m_pc~0; 614#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 662#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 518#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 519#L425 assume !(0 != activate_threads_~tmp~1#1); 692#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 623#L185 assume !(1 == ~t1_pc~0); 545#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 546#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 583#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 588#L433 assume !(0 != activate_threads_~tmp___0~0#1); 589#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 634#L204 assume 1 == ~t2_pc~0; 592#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 593#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 650#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 501#L441 assume !(0 != activate_threads_~tmp___1~0#1); 502#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 617#L382 assume !(1 == ~M_E~0); 491#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 492#L387-1 assume !(1 == ~T2_E~0); 603#L392-1 assume !(1 == ~E_M~0); 627#L397-1 assume !(1 == ~E_1~0); 628#L402-1 assume !(1 == ~E_2~0); 618#L407-1 assume { :end_inline_reset_delta_events } true; 619#L553-2 [2022-02-21 04:21:44,813 INFO L793 eck$LassoCheckResult]: Loop: 619#L553-2 assume !false; 679#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 674#L319 assume !false; 651#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 553#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 554#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 543#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 544#L286 assume !(0 != eval_~tmp~0#1); 526#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 527#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 688#L344-3 assume !(0 == ~M_E~0); 470#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 471#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 524#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 525#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 599#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 597#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 579#L166-12 assume 1 == ~m_pc~0; 580#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 549#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 550#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 573#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 574#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643#L185-12 assume !(1 == ~t1_pc~0); 531#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 532#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 660#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 689#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 653#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 654#L204-12 assume 1 == ~t2_pc~0; 675#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 558#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 548#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 591#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 522#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 523#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 601#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 637#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 484#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 485#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 495#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 481#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 482#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 503#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 631#L572 assume !(0 == start_simulation_~tmp~3#1); 542#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 515#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 516#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 499#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 500#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 610#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 682#L585 assume !(0 != start_simulation_~tmp___0~1#1); 619#L553-2 [2022-02-21 04:21:44,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,814 INFO L85 PathProgramCache]: Analyzing trace with hash 726917829, now seen corresponding path program 1 times [2022-02-21 04:21:44,814 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,814 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [301218813] [2022-02-21 04:21:44,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,839 INFO L290 TraceCheckUtils]: 0: Hoare triple {1148#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {1148#true} is VALID [2022-02-21 04:21:44,839 INFO L290 TraceCheckUtils]: 1: Hoare triple {1148#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {1150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:44,840 INFO L290 TraceCheckUtils]: 2: Hoare triple {1150#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:44,840 INFO L290 TraceCheckUtils]: 3: Hoare triple {1150#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:44,840 INFO L290 TraceCheckUtils]: 4: Hoare triple {1150#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {1150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:44,841 INFO L290 TraceCheckUtils]: 5: Hoare triple {1150#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:44,841 INFO L290 TraceCheckUtils]: 6: Hoare triple {1150#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1149#false} is VALID [2022-02-21 04:21:44,841 INFO L290 TraceCheckUtils]: 7: Hoare triple {1149#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1149#false} is VALID [2022-02-21 04:21:44,841 INFO L290 TraceCheckUtils]: 8: Hoare triple {1149#false} assume !(0 == ~M_E~0); {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 9: Hoare triple {1149#false} assume !(0 == ~T1_E~0); {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 10: Hoare triple {1149#false} assume !(0 == ~T2_E~0); {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 11: Hoare triple {1149#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 12: Hoare triple {1149#false} assume !(0 == ~E_1~0); {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 13: Hoare triple {1149#false} assume !(0 == ~E_2~0); {1149#false} is VALID [2022-02-21 04:21:44,842 INFO L290 TraceCheckUtils]: 14: Hoare triple {1149#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1149#false} is VALID [2022-02-21 04:21:44,843 INFO L290 TraceCheckUtils]: 15: Hoare triple {1149#false} assume 1 == ~m_pc~0; {1149#false} is VALID [2022-02-21 04:21:44,843 INFO L290 TraceCheckUtils]: 16: Hoare triple {1149#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1149#false} is VALID [2022-02-21 04:21:44,843 INFO L290 TraceCheckUtils]: 17: Hoare triple {1149#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1149#false} is VALID [2022-02-21 04:21:44,843 INFO L290 TraceCheckUtils]: 18: Hoare triple {1149#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1149#false} is VALID [2022-02-21 04:21:44,843 INFO L290 TraceCheckUtils]: 19: Hoare triple {1149#false} assume !(0 != activate_threads_~tmp~1#1); {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 20: Hoare triple {1149#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 21: Hoare triple {1149#false} assume !(1 == ~t1_pc~0); {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 22: Hoare triple {1149#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 23: Hoare triple {1149#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 24: Hoare triple {1149#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1149#false} is VALID [2022-02-21 04:21:44,844 INFO L290 TraceCheckUtils]: 25: Hoare triple {1149#false} assume !(0 != activate_threads_~tmp___0~0#1); {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 26: Hoare triple {1149#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 27: Hoare triple {1149#false} assume 1 == ~t2_pc~0; {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 28: Hoare triple {1149#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 29: Hoare triple {1149#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 30: Hoare triple {1149#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1149#false} is VALID [2022-02-21 04:21:44,845 INFO L290 TraceCheckUtils]: 31: Hoare triple {1149#false} assume !(0 != activate_threads_~tmp___1~0#1); {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 32: Hoare triple {1149#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 33: Hoare triple {1149#false} assume !(1 == ~M_E~0); {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 34: Hoare triple {1149#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 35: Hoare triple {1149#false} assume !(1 == ~T2_E~0); {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 36: Hoare triple {1149#false} assume !(1 == ~E_M~0); {1149#false} is VALID [2022-02-21 04:21:44,846 INFO L290 TraceCheckUtils]: 37: Hoare triple {1149#false} assume !(1 == ~E_1~0); {1149#false} is VALID [2022-02-21 04:21:44,847 INFO L290 TraceCheckUtils]: 38: Hoare triple {1149#false} assume !(1 == ~E_2~0); {1149#false} is VALID [2022-02-21 04:21:44,847 INFO L290 TraceCheckUtils]: 39: Hoare triple {1149#false} assume { :end_inline_reset_delta_events } true; {1149#false} is VALID [2022-02-21 04:21:44,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,847 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,848 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [301218813] [2022-02-21 04:21:44,848 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [301218813] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,848 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,848 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:44,848 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71713103] [2022-02-21 04:21:44,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,849 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:44,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:44,849 INFO L85 PathProgramCache]: Analyzing trace with hash 1606950136, now seen corresponding path program 1 times [2022-02-21 04:21:44,849 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:44,849 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135324850] [2022-02-21 04:21:44,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:44,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:44,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:44,893 INFO L290 TraceCheckUtils]: 0: Hoare triple {1151#true} assume !false; {1151#true} is VALID [2022-02-21 04:21:44,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {1151#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1151#true} is VALID [2022-02-21 04:21:44,894 INFO L290 TraceCheckUtils]: 2: Hoare triple {1151#true} assume !false; {1151#true} is VALID [2022-02-21 04:21:44,894 INFO L290 TraceCheckUtils]: 3: Hoare triple {1151#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1151#true} is VALID [2022-02-21 04:21:44,894 INFO L290 TraceCheckUtils]: 4: Hoare triple {1151#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1153#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:44,895 INFO L290 TraceCheckUtils]: 5: Hoare triple {1153#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1154#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:44,895 INFO L290 TraceCheckUtils]: 6: Hoare triple {1154#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {1155#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 7: Hoare triple {1155#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {1152#false} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 8: Hoare triple {1152#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1152#false} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 9: Hoare triple {1152#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1152#false} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 10: Hoare triple {1152#false} assume !(0 == ~M_E~0); {1152#false} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 11: Hoare triple {1152#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1152#false} is VALID [2022-02-21 04:21:44,896 INFO L290 TraceCheckUtils]: 12: Hoare triple {1152#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 13: Hoare triple {1152#false} assume 0 == ~E_M~0;~E_M~0 := 1; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 14: Hoare triple {1152#false} assume 0 == ~E_1~0;~E_1~0 := 1; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 15: Hoare triple {1152#false} assume 0 == ~E_2~0;~E_2~0 := 1; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 16: Hoare triple {1152#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 17: Hoare triple {1152#false} assume 1 == ~m_pc~0; {1152#false} is VALID [2022-02-21 04:21:44,897 INFO L290 TraceCheckUtils]: 18: Hoare triple {1152#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 19: Hoare triple {1152#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 20: Hoare triple {1152#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 21: Hoare triple {1152#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 22: Hoare triple {1152#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 23: Hoare triple {1152#false} assume !(1 == ~t1_pc~0); {1152#false} is VALID [2022-02-21 04:21:44,898 INFO L290 TraceCheckUtils]: 24: Hoare triple {1152#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 25: Hoare triple {1152#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 26: Hoare triple {1152#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 27: Hoare triple {1152#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 28: Hoare triple {1152#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 29: Hoare triple {1152#false} assume 1 == ~t2_pc~0; {1152#false} is VALID [2022-02-21 04:21:44,899 INFO L290 TraceCheckUtils]: 30: Hoare triple {1152#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 31: Hoare triple {1152#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 32: Hoare triple {1152#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 33: Hoare triple {1152#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 34: Hoare triple {1152#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 35: Hoare triple {1152#false} assume 1 == ~M_E~0;~M_E~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,900 INFO L290 TraceCheckUtils]: 36: Hoare triple {1152#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 37: Hoare triple {1152#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 38: Hoare triple {1152#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 39: Hoare triple {1152#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 40: Hoare triple {1152#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 41: Hoare triple {1152#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 42: Hoare triple {1152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1152#false} is VALID [2022-02-21 04:21:44,901 INFO L290 TraceCheckUtils]: 43: Hoare triple {1152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 44: Hoare triple {1152#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 45: Hoare triple {1152#false} assume !(0 == start_simulation_~tmp~3#1); {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 46: Hoare triple {1152#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 47: Hoare triple {1152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 48: Hoare triple {1152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {1152#false} is VALID [2022-02-21 04:21:44,902 INFO L290 TraceCheckUtils]: 49: Hoare triple {1152#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {1152#false} is VALID [2022-02-21 04:21:44,903 INFO L290 TraceCheckUtils]: 50: Hoare triple {1152#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1152#false} is VALID [2022-02-21 04:21:44,903 INFO L290 TraceCheckUtils]: 51: Hoare triple {1152#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1152#false} is VALID [2022-02-21 04:21:44,903 INFO L290 TraceCheckUtils]: 52: Hoare triple {1152#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {1152#false} is VALID [2022-02-21 04:21:44,903 INFO L290 TraceCheckUtils]: 53: Hoare triple {1152#false} assume !(0 != start_simulation_~tmp___0~1#1); {1152#false} is VALID [2022-02-21 04:21:44,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:44,904 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:44,904 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135324850] [2022-02-21 04:21:44,904 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135324850] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:44,904 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:44,904 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:44,904 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146263889] [2022-02-21 04:21:44,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:44,905 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:44,905 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:44,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:44,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:44,906 INFO L87 Difference]: Start difference. First operand 225 states and 335 transitions. cyclomatic complexity: 111 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,070 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2022-02-21 04:21:45,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:45,070 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,096 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:45,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,101 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-02-21 04:21:45,105 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 334 transitions. [2022-02-21 04:21:45,106 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2022-02-21 04:21:45,106 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2022-02-21 04:21:45,106 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:45,107 INFO L681 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-02-21 04:21:45,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2022-02-21 04:21:45,112 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:45,112 INFO L82 GeneralOperation]: Start isEquivalent. First operand 225 states and 334 transitions. Second operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,113 INFO L74 IsIncluded]: Start isIncluded. First operand 225 states and 334 transitions. Second operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,113 INFO L87 Difference]: Start difference. First operand 225 states and 334 transitions. Second operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,117 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2022-02-21 04:21:45,118 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,118 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,118 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,119 INFO L74 IsIncluded]: Start isIncluded. First operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 225 states and 334 transitions. [2022-02-21 04:21:45,119 INFO L87 Difference]: Start difference. First operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 225 states and 334 transitions. [2022-02-21 04:21:45,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,123 INFO L93 Difference]: Finished difference Result 225 states and 334 transitions. [2022-02-21 04:21:45,124 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,124 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,124 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,124 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:45,124 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:45,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225 states, 225 states have (on average 1.4844444444444445) internal successors, (334), 224 states have internal predecessors, (334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 334 transitions. [2022-02-21 04:21:45,129 INFO L704 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-02-21 04:21:45,129 INFO L587 BuchiCegarLoop]: Abstraction has 225 states and 334 transitions. [2022-02-21 04:21:45,129 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:45,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225 states and 334 transitions. [2022-02-21 04:21:45,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2022-02-21 04:21:45,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,131 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,131 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,131 INFO L791 eck$LassoCheckResult]: Stem: 1605#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 1583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1584#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1594#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1511#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 1383#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1384#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1559#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1431#L344 assume !(0 == ~M_E~0); 1432#L344-2 assume !(0 == ~T1_E~0); 1580#L349-1 assume !(0 == ~T2_E~0); 1450#L354-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1451#L359-1 assume !(0 == ~E_1~0); 1445#L364-1 assume !(0 == ~E_2~0); 1446#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1524#L166 assume 1 == ~m_pc~0; 1525#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1573#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1429#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1430#L425 assume !(0 != activate_threads_~tmp~1#1); 1603#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1534#L185 assume !(1 == ~t1_pc~0); 1456#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1457#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1494#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1499#L433 assume !(0 != activate_threads_~tmp___0~0#1); 1500#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1545#L204 assume 1 == ~t2_pc~0; 1503#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1504#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1561#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1412#L441 assume !(0 != activate_threads_~tmp___1~0#1); 1413#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1528#L382 assume !(1 == ~M_E~0); 1402#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1403#L387-1 assume !(1 == ~T2_E~0); 1514#L392-1 assume !(1 == ~E_M~0); 1538#L397-1 assume !(1 == ~E_1~0); 1539#L402-1 assume !(1 == ~E_2~0); 1529#L407-1 assume { :end_inline_reset_delta_events } true; 1530#L553-2 [2022-02-21 04:21:45,132 INFO L793 eck$LassoCheckResult]: Loop: 1530#L553-2 assume !false; 1590#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1585#L319 assume !false; 1562#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1464#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1465#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1454#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1455#L286 assume !(0 != eval_~tmp~0#1); 1437#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1438#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1599#L344-3 assume !(0 == ~M_E~0); 1381#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1382#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1435#L354-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1436#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1510#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1508#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490#L166-12 assume 1 == ~m_pc~0; 1491#L167-4 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1460#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1461#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1484#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1485#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1554#L185-12 assume !(1 == ~t1_pc~0); 1442#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 1443#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1571#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1600#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1564#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1565#L204-12 assume 1 == ~t2_pc~0; 1586#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1469#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1458#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1459#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1502#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1433#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1434#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1512#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1548#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1395#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1396#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1406#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1392#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1393#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1414#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1542#L572 assume !(0 == start_simulation_~tmp~3#1); 1453#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1426#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1427#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1410#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1411#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1520#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1521#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1593#L585 assume !(0 != start_simulation_~tmp___0~1#1); 1530#L553-2 [2022-02-21 04:21:45,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1324066169, now seen corresponding path program 1 times [2022-02-21 04:21:45,132 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,133 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330148201] [2022-02-21 04:21:45,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,163 INFO L290 TraceCheckUtils]: 0: Hoare triple {2059#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,164 INFO L290 TraceCheckUtils]: 1: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,164 INFO L290 TraceCheckUtils]: 3: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,165 INFO L290 TraceCheckUtils]: 4: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,165 INFO L290 TraceCheckUtils]: 5: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,165 INFO L290 TraceCheckUtils]: 6: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,166 INFO L290 TraceCheckUtils]: 7: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2061#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:45,166 INFO L290 TraceCheckUtils]: 8: Hoare triple {2061#(= ~E_M~0 ~M_E~0)} assume !(0 == ~M_E~0); {2062#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:45,166 INFO L290 TraceCheckUtils]: 9: Hoare triple {2062#(not (= ~E_M~0 0))} assume !(0 == ~T1_E~0); {2062#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:45,167 INFO L290 TraceCheckUtils]: 10: Hoare triple {2062#(not (= ~E_M~0 0))} assume !(0 == ~T2_E~0); {2062#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:45,167 INFO L290 TraceCheckUtils]: 11: Hoare triple {2062#(not (= ~E_M~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {2060#false} is VALID [2022-02-21 04:21:45,167 INFO L290 TraceCheckUtils]: 12: Hoare triple {2060#false} assume !(0 == ~E_1~0); {2060#false} is VALID [2022-02-21 04:21:45,167 INFO L290 TraceCheckUtils]: 13: Hoare triple {2060#false} assume !(0 == ~E_2~0); {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 14: Hoare triple {2060#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 15: Hoare triple {2060#false} assume 1 == ~m_pc~0; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 16: Hoare triple {2060#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 17: Hoare triple {2060#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 18: Hoare triple {2060#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 19: Hoare triple {2060#false} assume !(0 != activate_threads_~tmp~1#1); {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 20: Hoare triple {2060#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2060#false} is VALID [2022-02-21 04:21:45,168 INFO L290 TraceCheckUtils]: 21: Hoare triple {2060#false} assume !(1 == ~t1_pc~0); {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 22: Hoare triple {2060#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 23: Hoare triple {2060#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 24: Hoare triple {2060#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 25: Hoare triple {2060#false} assume !(0 != activate_threads_~tmp___0~0#1); {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 26: Hoare triple {2060#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 27: Hoare triple {2060#false} assume 1 == ~t2_pc~0; {2060#false} is VALID [2022-02-21 04:21:45,169 INFO L290 TraceCheckUtils]: 28: Hoare triple {2060#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 29: Hoare triple {2060#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 30: Hoare triple {2060#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 31: Hoare triple {2060#false} assume !(0 != activate_threads_~tmp___1~0#1); {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 32: Hoare triple {2060#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 33: Hoare triple {2060#false} assume !(1 == ~M_E~0); {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 34: Hoare triple {2060#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 35: Hoare triple {2060#false} assume !(1 == ~T2_E~0); {2060#false} is VALID [2022-02-21 04:21:45,170 INFO L290 TraceCheckUtils]: 36: Hoare triple {2060#false} assume !(1 == ~E_M~0); {2060#false} is VALID [2022-02-21 04:21:45,171 INFO L290 TraceCheckUtils]: 37: Hoare triple {2060#false} assume !(1 == ~E_1~0); {2060#false} is VALID [2022-02-21 04:21:45,171 INFO L290 TraceCheckUtils]: 38: Hoare triple {2060#false} assume !(1 == ~E_2~0); {2060#false} is VALID [2022-02-21 04:21:45,171 INFO L290 TraceCheckUtils]: 39: Hoare triple {2060#false} assume { :end_inline_reset_delta_events } true; {2060#false} is VALID [2022-02-21 04:21:45,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,171 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,172 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330148201] [2022-02-21 04:21:45,172 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330148201] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,172 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,172 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:45,172 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988854758] [2022-02-21 04:21:45,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,172 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:45,173 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,173 INFO L85 PathProgramCache]: Analyzing trace with hash 1606950136, now seen corresponding path program 2 times [2022-02-21 04:21:45,173 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,173 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173509830] [2022-02-21 04:21:45,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,207 INFO L290 TraceCheckUtils]: 0: Hoare triple {2063#true} assume !false; {2063#true} is VALID [2022-02-21 04:21:45,207 INFO L290 TraceCheckUtils]: 1: Hoare triple {2063#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2063#true} is VALID [2022-02-21 04:21:45,207 INFO L290 TraceCheckUtils]: 2: Hoare triple {2063#true} assume !false; {2063#true} is VALID [2022-02-21 04:21:45,207 INFO L290 TraceCheckUtils]: 3: Hoare triple {2063#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {2063#true} is VALID [2022-02-21 04:21:45,208 INFO L290 TraceCheckUtils]: 4: Hoare triple {2063#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {2065#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:45,208 INFO L290 TraceCheckUtils]: 5: Hoare triple {2065#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {2066#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 6: Hoare triple {2066#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {2067#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 7: Hoare triple {2067#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {2064#false} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 8: Hoare triple {2064#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2064#false} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 9: Hoare triple {2064#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2064#false} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 10: Hoare triple {2064#false} assume !(0 == ~M_E~0); {2064#false} is VALID [2022-02-21 04:21:45,209 INFO L290 TraceCheckUtils]: 11: Hoare triple {2064#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 12: Hoare triple {2064#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 13: Hoare triple {2064#false} assume 0 == ~E_M~0;~E_M~0 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 14: Hoare triple {2064#false} assume 0 == ~E_1~0;~E_1~0 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 15: Hoare triple {2064#false} assume 0 == ~E_2~0;~E_2~0 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 16: Hoare triple {2064#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 17: Hoare triple {2064#false} assume 1 == ~m_pc~0; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 18: Hoare triple {2064#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2064#false} is VALID [2022-02-21 04:21:45,210 INFO L290 TraceCheckUtils]: 19: Hoare triple {2064#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 20: Hoare triple {2064#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 21: Hoare triple {2064#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 22: Hoare triple {2064#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 23: Hoare triple {2064#false} assume !(1 == ~t1_pc~0); {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 24: Hoare triple {2064#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 25: Hoare triple {2064#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 26: Hoare triple {2064#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {2064#false} is VALID [2022-02-21 04:21:45,211 INFO L290 TraceCheckUtils]: 27: Hoare triple {2064#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 28: Hoare triple {2064#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 29: Hoare triple {2064#false} assume 1 == ~t2_pc~0; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 30: Hoare triple {2064#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 31: Hoare triple {2064#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 32: Hoare triple {2064#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 33: Hoare triple {2064#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 34: Hoare triple {2064#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2064#false} is VALID [2022-02-21 04:21:45,212 INFO L290 TraceCheckUtils]: 35: Hoare triple {2064#false} assume 1 == ~M_E~0;~M_E~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 36: Hoare triple {2064#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 37: Hoare triple {2064#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 38: Hoare triple {2064#false} assume 1 == ~E_M~0;~E_M~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 39: Hoare triple {2064#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 40: Hoare triple {2064#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 41: Hoare triple {2064#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 42: Hoare triple {2064#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 43: Hoare triple {2064#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {2064#false} is VALID [2022-02-21 04:21:45,213 INFO L290 TraceCheckUtils]: 44: Hoare triple {2064#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 45: Hoare triple {2064#false} assume !(0 == start_simulation_~tmp~3#1); {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 46: Hoare triple {2064#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 47: Hoare triple {2064#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 48: Hoare triple {2064#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 49: Hoare triple {2064#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 50: Hoare triple {2064#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 51: Hoare triple {2064#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2064#false} is VALID [2022-02-21 04:21:45,214 INFO L290 TraceCheckUtils]: 52: Hoare triple {2064#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {2064#false} is VALID [2022-02-21 04:21:45,215 INFO L290 TraceCheckUtils]: 53: Hoare triple {2064#false} assume !(0 != start_simulation_~tmp___0~1#1); {2064#false} is VALID [2022-02-21 04:21:45,215 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,215 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,215 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173509830] [2022-02-21 04:21:45,215 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173509830] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,215 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,216 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:45,216 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [327405070] [2022-02-21 04:21:45,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,216 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:45,216 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:45,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:45,217 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:45,217 INFO L87 Difference]: Start difference. First operand 225 states and 334 transitions. cyclomatic complexity: 110 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,689 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2022-02-21 04:21:45,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:45,690 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,716 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:45,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 362 states and 534 transitions. [2022-02-21 04:21:45,724 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2022-02-21 04:21:45,731 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 362 states to 362 states and 534 transitions. [2022-02-21 04:21:45,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 362 [2022-02-21 04:21:45,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 362 [2022-02-21 04:21:45,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 534 transitions. [2022-02-21 04:21:45,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:45,733 INFO L681 BuchiCegarLoop]: Abstraction has 362 states and 534 transitions. [2022-02-21 04:21:45,733 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 534 transitions. [2022-02-21 04:21:45,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 361. [2022-02-21 04:21:45,740 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:45,740 INFO L82 GeneralOperation]: Start isEquivalent. First operand 362 states and 534 transitions. Second operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,741 INFO L74 IsIncluded]: Start isIncluded. First operand 362 states and 534 transitions. Second operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,742 INFO L87 Difference]: Start difference. First operand 362 states and 534 transitions. Second operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,749 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2022-02-21 04:21:45,749 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 534 transitions. [2022-02-21 04:21:45,749 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,749 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,750 INFO L74 IsIncluded]: Start isIncluded. First operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 362 states and 534 transitions. [2022-02-21 04:21:45,751 INFO L87 Difference]: Start difference. First operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 362 states and 534 transitions. [2022-02-21 04:21:45,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:45,758 INFO L93 Difference]: Finished difference Result 362 states and 534 transitions. [2022-02-21 04:21:45,758 INFO L276 IsEmpty]: Start isEmpty. Operand 362 states and 534 transitions. [2022-02-21 04:21:45,759 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:45,759 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:45,759 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:45,759 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:45,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 361 states, 361 states have (on average 1.4764542936288088) internal successors, (533), 360 states have internal predecessors, (533), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 361 states to 361 states and 533 transitions. [2022-02-21 04:21:45,767 INFO L704 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2022-02-21 04:21:45,767 INFO L587 BuchiCegarLoop]: Abstraction has 361 states and 533 transitions. [2022-02-21 04:21:45,767 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:45,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 361 states and 533 transitions. [2022-02-21 04:21:45,768 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 312 [2022-02-21 04:21:45,769 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,769 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,769 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,769 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,770 INFO L791 eck$LassoCheckResult]: Stem: 2680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 2652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2653#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2665#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2563#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 2434#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2435#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2620#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2482#L344 assume !(0 == ~M_E~0); 2483#L344-2 assume !(0 == ~T1_E~0); 2647#L349-1 assume !(0 == ~T2_E~0); 2502#L354-1 assume !(0 == ~E_M~0); 2503#L359-1 assume !(0 == ~E_1~0); 2497#L364-1 assume !(0 == ~E_2~0); 2498#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2579#L166 assume 1 == ~m_pc~0; 2580#L167 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2640#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2480#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2481#L425 assume !(0 != activate_threads_~tmp~1#1); 2678#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2589#L185 assume !(1 == ~t1_pc~0); 2508#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2509#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2546#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2551#L433 assume !(0 != activate_threads_~tmp___0~0#1); 2552#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2601#L204 assume 1 == ~t2_pc~0; 2555#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2556#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2622#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2463#L441 assume !(0 != activate_threads_~tmp___1~0#1); 2464#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2583#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 2605#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2730#L387-1 assume !(1 == ~T2_E~0); 2669#L392-1 assume !(1 == ~E_M~0); 2593#L397-1 assume !(1 == ~E_1~0); 2594#L402-1 assume !(1 == ~E_2~0); 2626#L407-1 assume { :end_inline_reset_delta_events } true; 2695#L553-2 [2022-02-21 04:21:45,770 INFO L793 eck$LassoCheckResult]: Loop: 2695#L553-2 assume !false; 2683#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2654#L319 assume !false; 2623#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2624#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2650#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2651#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2567#L286 assume !(0 != eval_~tmp~0#1); 2569#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2681#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2682#L344-3 assume !(0 == ~M_E~0); 2432#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2433#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L354-3 assume !(0 == ~E_M~0); 2488#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2562#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2560#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2542#L166-12 assume !(1 == ~m_pc~0); 2544#L166-14 is_master_triggered_~__retres1~0#1 := 0; 2512#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2513#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2536#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2537#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2611#L185-12 assume !(1 == ~t1_pc~0); 2494#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 2495#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2777#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2776#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2775#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2774#L204-12 assume 1 == ~t2_pc~0; 2772#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2771#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2770#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2769#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2768#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2767#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2485#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2766#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2765#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2635#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2764#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2763#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2760#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2759#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2758#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2757#L572 assume !(0 == start_simulation_~tmp~3#1); 2505#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2477#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2478#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2461#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2462#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2575#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2576#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2670#L585 assume !(0 != start_simulation_~tmp___0~1#1); 2695#L553-2 [2022-02-21 04:21:45,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,770 INFO L85 PathProgramCache]: Analyzing trace with hash -1712870137, now seen corresponding path program 1 times [2022-02-21 04:21:45,770 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,771 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564678513] [2022-02-21 04:21:45,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,791 INFO L290 TraceCheckUtils]: 0: Hoare triple {3520#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,792 INFO L290 TraceCheckUtils]: 1: Hoare triple {3522#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,792 INFO L290 TraceCheckUtils]: 2: Hoare triple {3522#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,792 INFO L290 TraceCheckUtils]: 3: Hoare triple {3522#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,793 INFO L290 TraceCheckUtils]: 4: Hoare triple {3522#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,793 INFO L290 TraceCheckUtils]: 5: Hoare triple {3522#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,793 INFO L290 TraceCheckUtils]: 6: Hoare triple {3522#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,793 INFO L290 TraceCheckUtils]: 7: Hoare triple {3522#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,794 INFO L290 TraceCheckUtils]: 8: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,794 INFO L290 TraceCheckUtils]: 9: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,794 INFO L290 TraceCheckUtils]: 10: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,795 INFO L290 TraceCheckUtils]: 11: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,795 INFO L290 TraceCheckUtils]: 12: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,795 INFO L290 TraceCheckUtils]: 13: Hoare triple {3522#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,795 INFO L290 TraceCheckUtils]: 14: Hoare triple {3522#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3522#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 15: Hoare triple {3522#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {3521#false} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 16: Hoare triple {3521#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {3521#false} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 17: Hoare triple {3521#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3521#false} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 18: Hoare triple {3521#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {3521#false} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 19: Hoare triple {3521#false} assume !(0 != activate_threads_~tmp~1#1); {3521#false} is VALID [2022-02-21 04:21:45,796 INFO L290 TraceCheckUtils]: 20: Hoare triple {3521#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 21: Hoare triple {3521#false} assume !(1 == ~t1_pc~0); {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 22: Hoare triple {3521#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 23: Hoare triple {3521#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 24: Hoare triple {3521#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 25: Hoare triple {3521#false} assume !(0 != activate_threads_~tmp___0~0#1); {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 26: Hoare triple {3521#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 27: Hoare triple {3521#false} assume 1 == ~t2_pc~0; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 28: Hoare triple {3521#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3521#false} is VALID [2022-02-21 04:21:45,797 INFO L290 TraceCheckUtils]: 29: Hoare triple {3521#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 30: Hoare triple {3521#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 31: Hoare triple {3521#false} assume !(0 != activate_threads_~tmp___1~0#1); {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 32: Hoare triple {3521#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 33: Hoare triple {3521#false} assume 1 == ~M_E~0;~M_E~0 := 2; {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 34: Hoare triple {3521#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 35: Hoare triple {3521#false} assume !(1 == ~T2_E~0); {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 36: Hoare triple {3521#false} assume !(1 == ~E_M~0); {3521#false} is VALID [2022-02-21 04:21:45,798 INFO L290 TraceCheckUtils]: 37: Hoare triple {3521#false} assume !(1 == ~E_1~0); {3521#false} is VALID [2022-02-21 04:21:45,799 INFO L290 TraceCheckUtils]: 38: Hoare triple {3521#false} assume !(1 == ~E_2~0); {3521#false} is VALID [2022-02-21 04:21:45,799 INFO L290 TraceCheckUtils]: 39: Hoare triple {3521#false} assume { :end_inline_reset_delta_events } true; {3521#false} is VALID [2022-02-21 04:21:45,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,799 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,799 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564678513] [2022-02-21 04:21:45,800 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564678513] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,800 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,800 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:45,800 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301422109] [2022-02-21 04:21:45,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,800 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:45,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,801 INFO L85 PathProgramCache]: Analyzing trace with hash -1139110469, now seen corresponding path program 1 times [2022-02-21 04:21:45,801 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:45,801 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723109196] [2022-02-21 04:21:45,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:45,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:45,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:45,830 INFO L290 TraceCheckUtils]: 0: Hoare triple {3523#true} assume !false; {3523#true} is VALID [2022-02-21 04:21:45,831 INFO L290 TraceCheckUtils]: 1: Hoare triple {3523#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3523#true} is VALID [2022-02-21 04:21:45,831 INFO L290 TraceCheckUtils]: 2: Hoare triple {3523#true} assume !false; {3523#true} is VALID [2022-02-21 04:21:45,831 INFO L290 TraceCheckUtils]: 3: Hoare triple {3523#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3523#true} is VALID [2022-02-21 04:21:45,831 INFO L290 TraceCheckUtils]: 4: Hoare triple {3523#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3525#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:45,832 INFO L290 TraceCheckUtils]: 5: Hoare triple {3525#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3526#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:45,832 INFO L290 TraceCheckUtils]: 6: Hoare triple {3526#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {3527#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:45,832 INFO L290 TraceCheckUtils]: 7: Hoare triple {3527#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 8: Hoare triple {3524#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 9: Hoare triple {3524#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 10: Hoare triple {3524#false} assume !(0 == ~M_E~0); {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 11: Hoare triple {3524#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 12: Hoare triple {3524#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 13: Hoare triple {3524#false} assume !(0 == ~E_M~0); {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 14: Hoare triple {3524#false} assume 0 == ~E_1~0;~E_1~0 := 1; {3524#false} is VALID [2022-02-21 04:21:45,833 INFO L290 TraceCheckUtils]: 15: Hoare triple {3524#false} assume 0 == ~E_2~0;~E_2~0 := 1; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 16: Hoare triple {3524#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 17: Hoare triple {3524#false} assume !(1 == ~m_pc~0); {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 18: Hoare triple {3524#false} is_master_triggered_~__retres1~0#1 := 0; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 19: Hoare triple {3524#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 20: Hoare triple {3524#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 21: Hoare triple {3524#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 22: Hoare triple {3524#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 23: Hoare triple {3524#false} assume !(1 == ~t1_pc~0); {3524#false} is VALID [2022-02-21 04:21:45,834 INFO L290 TraceCheckUtils]: 24: Hoare triple {3524#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 25: Hoare triple {3524#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 26: Hoare triple {3524#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 27: Hoare triple {3524#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 28: Hoare triple {3524#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 29: Hoare triple {3524#false} assume 1 == ~t2_pc~0; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 30: Hoare triple {3524#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 31: Hoare triple {3524#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3524#false} is VALID [2022-02-21 04:21:45,835 INFO L290 TraceCheckUtils]: 32: Hoare triple {3524#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 33: Hoare triple {3524#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 34: Hoare triple {3524#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 35: Hoare triple {3524#false} assume 1 == ~M_E~0;~M_E~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 36: Hoare triple {3524#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 37: Hoare triple {3524#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 38: Hoare triple {3524#false} assume 1 == ~E_M~0;~E_M~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 39: Hoare triple {3524#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,836 INFO L290 TraceCheckUtils]: 40: Hoare triple {3524#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 41: Hoare triple {3524#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 42: Hoare triple {3524#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 43: Hoare triple {3524#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 44: Hoare triple {3524#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 45: Hoare triple {3524#false} assume !(0 == start_simulation_~tmp~3#1); {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 46: Hoare triple {3524#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 47: Hoare triple {3524#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 48: Hoare triple {3524#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {3524#false} is VALID [2022-02-21 04:21:45,837 INFO L290 TraceCheckUtils]: 49: Hoare triple {3524#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {3524#false} is VALID [2022-02-21 04:21:45,838 INFO L290 TraceCheckUtils]: 50: Hoare triple {3524#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3524#false} is VALID [2022-02-21 04:21:45,838 INFO L290 TraceCheckUtils]: 51: Hoare triple {3524#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3524#false} is VALID [2022-02-21 04:21:45,838 INFO L290 TraceCheckUtils]: 52: Hoare triple {3524#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {3524#false} is VALID [2022-02-21 04:21:45,838 INFO L290 TraceCheckUtils]: 53: Hoare triple {3524#false} assume !(0 != start_simulation_~tmp___0~1#1); {3524#false} is VALID [2022-02-21 04:21:45,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:45,838 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:45,839 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723109196] [2022-02-21 04:21:45,839 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723109196] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:45,839 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:45,839 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:45,839 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820455933] [2022-02-21 04:21:45,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:45,839 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:45,840 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:45,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:45,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:45,840 INFO L87 Difference]: Start difference. First operand 361 states and 533 transitions. cyclomatic complexity: 174 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,146 INFO L93 Difference]: Finished difference Result 658 states and 955 transitions. [2022-02-21 04:21:46,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:46,147 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,178 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,179 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 658 states and 955 transitions. [2022-02-21 04:21:46,195 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2022-02-21 04:21:46,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 658 states to 658 states and 955 transitions. [2022-02-21 04:21:46,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 658 [2022-02-21 04:21:46,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 658 [2022-02-21 04:21:46,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 658 states and 955 transitions. [2022-02-21 04:21:46,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:46,212 INFO L681 BuchiCegarLoop]: Abstraction has 658 states and 955 transitions. [2022-02-21 04:21:46,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 658 states and 955 transitions. [2022-02-21 04:21:46,222 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 658 to 618. [2022-02-21 04:21:46,222 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:46,223 INFO L82 GeneralOperation]: Start isEquivalent. First operand 658 states and 955 transitions. Second operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,224 INFO L74 IsIncluded]: Start isIncluded. First operand 658 states and 955 transitions. Second operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,225 INFO L87 Difference]: Start difference. First operand 658 states and 955 transitions. Second operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,240 INFO L93 Difference]: Finished difference Result 658 states and 955 transitions. [2022-02-21 04:21:46,241 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 955 transitions. [2022-02-21 04:21:46,241 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,242 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,243 INFO L74 IsIncluded]: Start isIncluded. First operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 658 states and 955 transitions. [2022-02-21 04:21:46,244 INFO L87 Difference]: Start difference. First operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 658 states and 955 transitions. [2022-02-21 04:21:46,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,259 INFO L93 Difference]: Finished difference Result 658 states and 955 transitions. [2022-02-21 04:21:46,260 INFO L276 IsEmpty]: Start isEmpty. Operand 658 states and 955 transitions. [2022-02-21 04:21:46,261 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,261 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,261 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:46,261 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:46,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 618 states, 618 states have (on average 1.4579288025889967) internal successors, (901), 617 states have internal predecessors, (901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 618 states to 618 states and 901 transitions. [2022-02-21 04:21:46,277 INFO L704 BuchiCegarLoop]: Abstraction has 618 states and 901 transitions. [2022-02-21 04:21:46,277 INFO L587 BuchiCegarLoop]: Abstraction has 618 states and 901 transitions. [2022-02-21 04:21:46,277 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:46,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 618 states and 901 transitions. [2022-02-21 04:21:46,280 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 568 [2022-02-21 04:21:46,280 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:46,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:46,282 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,282 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,283 INFO L791 eck$LassoCheckResult]: Stem: 4464#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 4417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4418#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4436#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4323#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 4188#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4189#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4384#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4237#L344 assume !(0 == ~M_E~0); 4238#L344-2 assume !(0 == ~T1_E~0); 4411#L349-1 assume !(0 == ~T2_E~0); 4258#L354-1 assume !(0 == ~E_M~0); 4259#L359-1 assume !(0 == ~E_1~0); 4253#L364-1 assume !(0 == ~E_2~0); 4254#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4344#L166 assume !(1 == ~m_pc~0); 4345#L166-2 is_master_triggered_~__retres1~0#1 := 0; 4420#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4235#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4236#L425 assume !(0 != activate_threads_~tmp~1#1); 4455#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4353#L185 assume !(1 == ~t1_pc~0); 4264#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4265#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4302#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4307#L433 assume !(0 != activate_threads_~tmp___0~0#1); 4308#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4367#L204 assume 1 == ~t2_pc~0; 4312#L205 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4313#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4386#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4217#L441 assume !(0 != activate_threads_~tmp___1~0#1); 4218#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4347#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 4207#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4208#L387-1 assume !(1 == ~T2_E~0); 4328#L392-1 assume !(1 == ~E_M~0); 4359#L397-1 assume !(1 == ~E_1~0); 4360#L402-1 assume !(1 == ~E_2~0); 4348#L407-1 assume { :end_inline_reset_delta_events } true; 4349#L553-2 [2022-02-21 04:21:46,283 INFO L793 eck$LassoCheckResult]: Loop: 4349#L553-2 assume !false; 4564#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4482#L319 assume !false; 4388#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4389#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4415#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4416#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4329#L286 assume !(0 != eval_~tmp~0#1); 4330#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4592#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4593#L344-3 assume !(0 == ~M_E~0); 4186#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4187#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4324#L354-3 assume !(0 == ~E_M~0); 4547#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4546#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4545#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4544#L166-12 assume !(1 == ~m_pc~0); 4543#L166-14 is_master_triggered_~__retres1~0#1 := 0; 4542#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4541#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4540#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4539#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4538#L185-12 assume !(1 == ~t1_pc~0); 4536#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 4535#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4533#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4531#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4529#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4527#L204-12 assume 1 == ~t2_pc~0; 4524#L205-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4522#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4520#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4517#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4515#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4513#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4511#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4509#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4507#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4504#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4502#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4500#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4485#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4483#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4480#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4361#L572 assume !(0 == start_simulation_~tmp~3#1); 4261#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4232#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4233#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4215#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 4216#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4569#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4568#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 4567#L585 assume !(0 != start_simulation_~tmp___0~1#1); 4349#L553-2 [2022-02-21 04:21:46,284 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,284 INFO L85 PathProgramCache]: Analyzing trace with hash 524493128, now seen corresponding path program 1 times [2022-02-21 04:21:46,284 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,284 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30382279] [2022-02-21 04:21:46,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 0: Hoare triple {6123#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 1: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,321 INFO L290 TraceCheckUtils]: 2: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,321 INFO L290 TraceCheckUtils]: 3: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,321 INFO L290 TraceCheckUtils]: 4: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,322 INFO L290 TraceCheckUtils]: 5: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,322 INFO L290 TraceCheckUtils]: 6: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,322 INFO L290 TraceCheckUtils]: 7: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,322 INFO L290 TraceCheckUtils]: 8: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 9: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 10: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 11: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_M~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,324 INFO L290 TraceCheckUtils]: 12: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,324 INFO L290 TraceCheckUtils]: 13: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,324 INFO L290 TraceCheckUtils]: 14: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6125#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 15: Hoare triple {6125#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 16: Hoare triple {6126#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 17: Hoare triple {6126#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 18: Hoare triple {6126#(not (= ~t2_pc~0 1))} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,326 INFO L290 TraceCheckUtils]: 19: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,326 INFO L290 TraceCheckUtils]: 20: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,326 INFO L290 TraceCheckUtils]: 21: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,327 INFO L290 TraceCheckUtils]: 22: Hoare triple {6126#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,327 INFO L290 TraceCheckUtils]: 23: Hoare triple {6126#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,327 INFO L290 TraceCheckUtils]: 24: Hoare triple {6126#(not (= ~t2_pc~0 1))} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,327 INFO L290 TraceCheckUtils]: 25: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 26: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6126#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 27: Hoare triple {6126#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {6124#false} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 28: Hoare triple {6124#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6124#false} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 29: Hoare triple {6124#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6124#false} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 30: Hoare triple {6124#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6124#false} is VALID [2022-02-21 04:21:46,328 INFO L290 TraceCheckUtils]: 31: Hoare triple {6124#false} assume !(0 != activate_threads_~tmp___1~0#1); {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 32: Hoare triple {6124#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 33: Hoare triple {6124#false} assume 1 == ~M_E~0;~M_E~0 := 2; {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 34: Hoare triple {6124#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 35: Hoare triple {6124#false} assume !(1 == ~T2_E~0); {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 36: Hoare triple {6124#false} assume !(1 == ~E_M~0); {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 37: Hoare triple {6124#false} assume !(1 == ~E_1~0); {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 38: Hoare triple {6124#false} assume !(1 == ~E_2~0); {6124#false} is VALID [2022-02-21 04:21:46,329 INFO L290 TraceCheckUtils]: 39: Hoare triple {6124#false} assume { :end_inline_reset_delta_events } true; {6124#false} is VALID [2022-02-21 04:21:46,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,330 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,330 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [30382279] [2022-02-21 04:21:46,330 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [30382279] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,330 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,330 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:46,330 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325136738] [2022-02-21 04:21:46,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,331 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:46,331 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,331 INFO L85 PathProgramCache]: Analyzing trace with hash -1139110469, now seen corresponding path program 2 times [2022-02-21 04:21:46,331 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,331 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729427485] [2022-02-21 04:21:46,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,360 INFO L290 TraceCheckUtils]: 0: Hoare triple {6127#true} assume !false; {6127#true} is VALID [2022-02-21 04:21:46,361 INFO L290 TraceCheckUtils]: 1: Hoare triple {6127#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6127#true} is VALID [2022-02-21 04:21:46,361 INFO L290 TraceCheckUtils]: 2: Hoare triple {6127#true} assume !false; {6127#true} is VALID [2022-02-21 04:21:46,375 INFO L290 TraceCheckUtils]: 3: Hoare triple {6127#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6127#true} is VALID [2022-02-21 04:21:46,376 INFO L290 TraceCheckUtils]: 4: Hoare triple {6127#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6129#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:46,376 INFO L290 TraceCheckUtils]: 5: Hoare triple {6129#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6130#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:46,376 INFO L290 TraceCheckUtils]: 6: Hoare triple {6130#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {6131#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 7: Hoare triple {6131#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {6128#false} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 8: Hoare triple {6128#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6128#false} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 9: Hoare triple {6128#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6128#false} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 10: Hoare triple {6128#false} assume !(0 == ~M_E~0); {6128#false} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 11: Hoare triple {6128#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6128#false} is VALID [2022-02-21 04:21:46,377 INFO L290 TraceCheckUtils]: 12: Hoare triple {6128#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 13: Hoare triple {6128#false} assume !(0 == ~E_M~0); {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 14: Hoare triple {6128#false} assume 0 == ~E_1~0;~E_1~0 := 1; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 15: Hoare triple {6128#false} assume 0 == ~E_2~0;~E_2~0 := 1; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 16: Hoare triple {6128#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 17: Hoare triple {6128#false} assume !(1 == ~m_pc~0); {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 18: Hoare triple {6128#false} is_master_triggered_~__retres1~0#1 := 0; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 19: Hoare triple {6128#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6128#false} is VALID [2022-02-21 04:21:46,378 INFO L290 TraceCheckUtils]: 20: Hoare triple {6128#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 21: Hoare triple {6128#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 22: Hoare triple {6128#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 23: Hoare triple {6128#false} assume !(1 == ~t1_pc~0); {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 24: Hoare triple {6128#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 25: Hoare triple {6128#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 26: Hoare triple {6128#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 27: Hoare triple {6128#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6128#false} is VALID [2022-02-21 04:21:46,379 INFO L290 TraceCheckUtils]: 28: Hoare triple {6128#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 29: Hoare triple {6128#false} assume 1 == ~t2_pc~0; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 30: Hoare triple {6128#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 31: Hoare triple {6128#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 32: Hoare triple {6128#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 33: Hoare triple {6128#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 34: Hoare triple {6128#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 35: Hoare triple {6128#false} assume 1 == ~M_E~0;~M_E~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,380 INFO L290 TraceCheckUtils]: 36: Hoare triple {6128#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 37: Hoare triple {6128#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 38: Hoare triple {6128#false} assume 1 == ~E_M~0;~E_M~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 39: Hoare triple {6128#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 40: Hoare triple {6128#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 41: Hoare triple {6128#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 42: Hoare triple {6128#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 43: Hoare triple {6128#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6128#false} is VALID [2022-02-21 04:21:46,381 INFO L290 TraceCheckUtils]: 44: Hoare triple {6128#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 45: Hoare triple {6128#false} assume !(0 == start_simulation_~tmp~3#1); {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 46: Hoare triple {6128#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 47: Hoare triple {6128#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 48: Hoare triple {6128#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 49: Hoare triple {6128#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 50: Hoare triple {6128#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 51: Hoare triple {6128#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6128#false} is VALID [2022-02-21 04:21:46,382 INFO L290 TraceCheckUtils]: 52: Hoare triple {6128#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {6128#false} is VALID [2022-02-21 04:21:46,383 INFO L290 TraceCheckUtils]: 53: Hoare triple {6128#false} assume !(0 != start_simulation_~tmp___0~1#1); {6128#false} is VALID [2022-02-21 04:21:46,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,383 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,383 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729427485] [2022-02-21 04:21:46,383 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729427485] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,383 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,383 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:46,384 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [387871504] [2022-02-21 04:21:46,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,384 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:46,384 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:46,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:46,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:46,385 INFO L87 Difference]: Start difference. First operand 618 states and 901 transitions. cyclomatic complexity: 287 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,971 INFO L93 Difference]: Finished difference Result 1401 states and 2004 transitions. [2022-02-21 04:21:46,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:46,972 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 10.0) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,995 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,065 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1296 [2022-02-21 04:21:47,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1401 states to 1401 states and 2004 transitions. [2022-02-21 04:21:47,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1401 [2022-02-21 04:21:47,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1401 [2022-02-21 04:21:47,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:47,130 INFO L681 BuchiCegarLoop]: Abstraction has 1401 states and 2004 transitions. [2022-02-21 04:21:47,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1401 to 1118. [2022-02-21 04:21:47,143 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:47,145 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1401 states and 2004 transitions. Second operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,149 INFO L74 IsIncluded]: Start isIncluded. First operand 1401 states and 2004 transitions. Second operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,151 INFO L87 Difference]: Start difference. First operand 1401 states and 2004 transitions. Second operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,213 INFO L93 Difference]: Finished difference Result 1401 states and 2004 transitions. [2022-02-21 04:21:47,213 INFO L276 IsEmpty]: Start isEmpty. Operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,215 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,215 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,217 INFO L74 IsIncluded]: Start isIncluded. First operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,219 INFO L87 Difference]: Start difference. First operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,270 INFO L93 Difference]: Finished difference Result 1401 states and 2004 transitions. [2022-02-21 04:21:47,270 INFO L276 IsEmpty]: Start isEmpty. Operand 1401 states and 2004 transitions. [2022-02-21 04:21:47,272 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,272 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,273 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:47,273 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:47,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1118 states, 1118 states have (on average 1.4445438282647585) internal successors, (1615), 1117 states have internal predecessors, (1615), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1615 transitions. [2022-02-21 04:21:47,311 INFO L704 BuchiCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2022-02-21 04:21:47,311 INFO L587 BuchiCegarLoop]: Abstraction has 1118 states and 1615 transitions. [2022-02-21 04:21:47,311 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:47,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1118 states and 1615 transitions. [2022-02-21 04:21:47,315 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1067 [2022-02-21 04:21:47,315 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:47,315 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:47,315 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,315 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,316 INFO L791 eck$LassoCheckResult]: Stem: 7808#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 7770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7771#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7791#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7673#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 7537#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7538#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7736#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7588#L344 assume !(0 == ~M_E~0); 7589#L344-2 assume !(0 == ~T1_E~0); 7764#L349-1 assume !(0 == ~T2_E~0); 7609#L354-1 assume !(0 == ~E_M~0); 7610#L359-1 assume !(0 == ~E_1~0); 7604#L364-1 assume !(0 == ~E_2~0); 7605#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7689#L166 assume !(1 == ~m_pc~0); 7690#L166-2 is_master_triggered_~__retres1~0#1 := 0; 7776#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7586#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7587#L425 assume !(0 != activate_threads_~tmp~1#1); 7803#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7700#L185 assume !(1 == ~t1_pc~0); 7615#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7616#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7654#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7660#L433 assume !(0 != activate_threads_~tmp___0~0#1); 7661#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7718#L204 assume !(1 == ~t2_pc~0); 7698#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7699#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7738#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7568#L441 assume !(0 != activate_threads_~tmp___1~0#1); 7569#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7692#L382 assume 1 == ~M_E~0;~M_E~0 := 2; 7723#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7675#L387-1 assume !(1 == ~T2_E~0); 7676#L392-1 assume !(1 == ~E_M~0); 7706#L397-1 assume !(1 == ~E_1~0); 7707#L402-1 assume !(1 == ~E_2~0); 7693#L407-1 assume { :end_inline_reset_delta_events } true; 7694#L553-2 [2022-02-21 04:21:47,316 INFO L793 eck$LassoCheckResult]: Loop: 7694#L553-2 assume !false; 7785#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7780#L319 assume !false; 7739#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7625#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7626#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7613#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7614#L286 assume !(0 != eval_~tmp~0#1); 7595#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7596#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7796#L344-3 assume !(0 == ~M_E~0); 7535#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7536#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8637#L354-3 assume !(0 == ~E_M~0); 7703#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7704#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8636#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8635#L166-12 assume !(1 == ~m_pc~0); 7782#L166-14 is_master_triggered_~__retres1~0#1 := 0; 7621#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7622#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7645#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7646#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7729#L185-12 assume !(1 == ~t1_pc~0); 7600#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 7601#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7755#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7797#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7743#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7744#L204-12 assume !(1 == ~t2_pc~0); 7630#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 7631#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7617#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7618#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7663#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7664#L382-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7591#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7672#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7751#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7549#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7550#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7561#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7546#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7547#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7570#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7711#L572 assume !(0 == start_simulation_~tmp~3#1); 7612#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7583#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7584#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7566#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7567#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7682#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7683#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 7789#L585 assume !(0 != start_simulation_~tmp___0~1#1); 7694#L553-2 [2022-02-21 04:21:47,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,316 INFO L85 PathProgramCache]: Analyzing trace with hash -754831607, now seen corresponding path program 1 times [2022-02-21 04:21:47,317 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,317 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68913799] [2022-02-21 04:21:47,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,349 INFO L290 TraceCheckUtils]: 0: Hoare triple {11458#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,350 INFO L290 TraceCheckUtils]: 1: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,350 INFO L290 TraceCheckUtils]: 2: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,353 INFO L290 TraceCheckUtils]: 3: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,353 INFO L290 TraceCheckUtils]: 4: Hoare triple {11460#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,354 INFO L290 TraceCheckUtils]: 5: Hoare triple {11460#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,354 INFO L290 TraceCheckUtils]: 6: Hoare triple {11460#(= ~M_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,354 INFO L290 TraceCheckUtils]: 7: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,354 INFO L290 TraceCheckUtils]: 8: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~M_E~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,355 INFO L290 TraceCheckUtils]: 9: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~T1_E~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,355 INFO L290 TraceCheckUtils]: 10: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~T2_E~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,355 INFO L290 TraceCheckUtils]: 11: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~E_M~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,356 INFO L290 TraceCheckUtils]: 12: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~E_1~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,356 INFO L290 TraceCheckUtils]: 13: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 == ~E_2~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,356 INFO L290 TraceCheckUtils]: 14: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,357 INFO L290 TraceCheckUtils]: 15: Hoare triple {11460#(= ~M_E~0 2)} assume !(1 == ~m_pc~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,357 INFO L290 TraceCheckUtils]: 16: Hoare triple {11460#(= ~M_E~0 2)} is_master_triggered_~__retres1~0#1 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,371 INFO L290 TraceCheckUtils]: 17: Hoare triple {11460#(= ~M_E~0 2)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 18: Hoare triple {11460#(= ~M_E~0 2)} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 19: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp~1#1); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 20: Hoare triple {11460#(= ~M_E~0 2)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 21: Hoare triple {11460#(= ~M_E~0 2)} assume !(1 == ~t1_pc~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 22: Hoare triple {11460#(= ~M_E~0 2)} is_transmit1_triggered_~__retres1~1#1 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 23: Hoare triple {11460#(= ~M_E~0 2)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 24: Hoare triple {11460#(= ~M_E~0 2)} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 25: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___0~0#1); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 26: Hoare triple {11460#(= ~M_E~0 2)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 27: Hoare triple {11460#(= ~M_E~0 2)} assume !(1 == ~t2_pc~0); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 28: Hoare triple {11460#(= ~M_E~0 2)} is_transmit2_triggered_~__retres1~2#1 := 0; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 29: Hoare triple {11460#(= ~M_E~0 2)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 30: Hoare triple {11460#(= ~M_E~0 2)} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,376 INFO L290 TraceCheckUtils]: 31: Hoare triple {11460#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___1~0#1); {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,376 INFO L290 TraceCheckUtils]: 32: Hoare triple {11460#(= ~M_E~0 2)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11460#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:47,376 INFO L290 TraceCheckUtils]: 33: Hoare triple {11460#(= ~M_E~0 2)} assume 1 == ~M_E~0;~M_E~0 := 2; {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 34: Hoare triple {11459#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 35: Hoare triple {11459#false} assume !(1 == ~T2_E~0); {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 36: Hoare triple {11459#false} assume !(1 == ~E_M~0); {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 37: Hoare triple {11459#false} assume !(1 == ~E_1~0); {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 38: Hoare triple {11459#false} assume !(1 == ~E_2~0); {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L290 TraceCheckUtils]: 39: Hoare triple {11459#false} assume { :end_inline_reset_delta_events } true; {11459#false} is VALID [2022-02-21 04:21:47,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,378 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,378 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [68913799] [2022-02-21 04:21:47,378 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [68913799] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,378 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,378 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:47,378 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1460307767] [2022-02-21 04:21:47,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,378 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:47,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1098252796, now seen corresponding path program 1 times [2022-02-21 04:21:47,379 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,379 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906543199] [2022-02-21 04:21:47,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,414 INFO L290 TraceCheckUtils]: 0: Hoare triple {11461#true} assume !false; {11461#true} is VALID [2022-02-21 04:21:47,414 INFO L290 TraceCheckUtils]: 1: Hoare triple {11461#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {11461#true} is VALID [2022-02-21 04:21:47,414 INFO L290 TraceCheckUtils]: 2: Hoare triple {11461#true} assume !false; {11461#true} is VALID [2022-02-21 04:21:47,414 INFO L290 TraceCheckUtils]: 3: Hoare triple {11461#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {11461#true} is VALID [2022-02-21 04:21:47,415 INFO L290 TraceCheckUtils]: 4: Hoare triple {11461#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {11463#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:47,415 INFO L290 TraceCheckUtils]: 5: Hoare triple {11463#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {11464#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:47,415 INFO L290 TraceCheckUtils]: 6: Hoare triple {11464#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {11465#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 7: Hoare triple {11465#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 8: Hoare triple {11462#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 9: Hoare triple {11462#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 10: Hoare triple {11462#false} assume !(0 == ~M_E~0); {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 11: Hoare triple {11462#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 12: Hoare triple {11462#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 13: Hoare triple {11462#false} assume !(0 == ~E_M~0); {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 14: Hoare triple {11462#false} assume 0 == ~E_1~0;~E_1~0 := 1; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 15: Hoare triple {11462#false} assume 0 == ~E_2~0;~E_2~0 := 1; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 16: Hoare triple {11462#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 17: Hoare triple {11462#false} assume !(1 == ~m_pc~0); {11462#false} is VALID [2022-02-21 04:21:47,416 INFO L290 TraceCheckUtils]: 18: Hoare triple {11462#false} is_master_triggered_~__retres1~0#1 := 0; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 19: Hoare triple {11462#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 20: Hoare triple {11462#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 21: Hoare triple {11462#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 22: Hoare triple {11462#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 23: Hoare triple {11462#false} assume !(1 == ~t1_pc~0); {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 24: Hoare triple {11462#false} is_transmit1_triggered_~__retres1~1#1 := 0; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 25: Hoare triple {11462#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 26: Hoare triple {11462#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 27: Hoare triple {11462#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 28: Hoare triple {11462#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11462#false} is VALID [2022-02-21 04:21:47,422 INFO L290 TraceCheckUtils]: 29: Hoare triple {11462#false} assume !(1 == ~t2_pc~0); {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 30: Hoare triple {11462#false} is_transmit2_triggered_~__retres1~2#1 := 0; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 31: Hoare triple {11462#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 32: Hoare triple {11462#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 33: Hoare triple {11462#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 34: Hoare triple {11462#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 35: Hoare triple {11462#false} assume 1 == ~M_E~0;~M_E~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 36: Hoare triple {11462#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 37: Hoare triple {11462#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 38: Hoare triple {11462#false} assume 1 == ~E_M~0;~E_M~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 39: Hoare triple {11462#false} assume 1 == ~E_1~0;~E_1~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 40: Hoare triple {11462#false} assume 1 == ~E_2~0;~E_2~0 := 2; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 41: Hoare triple {11462#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 42: Hoare triple {11462#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 43: Hoare triple {11462#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 44: Hoare triple {11462#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 45: Hoare triple {11462#false} assume !(0 == start_simulation_~tmp~3#1); {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 46: Hoare triple {11462#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {11462#false} is VALID [2022-02-21 04:21:47,423 INFO L290 TraceCheckUtils]: 47: Hoare triple {11462#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 48: Hoare triple {11462#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 49: Hoare triple {11462#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 50: Hoare triple {11462#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 51: Hoare triple {11462#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 52: Hoare triple {11462#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L290 TraceCheckUtils]: 53: Hoare triple {11462#false} assume !(0 != start_simulation_~tmp___0~1#1); {11462#false} is VALID [2022-02-21 04:21:47,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,424 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,424 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906543199] [2022-02-21 04:21:47,424 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906543199] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,424 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,424 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:47,425 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920742175] [2022-02-21 04:21:47,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,425 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:47,425 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:47,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:47,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:47,425 INFO L87 Difference]: Start difference. First operand 1118 states and 1615 transitions. cyclomatic complexity: 501 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,705 INFO L93 Difference]: Finished difference Result 1641 states and 2364 transitions. [2022-02-21 04:21:47,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:47,705 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,731 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:47,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1641 states and 2364 transitions. [2022-02-21 04:21:47,812 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1591 [2022-02-21 04:21:47,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1641 states to 1641 states and 2364 transitions. [2022-02-21 04:21:47,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1641 [2022-02-21 04:21:47,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1641 [2022-02-21 04:21:47,881 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1641 states and 2364 transitions. [2022-02-21 04:21:47,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:47,883 INFO L681 BuchiCegarLoop]: Abstraction has 1641 states and 2364 transitions. [2022-02-21 04:21:47,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1641 states and 2364 transitions. [2022-02-21 04:21:47,895 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1641 to 1181. [2022-02-21 04:21:47,895 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:47,897 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1641 states and 2364 transitions. Second operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,898 INFO L74 IsIncluded]: Start isIncluded. First operand 1641 states and 2364 transitions. Second operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,900 INFO L87 Difference]: Start difference. First operand 1641 states and 2364 transitions. Second operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,964 INFO L93 Difference]: Finished difference Result 1641 states and 2364 transitions. [2022-02-21 04:21:47,965 INFO L276 IsEmpty]: Start isEmpty. Operand 1641 states and 2364 transitions. [2022-02-21 04:21:47,967 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,967 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,969 INFO L74 IsIncluded]: Start isIncluded. First operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1641 states and 2364 transitions. [2022-02-21 04:21:47,970 INFO L87 Difference]: Start difference. First operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1641 states and 2364 transitions. [2022-02-21 04:21:48,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,039 INFO L93 Difference]: Finished difference Result 1641 states and 2364 transitions. [2022-02-21 04:21:48,039 INFO L276 IsEmpty]: Start isEmpty. Operand 1641 states and 2364 transitions. [2022-02-21 04:21:48,041 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,041 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,041 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,041 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4428450465707028) internal successors, (1704), 1180 states have internal predecessors, (1704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1704 transitions. [2022-02-21 04:21:48,081 INFO L704 BuchiCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2022-02-21 04:21:48,081 INFO L587 BuchiCegarLoop]: Abstraction has 1181 states and 1704 transitions. [2022-02-21 04:21:48,081 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:48,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1704 transitions. [2022-02-21 04:21:48,085 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-02-21 04:21:48,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,086 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,088 INFO L791 eck$LassoCheckResult]: Stem: 13379#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 13334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 13335#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13358#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13242#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 13109#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13110#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13303#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13160#L344 assume !(0 == ~M_E~0); 13161#L344-2 assume !(0 == ~T1_E~0); 13329#L349-1 assume !(0 == ~T2_E~0); 13180#L354-1 assume !(0 == ~E_M~0); 13181#L359-1 assume !(0 == ~E_1~0); 13175#L364-1 assume !(0 == ~E_2~0); 13176#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13259#L166 assume !(1 == ~m_pc~0); 13260#L166-2 is_master_triggered_~__retres1~0#1 := 0; 13341#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13158#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 13159#L425 assume !(0 != activate_threads_~tmp~1#1); 13374#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13271#L185 assume !(1 == ~t1_pc~0); 13186#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13187#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13226#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 13231#L433 assume !(0 != activate_threads_~tmp___0~0#1); 13232#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13287#L204 assume !(1 == ~t2_pc~0); 13269#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13270#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13305#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13140#L441 assume !(0 != activate_threads_~tmp___1~0#1); 13141#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13263#L382 assume !(1 == ~M_E~0); 13128#L382-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13129#L387-1 assume !(1 == ~T2_E~0); 13244#L392-1 assume !(1 == ~E_M~0); 13277#L397-1 assume !(1 == ~E_1~0); 13278#L402-1 assume !(1 == ~E_2~0); 13266#L407-1 assume { :end_inline_reset_delta_events } true; 13267#L553-2 [2022-02-21 04:21:48,088 INFO L793 eck$LassoCheckResult]: Loop: 13267#L553-2 assume !false; 14210#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13362#L319 assume !false; 13306#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13196#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13197#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13333#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13245#L286 assume !(0 != eval_~tmp~0#1); 13246#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14275#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14274#L344-3 assume !(0 == ~M_E~0); 14273#L344-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14271#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14269#L354-3 assume !(0 == ~E_M~0); 14268#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14265#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14243#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14206#L166-12 assume !(1 == ~m_pc~0); 14205#L166-14 is_master_triggered_~__retres1~0#1 := 0; 14204#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14203#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14202#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14201#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14200#L185-12 assume !(1 == ~t1_pc~0); 14198#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 14197#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14196#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14195#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14191#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13491#L204-12 assume !(1 == ~t2_pc~0); 13487#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 13484#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13481#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13479#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13477#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13470#L382-3 assume !(1 == ~M_E~0); 13465#L382-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13463#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13461#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13459#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13457#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13455#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 13450#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 13441#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 13437#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 13430#L572 assume !(0 == start_simulation_~tmp~3#1); 13431#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 14218#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 14216#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 14215#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 14214#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14213#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14212#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 14211#L585 assume !(0 != start_simulation_~tmp___0~1#1); 13267#L553-2 [2022-02-21 04:21:48,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1020175755, now seen corresponding path program 1 times [2022-02-21 04:21:48,089 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,089 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544332188] [2022-02-21 04:21:48,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,137 INFO L290 TraceCheckUtils]: 0: Hoare triple {17573#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,138 INFO L290 TraceCheckUtils]: 1: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,138 INFO L290 TraceCheckUtils]: 2: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,138 INFO L290 TraceCheckUtils]: 3: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,139 INFO L290 TraceCheckUtils]: 4: Hoare triple {17575#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,139 INFO L290 TraceCheckUtils]: 5: Hoare triple {17575#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,139 INFO L290 TraceCheckUtils]: 6: Hoare triple {17575#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,139 INFO L290 TraceCheckUtils]: 7: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,140 INFO L290 TraceCheckUtils]: 8: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,140 INFO L290 TraceCheckUtils]: 9: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~T1_E~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,140 INFO L290 TraceCheckUtils]: 10: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~T2_E~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,141 INFO L290 TraceCheckUtils]: 11: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~E_M~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,141 INFO L290 TraceCheckUtils]: 12: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~E_1~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,141 INFO L290 TraceCheckUtils]: 13: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 == ~E_2~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,141 INFO L290 TraceCheckUtils]: 14: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,142 INFO L290 TraceCheckUtils]: 15: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(1 == ~m_pc~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,142 INFO L290 TraceCheckUtils]: 16: Hoare triple {17575#(<= 2 ~T1_E~0)} is_master_triggered_~__retres1~0#1 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,142 INFO L290 TraceCheckUtils]: 17: Hoare triple {17575#(<= 2 ~T1_E~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,142 INFO L290 TraceCheckUtils]: 18: Hoare triple {17575#(<= 2 ~T1_E~0)} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,143 INFO L290 TraceCheckUtils]: 19: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 != activate_threads_~tmp~1#1); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,143 INFO L290 TraceCheckUtils]: 20: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,143 INFO L290 TraceCheckUtils]: 21: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(1 == ~t1_pc~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,144 INFO L290 TraceCheckUtils]: 22: Hoare triple {17575#(<= 2 ~T1_E~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,144 INFO L290 TraceCheckUtils]: 23: Hoare triple {17575#(<= 2 ~T1_E~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,144 INFO L290 TraceCheckUtils]: 24: Hoare triple {17575#(<= 2 ~T1_E~0)} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,145 INFO L290 TraceCheckUtils]: 25: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 != activate_threads_~tmp___0~0#1); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,145 INFO L290 TraceCheckUtils]: 26: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,145 INFO L290 TraceCheckUtils]: 27: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(1 == ~t2_pc~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,146 INFO L290 TraceCheckUtils]: 28: Hoare triple {17575#(<= 2 ~T1_E~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,146 INFO L290 TraceCheckUtils]: 29: Hoare triple {17575#(<= 2 ~T1_E~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,146 INFO L290 TraceCheckUtils]: 30: Hoare triple {17575#(<= 2 ~T1_E~0)} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,146 INFO L290 TraceCheckUtils]: 31: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(0 != activate_threads_~tmp___1~0#1); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,147 INFO L290 TraceCheckUtils]: 32: Hoare triple {17575#(<= 2 ~T1_E~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,147 INFO L290 TraceCheckUtils]: 33: Hoare triple {17575#(<= 2 ~T1_E~0)} assume !(1 == ~M_E~0); {17575#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:48,147 INFO L290 TraceCheckUtils]: 34: Hoare triple {17575#(<= 2 ~T1_E~0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17574#false} is VALID [2022-02-21 04:21:48,147 INFO L290 TraceCheckUtils]: 35: Hoare triple {17574#false} assume !(1 == ~T2_E~0); {17574#false} is VALID [2022-02-21 04:21:48,148 INFO L290 TraceCheckUtils]: 36: Hoare triple {17574#false} assume !(1 == ~E_M~0); {17574#false} is VALID [2022-02-21 04:21:48,148 INFO L290 TraceCheckUtils]: 37: Hoare triple {17574#false} assume !(1 == ~E_1~0); {17574#false} is VALID [2022-02-21 04:21:48,148 INFO L290 TraceCheckUtils]: 38: Hoare triple {17574#false} assume !(1 == ~E_2~0); {17574#false} is VALID [2022-02-21 04:21:48,148 INFO L290 TraceCheckUtils]: 39: Hoare triple {17574#false} assume { :end_inline_reset_delta_events } true; {17574#false} is VALID [2022-02-21 04:21:48,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,148 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,148 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544332188] [2022-02-21 04:21:48,149 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544332188] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,149 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,149 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:48,149 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175459738] [2022-02-21 04:21:48,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,149 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:48,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,150 INFO L85 PathProgramCache]: Analyzing trace with hash -590690946, now seen corresponding path program 1 times [2022-02-21 04:21:48,150 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,150 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009643490] [2022-02-21 04:21:48,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,199 INFO L290 TraceCheckUtils]: 0: Hoare triple {17576#true} assume !false; {17576#true} is VALID [2022-02-21 04:21:48,199 INFO L290 TraceCheckUtils]: 1: Hoare triple {17576#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17576#true} is VALID [2022-02-21 04:21:48,199 INFO L290 TraceCheckUtils]: 2: Hoare triple {17576#true} assume !false; {17576#true} is VALID [2022-02-21 04:21:48,199 INFO L290 TraceCheckUtils]: 3: Hoare triple {17576#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {17576#true} is VALID [2022-02-21 04:21:48,200 INFO L290 TraceCheckUtils]: 4: Hoare triple {17576#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {17578#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:48,200 INFO L290 TraceCheckUtils]: 5: Hoare triple {17578#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {17579#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:48,200 INFO L290 TraceCheckUtils]: 6: Hoare triple {17579#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {17580#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 7: Hoare triple {17580#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 8: Hoare triple {17577#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 9: Hoare triple {17577#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 10: Hoare triple {17577#false} assume !(0 == ~M_E~0); {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 11: Hoare triple {17577#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 12: Hoare triple {17577#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 13: Hoare triple {17577#false} assume !(0 == ~E_M~0); {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 14: Hoare triple {17577#false} assume 0 == ~E_1~0;~E_1~0 := 1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 15: Hoare triple {17577#false} assume 0 == ~E_2~0;~E_2~0 := 1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 16: Hoare triple {17577#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 17: Hoare triple {17577#false} assume !(1 == ~m_pc~0); {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 18: Hoare triple {17577#false} is_master_triggered_~__retres1~0#1 := 0; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 19: Hoare triple {17577#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 20: Hoare triple {17577#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 21: Hoare triple {17577#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 22: Hoare triple {17577#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 23: Hoare triple {17577#false} assume !(1 == ~t1_pc~0); {17577#false} is VALID [2022-02-21 04:21:48,201 INFO L290 TraceCheckUtils]: 24: Hoare triple {17577#false} is_transmit1_triggered_~__retres1~1#1 := 0; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 25: Hoare triple {17577#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 26: Hoare triple {17577#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 27: Hoare triple {17577#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 28: Hoare triple {17577#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 29: Hoare triple {17577#false} assume !(1 == ~t2_pc~0); {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 30: Hoare triple {17577#false} is_transmit2_triggered_~__retres1~2#1 := 0; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 31: Hoare triple {17577#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 32: Hoare triple {17577#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 33: Hoare triple {17577#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 34: Hoare triple {17577#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 35: Hoare triple {17577#false} assume !(1 == ~M_E~0); {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 36: Hoare triple {17577#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 37: Hoare triple {17577#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 38: Hoare triple {17577#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 39: Hoare triple {17577#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 40: Hoare triple {17577#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 41: Hoare triple {17577#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 42: Hoare triple {17577#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {17577#false} is VALID [2022-02-21 04:21:48,202 INFO L290 TraceCheckUtils]: 43: Hoare triple {17577#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 44: Hoare triple {17577#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 45: Hoare triple {17577#false} assume !(0 == start_simulation_~tmp~3#1); {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 46: Hoare triple {17577#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 47: Hoare triple {17577#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 48: Hoare triple {17577#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 49: Hoare triple {17577#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 50: Hoare triple {17577#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 51: Hoare triple {17577#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 52: Hoare triple {17577#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L290 TraceCheckUtils]: 53: Hoare triple {17577#false} assume !(0 != start_simulation_~tmp___0~1#1); {17577#false} is VALID [2022-02-21 04:21:48,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,203 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,203 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2009643490] [2022-02-21 04:21:48,203 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2009643490] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,204 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,204 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:48,204 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834229762] [2022-02-21 04:21:48,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,204 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:48,204 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:48,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:48,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:48,205 INFO L87 Difference]: Start difference. First operand 1181 states and 1704 transitions. cyclomatic complexity: 525 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,395 INFO L93 Difference]: Finished difference Result 1181 states and 1678 transitions. [2022-02-21 04:21:48,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:48,396 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 2 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,419 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:48,421 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,458 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-02-21 04:21:48,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1181 states to 1181 states and 1678 transitions. [2022-02-21 04:21:48,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1181 [2022-02-21 04:21:48,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1181 [2022-02-21 04:21:48,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:48,496 INFO L681 BuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-02-21 04:21:48,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1181 to 1181. [2022-02-21 04:21:48,506 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:48,508 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1181 states and 1678 transitions. Second operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,515 INFO L74 IsIncluded]: Start isIncluded. First operand 1181 states and 1678 transitions. Second operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,517 INFO L87 Difference]: Start difference. First operand 1181 states and 1678 transitions. Second operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,564 INFO L93 Difference]: Finished difference Result 1181 states and 1678 transitions. [2022-02-21 04:21:48,564 INFO L276 IsEmpty]: Start isEmpty. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,565 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,565 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,567 INFO L74 IsIncluded]: Start isIncluded. First operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,568 INFO L87 Difference]: Start difference. First operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,602 INFO L93 Difference]: Finished difference Result 1181 states and 1678 transitions. [2022-02-21 04:21:48,603 INFO L276 IsEmpty]: Start isEmpty. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,604 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,604 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,604 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,604 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1181 states, 1181 states have (on average 1.4208298052497883) internal successors, (1678), 1180 states have internal predecessors, (1678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1181 states to 1181 states and 1678 transitions. [2022-02-21 04:21:48,640 INFO L704 BuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-02-21 04:21:48,640 INFO L587 BuchiCegarLoop]: Abstraction has 1181 states and 1678 transitions. [2022-02-21 04:21:48,640 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:48,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1181 states and 1678 transitions. [2022-02-21 04:21:48,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1136 [2022-02-21 04:21:48,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,644 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,644 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,644 INFO L791 eck$LassoCheckResult]: Stem: 19031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 18991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18992#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19010#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18900#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 18764#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18765#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18960#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18814#L344 assume !(0 == ~M_E~0); 18815#L344-2 assume !(0 == ~T1_E~0); 18986#L349-1 assume !(0 == ~T2_E~0); 18833#L354-1 assume !(0 == ~E_M~0); 18834#L359-1 assume !(0 == ~E_1~0); 18828#L364-1 assume !(0 == ~E_2~0); 18829#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18916#L166 assume !(1 == ~m_pc~0); 18917#L166-2 is_master_triggered_~__retres1~0#1 := 0; 18995#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18812#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18813#L425 assume !(0 != activate_threads_~tmp~1#1); 19026#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18929#L185 assume !(1 == ~t1_pc~0); 18839#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18840#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18880#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18886#L433 assume !(0 != activate_threads_~tmp___0~0#1); 18887#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18945#L204 assume !(1 == ~t2_pc~0); 18927#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18928#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18963#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 18794#L441 assume !(0 != activate_threads_~tmp___1~0#1); 18795#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18920#L382 assume !(1 == ~M_E~0); 18783#L382-2 assume !(1 == ~T1_E~0); 18784#L387-1 assume !(1 == ~T2_E~0); 18903#L392-1 assume !(1 == ~E_M~0); 18935#L397-1 assume !(1 == ~E_1~0); 18936#L402-1 assume !(1 == ~E_2~0); 18923#L407-1 assume { :end_inline_reset_delta_events } true; 18924#L553-2 [2022-02-21 04:21:48,645 INFO L793 eck$LassoCheckResult]: Loop: 18924#L553-2 assume !false; 19143#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19110#L319 assume !false; 19138#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 19139#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19132#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19133#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19127#L286 assume !(0 != eval_~tmp~0#1); 19129#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19296#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19297#L344-3 assume !(0 == ~M_E~0); 19288#L344-5 assume !(0 == ~T1_E~0); 19289#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19280#L354-3 assume !(0 == ~E_M~0); 19281#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19274#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19275#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19266#L166-12 assume !(1 == ~m_pc~0); 19267#L166-14 is_master_triggered_~__retres1~0#1 := 0; 19258#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19259#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 19250#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19251#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19241#L185-12 assume !(1 == ~t1_pc~0); 19242#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 19233#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19234#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 19226#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19227#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19221#L204-12 assume !(1 == ~t2_pc~0); 19219#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 19217#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19215#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 19213#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19211#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19209#L382-3 assume !(1 == ~M_E~0); 19208#L382-5 assume !(1 == ~T1_E~0); 19445#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19444#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19443#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19442#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19441#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 19438#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19437#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19436#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 19435#L572 assume !(0 == start_simulation_~tmp~3#1); 19433#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 19169#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 19167#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 19162#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 19158#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19159#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19425#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 19423#L585 assume !(0 != start_simulation_~tmp___0~1#1); 18924#L553-2 [2022-02-21 04:21:48,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,645 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 1 times [2022-02-21 04:21:48,645 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,645 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505509367] [2022-02-21 04:21:48,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,651 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:48,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:48,681 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:48,682 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,682 INFO L85 PathProgramCache]: Analyzing trace with hash 812738366, now seen corresponding path program 1 times [2022-02-21 04:21:48,682 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,682 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188424708] [2022-02-21 04:21:48,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,718 INFO L290 TraceCheckUtils]: 0: Hoare triple {22310#true} assume !false; {22310#true} is VALID [2022-02-21 04:21:48,718 INFO L290 TraceCheckUtils]: 1: Hoare triple {22310#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {22310#true} is VALID [2022-02-21 04:21:48,718 INFO L290 TraceCheckUtils]: 2: Hoare triple {22310#true} assume !false; {22310#true} is VALID [2022-02-21 04:21:48,718 INFO L290 TraceCheckUtils]: 3: Hoare triple {22310#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {22310#true} is VALID [2022-02-21 04:21:48,719 INFO L290 TraceCheckUtils]: 4: Hoare triple {22310#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {22312#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} is VALID [2022-02-21 04:21:48,719 INFO L290 TraceCheckUtils]: 5: Hoare triple {22312#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~3#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {22313#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:48,719 INFO L290 TraceCheckUtils]: 6: Hoare triple {22313#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {22314#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:48,719 INFO L290 TraceCheckUtils]: 7: Hoare triple {22314#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 8: Hoare triple {22311#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 9: Hoare triple {22311#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 10: Hoare triple {22311#false} assume !(0 == ~M_E~0); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 11: Hoare triple {22311#false} assume !(0 == ~T1_E~0); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 12: Hoare triple {22311#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 13: Hoare triple {22311#false} assume !(0 == ~E_M~0); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 14: Hoare triple {22311#false} assume 0 == ~E_1~0;~E_1~0 := 1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 15: Hoare triple {22311#false} assume 0 == ~E_2~0;~E_2~0 := 1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 16: Hoare triple {22311#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 17: Hoare triple {22311#false} assume !(1 == ~m_pc~0); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 18: Hoare triple {22311#false} is_master_triggered_~__retres1~0#1 := 0; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 19: Hoare triple {22311#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 20: Hoare triple {22311#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 21: Hoare triple {22311#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 22: Hoare triple {22311#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 23: Hoare triple {22311#false} assume !(1 == ~t1_pc~0); {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 24: Hoare triple {22311#false} is_transmit1_triggered_~__retres1~1#1 := 0; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 25: Hoare triple {22311#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 26: Hoare triple {22311#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {22311#false} is VALID [2022-02-21 04:21:48,720 INFO L290 TraceCheckUtils]: 27: Hoare triple {22311#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 28: Hoare triple {22311#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 29: Hoare triple {22311#false} assume !(1 == ~t2_pc~0); {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 30: Hoare triple {22311#false} is_transmit2_triggered_~__retres1~2#1 := 0; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 31: Hoare triple {22311#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 32: Hoare triple {22311#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 33: Hoare triple {22311#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 34: Hoare triple {22311#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 35: Hoare triple {22311#false} assume !(1 == ~M_E~0); {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 36: Hoare triple {22311#false} assume !(1 == ~T1_E~0); {22311#false} is VALID [2022-02-21 04:21:48,721 INFO L290 TraceCheckUtils]: 37: Hoare triple {22311#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {22311#false} is VALID [2022-02-21 04:21:48,723 INFO L290 TraceCheckUtils]: 38: Hoare triple {22311#false} assume 1 == ~E_M~0;~E_M~0 := 2; {22311#false} is VALID [2022-02-21 04:21:48,723 INFO L290 TraceCheckUtils]: 39: Hoare triple {22311#false} assume 1 == ~E_1~0;~E_1~0 := 2; {22311#false} is VALID [2022-02-21 04:21:48,723 INFO L290 TraceCheckUtils]: 40: Hoare triple {22311#false} assume 1 == ~E_2~0;~E_2~0 := 2; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 41: Hoare triple {22311#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 42: Hoare triple {22311#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 43: Hoare triple {22311#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 44: Hoare triple {22311#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 45: Hoare triple {22311#false} assume !(0 == start_simulation_~tmp~3#1); {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 46: Hoare triple {22311#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 47: Hoare triple {22311#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 48: Hoare triple {22311#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 49: Hoare triple {22311#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 50: Hoare triple {22311#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 51: Hoare triple {22311#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 52: Hoare triple {22311#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L290 TraceCheckUtils]: 53: Hoare triple {22311#false} assume !(0 != start_simulation_~tmp___0~1#1); {22311#false} is VALID [2022-02-21 04:21:48,724 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,725 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,725 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188424708] [2022-02-21 04:21:48,726 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188424708] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,726 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,726 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:48,728 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043789495] [2022-02-21 04:21:48,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,729 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:48,729 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:48,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:48,731 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:48,731 INFO L87 Difference]: Start difference. First operand 1181 states and 1678 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,342 INFO L93 Difference]: Finished difference Result 2033 states and 2838 transitions. [2022-02-21 04:21:49,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:21:49,342 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 10.8) internal successors, (54), 5 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,366 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:49,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2033 states and 2838 transitions. [2022-02-21 04:21:49,541 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1984 [2022-02-21 04:21:49,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2033 states to 2033 states and 2838 transitions. [2022-02-21 04:21:49,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2033 [2022-02-21 04:21:49,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2033 [2022-02-21 04:21:49,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2033 states and 2838 transitions. [2022-02-21 04:21:49,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:49,677 INFO L681 BuchiCegarLoop]: Abstraction has 2033 states and 2838 transitions. [2022-02-21 04:21:49,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2033 states and 2838 transitions. [2022-02-21 04:21:49,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2033 to 1205. [2022-02-21 04:21:49,691 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:49,715 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2033 states and 2838 transitions. Second operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,716 INFO L74 IsIncluded]: Start isIncluded. First operand 2033 states and 2838 transitions. Second operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,719 INFO L87 Difference]: Start difference. First operand 2033 states and 2838 transitions. Second operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,840 INFO L93 Difference]: Finished difference Result 2033 states and 2838 transitions. [2022-02-21 04:21:49,840 INFO L276 IsEmpty]: Start isEmpty. Operand 2033 states and 2838 transitions. [2022-02-21 04:21:49,843 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:49,843 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:49,861 INFO L74 IsIncluded]: Start isIncluded. First operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2033 states and 2838 transitions. [2022-02-21 04:21:49,864 INFO L87 Difference]: Start difference. First operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2033 states and 2838 transitions. [2022-02-21 04:21:50,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,026 INFO L93 Difference]: Finished difference Result 2033 states and 2838 transitions. [2022-02-21 04:21:50,026 INFO L276 IsEmpty]: Start isEmpty. Operand 2033 states and 2838 transitions. [2022-02-21 04:21:50,046 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,047 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,047 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:50,047 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:50,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1205 states, 1205 states have (on average 1.412448132780083) internal successors, (1702), 1204 states have internal predecessors, (1702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1205 states to 1205 states and 1702 transitions. [2022-02-21 04:21:50,116 INFO L704 BuchiCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2022-02-21 04:21:50,116 INFO L587 BuchiCegarLoop]: Abstraction has 1205 states and 1702 transitions. [2022-02-21 04:21:50,116 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:50,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1205 states and 1702 transitions. [2022-02-21 04:21:50,120 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1160 [2022-02-21 04:21:50,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:50,120 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:50,135 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,135 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,136 INFO L791 eck$LassoCheckResult]: Stem: 24629#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 24583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 24584#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24602#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24488#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 24358#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24359#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24556#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24409#L344 assume !(0 == ~M_E~0); 24410#L344-2 assume !(0 == ~T1_E~0); 24576#L349-1 assume !(0 == ~T2_E~0); 24428#L354-1 assume !(0 == ~E_M~0); 24429#L359-1 assume !(0 == ~E_1~0); 24423#L364-1 assume !(0 == ~E_2~0); 24424#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24509#L166 assume !(1 == ~m_pc~0); 24510#L166-2 is_master_triggered_~__retres1~0#1 := 0; 24587#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24407#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24408#L425 assume !(0 != activate_threads_~tmp~1#1); 24623#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24523#L185 assume !(1 == ~t1_pc~0); 24434#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24435#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24473#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24479#L433 assume !(0 != activate_threads_~tmp___0~0#1); 24480#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24540#L204 assume !(1 == ~t2_pc~0); 24521#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24522#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24558#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24389#L441 assume !(0 != activate_threads_~tmp___1~0#1); 24390#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24515#L382 assume !(1 == ~M_E~0); 24377#L382-2 assume !(1 == ~T1_E~0); 24378#L387-1 assume !(1 == ~T2_E~0); 24495#L392-1 assume !(1 == ~E_M~0); 24530#L397-1 assume !(1 == ~E_1~0); 24531#L402-1 assume !(1 == ~E_2~0); 24516#L407-1 assume { :end_inline_reset_delta_events } true; 24517#L553-2 [2022-02-21 04:21:50,136 INFO L793 eck$LassoCheckResult]: Loop: 24517#L553-2 assume !false; 24597#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25510#L319 assume !false; 24559#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24444#L254 assume !(0 == ~m_st~0); 24446#L258 assume !(0 == ~t1_st~0); 24579#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 24580#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24581#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25272#L286 assume !(0 != eval_~tmp~0#1); 24415#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24416#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24610#L344-3 assume !(0 == ~M_E~0); 24356#L344-5 assume !(0 == ~T1_E~0); 24357#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25490#L354-3 assume !(0 == ~E_M~0); 24526#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24487#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24485#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24470#L166-12 assume !(1 == ~m_pc~0); 24471#L166-14 is_master_triggered_~__retres1~0#1 := 0; 24440#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24441#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 24464#L425-12 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24465#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24550#L185-12 assume !(1 == ~t1_pc~0); 24420#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 24421#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24569#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 25484#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24561#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24562#L204-12 assume !(1 == ~t2_pc~0); 24448#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 24449#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24436#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24437#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24482#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24411#L382-3 assume !(1 == ~M_E~0); 24412#L382-5 assume !(1 == ~T1_E~0); 24490#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24544#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 24370#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24371#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24381#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24382#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25543#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 25542#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 25541#L572 assume !(0 == start_simulation_~tmp~3#1); 25540#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 25538#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 25535#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24387#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 24388#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25531#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24606#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 24600#L585 assume !(0 != start_simulation_~tmp___0~1#1); 24517#L553-2 [2022-02-21 04:21:50,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 2 times [2022-02-21 04:21:50,136 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,136 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043219771] [2022-02-21 04:21:50,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:50,149 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:50,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:50,165 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:50,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,166 INFO L85 PathProgramCache]: Analyzing trace with hash -60432105, now seen corresponding path program 1 times [2022-02-21 04:21:50,166 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,166 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776632407] [2022-02-21 04:21:50,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 0: Hoare triple {29632#true} assume !false; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 1: Hoare triple {29632#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 2: Hoare triple {29632#true} assume !false; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 3: Hoare triple {29632#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 4: Hoare triple {29632#true} assume !(0 == ~m_st~0); {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 5: Hoare triple {29632#true} assume !(0 == ~t1_st~0); {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 6: Hoare triple {29632#true} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 7: Hoare triple {29632#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 8: Hoare triple {29632#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 9: Hoare triple {29632#true} assume !(0 != eval_~tmp~0#1); {29632#true} is VALID [2022-02-21 04:21:50,275 INFO L290 TraceCheckUtils]: 10: Hoare triple {29632#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 11: Hoare triple {29632#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 12: Hoare triple {29632#true} assume !(0 == ~M_E~0); {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 13: Hoare triple {29632#true} assume !(0 == ~T1_E~0); {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 14: Hoare triple {29632#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 15: Hoare triple {29632#true} assume !(0 == ~E_M~0); {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 16: Hoare triple {29632#true} assume 0 == ~E_1~0;~E_1~0 := 1; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 17: Hoare triple {29632#true} assume 0 == ~E_2~0;~E_2~0 := 1; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 18: Hoare triple {29632#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {29632#true} is VALID [2022-02-21 04:21:50,276 INFO L290 TraceCheckUtils]: 19: Hoare triple {29632#true} assume !(1 == ~m_pc~0); {29632#true} is VALID [2022-02-21 04:21:50,287 INFO L290 TraceCheckUtils]: 20: Hoare triple {29632#true} is_master_triggered_~__retres1~0#1 := 0; {29634#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:50,287 INFO L290 TraceCheckUtils]: 21: Hoare triple {29634#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {29635#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 22: Hoare triple {29635#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {29636#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 23: Hoare triple {29636#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 24: Hoare triple {29633#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 25: Hoare triple {29633#false} assume !(1 == ~t1_pc~0); {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 26: Hoare triple {29633#false} is_transmit1_triggered_~__retres1~1#1 := 0; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 27: Hoare triple {29633#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 28: Hoare triple {29633#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 29: Hoare triple {29633#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 30: Hoare triple {29633#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 31: Hoare triple {29633#false} assume !(1 == ~t2_pc~0); {29633#false} is VALID [2022-02-21 04:21:50,288 INFO L290 TraceCheckUtils]: 32: Hoare triple {29633#false} is_transmit2_triggered_~__retres1~2#1 := 0; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 33: Hoare triple {29633#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 34: Hoare triple {29633#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 35: Hoare triple {29633#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 36: Hoare triple {29633#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 37: Hoare triple {29633#false} assume !(1 == ~M_E~0); {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 38: Hoare triple {29633#false} assume !(1 == ~T1_E~0); {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 39: Hoare triple {29633#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 40: Hoare triple {29633#false} assume 1 == ~E_M~0;~E_M~0 := 2; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 41: Hoare triple {29633#false} assume 1 == ~E_1~0;~E_1~0 := 2; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 42: Hoare triple {29633#false} assume 1 == ~E_2~0;~E_2~0 := 2; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 43: Hoare triple {29633#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 44: Hoare triple {29633#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 45: Hoare triple {29633#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 46: Hoare triple {29633#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 47: Hoare triple {29633#false} assume !(0 == start_simulation_~tmp~3#1); {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 48: Hoare triple {29633#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 49: Hoare triple {29633#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 50: Hoare triple {29633#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 51: Hoare triple {29633#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 52: Hoare triple {29633#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {29633#false} is VALID [2022-02-21 04:21:50,289 INFO L290 TraceCheckUtils]: 53: Hoare triple {29633#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {29633#false} is VALID [2022-02-21 04:21:50,290 INFO L290 TraceCheckUtils]: 54: Hoare triple {29633#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {29633#false} is VALID [2022-02-21 04:21:50,290 INFO L290 TraceCheckUtils]: 55: Hoare triple {29633#false} assume !(0 != start_simulation_~tmp___0~1#1); {29633#false} is VALID [2022-02-21 04:21:50,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,290 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,290 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776632407] [2022-02-21 04:21:50,290 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776632407] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,290 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,290 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:50,290 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932571339] [2022-02-21 04:21:50,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,290 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:50,291 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:50,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:50,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:50,291 INFO L87 Difference]: Start difference. First operand 1205 states and 1702 transitions. cyclomatic complexity: 499 Second operand has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,450 INFO L93 Difference]: Finished difference Result 2347 states and 3283 transitions. [2022-02-21 04:21:51,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:51,450 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 11.2) internal successors, (56), 5 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,484 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:51,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2347 states and 3283 transitions. [2022-02-21 04:21:51,648 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2302 [2022-02-21 04:21:51,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2347 states to 2347 states and 3283 transitions. [2022-02-21 04:21:51,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2347 [2022-02-21 04:21:51,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2347 [2022-02-21 04:21:51,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2347 states and 3283 transitions. [2022-02-21 04:21:51,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:51,771 INFO L681 BuchiCegarLoop]: Abstraction has 2347 states and 3283 transitions. [2022-02-21 04:21:51,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2347 states and 3283 transitions. [2022-02-21 04:21:51,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2347 to 1253. [2022-02-21 04:21:51,788 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:51,790 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2347 states and 3283 transitions. Second operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,790 INFO L74 IsIncluded]: Start isIncluded. First operand 2347 states and 3283 transitions. Second operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,791 INFO L87 Difference]: Start difference. First operand 2347 states and 3283 transitions. Second operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,909 INFO L93 Difference]: Finished difference Result 2347 states and 3283 transitions. [2022-02-21 04:21:51,909 INFO L276 IsEmpty]: Start isEmpty. Operand 2347 states and 3283 transitions. [2022-02-21 04:21:51,912 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:51,912 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:51,914 INFO L74 IsIncluded]: Start isIncluded. First operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2347 states and 3283 transitions. [2022-02-21 04:21:51,915 INFO L87 Difference]: Start difference. First operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2347 states and 3283 transitions. [2022-02-21 04:21:52,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,034 INFO L93 Difference]: Finished difference Result 2347 states and 3283 transitions. [2022-02-21 04:21:52,034 INFO L276 IsEmpty]: Start isEmpty. Operand 2347 states and 3283 transitions. [2022-02-21 04:21:52,036 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,036 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,036 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:52,036 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:52,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1253 states, 1253 states have (on average 1.386272944932163) internal successors, (1737), 1252 states have internal predecessors, (1737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1253 states to 1253 states and 1737 transitions. [2022-02-21 04:21:52,071 INFO L704 BuchiCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2022-02-21 04:21:52,071 INFO L587 BuchiCegarLoop]: Abstraction has 1253 states and 1737 transitions. [2022-02-21 04:21:52,071 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:52,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1253 states and 1737 transitions. [2022-02-21 04:21:52,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1208 [2022-02-21 04:21:52,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:52,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:52,075 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,076 INFO L791 eck$LassoCheckResult]: Stem: 32277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 32225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 32226#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32250#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32123#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 31991#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31992#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32188#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32041#L344 assume !(0 == ~M_E~0); 32042#L344-2 assume !(0 == ~T1_E~0); 32220#L349-1 assume !(0 == ~T2_E~0); 32061#L354-1 assume !(0 == ~E_M~0); 32062#L359-1 assume !(0 == ~E_1~0); 32056#L364-1 assume !(0 == ~E_2~0); 32057#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32143#L166 assume !(1 == ~m_pc~0); 32144#L166-2 is_master_triggered_~__retres1~0#1 := 0; 32233#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32039#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32040#L425 assume !(0 != activate_threads_~tmp~1#1); 32268#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32155#L185 assume !(1 == ~t1_pc~0); 32067#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32068#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32105#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32112#L433 assume !(0 != activate_threads_~tmp___0~0#1); 32113#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32170#L204 assume !(1 == ~t2_pc~0); 32153#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32154#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32190#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32022#L441 assume !(0 != activate_threads_~tmp___1~0#1); 32023#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32146#L382 assume !(1 == ~M_E~0); 32010#L382-2 assume !(1 == ~T1_E~0); 32011#L387-1 assume !(1 == ~T2_E~0); 32129#L392-1 assume !(1 == ~E_M~0); 32159#L397-1 assume !(1 == ~E_1~0); 32160#L402-1 assume !(1 == ~E_2~0); 32147#L407-1 assume { :end_inline_reset_delta_events } true; 32148#L553-2 [2022-02-21 04:21:52,076 INFO L793 eck$LassoCheckResult]: Loop: 32148#L553-2 assume !false; 32613#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32610#L319 assume !false; 32609#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 32608#L254 assume !(0 == ~m_st~0); 32607#L258 assume !(0 == ~t1_st~0); 32604#L262 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 32602#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32600#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 32595#L286 assume !(0 != eval_~tmp~0#1); 32591#L334 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32586#L224-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32580#L344-3 assume !(0 == ~M_E~0); 32581#L344-5 assume !(0 == ~T1_E~0); 32571#L349-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32572#L354-3 assume !(0 == ~E_M~0); 32567#L359-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32568#L364-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32554#L369-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32555#L166-12 assume !(1 == ~m_pc~0); 32520#L166-14 is_master_triggered_~__retres1~0#1 := 0; 32521#L177-4 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32514#L178-4 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 32515#L425-12 assume !(0 != activate_threads_~tmp~1#1); 32509#L425-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32505#L185-12 assume !(1 == ~t1_pc~0); 32506#L185-14 is_transmit1_triggered_~__retres1~1#1 := 0; 32485#L196-4 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32486#L197-4 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 32477#L433-12 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32478#L433-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32470#L204-12 assume !(1 == ~t2_pc~0); 32468#L204-14 is_transmit2_triggered_~__retres1~2#1 := 0; 32466#L215-4 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32464#L216-4 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32462#L441-12 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32460#L441-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32458#L382-3 assume !(1 == ~M_E~0); 32457#L382-5 assume !(1 == ~T1_E~0); 32687#L387-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32686#L392-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32685#L397-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32684#L402-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32683#L407-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 32641#L254-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 32640#L271-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32639#L272-1 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 32638#L572 assume !(0 == start_simulation_~tmp~3#1); 32636#L572-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 32634#L254-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 32632#L271-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32631#L272-2 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 32629#L527 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32627#L534 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32624#L535 start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 32623#L585 assume !(0 != start_simulation_~tmp___0~1#1); 32148#L553-2 [2022-02-21 04:21:52,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1077434057, now seen corresponding path program 3 times [2022-02-21 04:21:52,077 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,077 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1335688995] [2022-02-21 04:21:52,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,086 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:52,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,092 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:52,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,092 INFO L85 PathProgramCache]: Analyzing trace with hash -132818663, now seen corresponding path program 1 times [2022-02-21 04:21:52,092 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,093 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307458024] [2022-02-21 04:21:52,093 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,106 INFO L290 TraceCheckUtils]: 0: Hoare triple {37941#true} assume !false; {37941#true} is VALID [2022-02-21 04:21:52,107 INFO L290 TraceCheckUtils]: 1: Hoare triple {37941#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37941#true} is VALID [2022-02-21 04:21:52,107 INFO L290 TraceCheckUtils]: 2: Hoare triple {37941#true} assume !false; {37941#true} is VALID [2022-02-21 04:21:52,107 INFO L290 TraceCheckUtils]: 3: Hoare triple {37941#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {37941#true} is VALID [2022-02-21 04:21:52,107 INFO L290 TraceCheckUtils]: 4: Hoare triple {37941#true} assume !(0 == ~m_st~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,107 INFO L290 TraceCheckUtils]: 5: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,108 INFO L290 TraceCheckUtils]: 6: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,108 INFO L290 TraceCheckUtils]: 7: Hoare triple {37943#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,108 INFO L290 TraceCheckUtils]: 8: Hoare triple {37943#(not (= ~m_st~0 0))} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,108 INFO L290 TraceCheckUtils]: 9: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,109 INFO L290 TraceCheckUtils]: 10: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,109 INFO L290 TraceCheckUtils]: 11: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,109 INFO L290 TraceCheckUtils]: 12: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 == ~M_E~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,110 INFO L290 TraceCheckUtils]: 13: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 == ~T1_E~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,110 INFO L290 TraceCheckUtils]: 14: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 == ~T2_E~0;~T2_E~0 := 1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,110 INFO L290 TraceCheckUtils]: 15: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 == ~E_M~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,110 INFO L290 TraceCheckUtils]: 16: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,111 INFO L290 TraceCheckUtils]: 17: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 == ~E_2~0;~E_2~0 := 1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,111 INFO L290 TraceCheckUtils]: 18: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,111 INFO L290 TraceCheckUtils]: 19: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,111 INFO L290 TraceCheckUtils]: 20: Hoare triple {37943#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,112 INFO L290 TraceCheckUtils]: 21: Hoare triple {37943#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,112 INFO L290 TraceCheckUtils]: 22: Hoare triple {37943#(not (= ~m_st~0 0))} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,112 INFO L290 TraceCheckUtils]: 23: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,112 INFO L290 TraceCheckUtils]: 24: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,113 INFO L290 TraceCheckUtils]: 25: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,113 INFO L290 TraceCheckUtils]: 26: Hoare triple {37943#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,113 INFO L290 TraceCheckUtils]: 27: Hoare triple {37943#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,114 INFO L290 TraceCheckUtils]: 28: Hoare triple {37943#(not (= ~m_st~0 0))} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,114 INFO L290 TraceCheckUtils]: 29: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,114 INFO L290 TraceCheckUtils]: 30: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,114 INFO L290 TraceCheckUtils]: 31: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(1 == ~t2_pc~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,115 INFO L290 TraceCheckUtils]: 32: Hoare triple {37943#(not (= ~m_st~0 0))} is_transmit2_triggered_~__retres1~2#1 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,115 INFO L290 TraceCheckUtils]: 33: Hoare triple {37943#(not (= ~m_st~0 0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,115 INFO L290 TraceCheckUtils]: 34: Hoare triple {37943#(not (= ~m_st~0 0))} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,115 INFO L290 TraceCheckUtils]: 35: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,116 INFO L290 TraceCheckUtils]: 36: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,116 INFO L290 TraceCheckUtils]: 37: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(1 == ~M_E~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,116 INFO L290 TraceCheckUtils]: 38: Hoare triple {37943#(not (= ~m_st~0 0))} assume !(1 == ~T1_E~0); {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,116 INFO L290 TraceCheckUtils]: 39: Hoare triple {37943#(not (= ~m_st~0 0))} assume 1 == ~T2_E~0;~T2_E~0 := 2; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,117 INFO L290 TraceCheckUtils]: 40: Hoare triple {37943#(not (= ~m_st~0 0))} assume 1 == ~E_M~0;~E_M~0 := 2; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,117 INFO L290 TraceCheckUtils]: 41: Hoare triple {37943#(not (= ~m_st~0 0))} assume 1 == ~E_1~0;~E_1~0 := 2; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,117 INFO L290 TraceCheckUtils]: 42: Hoare triple {37943#(not (= ~m_st~0 0))} assume 1 == ~E_2~0;~E_2~0 := 2; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,117 INFO L290 TraceCheckUtils]: 43: Hoare triple {37943#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {37943#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 44: Hoare triple {37943#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 45: Hoare triple {37942#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 46: Hoare triple {37942#false} start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 47: Hoare triple {37942#false} assume !(0 == start_simulation_~tmp~3#1); {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 48: Hoare triple {37942#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 49: Hoare triple {37942#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 50: Hoare triple {37942#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {37942#false} is VALID [2022-02-21 04:21:52,118 INFO L290 TraceCheckUtils]: 51: Hoare triple {37942#false} stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; {37942#false} is VALID [2022-02-21 04:21:52,119 INFO L290 TraceCheckUtils]: 52: Hoare triple {37942#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37942#false} is VALID [2022-02-21 04:21:52,119 INFO L290 TraceCheckUtils]: 53: Hoare triple {37942#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37942#false} is VALID [2022-02-21 04:21:52,119 INFO L290 TraceCheckUtils]: 54: Hoare triple {37942#false} start_simulation_#t~ret14#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; {37942#false} is VALID [2022-02-21 04:21:52,119 INFO L290 TraceCheckUtils]: 55: Hoare triple {37942#false} assume !(0 != start_simulation_~tmp___0~1#1); {37942#false} is VALID [2022-02-21 04:21:52,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,119 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,119 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1307458024] [2022-02-21 04:21:52,119 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1307458024] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,120 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,120 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:52,120 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [711329883] [2022-02-21 04:21:52,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,120 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:52,120 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:52,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:52,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:52,121 INFO L87 Difference]: Start difference. First operand 1253 states and 1737 transitions. cyclomatic complexity: 486 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,454 INFO L93 Difference]: Finished difference Result 1866 states and 2547 transitions. [2022-02-21 04:21:52,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:52,454 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,492 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:52,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,576 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1821 [2022-02-21 04:21:52,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1866 states to 1866 states and 2547 transitions. [2022-02-21 04:21:52,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1866 [2022-02-21 04:21:52,651 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1866 [2022-02-21 04:21:52,651 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:52,653 INFO L681 BuchiCegarLoop]: Abstraction has 1866 states and 2547 transitions. [2022-02-21 04:21:52,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1866 to 1804. [2022-02-21 04:21:52,670 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:52,672 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1866 states and 2547 transitions. Second operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,673 INFO L74 IsIncluded]: Start isIncluded. First operand 1866 states and 2547 transitions. Second operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,675 INFO L87 Difference]: Start difference. First operand 1866 states and 2547 transitions. Second operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,747 INFO L93 Difference]: Finished difference Result 1866 states and 2547 transitions. [2022-02-21 04:21:52,747 INFO L276 IsEmpty]: Start isEmpty. Operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,749 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,749 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,751 INFO L74 IsIncluded]: Start isIncluded. First operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,752 INFO L87 Difference]: Start difference. First operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,826 INFO L93 Difference]: Finished difference Result 1866 states and 2547 transitions. [2022-02-21 04:21:52,826 INFO L276 IsEmpty]: Start isEmpty. Operand 1866 states and 2547 transitions. [2022-02-21 04:21:52,828 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,828 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,828 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:52,828 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:52,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1804 states, 1804 states have (on average 1.3664079822616408) internal successors, (2465), 1803 states have internal predecessors, (2465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1804 states to 1804 states and 2465 transitions. [2022-02-21 04:21:52,897 INFO L704 BuchiCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2022-02-21 04:21:52,897 INFO L587 BuchiCegarLoop]: Abstraction has 1804 states and 2465 transitions. [2022-02-21 04:21:52,897 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:21:52,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1804 states and 2465 transitions. [2022-02-21 04:21:52,901 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1759 [2022-02-21 04:21:52,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:52,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:52,902 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,902 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,902 INFO L791 eck$LassoCheckResult]: Stem: 40102#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 40049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 40050#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40076#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39943#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 39812#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39813#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40015#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39861#L344 assume !(0 == ~M_E~0); 39862#L344-2 assume !(0 == ~T1_E~0); 40043#L349-1 assume !(0 == ~T2_E~0); 39881#L354-1 assume !(0 == ~E_M~0); 39882#L359-1 assume !(0 == ~E_1~0); 39876#L364-1 assume !(0 == ~E_2~0); 39877#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39967#L166 assume !(1 == ~m_pc~0); 39968#L166-2 is_master_triggered_~__retres1~0#1 := 0; 40058#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39859#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 39860#L425 assume !(0 != activate_threads_~tmp~1#1); 40094#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39979#L185 assume !(1 == ~t1_pc~0); 39887#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39888#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39926#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 39932#L433 assume !(0 != activate_threads_~tmp___0~0#1); 39933#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39996#L204 assume !(1 == ~t2_pc~0); 39977#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39978#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40017#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39844#L441 assume !(0 != activate_threads_~tmp___1~0#1); 39845#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39971#L382 assume !(1 == ~M_E~0); 39832#L382-2 assume !(1 == ~T1_E~0); 39833#L387-1 assume !(1 == ~T2_E~0); 39950#L392-1 assume !(1 == ~E_M~0); 39986#L397-1 assume !(1 == ~E_1~0); 39987#L402-1 assume !(1 == ~E_2~0); 39972#L407-1 assume { :end_inline_reset_delta_events } true; 39973#L553-2 assume !false; 40701#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40657#L319 [2022-02-21 04:21:52,902 INFO L793 eck$LassoCheckResult]: Loop: 40657#L319 assume !false; 40698#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40694#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40691#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40688#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40683#L286 assume 0 != eval_~tmp~0#1; 40677#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40672#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 40665#L291 assume !(0 == ~t1_st~0); 40661#L305 assume !(0 == ~t2_st~0); 40657#L319 [2022-02-21 04:21:52,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,902 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 1 times [2022-02-21 04:21:52,903 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,903 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170522487] [2022-02-21 04:21:52,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,911 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:52,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,926 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:52,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,927 INFO L85 PathProgramCache]: Analyzing trace with hash 698755222, now seen corresponding path program 1 times [2022-02-21 04:21:52,927 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,928 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691263756] [2022-02-21 04:21:52,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,931 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:52,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:52,934 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:52,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1780390720, now seen corresponding path program 1 times [2022-02-21 04:21:52,935 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,935 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254327388] [2022-02-21 04:21:52,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,963 INFO L290 TraceCheckUtils]: 0: Hoare triple {45353#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {45353#true} is VALID [2022-02-21 04:21:52,963 INFO L290 TraceCheckUtils]: 1: Hoare triple {45353#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {45353#true} is VALID [2022-02-21 04:21:52,963 INFO L290 TraceCheckUtils]: 2: Hoare triple {45353#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {45353#true} is VALID [2022-02-21 04:21:52,964 INFO L290 TraceCheckUtils]: 3: Hoare triple {45353#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {45353#true} is VALID [2022-02-21 04:21:52,964 INFO L290 TraceCheckUtils]: 4: Hoare triple {45353#true} assume 1 == ~m_i~0;~m_st~0 := 0; {45353#true} is VALID [2022-02-21 04:21:52,964 INFO L290 TraceCheckUtils]: 5: Hoare triple {45353#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,964 INFO L290 TraceCheckUtils]: 6: Hoare triple {45355#(= ~t1_st~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,964 INFO L290 TraceCheckUtils]: 7: Hoare triple {45355#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,965 INFO L290 TraceCheckUtils]: 8: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,965 INFO L290 TraceCheckUtils]: 9: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,965 INFO L290 TraceCheckUtils]: 10: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~T2_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,965 INFO L290 TraceCheckUtils]: 11: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~E_M~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,966 INFO L290 TraceCheckUtils]: 12: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,966 INFO L290 TraceCheckUtils]: 13: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~E_2~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,966 INFO L290 TraceCheckUtils]: 14: Hoare triple {45355#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,966 INFO L290 TraceCheckUtils]: 15: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,967 INFO L290 TraceCheckUtils]: 16: Hoare triple {45355#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,967 INFO L290 TraceCheckUtils]: 17: Hoare triple {45355#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,967 INFO L290 TraceCheckUtils]: 18: Hoare triple {45355#(= ~t1_st~0 0)} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,968 INFO L290 TraceCheckUtils]: 19: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,968 INFO L290 TraceCheckUtils]: 20: Hoare triple {45355#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,968 INFO L290 TraceCheckUtils]: 21: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,968 INFO L290 TraceCheckUtils]: 22: Hoare triple {45355#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,969 INFO L290 TraceCheckUtils]: 23: Hoare triple {45355#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,969 INFO L290 TraceCheckUtils]: 24: Hoare triple {45355#(= ~t1_st~0 0)} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,969 INFO L290 TraceCheckUtils]: 25: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,969 INFO L290 TraceCheckUtils]: 26: Hoare triple {45355#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,970 INFO L290 TraceCheckUtils]: 27: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~t2_pc~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,970 INFO L290 TraceCheckUtils]: 28: Hoare triple {45355#(= ~t1_st~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,970 INFO L290 TraceCheckUtils]: 29: Hoare triple {45355#(= ~t1_st~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,971 INFO L290 TraceCheckUtils]: 30: Hoare triple {45355#(= ~t1_st~0 0)} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,971 INFO L290 TraceCheckUtils]: 31: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,971 INFO L290 TraceCheckUtils]: 32: Hoare triple {45355#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,971 INFO L290 TraceCheckUtils]: 33: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,972 INFO L290 TraceCheckUtils]: 34: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,972 INFO L290 TraceCheckUtils]: 35: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~T2_E~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,972 INFO L290 TraceCheckUtils]: 36: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~E_M~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,972 INFO L290 TraceCheckUtils]: 37: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,973 INFO L290 TraceCheckUtils]: 38: Hoare triple {45355#(= ~t1_st~0 0)} assume !(1 == ~E_2~0); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,973 INFO L290 TraceCheckUtils]: 39: Hoare triple {45355#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,973 INFO L290 TraceCheckUtils]: 40: Hoare triple {45355#(= ~t1_st~0 0)} assume !false; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,973 INFO L290 TraceCheckUtils]: 41: Hoare triple {45355#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,974 INFO L290 TraceCheckUtils]: 42: Hoare triple {45355#(= ~t1_st~0 0)} assume !false; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,974 INFO L290 TraceCheckUtils]: 43: Hoare triple {45355#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,974 INFO L290 TraceCheckUtils]: 44: Hoare triple {45355#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,974 INFO L290 TraceCheckUtils]: 45: Hoare triple {45355#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,975 INFO L290 TraceCheckUtils]: 46: Hoare triple {45355#(= ~t1_st~0 0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,975 INFO L290 TraceCheckUtils]: 47: Hoare triple {45355#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,975 INFO L290 TraceCheckUtils]: 48: Hoare triple {45355#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,975 INFO L290 TraceCheckUtils]: 49: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {45355#(= ~t1_st~0 0)} is VALID [2022-02-21 04:21:52,976 INFO L290 TraceCheckUtils]: 50: Hoare triple {45355#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {45354#false} is VALID [2022-02-21 04:21:52,976 INFO L290 TraceCheckUtils]: 51: Hoare triple {45354#false} assume !(0 == ~t2_st~0); {45354#false} is VALID [2022-02-21 04:21:52,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,976 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,977 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254327388] [2022-02-21 04:21:52,977 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254327388] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,977 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,977 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:52,977 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778578651] [2022-02-21 04:21:52,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,036 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:53,036 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:53,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:53,036 INFO L87 Difference]: Start difference. First operand 1804 states and 2465 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,471 INFO L93 Difference]: Finished difference Result 3072 states and 4139 transitions. [2022-02-21 04:21:53,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:53,471 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.333333333333332) internal successors, (52), 3 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,496 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:53,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3072 states and 4139 transitions. [2022-02-21 04:21:53,818 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2988 [2022-02-21 04:21:54,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3072 states to 3072 states and 4139 transitions. [2022-02-21 04:21:54,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3072 [2022-02-21 04:21:54,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3072 [2022-02-21 04:21:54,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,083 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:54,083 INFO L681 BuchiCegarLoop]: Abstraction has 3072 states and 4139 transitions. [2022-02-21 04:21:54,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3072 to 2925. [2022-02-21 04:21:54,107 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:54,110 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3072 states and 4139 transitions. Second operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,112 INFO L74 IsIncluded]: Start isIncluded. First operand 3072 states and 4139 transitions. Second operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,115 INFO L87 Difference]: Start difference. First operand 3072 states and 4139 transitions. Second operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,311 INFO L93 Difference]: Finished difference Result 3072 states and 4139 transitions. [2022-02-21 04:21:54,311 INFO L276 IsEmpty]: Start isEmpty. Operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,313 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:54,313 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:54,317 INFO L74 IsIncluded]: Start isIncluded. First operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,320 INFO L87 Difference]: Start difference. First operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,529 INFO L93 Difference]: Finished difference Result 3072 states and 4139 transitions. [2022-02-21 04:21:54,529 INFO L276 IsEmpty]: Start isEmpty. Operand 3072 states and 4139 transitions. [2022-02-21 04:21:54,531 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:54,531 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:54,531 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:54,532 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:54,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2925 states, 2925 states have (on average 1.3552136752136752) internal successors, (3964), 2924 states have internal predecessors, (3964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2925 states to 2925 states and 3964 transitions. [2022-02-21 04:21:54,724 INFO L704 BuchiCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2022-02-21 04:21:54,724 INFO L587 BuchiCegarLoop]: Abstraction has 2925 states and 3964 transitions. [2022-02-21 04:21:54,724 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:21:54,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2925 states and 3964 transitions. [2022-02-21 04:21:54,730 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-02-21 04:21:54,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:54,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:54,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,730 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,731 INFO L791 eck$LassoCheckResult]: Stem: 48745#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 48677#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 48678#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48707#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48567#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 48430#L231-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 48431#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48642#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48480#L344 assume !(0 == ~M_E~0); 48481#L344-2 assume !(0 == ~T1_E~0); 48670#L349-1 assume !(0 == ~T2_E~0); 48500#L354-1 assume !(0 == ~E_M~0); 48501#L359-1 assume !(0 == ~E_1~0); 48495#L364-1 assume !(0 == ~E_2~0); 48496#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48592#L166 assume !(1 == ~m_pc~0); 48593#L166-2 is_master_triggered_~__retres1~0#1 := 0; 48682#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48478#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 48479#L425 assume !(0 != activate_threads_~tmp~1#1); 48736#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48604#L185 assume !(1 == ~t1_pc~0); 48506#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48507#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48547#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 48553#L433 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48554#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50349#L204 assume !(1 == ~t2_pc~0); 50348#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 50347#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50346#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 50345#L441 assume !(0 != activate_threads_~tmp___1~0#1); 50344#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50343#L382 assume !(1 == ~M_E~0); 50342#L382-2 assume !(1 == ~T1_E~0); 50341#L387-1 assume !(1 == ~T2_E~0); 50340#L392-1 assume !(1 == ~E_M~0); 48611#L397-1 assume !(1 == ~E_1~0); 48612#L402-1 assume !(1 == ~E_2~0); 48597#L407-1 assume { :end_inline_reset_delta_events } true; 48598#L553-2 assume !false; 50853#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50489#L319 [2022-02-21 04:21:54,731 INFO L793 eck$LassoCheckResult]: Loop: 50489#L319 assume !false; 50850#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 50846#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 50842#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 50839#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50837#L286 assume 0 != eval_~tmp~0#1; 50835#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 48622#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 48623#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 50290#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 50492#L305 assume !(0 == ~t2_st~0); 50489#L319 [2022-02-21 04:21:54,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:54,731 INFO L85 PathProgramCache]: Analyzing trace with hash -1720071637, now seen corresponding path program 1 times [2022-02-21 04:21:54,731 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:54,731 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84223196] [2022-02-21 04:21:54,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:54,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:54,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:54,743 INFO L290 TraceCheckUtils]: 0: Hoare triple {57500#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {57500#true} is VALID [2022-02-21 04:21:54,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {57500#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {57502#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:54,743 INFO L290 TraceCheckUtils]: 2: Hoare triple {57502#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {57502#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 3: Hoare triple {57502#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {57502#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 4: Hoare triple {57502#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {57502#(= ~t1_i~0 1)} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 5: Hoare triple {57502#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {57501#false} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 6: Hoare triple {57501#false} assume 1 == ~t2_i~0;~t2_st~0 := 0; {57501#false} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 7: Hoare triple {57501#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {57501#false} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 8: Hoare triple {57501#false} assume !(0 == ~M_E~0); {57501#false} is VALID [2022-02-21 04:21:54,744 INFO L290 TraceCheckUtils]: 9: Hoare triple {57501#false} assume !(0 == ~T1_E~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 10: Hoare triple {57501#false} assume !(0 == ~T2_E~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 11: Hoare triple {57501#false} assume !(0 == ~E_M~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 12: Hoare triple {57501#false} assume !(0 == ~E_1~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 13: Hoare triple {57501#false} assume !(0 == ~E_2~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 14: Hoare triple {57501#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 15: Hoare triple {57501#false} assume !(1 == ~m_pc~0); {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 16: Hoare triple {57501#false} is_master_triggered_~__retres1~0#1 := 0; {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 17: Hoare triple {57501#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 18: Hoare triple {57501#false} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {57501#false} is VALID [2022-02-21 04:21:54,745 INFO L290 TraceCheckUtils]: 19: Hoare triple {57501#false} assume !(0 != activate_threads_~tmp~1#1); {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 20: Hoare triple {57501#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 21: Hoare triple {57501#false} assume !(1 == ~t1_pc~0); {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 22: Hoare triple {57501#false} is_transmit1_triggered_~__retres1~1#1 := 0; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 23: Hoare triple {57501#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 24: Hoare triple {57501#false} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 25: Hoare triple {57501#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 26: Hoare triple {57501#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 27: Hoare triple {57501#false} assume !(1 == ~t2_pc~0); {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 28: Hoare triple {57501#false} is_transmit2_triggered_~__retres1~2#1 := 0; {57501#false} is VALID [2022-02-21 04:21:54,746 INFO L290 TraceCheckUtils]: 29: Hoare triple {57501#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 30: Hoare triple {57501#false} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 31: Hoare triple {57501#false} assume !(0 != activate_threads_~tmp___1~0#1); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 32: Hoare triple {57501#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 33: Hoare triple {57501#false} assume !(1 == ~M_E~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 34: Hoare triple {57501#false} assume !(1 == ~T1_E~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 35: Hoare triple {57501#false} assume !(1 == ~T2_E~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 36: Hoare triple {57501#false} assume !(1 == ~E_M~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 37: Hoare triple {57501#false} assume !(1 == ~E_1~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 38: Hoare triple {57501#false} assume !(1 == ~E_2~0); {57501#false} is VALID [2022-02-21 04:21:54,747 INFO L290 TraceCheckUtils]: 39: Hoare triple {57501#false} assume { :end_inline_reset_delta_events } true; {57501#false} is VALID [2022-02-21 04:21:54,748 INFO L290 TraceCheckUtils]: 40: Hoare triple {57501#false} assume !false; {57501#false} is VALID [2022-02-21 04:21:54,748 INFO L290 TraceCheckUtils]: 41: Hoare triple {57501#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {57501#false} is VALID [2022-02-21 04:21:54,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:54,748 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:54,748 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84223196] [2022-02-21 04:21:54,748 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84223196] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:54,748 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:54,748 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:54,749 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360589567] [2022-02-21 04:21:54,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:54,749 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:54,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:54,749 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 1 times [2022-02-21 04:21:54,749 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:54,749 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380432618] [2022-02-21 04:21:54,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:54,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:54,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:54,752 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:54,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:54,754 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:54,810 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:54,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:54,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:54,811 INFO L87 Difference]: Start difference. First operand 2925 states and 3964 transitions. cyclomatic complexity: 1042 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,130 INFO L93 Difference]: Finished difference Result 2888 states and 3915 transitions. [2022-02-21 04:21:55,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:55,130 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,154 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 42 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:55,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,340 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-02-21 04:21:55,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2888 states to 2888 states and 3915 transitions. [2022-02-21 04:21:55,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2888 [2022-02-21 04:21:55,538 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2888 [2022-02-21 04:21:55,538 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:55,540 INFO L681 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-02-21 04:21:55,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,566 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2888 to 2888. [2022-02-21 04:21:55,566 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:55,569 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2888 states and 3915 transitions. Second operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,571 INFO L74 IsIncluded]: Start isIncluded. First operand 2888 states and 3915 transitions. Second operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,573 INFO L87 Difference]: Start difference. First operand 2888 states and 3915 transitions. Second operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,748 INFO L93 Difference]: Finished difference Result 2888 states and 3915 transitions. [2022-02-21 04:21:55,748 INFO L276 IsEmpty]: Start isEmpty. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,750 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,751 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,754 INFO L74 IsIncluded]: Start isIncluded. First operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,756 INFO L87 Difference]: Start difference. First operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,976 INFO L93 Difference]: Finished difference Result 2888 states and 3915 transitions. [2022-02-21 04:21:55,976 INFO L276 IsEmpty]: Start isEmpty. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:55,979 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,979 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,979 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:55,979 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:55,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2888 states, 2888 states have (on average 1.3556094182825484) internal successors, (3915), 2887 states have internal predecessors, (3915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2888 states to 2888 states and 3915 transitions. [2022-02-21 04:21:56,201 INFO L704 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-02-21 04:21:56,203 INFO L587 BuchiCegarLoop]: Abstraction has 2888 states and 3915 transitions. [2022-02-21 04:21:56,203 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:21:56,203 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2888 states and 3915 transitions. [2022-02-21 04:21:56,210 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2841 [2022-02-21 04:21:56,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,211 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,212 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,212 INFO L791 eck$LassoCheckResult]: Stem: 60673#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 60620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 60621#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60646#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60524#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 60395#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60396#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60585#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60444#L344 assume !(0 == ~M_E~0); 60445#L344-2 assume !(0 == ~T1_E~0); 60614#L349-1 assume !(0 == ~T2_E~0); 60463#L354-1 assume !(0 == ~E_M~0); 60464#L359-1 assume !(0 == ~E_1~0); 60458#L364-1 assume !(0 == ~E_2~0); 60459#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60541#L166 assume !(1 == ~m_pc~0); 60542#L166-2 is_master_triggered_~__retres1~0#1 := 0; 60627#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60442#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 60443#L425 assume !(0 != activate_threads_~tmp~1#1); 60665#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60553#L185 assume !(1 == ~t1_pc~0); 60469#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60470#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60507#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 60513#L433 assume !(0 != activate_threads_~tmp___0~0#1); 60514#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60569#L204 assume !(1 == ~t2_pc~0); 60551#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 60552#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60587#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60424#L441 assume !(0 != activate_threads_~tmp___1~0#1); 60425#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60544#L382 assume !(1 == ~M_E~0); 60414#L382-2 assume !(1 == ~T1_E~0); 60415#L387-1 assume !(1 == ~T2_E~0); 60528#L392-1 assume !(1 == ~E_M~0); 60559#L397-1 assume !(1 == ~E_1~0); 60560#L402-1 assume !(1 == ~E_2~0); 60545#L407-1 assume { :end_inline_reset_delta_events } true; 60546#L553-2 assume !false; 62488#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 62294#L319 [2022-02-21 04:21:56,212 INFO L793 eck$LassoCheckResult]: Loop: 62294#L319 assume !false; 62485#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 62482#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 62481#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 62476#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 62472#L286 assume 0 != eval_~tmp~0#1; 62468#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 62463#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 62300#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 62297#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 62295#L305 assume !(0 == ~t2_st~0); 62294#L319 [2022-02-21 04:21:56,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,213 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 2 times [2022-02-21 04:21:56,213 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,213 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492812288] [2022-02-21 04:21:56,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:56,219 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:56,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:56,225 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:56,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,226 INFO L85 PathProgramCache]: Analyzing trace with hash 186468612, now seen corresponding path program 2 times [2022-02-21 04:21:56,226 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,226 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1571375802] [2022-02-21 04:21:56,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:56,229 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:56,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:56,231 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:56,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,232 INFO L85 PathProgramCache]: Analyzing trace with hash -642569318, now seen corresponding path program 1 times [2022-02-21 04:21:56,232 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,232 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767555124] [2022-02-21 04:21:56,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,248 INFO L290 TraceCheckUtils]: 0: Hoare triple {69064#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; {69064#true} is VALID [2022-02-21 04:21:56,249 INFO L290 TraceCheckUtils]: 1: Hoare triple {69064#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; {69064#true} is VALID [2022-02-21 04:21:56,249 INFO L290 TraceCheckUtils]: 2: Hoare triple {69064#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {69064#true} is VALID [2022-02-21 04:21:56,249 INFO L290 TraceCheckUtils]: 3: Hoare triple {69064#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {69064#true} is VALID [2022-02-21 04:21:56,249 INFO L290 TraceCheckUtils]: 4: Hoare triple {69064#true} assume 1 == ~m_i~0;~m_st~0 := 0; {69064#true} is VALID [2022-02-21 04:21:56,249 INFO L290 TraceCheckUtils]: 5: Hoare triple {69064#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {69064#true} is VALID [2022-02-21 04:21:56,250 INFO L290 TraceCheckUtils]: 6: Hoare triple {69064#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,250 INFO L290 TraceCheckUtils]: 7: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,250 INFO L290 TraceCheckUtils]: 8: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~M_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,251 INFO L290 TraceCheckUtils]: 9: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~T1_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,251 INFO L290 TraceCheckUtils]: 10: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~T2_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,251 INFO L290 TraceCheckUtils]: 11: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~E_M~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,252 INFO L290 TraceCheckUtils]: 12: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~E_1~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,252 INFO L290 TraceCheckUtils]: 13: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~E_2~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,252 INFO L290 TraceCheckUtils]: 14: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,253 INFO L290 TraceCheckUtils]: 15: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~m_pc~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,253 INFO L290 TraceCheckUtils]: 16: Hoare triple {69066#(= 0 ~t2_st~0)} is_master_triggered_~__retres1~0#1 := 0; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,253 INFO L290 TraceCheckUtils]: 17: Hoare triple {69066#(= 0 ~t2_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,254 INFO L290 TraceCheckUtils]: 18: Hoare triple {69066#(= 0 ~t2_st~0)} activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,254 INFO L290 TraceCheckUtils]: 19: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp~1#1); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,255 INFO L290 TraceCheckUtils]: 20: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,255 INFO L290 TraceCheckUtils]: 21: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~t1_pc~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,255 INFO L290 TraceCheckUtils]: 22: Hoare triple {69066#(= 0 ~t2_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,256 INFO L290 TraceCheckUtils]: 23: Hoare triple {69066#(= 0 ~t2_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,256 INFO L290 TraceCheckUtils]: 24: Hoare triple {69066#(= 0 ~t2_st~0)} activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,256 INFO L290 TraceCheckUtils]: 25: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,257 INFO L290 TraceCheckUtils]: 26: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,257 INFO L290 TraceCheckUtils]: 27: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~t2_pc~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,257 INFO L290 TraceCheckUtils]: 28: Hoare triple {69066#(= 0 ~t2_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,258 INFO L290 TraceCheckUtils]: 29: Hoare triple {69066#(= 0 ~t2_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,258 INFO L290 TraceCheckUtils]: 30: Hoare triple {69066#(= 0 ~t2_st~0)} activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,258 INFO L290 TraceCheckUtils]: 31: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,259 INFO L290 TraceCheckUtils]: 32: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,259 INFO L290 TraceCheckUtils]: 33: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~M_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,259 INFO L290 TraceCheckUtils]: 34: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~T1_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,259 INFO L290 TraceCheckUtils]: 35: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~T2_E~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,260 INFO L290 TraceCheckUtils]: 36: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~E_M~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,260 INFO L290 TraceCheckUtils]: 37: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~E_1~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,260 INFO L290 TraceCheckUtils]: 38: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(1 == ~E_2~0); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,261 INFO L290 TraceCheckUtils]: 39: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :end_inline_reset_delta_events } true; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,261 INFO L290 TraceCheckUtils]: 40: Hoare triple {69066#(= 0 ~t2_st~0)} assume !false; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,261 INFO L290 TraceCheckUtils]: 41: Hoare triple {69066#(= 0 ~t2_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,262 INFO L290 TraceCheckUtils]: 42: Hoare triple {69066#(= 0 ~t2_st~0)} assume !false; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,262 INFO L290 TraceCheckUtils]: 43: Hoare triple {69066#(= 0 ~t2_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,262 INFO L290 TraceCheckUtils]: 44: Hoare triple {69066#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,263 INFO L290 TraceCheckUtils]: 45: Hoare triple {69066#(= 0 ~t2_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,263 INFO L290 TraceCheckUtils]: 46: Hoare triple {69066#(= 0 ~t2_st~0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,263 INFO L290 TraceCheckUtils]: 47: Hoare triple {69066#(= 0 ~t2_st~0)} assume 0 != eval_~tmp~0#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,264 INFO L290 TraceCheckUtils]: 48: Hoare triple {69066#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,264 INFO L290 TraceCheckUtils]: 49: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,264 INFO L290 TraceCheckUtils]: 50: Hoare triple {69066#(= 0 ~t2_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,265 INFO L290 TraceCheckUtils]: 51: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {69066#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:21:56,265 INFO L290 TraceCheckUtils]: 52: Hoare triple {69066#(= 0 ~t2_st~0)} assume !(0 == ~t2_st~0); {69065#false} is VALID [2022-02-21 04:21:56,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,265 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,266 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767555124] [2022-02-21 04:21:56,266 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767555124] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,266 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,266 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:56,266 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130521785] [2022-02-21 04:21:56,266 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,333 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:56,334 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:56,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:56,334 INFO L87 Difference]: Start difference. First operand 2888 states and 3915 transitions. cyclomatic complexity: 1030 Second operand has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,177 INFO L93 Difference]: Finished difference Result 4907 states and 6588 transitions. [2022-02-21 04:21:57,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:57,177 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 26.5) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,238 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 53 edges. 53 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:57,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4907 states and 6588 transitions. [2022-02-21 04:21:57,836 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4856 [2022-02-21 04:21:58,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4907 states to 4907 states and 6588 transitions. [2022-02-21 04:21:58,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4907 [2022-02-21 04:21:58,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4907 [2022-02-21 04:21:58,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4907 states and 6588 transitions. [2022-02-21 04:21:58,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:58,433 INFO L681 BuchiCegarLoop]: Abstraction has 4907 states and 6588 transitions. [2022-02-21 04:21:58,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4907 states and 6588 transitions. [2022-02-21 04:21:58,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4907 to 4851. [2022-02-21 04:21:58,468 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:58,472 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4907 states and 6588 transitions. Second operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,477 INFO L74 IsIncluded]: Start isIncluded. First operand 4907 states and 6588 transitions. Second operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,480 INFO L87 Difference]: Start difference. First operand 4907 states and 6588 transitions. Second operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,007 INFO L93 Difference]: Finished difference Result 4907 states and 6588 transitions. [2022-02-21 04:21:59,007 INFO L276 IsEmpty]: Start isEmpty. Operand 4907 states and 6588 transitions. [2022-02-21 04:21:59,011 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,011 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,016 INFO L74 IsIncluded]: Start isIncluded. First operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4907 states and 6588 transitions. [2022-02-21 04:21:59,019 INFO L87 Difference]: Start difference. First operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4907 states and 6588 transitions. [2022-02-21 04:21:59,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,548 INFO L93 Difference]: Finished difference Result 4907 states and 6588 transitions. [2022-02-21 04:21:59,548 INFO L276 IsEmpty]: Start isEmpty. Operand 4907 states and 6588 transitions. [2022-02-21 04:21:59,553 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,554 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,554 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:59,554 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:59,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4851 states, 4851 states have (on average 1.3465264893836322) internal successors, (6532), 4850 states have internal predecessors, (6532), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4851 states to 4851 states and 6532 transitions. [2022-02-21 04:22:00,144 INFO L704 BuchiCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2022-02-21 04:22:00,144 INFO L587 BuchiCegarLoop]: Abstraction has 4851 states and 6532 transitions. [2022-02-21 04:22:00,144 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:22:00,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4851 states and 6532 transitions. [2022-02-21 04:22:00,152 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4800 [2022-02-21 04:22:00,153 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:00,153 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:00,153 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,153 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,153 INFO L791 eck$LassoCheckResult]: Stem: 74256#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~token~0 := 0;~local~0 := 0; 74204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 74205#L516 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74228#L224 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74107#L231 assume 1 == ~m_i~0;~m_st~0 := 0; 73976#L231-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73977#L236-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74172#L241-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74026#L344 assume !(0 == ~M_E~0); 74027#L344-2 assume !(0 == ~T1_E~0); 74197#L349-1 assume !(0 == ~T2_E~0); 74045#L354-1 assume !(0 == ~E_M~0); 74046#L359-1 assume !(0 == ~E_1~0); 74040#L364-1 assume !(0 == ~E_2~0); 74041#L369-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74128#L166 assume !(1 == ~m_pc~0); 74129#L166-2 is_master_triggered_~__retres1~0#1 := 0; 74211#L177 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74024#L178 activate_threads_#t~ret9#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 74025#L425 assume !(0 != activate_threads_~tmp~1#1); 74248#L425-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74139#L185 assume !(1 == ~t1_pc~0); 74051#L185-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74052#L196 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74088#L197 activate_threads_#t~ret10#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 74095#L433 assume !(0 != activate_threads_~tmp___0~0#1); 74096#L433-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74155#L204 assume !(1 == ~t2_pc~0); 74137#L204-2 is_transmit2_triggered_~__retres1~2#1 := 0; 74138#L215 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74175#L216 activate_threads_#t~ret11#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 74006#L441 assume !(0 != activate_threads_~tmp___1~0#1); 74007#L441-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74131#L382 assume !(1 == ~M_E~0); 73994#L382-2 assume !(1 == ~T1_E~0); 73995#L387-1 assume !(1 == ~T2_E~0); 74112#L392-1 assume !(1 == ~E_M~0); 74145#L397-1 assume !(1 == ~E_1~0); 74146#L402-1 assume !(1 == ~E_2~0); 74132#L407-1 assume { :end_inline_reset_delta_events } true; 74133#L553-2 assume !false; 76805#L554 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76800#L319 [2022-02-21 04:22:00,154 INFO L793 eck$LassoCheckResult]: Loop: 76800#L319 assume !false; 76796#L282 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 76790#L254 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 76778#L271 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 76775#L272 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 76770#L286 assume 0 != eval_~tmp~0#1; 76762#L286-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 76753#L294 assume !(0 != eval_~tmp_ndt_1~0#1); 76747#L291 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 76715#L308 assume !(0 != eval_~tmp_ndt_2~0#1); 76743#L305 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 75266#L322 assume !(0 != eval_~tmp_ndt_3~0#1); 76800#L319 [2022-02-21 04:22:00,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,154 INFO L85 PathProgramCache]: Analyzing trace with hash 327016235, now seen corresponding path program 3 times [2022-02-21 04:22:00,154 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,154 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184114605] [2022-02-21 04:22:00,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,159 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:00,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,163 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:00,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1485556888, now seen corresponding path program 1 times [2022-02-21 04:22:00,164 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,164 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75168676] [2022-02-21 04:22:00,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,166 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:00,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,168 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:00,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1555184834, now seen corresponding path program 1 times [2022-02-21 04:22:00,168 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,168 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287813661] [2022-02-21 04:22:00,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,172 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:00,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:00,178 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:00,813 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:22:00 BoogieIcfgContainer [2022-02-21 04:22:00,814 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:22:00,814 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:22:00,814 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:22:00,814 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:22:00,815 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:43" (3/4) ... [2022-02-21 04:22:00,818 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:22:00,855 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:22:00,856 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:22:00,858 INFO L158 Benchmark]: Toolchain (without parser) took 18085.49ms. Allocated memory was 104.9MB in the beginning and 255.9MB in the end (delta: 151.0MB). Free memory was 78.7MB in the beginning and 175.2MB in the end (delta: -96.5MB). Peak memory consumption was 54.4MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,858 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 104.9MB. Free memory is still 64.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:22:00,859 INFO L158 Benchmark]: CACSL2BoogieTranslator took 306.70ms. Allocated memory was 104.9MB in the beginning and 146.8MB in the end (delta: 41.9MB). Free memory was 78.6MB in the beginning and 118.3MB in the end (delta: -39.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,859 INFO L158 Benchmark]: Boogie Procedure Inliner took 55.29ms. Allocated memory is still 146.8MB. Free memory was 118.3MB in the beginning and 114.4MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,859 INFO L158 Benchmark]: Boogie Preprocessor took 35.63ms. Allocated memory is still 146.8MB. Free memory was 114.4MB in the beginning and 111.8MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,859 INFO L158 Benchmark]: RCFGBuilder took 664.87ms. Allocated memory is still 146.8MB. Free memory was 111.8MB in the beginning and 83.7MB in the end (delta: 28.1MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,860 INFO L158 Benchmark]: BuchiAutomizer took 16976.50ms. Allocated memory was 146.8MB in the beginning and 255.9MB in the end (delta: 109.1MB). Free memory was 83.7MB in the beginning and 178.3MB in the end (delta: -94.6MB). Peak memory consumption was 120.8MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,860 INFO L158 Benchmark]: Witness Printer took 41.91ms. Allocated memory is still 255.9MB. Free memory was 178.3MB in the beginning and 175.2MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:22:00,863 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 104.9MB. Free memory is still 64.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 306.70ms. Allocated memory was 104.9MB in the beginning and 146.8MB in the end (delta: 41.9MB). Free memory was 78.6MB in the beginning and 118.3MB in the end (delta: -39.7MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 55.29ms. Allocated memory is still 146.8MB. Free memory was 118.3MB in the beginning and 114.4MB in the end (delta: 3.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 35.63ms. Allocated memory is still 146.8MB. Free memory was 114.4MB in the beginning and 111.8MB in the end (delta: 2.6MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 664.87ms. Allocated memory is still 146.8MB. Free memory was 111.8MB in the beginning and 83.7MB in the end (delta: 28.1MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 16976.50ms. Allocated memory was 146.8MB in the beginning and 255.9MB in the end (delta: 109.1MB). Free memory was 83.7MB in the beginning and 178.3MB in the end (delta: -94.6MB). Peak memory consumption was 120.8MB. Max. memory is 16.1GB. * Witness Printer took 41.91ms. Allocated memory is still 255.9MB. Free memory was 178.3MB in the beginning and 175.2MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 4851 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 16.9s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 2.1s. Construction of modules took 0.2s. Büchi inclusion checks took 6.2s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 4.7s AutomataMinimizationTime, 13 MinimizatonAttempts, 2971 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 3.2s Buchi closure took 0.0s. Biggest automaton had 4851 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 5176 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 5176 mSDsluCounter, 8821 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4401 mSDsCounter, 120 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 329 IncrementalHoareTripleChecker+Invalid, 449 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 120 mSolverCounterUnsat, 4420 mSDtfsCounter, 329 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 281]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2f6a318b=0, token=0, NULL=1, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1d39b8d3=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@115afd02=0, tmp_ndt_2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f1bfa3a=0, E_1=2, __retres1=1, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@59825319=0, \result=0, m_st=0, NULL=0, __retres1=0, tmp___0=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, __retres1=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3201c77c=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c3e4d0a=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31a77b6a=0, __retres1=0, M_E=2, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6fd416a9=0, t1_st=0, __retres1=0, local=0, t2_pc=0, E_M=2, kernel_st=1, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 281]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int t2_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int E_M = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L43] int token ; [L45] int local ; [L598] int __retres1 ; [L602] CALL init_model() [L512] m_i = 1 [L513] t1_i = 1 [L514] t2_i = 1 [L602] RET init_model() [L603] CALL start_simulation() [L539] int kernel_st ; [L540] int tmp ; [L541] int tmp___0 ; [L545] kernel_st = 0 [L546] FCALL update_channels() [L547] CALL init_threads() [L231] COND TRUE m_i == 1 [L232] m_st = 0 [L236] COND TRUE t1_i == 1 [L237] t1_st = 0 [L241] COND TRUE t2_i == 1 [L242] t2_st = 0 [L547] RET init_threads() [L548] CALL fire_delta_events() [L344] COND FALSE !(M_E == 0) [L349] COND FALSE !(T1_E == 0) [L354] COND FALSE !(T2_E == 0) [L359] COND FALSE !(E_M == 0) [L364] COND FALSE !(E_1 == 0) [L369] COND FALSE !(E_2 == 0) [L548] RET fire_delta_events() [L549] CALL activate_threads() [L417] int tmp ; [L418] int tmp___0 ; [L419] int tmp___1 ; [L423] CALL, EXPR is_master_triggered() [L163] int __retres1 ; [L166] COND FALSE !(m_pc == 1) [L176] __retres1 = 0 [L178] return (__retres1); [L423] RET, EXPR is_master_triggered() [L423] tmp = is_master_triggered() [L425] COND FALSE !(\read(tmp)) [L431] CALL, EXPR is_transmit1_triggered() [L182] int __retres1 ; [L185] COND FALSE !(t1_pc == 1) [L195] __retres1 = 0 [L197] return (__retres1); [L431] RET, EXPR is_transmit1_triggered() [L431] tmp___0 = is_transmit1_triggered() [L433] COND FALSE !(\read(tmp___0)) [L439] CALL, EXPR is_transmit2_triggered() [L201] int __retres1 ; [L204] COND FALSE !(t2_pc == 1) [L214] __retres1 = 0 [L216] return (__retres1); [L439] RET, EXPR is_transmit2_triggered() [L439] tmp___1 = is_transmit2_triggered() [L441] COND FALSE !(\read(tmp___1)) [L549] RET activate_threads() [L550] CALL reset_delta_events() [L382] COND FALSE !(M_E == 1) [L387] COND FALSE !(T1_E == 1) [L392] COND FALSE !(T2_E == 1) [L397] COND FALSE !(E_M == 1) [L402] COND FALSE !(E_1 == 1) [L407] COND FALSE !(E_2 == 1) [L550] RET reset_delta_events() [L553] COND TRUE 1 [L556] kernel_st = 1 [L557] CALL eval() [L277] int tmp ; Loop: [L281] COND TRUE 1 [L284] CALL, EXPR exists_runnable_thread() [L251] int __retres1 ; [L254] COND TRUE m_st == 0 [L255] __retres1 = 1 [L272] return (__retres1); [L284] RET, EXPR exists_runnable_thread() [L284] tmp = exists_runnable_thread() [L286] COND TRUE \read(tmp) [L291] COND TRUE m_st == 0 [L292] int tmp_ndt_1; [L293] tmp_ndt_1 = __VERIFIER_nondet_int() [L294] COND FALSE !(\read(tmp_ndt_1)) [L305] COND TRUE t1_st == 0 [L306] int tmp_ndt_2; [L307] tmp_ndt_2 = __VERIFIER_nondet_int() [L308] COND FALSE !(\read(tmp_ndt_2)) [L319] COND TRUE t2_st == 0 [L320] int tmp_ndt_3; [L321] tmp_ndt_3 = __VERIFIER_nondet_int() [L322] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:22:00,916 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)