./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:42,823 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:42,824 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:42,879 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:42,880 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:42,882 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:42,884 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:42,889 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:42,891 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:42,895 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:42,896 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:42,897 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:42,897 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:42,900 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:42,901 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:42,905 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:42,905 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:42,906 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:42,908 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:42,914 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:42,915 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:42,916 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:42,918 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:42,919 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:42,925 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:42,925 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:42,926 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:42,927 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:42,928 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:42,929 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:42,929 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:42,930 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:42,932 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:42,934 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:42,935 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:42,935 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:42,935 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:42,936 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:42,936 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:42,937 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:42,937 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:42,938 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:42,975 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:42,975 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:42,976 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:42,976 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:42,977 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:42,977 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:42,977 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:42,978 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:42,978 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:42,978 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:42,979 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:42,979 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:42,979 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:42,979 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:42,979 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:42,980 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:42,980 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:42,980 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:42,980 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:42,980 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:42,981 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:42,981 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:42,981 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:42,981 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:42,981 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:42,982 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:42,982 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:42,982 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:42,982 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:42,982 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:42,983 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:42,984 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:42,984 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2022-02-21 04:21:43,199 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:43,213 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:43,215 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:43,216 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:43,217 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:43,218 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2022-02-21 04:21:43,284 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d1ac0f66a/ca09cd568405454baaac730599771641/FLAG4afb82cdb [2022-02-21 04:21:43,767 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:43,767 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2022-02-21 04:21:43,799 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d1ac0f66a/ca09cd568405454baaac730599771641/FLAG4afb82cdb [2022-02-21 04:21:44,295 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d1ac0f66a/ca09cd568405454baaac730599771641 [2022-02-21 04:21:44,297 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:44,299 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:44,303 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:44,304 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:44,307 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:44,308 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,309 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@183b2800 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44, skipping insertion in model container [2022-02-21 04:21:44,309 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,316 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:44,355 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:44,493 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2022-02-21 04:21:44,553 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:44,563 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:44,572 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.03.cil-2.c[671,684] [2022-02-21 04:21:44,606 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:44,621 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:44,622 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44 WrapperNode [2022-02-21 04:21:44,622 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:44,623 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:44,623 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:44,624 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:44,629 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,637 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,693 INFO L137 Inliner]: procedures = 34, calls = 40, calls flagged for inlining = 35, calls inlined = 62, statements flattened = 813 [2022-02-21 04:21:44,693 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:44,694 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:44,694 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:44,694 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:44,701 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,702 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,714 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,715 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,725 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,741 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,744 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,750 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:44,750 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:44,751 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:44,751 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:44,752 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (1/1) ... [2022-02-21 04:21:44,776 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:44,784 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:44,796 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:44,803 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:44,831 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:44,831 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:44,831 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:44,831 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:44,958 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:44,959 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:45,697 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:45,714 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:45,714 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2022-02-21 04:21:45,717 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:45 BoogieIcfgContainer [2022-02-21 04:21:45,717 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:45,718 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:45,718 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:45,721 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:45,722 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:45,722 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:44" (1/3) ... [2022-02-21 04:21:45,723 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b25a945 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:45, skipping insertion in model container [2022-02-21 04:21:45,723 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:45,724 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:44" (2/3) ... [2022-02-21 04:21:45,724 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3b25a945 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:45, skipping insertion in model container [2022-02-21 04:21:45,724 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:45,724 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:45" (3/3) ... [2022-02-21 04:21:45,725 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2022-02-21 04:21:45,775 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:45,775 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:45,775 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:45,775 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:45,776 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:45,776 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:45,776 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:45,776 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:45,805 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2022-02-21 04:21:45,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,932 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,932 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,932 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:45,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:45,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 265 [2022-02-21 04:21:45,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:45,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:45,977 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,977 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:45,985 INFO L791 eck$LassoCheckResult]: Stem: 314#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 215#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 221#L641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 308#L285true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 112#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 204#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 194#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 254#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 144#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L439-1true assume !(0 == ~T3_E~0); 169#L444-1true assume !(0 == ~E_M~0); 277#L449-1true assume !(0 == ~E_1~0); 59#L454-1true assume !(0 == ~E_2~0); 301#L459-1true assume !(0 == ~E_3~0); 38#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 294#L208true assume 1 == ~m_pc~0; 299#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 324#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76#L220true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 48#L531true assume !(0 != activate_threads_~tmp~1#1); 133#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117#L227true assume !(1 == ~t1_pc~0); 47#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 195#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 197#L239true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 58#L539true assume !(0 != activate_threads_~tmp___0~0#1); 139#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77#L246true assume 1 == ~t2_pc~0; 130#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 149#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#L258true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 208#L547true assume !(0 != activate_threads_~tmp___1~0#1); 232#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83#L265true assume !(1 == ~t3_pc~0); 309#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 4#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 152#L277true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 320#L555true assume !(0 != activate_threads_~tmp___2~0#1); 64#L555-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199#L477true assume !(1 == ~M_E~0); 261#L477-2true assume !(1 == ~T1_E~0); 216#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 167#L487-1true assume !(1 == ~T3_E~0); 250#L492-1true assume !(1 == ~E_M~0); 41#L497-1true assume !(1 == ~E_1~0); 138#L502-1true assume !(1 == ~E_2~0); 29#L507-1true assume !(1 == ~E_3~0); 115#L512-1true assume { :end_inline_reset_delta_events } true; 191#L678-2true [2022-02-21 04:21:45,991 INFO L793 eck$LassoCheckResult]: Loop: 191#L678-2true assume !false; 282#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 140#L404true assume false; 5#L419true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63#L285-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 263#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 326#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 189#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 71#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 95#L454-3true assume 0 == ~E_2~0;~E_2~0 := 1; 234#L459-3true assume !(0 == ~E_3~0); 60#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246#L208-15true assume 1 == ~m_pc~0; 279#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 243#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52#L220-5true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 153#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 72#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286#L227-15true assume !(1 == ~t1_pc~0); 271#L227-17true is_transmit1_triggered_~__retres1~1#1 := 0; 235#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19#L239-5true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 205#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 186#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170#L246-15true assume !(1 == ~t2_pc~0); 14#L246-17true is_transmit2_triggered_~__retres1~2#1 := 0; 248#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 288#L258-5true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 311#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 200#L265-15true assume !(1 == ~t3_pc~0); 265#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 126#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90#L277-5true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 87#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 212#L555-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 176#L477-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 260#L482-3true assume !(1 == ~T2_E~0); 96#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 51#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 285#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 137#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 182#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 54#L343-1true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 207#L697true assume !(0 == start_simulation_~tmp~3#1); 3#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 251#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 81#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 70#L343-2true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 323#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 196#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 275#L660true start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 82#L710true assume !(0 != start_simulation_~tmp___0~1#1); 191#L678-2true [2022-02-21 04:21:45,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:45,997 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2022-02-21 04:21:46,007 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,008 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267878231] [2022-02-21 04:21:46,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,221 INFO L290 TraceCheckUtils]: 0: Hoare triple {328#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {328#true} is VALID [2022-02-21 04:21:46,222 INFO L290 TraceCheckUtils]: 1: Hoare triple {328#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {330#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:46,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {330#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {330#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:46,224 INFO L290 TraceCheckUtils]: 3: Hoare triple {330#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {330#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:46,225 INFO L290 TraceCheckUtils]: 4: Hoare triple {330#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {329#false} is VALID [2022-02-21 04:21:46,225 INFO L290 TraceCheckUtils]: 5: Hoare triple {329#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {329#false} is VALID [2022-02-21 04:21:46,226 INFO L290 TraceCheckUtils]: 6: Hoare triple {329#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {329#false} is VALID [2022-02-21 04:21:46,226 INFO L290 TraceCheckUtils]: 7: Hoare triple {329#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {329#false} is VALID [2022-02-21 04:21:46,226 INFO L290 TraceCheckUtils]: 8: Hoare triple {329#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {329#false} is VALID [2022-02-21 04:21:46,227 INFO L290 TraceCheckUtils]: 9: Hoare triple {329#false} assume !(0 == ~M_E~0); {329#false} is VALID [2022-02-21 04:21:46,227 INFO L290 TraceCheckUtils]: 10: Hoare triple {329#false} assume !(0 == ~T1_E~0); {329#false} is VALID [2022-02-21 04:21:46,227 INFO L290 TraceCheckUtils]: 11: Hoare triple {329#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {329#false} is VALID [2022-02-21 04:21:46,228 INFO L290 TraceCheckUtils]: 12: Hoare triple {329#false} assume !(0 == ~T3_E~0); {329#false} is VALID [2022-02-21 04:21:46,228 INFO L290 TraceCheckUtils]: 13: Hoare triple {329#false} assume !(0 == ~E_M~0); {329#false} is VALID [2022-02-21 04:21:46,228 INFO L290 TraceCheckUtils]: 14: Hoare triple {329#false} assume !(0 == ~E_1~0); {329#false} is VALID [2022-02-21 04:21:46,228 INFO L290 TraceCheckUtils]: 15: Hoare triple {329#false} assume !(0 == ~E_2~0); {329#false} is VALID [2022-02-21 04:21:46,229 INFO L290 TraceCheckUtils]: 16: Hoare triple {329#false} assume !(0 == ~E_3~0); {329#false} is VALID [2022-02-21 04:21:46,229 INFO L290 TraceCheckUtils]: 17: Hoare triple {329#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {329#false} is VALID [2022-02-21 04:21:46,230 INFO L290 TraceCheckUtils]: 18: Hoare triple {329#false} assume 1 == ~m_pc~0; {329#false} is VALID [2022-02-21 04:21:46,231 INFO L290 TraceCheckUtils]: 19: Hoare triple {329#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {329#false} is VALID [2022-02-21 04:21:46,231 INFO L290 TraceCheckUtils]: 20: Hoare triple {329#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {329#false} is VALID [2022-02-21 04:21:46,231 INFO L290 TraceCheckUtils]: 21: Hoare triple {329#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {329#false} is VALID [2022-02-21 04:21:46,231 INFO L290 TraceCheckUtils]: 22: Hoare triple {329#false} assume !(0 != activate_threads_~tmp~1#1); {329#false} is VALID [2022-02-21 04:21:46,232 INFO L290 TraceCheckUtils]: 23: Hoare triple {329#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {329#false} is VALID [2022-02-21 04:21:46,232 INFO L290 TraceCheckUtils]: 24: Hoare triple {329#false} assume !(1 == ~t1_pc~0); {329#false} is VALID [2022-02-21 04:21:46,232 INFO L290 TraceCheckUtils]: 25: Hoare triple {329#false} is_transmit1_triggered_~__retres1~1#1 := 0; {329#false} is VALID [2022-02-21 04:21:46,232 INFO L290 TraceCheckUtils]: 26: Hoare triple {329#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {329#false} is VALID [2022-02-21 04:21:46,233 INFO L290 TraceCheckUtils]: 27: Hoare triple {329#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {329#false} is VALID [2022-02-21 04:21:46,233 INFO L290 TraceCheckUtils]: 28: Hoare triple {329#false} assume !(0 != activate_threads_~tmp___0~0#1); {329#false} is VALID [2022-02-21 04:21:46,233 INFO L290 TraceCheckUtils]: 29: Hoare triple {329#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {329#false} is VALID [2022-02-21 04:21:46,234 INFO L290 TraceCheckUtils]: 30: Hoare triple {329#false} assume 1 == ~t2_pc~0; {329#false} is VALID [2022-02-21 04:21:46,234 INFO L290 TraceCheckUtils]: 31: Hoare triple {329#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {329#false} is VALID [2022-02-21 04:21:46,234 INFO L290 TraceCheckUtils]: 32: Hoare triple {329#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {329#false} is VALID [2022-02-21 04:21:46,234 INFO L290 TraceCheckUtils]: 33: Hoare triple {329#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {329#false} is VALID [2022-02-21 04:21:46,235 INFO L290 TraceCheckUtils]: 34: Hoare triple {329#false} assume !(0 != activate_threads_~tmp___1~0#1); {329#false} is VALID [2022-02-21 04:21:46,235 INFO L290 TraceCheckUtils]: 35: Hoare triple {329#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {329#false} is VALID [2022-02-21 04:21:46,235 INFO L290 TraceCheckUtils]: 36: Hoare triple {329#false} assume !(1 == ~t3_pc~0); {329#false} is VALID [2022-02-21 04:21:46,235 INFO L290 TraceCheckUtils]: 37: Hoare triple {329#false} is_transmit3_triggered_~__retres1~3#1 := 0; {329#false} is VALID [2022-02-21 04:21:46,236 INFO L290 TraceCheckUtils]: 38: Hoare triple {329#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {329#false} is VALID [2022-02-21 04:21:46,236 INFO L290 TraceCheckUtils]: 39: Hoare triple {329#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {329#false} is VALID [2022-02-21 04:21:46,236 INFO L290 TraceCheckUtils]: 40: Hoare triple {329#false} assume !(0 != activate_threads_~tmp___2~0#1); {329#false} is VALID [2022-02-21 04:21:46,237 INFO L290 TraceCheckUtils]: 41: Hoare triple {329#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {329#false} is VALID [2022-02-21 04:21:46,237 INFO L290 TraceCheckUtils]: 42: Hoare triple {329#false} assume !(1 == ~M_E~0); {329#false} is VALID [2022-02-21 04:21:46,238 INFO L290 TraceCheckUtils]: 43: Hoare triple {329#false} assume !(1 == ~T1_E~0); {329#false} is VALID [2022-02-21 04:21:46,239 INFO L290 TraceCheckUtils]: 44: Hoare triple {329#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {329#false} is VALID [2022-02-21 04:21:46,239 INFO L290 TraceCheckUtils]: 45: Hoare triple {329#false} assume !(1 == ~T3_E~0); {329#false} is VALID [2022-02-21 04:21:46,240 INFO L290 TraceCheckUtils]: 46: Hoare triple {329#false} assume !(1 == ~E_M~0); {329#false} is VALID [2022-02-21 04:21:46,240 INFO L290 TraceCheckUtils]: 47: Hoare triple {329#false} assume !(1 == ~E_1~0); {329#false} is VALID [2022-02-21 04:21:46,240 INFO L290 TraceCheckUtils]: 48: Hoare triple {329#false} assume !(1 == ~E_2~0); {329#false} is VALID [2022-02-21 04:21:46,245 INFO L290 TraceCheckUtils]: 49: Hoare triple {329#false} assume !(1 == ~E_3~0); {329#false} is VALID [2022-02-21 04:21:46,245 INFO L290 TraceCheckUtils]: 50: Hoare triple {329#false} assume { :end_inline_reset_delta_events } true; {329#false} is VALID [2022-02-21 04:21:46,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,248 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,248 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267878231] [2022-02-21 04:21:46,249 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267878231] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,250 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,250 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:46,251 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310774103] [2022-02-21 04:21:46,252 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,257 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:46,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,260 INFO L85 PathProgramCache]: Analyzing trace with hash -203279494, now seen corresponding path program 1 times [2022-02-21 04:21:46,260 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,261 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733614168] [2022-02-21 04:21:46,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:46,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:46,303 INFO L290 TraceCheckUtils]: 0: Hoare triple {331#true} assume !false; {331#true} is VALID [2022-02-21 04:21:46,304 INFO L290 TraceCheckUtils]: 1: Hoare triple {331#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {331#true} is VALID [2022-02-21 04:21:46,305 INFO L290 TraceCheckUtils]: 2: Hoare triple {331#true} assume false; {332#false} is VALID [2022-02-21 04:21:46,305 INFO L290 TraceCheckUtils]: 3: Hoare triple {332#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {332#false} is VALID [2022-02-21 04:21:46,305 INFO L290 TraceCheckUtils]: 4: Hoare triple {332#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {332#false} is VALID [2022-02-21 04:21:46,305 INFO L290 TraceCheckUtils]: 5: Hoare triple {332#false} assume 0 == ~M_E~0;~M_E~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,306 INFO L290 TraceCheckUtils]: 6: Hoare triple {332#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,310 INFO L290 TraceCheckUtils]: 7: Hoare triple {332#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,310 INFO L290 TraceCheckUtils]: 8: Hoare triple {332#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,311 INFO L290 TraceCheckUtils]: 9: Hoare triple {332#false} assume 0 == ~E_M~0;~E_M~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,311 INFO L290 TraceCheckUtils]: 10: Hoare triple {332#false} assume 0 == ~E_1~0;~E_1~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,311 INFO L290 TraceCheckUtils]: 11: Hoare triple {332#false} assume 0 == ~E_2~0;~E_2~0 := 1; {332#false} is VALID [2022-02-21 04:21:46,312 INFO L290 TraceCheckUtils]: 12: Hoare triple {332#false} assume !(0 == ~E_3~0); {332#false} is VALID [2022-02-21 04:21:46,312 INFO L290 TraceCheckUtils]: 13: Hoare triple {332#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {332#false} is VALID [2022-02-21 04:21:46,312 INFO L290 TraceCheckUtils]: 14: Hoare triple {332#false} assume 1 == ~m_pc~0; {332#false} is VALID [2022-02-21 04:21:46,312 INFO L290 TraceCheckUtils]: 15: Hoare triple {332#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {332#false} is VALID [2022-02-21 04:21:46,312 INFO L290 TraceCheckUtils]: 16: Hoare triple {332#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {332#false} is VALID [2022-02-21 04:21:46,313 INFO L290 TraceCheckUtils]: 17: Hoare triple {332#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {332#false} is VALID [2022-02-21 04:21:46,313 INFO L290 TraceCheckUtils]: 18: Hoare triple {332#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {332#false} is VALID [2022-02-21 04:21:46,313 INFO L290 TraceCheckUtils]: 19: Hoare triple {332#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {332#false} is VALID [2022-02-21 04:21:46,313 INFO L290 TraceCheckUtils]: 20: Hoare triple {332#false} assume !(1 == ~t1_pc~0); {332#false} is VALID [2022-02-21 04:21:46,314 INFO L290 TraceCheckUtils]: 21: Hoare triple {332#false} is_transmit1_triggered_~__retres1~1#1 := 0; {332#false} is VALID [2022-02-21 04:21:46,314 INFO L290 TraceCheckUtils]: 22: Hoare triple {332#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {332#false} is VALID [2022-02-21 04:21:46,314 INFO L290 TraceCheckUtils]: 23: Hoare triple {332#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {332#false} is VALID [2022-02-21 04:21:46,314 INFO L290 TraceCheckUtils]: 24: Hoare triple {332#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {332#false} is VALID [2022-02-21 04:21:46,315 INFO L290 TraceCheckUtils]: 25: Hoare triple {332#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {332#false} is VALID [2022-02-21 04:21:46,315 INFO L290 TraceCheckUtils]: 26: Hoare triple {332#false} assume !(1 == ~t2_pc~0); {332#false} is VALID [2022-02-21 04:21:46,315 INFO L290 TraceCheckUtils]: 27: Hoare triple {332#false} is_transmit2_triggered_~__retres1~2#1 := 0; {332#false} is VALID [2022-02-21 04:21:46,315 INFO L290 TraceCheckUtils]: 28: Hoare triple {332#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {332#false} is VALID [2022-02-21 04:21:46,315 INFO L290 TraceCheckUtils]: 29: Hoare triple {332#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {332#false} is VALID [2022-02-21 04:21:46,316 INFO L290 TraceCheckUtils]: 30: Hoare triple {332#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {332#false} is VALID [2022-02-21 04:21:46,316 INFO L290 TraceCheckUtils]: 31: Hoare triple {332#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {332#false} is VALID [2022-02-21 04:21:46,316 INFO L290 TraceCheckUtils]: 32: Hoare triple {332#false} assume !(1 == ~t3_pc~0); {332#false} is VALID [2022-02-21 04:21:46,316 INFO L290 TraceCheckUtils]: 33: Hoare triple {332#false} is_transmit3_triggered_~__retres1~3#1 := 0; {332#false} is VALID [2022-02-21 04:21:46,317 INFO L290 TraceCheckUtils]: 34: Hoare triple {332#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {332#false} is VALID [2022-02-21 04:21:46,317 INFO L290 TraceCheckUtils]: 35: Hoare triple {332#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {332#false} is VALID [2022-02-21 04:21:46,317 INFO L290 TraceCheckUtils]: 36: Hoare triple {332#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {332#false} is VALID [2022-02-21 04:21:46,317 INFO L290 TraceCheckUtils]: 37: Hoare triple {332#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {332#false} is VALID [2022-02-21 04:21:46,317 INFO L290 TraceCheckUtils]: 38: Hoare triple {332#false} assume 1 == ~M_E~0;~M_E~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,318 INFO L290 TraceCheckUtils]: 39: Hoare triple {332#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,318 INFO L290 TraceCheckUtils]: 40: Hoare triple {332#false} assume !(1 == ~T2_E~0); {332#false} is VALID [2022-02-21 04:21:46,318 INFO L290 TraceCheckUtils]: 41: Hoare triple {332#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,318 INFO L290 TraceCheckUtils]: 42: Hoare triple {332#false} assume 1 == ~E_M~0;~E_M~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,318 INFO L290 TraceCheckUtils]: 43: Hoare triple {332#false} assume 1 == ~E_1~0;~E_1~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,319 INFO L290 TraceCheckUtils]: 44: Hoare triple {332#false} assume 1 == ~E_2~0;~E_2~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,319 INFO L290 TraceCheckUtils]: 45: Hoare triple {332#false} assume 1 == ~E_3~0;~E_3~0 := 2; {332#false} is VALID [2022-02-21 04:21:46,319 INFO L290 TraceCheckUtils]: 46: Hoare triple {332#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {332#false} is VALID [2022-02-21 04:21:46,319 INFO L290 TraceCheckUtils]: 47: Hoare triple {332#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {332#false} is VALID [2022-02-21 04:21:46,319 INFO L290 TraceCheckUtils]: 48: Hoare triple {332#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {332#false} is VALID [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 49: Hoare triple {332#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {332#false} is VALID [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 50: Hoare triple {332#false} assume !(0 == start_simulation_~tmp~3#1); {332#false} is VALID [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 51: Hoare triple {332#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {332#false} is VALID [2022-02-21 04:21:46,320 INFO L290 TraceCheckUtils]: 52: Hoare triple {332#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {332#false} is VALID [2022-02-21 04:21:46,322 INFO L290 TraceCheckUtils]: 53: Hoare triple {332#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {332#false} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 54: Hoare triple {332#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {332#false} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 55: Hoare triple {332#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {332#false} is VALID [2022-02-21 04:21:46,323 INFO L290 TraceCheckUtils]: 56: Hoare triple {332#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {332#false} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 57: Hoare triple {332#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {332#false} is VALID [2022-02-21 04:21:46,325 INFO L290 TraceCheckUtils]: 58: Hoare triple {332#false} assume !(0 != start_simulation_~tmp___0~1#1); {332#false} is VALID [2022-02-21 04:21:46,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:46,326 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:46,326 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733614168] [2022-02-21 04:21:46,326 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733614168] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:46,327 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:46,327 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:46,327 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1720514553] [2022-02-21 04:21:46,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:46,330 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:46,331 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:46,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:46,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:46,362 INFO L87 Difference]: Start difference. First operand has 324 states, 323 states have (on average 1.5356037151702786) internal successors, (496), 323 states have internal predecessors, (496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,783 INFO L93 Difference]: Finished difference Result 323 states and 481 transitions. [2022-02-21 04:21:46,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:46,784 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,836 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:46,841 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 481 transitions. [2022-02-21 04:21:46,855 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:46,871 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 318 states and 476 transitions. [2022-02-21 04:21:46,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2022-02-21 04:21:46,873 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2022-02-21 04:21:46,873 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 476 transitions. [2022-02-21 04:21:46,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:46,875 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2022-02-21 04:21:46,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 476 transitions. [2022-02-21 04:21:46,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2022-02-21 04:21:46,910 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:46,913 INFO L82 GeneralOperation]: Start isEquivalent. First operand 318 states and 476 transitions. Second operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,916 INFO L74 IsIncluded]: Start isIncluded. First operand 318 states and 476 transitions. Second operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,919 INFO L87 Difference]: Start difference. First operand 318 states and 476 transitions. Second operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,933 INFO L93 Difference]: Finished difference Result 318 states and 476 transitions. [2022-02-21 04:21:46,934 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 476 transitions. [2022-02-21 04:21:46,951 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,952 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,953 INFO L74 IsIncluded]: Start isIncluded. First operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 476 transitions. [2022-02-21 04:21:46,954 INFO L87 Difference]: Start difference. First operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 476 transitions. [2022-02-21 04:21:46,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:46,966 INFO L93 Difference]: Finished difference Result 318 states and 476 transitions. [2022-02-21 04:21:46,966 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 476 transitions. [2022-02-21 04:21:46,968 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:46,968 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:46,968 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:46,969 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:46,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4968553459119496) internal successors, (476), 317 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:46,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 476 transitions. [2022-02-21 04:21:46,980 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2022-02-21 04:21:46,980 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 476 transitions. [2022-02-21 04:21:46,980 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:46,981 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 476 transitions. [2022-02-21 04:21:46,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:46,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:46,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:46,985 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,985 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:46,986 INFO L791 eck$LassoCheckResult]: Stem: 973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 942#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 943#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 947#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 847#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 848#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 934#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 919#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 920#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 927#L429 assume !(0 == ~M_E~0); 756#L429-2 assume !(0 == ~T1_E~0); 757#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 878#L439-1 assume !(0 == ~T3_E~0); 900#L444-1 assume !(0 == ~E_M~0); 901#L449-1 assume !(0 == ~E_1~0); 762#L454-1 assume !(0 == ~E_2~0); 763#L459-1 assume !(0 == ~E_3~0); 723#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 724#L208 assume 1 == ~m_pc~0; 969#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 971#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 743#L531 assume !(0 != activate_threads_~tmp~1#1); 744#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 853#L227 assume !(1 == ~t1_pc~0); 741#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 742#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 928#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 760#L539 assume !(0 != activate_threads_~tmp___0~0#1); 761#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 793#L246 assume 1 == ~t2_pc~0; 794#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 866#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 881#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 933#L547 assume !(0 != activate_threads_~tmp___1~0#1); 938#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 803#L265 assume !(1 == ~t3_pc~0); 685#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 658#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 659#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 883#L555 assume !(0 != activate_threads_~tmp___2~0#1); 775#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 776#L477 assume !(1 == ~M_E~0); 932#L477-2 assume !(1 == ~T1_E~0); 944#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 895#L487-1 assume !(1 == ~T3_E~0); 896#L492-1 assume !(1 == ~E_M~0); 731#L497-1 assume !(1 == ~E_1~0); 732#L502-1 assume !(1 == ~E_2~0); 710#L507-1 assume !(1 == ~E_3~0); 711#L512-1 assume { :end_inline_reset_delta_events } true; 800#L678-2 [2022-02-21 04:21:46,986 INFO L793 eck$LassoCheckResult]: Loop: 800#L678-2 assume !false; 925#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 689#L404 assume !false; 852#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 833#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 695#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 727#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 780#L357 assume !(0 != eval_~tmp~0#1); 660#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 661#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 771#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 962#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 921#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 922#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 769#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 770#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 787#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 819#L459-3 assume !(0 == ~E_3~0); 764#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 765#L208-15 assume !(1 == ~m_pc~0); 906#L208-17 is_master_triggered_~__retres1~0#1 := 0; 907#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 751#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 752#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 788#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 789#L227-15 assume !(1 == ~t1_pc~0); 965#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 952#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 686#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 687#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 917#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 902#L246-15 assume 1 == ~t2_pc~0; 666#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 667#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 958#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 966#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 753#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 754#L265-15 assume 1 == ~t3_pc~0; 828#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 830#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 811#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 806#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 807#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 908#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 909#L482-3 assume !(1 == ~T2_E~0); 818#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 747#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 748#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 872#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 873#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 842#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 714#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 675#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 676#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 755#L697 assume !(0 == start_simulation_~tmp~3#1); 656#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 657#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 798#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 783#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 784#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 929#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 930#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 799#L710 assume !(0 != start_simulation_~tmp___0~1#1); 800#L678-2 [2022-02-21 04:21:46,986 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:46,987 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2022-02-21 04:21:46,987 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:46,987 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111881399] [2022-02-21 04:21:46,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:46,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,024 INFO L290 TraceCheckUtils]: 0: Hoare triple {1613#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {1613#true} is VALID [2022-02-21 04:21:47,025 INFO L290 TraceCheckUtils]: 1: Hoare triple {1613#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {1615#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:47,026 INFO L290 TraceCheckUtils]: 2: Hoare triple {1615#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {1615#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:47,027 INFO L290 TraceCheckUtils]: 3: Hoare triple {1615#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {1615#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:47,035 INFO L290 TraceCheckUtils]: 4: Hoare triple {1615#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {1615#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:47,036 INFO L290 TraceCheckUtils]: 5: Hoare triple {1615#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {1615#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:47,036 INFO L290 TraceCheckUtils]: 6: Hoare triple {1615#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {1614#false} is VALID [2022-02-21 04:21:47,036 INFO L290 TraceCheckUtils]: 7: Hoare triple {1614#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {1614#false} is VALID [2022-02-21 04:21:47,037 INFO L290 TraceCheckUtils]: 8: Hoare triple {1614#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {1614#false} is VALID [2022-02-21 04:21:47,037 INFO L290 TraceCheckUtils]: 9: Hoare triple {1614#false} assume !(0 == ~M_E~0); {1614#false} is VALID [2022-02-21 04:21:47,037 INFO L290 TraceCheckUtils]: 10: Hoare triple {1614#false} assume !(0 == ~T1_E~0); {1614#false} is VALID [2022-02-21 04:21:47,037 INFO L290 TraceCheckUtils]: 11: Hoare triple {1614#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1614#false} is VALID [2022-02-21 04:21:47,037 INFO L290 TraceCheckUtils]: 12: Hoare triple {1614#false} assume !(0 == ~T3_E~0); {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 13: Hoare triple {1614#false} assume !(0 == ~E_M~0); {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 14: Hoare triple {1614#false} assume !(0 == ~E_1~0); {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 15: Hoare triple {1614#false} assume !(0 == ~E_2~0); {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 16: Hoare triple {1614#false} assume !(0 == ~E_3~0); {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 17: Hoare triple {1614#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1614#false} is VALID [2022-02-21 04:21:47,038 INFO L290 TraceCheckUtils]: 18: Hoare triple {1614#false} assume 1 == ~m_pc~0; {1614#false} is VALID [2022-02-21 04:21:47,039 INFO L290 TraceCheckUtils]: 19: Hoare triple {1614#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {1614#false} is VALID [2022-02-21 04:21:47,039 INFO L290 TraceCheckUtils]: 20: Hoare triple {1614#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1614#false} is VALID [2022-02-21 04:21:47,039 INFO L290 TraceCheckUtils]: 21: Hoare triple {1614#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1614#false} is VALID [2022-02-21 04:21:47,039 INFO L290 TraceCheckUtils]: 22: Hoare triple {1614#false} assume !(0 != activate_threads_~tmp~1#1); {1614#false} is VALID [2022-02-21 04:21:47,039 INFO L290 TraceCheckUtils]: 23: Hoare triple {1614#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1614#false} is VALID [2022-02-21 04:21:47,040 INFO L290 TraceCheckUtils]: 24: Hoare triple {1614#false} assume !(1 == ~t1_pc~0); {1614#false} is VALID [2022-02-21 04:21:47,040 INFO L290 TraceCheckUtils]: 25: Hoare triple {1614#false} is_transmit1_triggered_~__retres1~1#1 := 0; {1614#false} is VALID [2022-02-21 04:21:47,040 INFO L290 TraceCheckUtils]: 26: Hoare triple {1614#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1614#false} is VALID [2022-02-21 04:21:47,040 INFO L290 TraceCheckUtils]: 27: Hoare triple {1614#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1614#false} is VALID [2022-02-21 04:21:47,040 INFO L290 TraceCheckUtils]: 28: Hoare triple {1614#false} assume !(0 != activate_threads_~tmp___0~0#1); {1614#false} is VALID [2022-02-21 04:21:47,041 INFO L290 TraceCheckUtils]: 29: Hoare triple {1614#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1614#false} is VALID [2022-02-21 04:21:47,041 INFO L290 TraceCheckUtils]: 30: Hoare triple {1614#false} assume 1 == ~t2_pc~0; {1614#false} is VALID [2022-02-21 04:21:47,041 INFO L290 TraceCheckUtils]: 31: Hoare triple {1614#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1614#false} is VALID [2022-02-21 04:21:47,041 INFO L290 TraceCheckUtils]: 32: Hoare triple {1614#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1614#false} is VALID [2022-02-21 04:21:47,041 INFO L290 TraceCheckUtils]: 33: Hoare triple {1614#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {1614#false} is VALID [2022-02-21 04:21:47,042 INFO L290 TraceCheckUtils]: 34: Hoare triple {1614#false} assume !(0 != activate_threads_~tmp___1~0#1); {1614#false} is VALID [2022-02-21 04:21:47,042 INFO L290 TraceCheckUtils]: 35: Hoare triple {1614#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1614#false} is VALID [2022-02-21 04:21:47,042 INFO L290 TraceCheckUtils]: 36: Hoare triple {1614#false} assume !(1 == ~t3_pc~0); {1614#false} is VALID [2022-02-21 04:21:47,042 INFO L290 TraceCheckUtils]: 37: Hoare triple {1614#false} is_transmit3_triggered_~__retres1~3#1 := 0; {1614#false} is VALID [2022-02-21 04:21:47,042 INFO L290 TraceCheckUtils]: 38: Hoare triple {1614#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 39: Hoare triple {1614#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 40: Hoare triple {1614#false} assume !(0 != activate_threads_~tmp___2~0#1); {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 41: Hoare triple {1614#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 42: Hoare triple {1614#false} assume !(1 == ~M_E~0); {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 43: Hoare triple {1614#false} assume !(1 == ~T1_E~0); {1614#false} is VALID [2022-02-21 04:21:47,043 INFO L290 TraceCheckUtils]: 44: Hoare triple {1614#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {1614#false} is VALID [2022-02-21 04:21:47,044 INFO L290 TraceCheckUtils]: 45: Hoare triple {1614#false} assume !(1 == ~T3_E~0); {1614#false} is VALID [2022-02-21 04:21:47,044 INFO L290 TraceCheckUtils]: 46: Hoare triple {1614#false} assume !(1 == ~E_M~0); {1614#false} is VALID [2022-02-21 04:21:47,044 INFO L290 TraceCheckUtils]: 47: Hoare triple {1614#false} assume !(1 == ~E_1~0); {1614#false} is VALID [2022-02-21 04:21:47,044 INFO L290 TraceCheckUtils]: 48: Hoare triple {1614#false} assume !(1 == ~E_2~0); {1614#false} is VALID [2022-02-21 04:21:47,044 INFO L290 TraceCheckUtils]: 49: Hoare triple {1614#false} assume !(1 == ~E_3~0); {1614#false} is VALID [2022-02-21 04:21:47,045 INFO L290 TraceCheckUtils]: 50: Hoare triple {1614#false} assume { :end_inline_reset_delta_events } true; {1614#false} is VALID [2022-02-21 04:21:47,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,045 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,046 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111881399] [2022-02-21 04:21:47,046 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111881399] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,046 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,046 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:47,046 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [92087910] [2022-02-21 04:21:47,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,047 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:47,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,048 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 1 times [2022-02-21 04:21:47,048 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,048 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932537931] [2022-02-21 04:21:47,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,123 INFO L290 TraceCheckUtils]: 0: Hoare triple {1616#true} assume !false; {1616#true} is VALID [2022-02-21 04:21:47,123 INFO L290 TraceCheckUtils]: 1: Hoare triple {1616#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {1616#true} is VALID [2022-02-21 04:21:47,123 INFO L290 TraceCheckUtils]: 2: Hoare triple {1616#true} assume !false; {1616#true} is VALID [2022-02-21 04:21:47,123 INFO L290 TraceCheckUtils]: 3: Hoare triple {1616#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {1616#true} is VALID [2022-02-21 04:21:47,124 INFO L290 TraceCheckUtils]: 4: Hoare triple {1616#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {1616#true} is VALID [2022-02-21 04:21:47,124 INFO L290 TraceCheckUtils]: 5: Hoare triple {1616#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {1616#true} is VALID [2022-02-21 04:21:47,124 INFO L290 TraceCheckUtils]: 6: Hoare triple {1616#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {1616#true} is VALID [2022-02-21 04:21:47,124 INFO L290 TraceCheckUtils]: 7: Hoare triple {1616#true} assume !(0 != eval_~tmp~0#1); {1616#true} is VALID [2022-02-21 04:21:47,124 INFO L290 TraceCheckUtils]: 8: Hoare triple {1616#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {1616#true} is VALID [2022-02-21 04:21:47,125 INFO L290 TraceCheckUtils]: 9: Hoare triple {1616#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {1616#true} is VALID [2022-02-21 04:21:47,125 INFO L290 TraceCheckUtils]: 10: Hoare triple {1616#true} assume 0 == ~M_E~0;~M_E~0 := 1; {1616#true} is VALID [2022-02-21 04:21:47,125 INFO L290 TraceCheckUtils]: 11: Hoare triple {1616#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {1616#true} is VALID [2022-02-21 04:21:47,126 INFO L290 TraceCheckUtils]: 12: Hoare triple {1616#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,126 INFO L290 TraceCheckUtils]: 13: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,126 INFO L290 TraceCheckUtils]: 14: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,127 INFO L290 TraceCheckUtils]: 15: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,127 INFO L290 TraceCheckUtils]: 16: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,128 INFO L290 TraceCheckUtils]: 17: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_3~0); {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,128 INFO L290 TraceCheckUtils]: 18: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,129 INFO L290 TraceCheckUtils]: 19: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,129 INFO L290 TraceCheckUtils]: 20: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,130 INFO L290 TraceCheckUtils]: 21: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,130 INFO L290 TraceCheckUtils]: 22: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,130 INFO L290 TraceCheckUtils]: 23: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,131 INFO L290 TraceCheckUtils]: 24: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,131 INFO L290 TraceCheckUtils]: 25: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,132 INFO L290 TraceCheckUtils]: 26: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,132 INFO L290 TraceCheckUtils]: 27: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,133 INFO L290 TraceCheckUtils]: 28: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,133 INFO L290 TraceCheckUtils]: 29: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,133 INFO L290 TraceCheckUtils]: 30: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,134 INFO L290 TraceCheckUtils]: 31: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,134 INFO L290 TraceCheckUtils]: 32: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,135 INFO L290 TraceCheckUtils]: 33: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,135 INFO L290 TraceCheckUtils]: 34: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,135 INFO L290 TraceCheckUtils]: 35: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,136 INFO L290 TraceCheckUtils]: 36: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,136 INFO L290 TraceCheckUtils]: 37: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,137 INFO L290 TraceCheckUtils]: 38: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,137 INFO L290 TraceCheckUtils]: 39: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,137 INFO L290 TraceCheckUtils]: 40: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,141 INFO L290 TraceCheckUtils]: 41: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,142 INFO L290 TraceCheckUtils]: 42: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,143 INFO L290 TraceCheckUtils]: 43: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,143 INFO L290 TraceCheckUtils]: 44: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {1618#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 45: Hoare triple {1618#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {1617#false} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 46: Hoare triple {1617#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {1617#false} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 47: Hoare triple {1617#false} assume 1 == ~E_M~0;~E_M~0 := 2; {1617#false} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 48: Hoare triple {1617#false} assume 1 == ~E_1~0;~E_1~0 := 2; {1617#false} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 49: Hoare triple {1617#false} assume 1 == ~E_2~0;~E_2~0 := 2; {1617#false} is VALID [2022-02-21 04:21:47,144 INFO L290 TraceCheckUtils]: 50: Hoare triple {1617#false} assume 1 == ~E_3~0;~E_3~0 := 2; {1617#false} is VALID [2022-02-21 04:21:47,145 INFO L290 TraceCheckUtils]: 51: Hoare triple {1617#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {1617#false} is VALID [2022-02-21 04:21:47,145 INFO L290 TraceCheckUtils]: 52: Hoare triple {1617#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {1617#false} is VALID [2022-02-21 04:21:47,145 INFO L290 TraceCheckUtils]: 53: Hoare triple {1617#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {1617#false} is VALID [2022-02-21 04:21:47,145 INFO L290 TraceCheckUtils]: 54: Hoare triple {1617#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {1617#false} is VALID [2022-02-21 04:21:47,145 INFO L290 TraceCheckUtils]: 55: Hoare triple {1617#false} assume !(0 == start_simulation_~tmp~3#1); {1617#false} is VALID [2022-02-21 04:21:47,146 INFO L290 TraceCheckUtils]: 56: Hoare triple {1617#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {1617#false} is VALID [2022-02-21 04:21:47,146 INFO L290 TraceCheckUtils]: 57: Hoare triple {1617#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {1617#false} is VALID [2022-02-21 04:21:47,146 INFO L290 TraceCheckUtils]: 58: Hoare triple {1617#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {1617#false} is VALID [2022-02-21 04:21:47,146 INFO L290 TraceCheckUtils]: 59: Hoare triple {1617#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {1617#false} is VALID [2022-02-21 04:21:47,146 INFO L290 TraceCheckUtils]: 60: Hoare triple {1617#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {1617#false} is VALID [2022-02-21 04:21:47,148 INFO L290 TraceCheckUtils]: 61: Hoare triple {1617#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {1617#false} is VALID [2022-02-21 04:21:47,149 INFO L290 TraceCheckUtils]: 62: Hoare triple {1617#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {1617#false} is VALID [2022-02-21 04:21:47,149 INFO L290 TraceCheckUtils]: 63: Hoare triple {1617#false} assume !(0 != start_simulation_~tmp___0~1#1); {1617#false} is VALID [2022-02-21 04:21:47,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,152 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,152 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932537931] [2022-02-21 04:21:47,152 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932537931] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,153 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,153 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:47,154 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [108644481] [2022-02-21 04:21:47,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,154 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:47,154 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:47,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:47,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:47,155 INFO L87 Difference]: Start difference. First operand 318 states and 476 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,462 INFO L93 Difference]: Finished difference Result 318 states and 475 transitions. [2022-02-21 04:21:47,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:47,462 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,503 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:47,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:47,524 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 475 transitions. [2022-02-21 04:21:47,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2022-02-21 04:21:47,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2022-02-21 04:21:47,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:47,529 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2022-02-21 04:21:47,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2022-02-21 04:21:47,551 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:47,552 INFO L82 GeneralOperation]: Start isEquivalent. First operand 318 states and 475 transitions. Second operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,553 INFO L74 IsIncluded]: Start isIncluded. First operand 318 states and 475 transitions. Second operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,554 INFO L87 Difference]: Start difference. First operand 318 states and 475 transitions. Second operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,563 INFO L93 Difference]: Finished difference Result 318 states and 475 transitions. [2022-02-21 04:21:47,563 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,564 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,564 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,565 INFO L74 IsIncluded]: Start isIncluded. First operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 475 transitions. [2022-02-21 04:21:47,566 INFO L87 Difference]: Start difference. First operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 475 transitions. [2022-02-21 04:21:47,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,574 INFO L93 Difference]: Finished difference Result 318 states and 475 transitions. [2022-02-21 04:21:47,575 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,575 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:47,575 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:47,576 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:47,576 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:47,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.4937106918238994) internal successors, (475), 317 states have internal predecessors, (475), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 475 transitions. [2022-02-21 04:21:47,598 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2022-02-21 04:21:47,598 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 475 transitions. [2022-02-21 04:21:47,598 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:47,598 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 475 transitions. [2022-02-21 04:21:47,600 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:47,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:47,600 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:47,602 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,602 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,602 INFO L791 eck$LassoCheckResult]: Stem: 2254#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2224#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2228#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2126#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2127#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2215#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2199#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2200#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2208#L429 assume !(0 == ~M_E~0); 2037#L429-2 assume !(0 == ~T1_E~0); 2038#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2158#L439-1 assume !(0 == ~T3_E~0); 2181#L444-1 assume !(0 == ~E_M~0); 2182#L449-1 assume !(0 == ~E_1~0); 2043#L454-1 assume !(0 == ~E_2~0); 2044#L459-1 assume !(0 == ~E_3~0); 2004#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2005#L208 assume 1 == ~m_pc~0; 2250#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2252#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2072#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2024#L531 assume !(0 != activate_threads_~tmp~1#1); 2025#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2134#L227 assume !(1 == ~t1_pc~0); 2022#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2023#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2209#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2041#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2042#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2073#L246 assume 1 == ~t2_pc~0; 2074#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2147#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2162#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2214#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2218#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2082#L265 assume !(1 == ~t3_pc~0); 1966#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1939#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1940#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2164#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2053#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2054#L477 assume !(1 == ~M_E~0); 2213#L477-2 assume !(1 == ~T1_E~0); 2225#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2176#L487-1 assume !(1 == ~T3_E~0); 2177#L492-1 assume !(1 == ~E_M~0); 2009#L497-1 assume !(1 == ~E_1~0); 2010#L502-1 assume !(1 == ~E_2~0); 1991#L507-1 assume !(1 == ~E_3~0); 1992#L512-1 assume { :end_inline_reset_delta_events } true; 2081#L678-2 [2022-02-21 04:21:47,602 INFO L793 eck$LassoCheckResult]: Loop: 2081#L678-2 assume !false; 2204#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1970#L404 assume !false; 2133#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2109#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1976#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2008#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2060#L357 assume !(0 != eval_~tmp~0#1); 1941#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1942#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2052#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2243#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2202#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2203#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2050#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2051#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2066#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2099#L459-3 assume !(0 == ~E_3~0); 2045#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2046#L208-15 assume !(1 == ~m_pc~0); 2187#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2188#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2032#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2033#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2067#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2068#L227-15 assume !(1 == ~t1_pc~0); 2245#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2233#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1967#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1968#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2198#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2183#L246-15 assume !(1 == ~t2_pc~0); 1953#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 1952#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2239#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2248#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2034#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2035#L265-15 assume 1 == ~t3_pc~0; 2110#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2112#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2093#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2088#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2089#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2221#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2189#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2190#L482-3 assume !(1 == ~T2_E~0); 2100#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2030#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2031#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2153#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2154#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2124#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1995#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1958#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1959#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2036#L697 assume !(0 == start_simulation_~tmp~3#1); 1937#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1938#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2079#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2064#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2065#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2210#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2211#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2080#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2081#L678-2 [2022-02-21 04:21:47,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2022-02-21 04:21:47,603 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,603 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131124579] [2022-02-21 04:21:47,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,677 INFO L290 TraceCheckUtils]: 0: Hoare triple {2894#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {2894#true} is VALID [2022-02-21 04:21:47,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {2894#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,678 INFO L290 TraceCheckUtils]: 2: Hoare triple {2896#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,678 INFO L290 TraceCheckUtils]: 3: Hoare triple {2896#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,678 INFO L290 TraceCheckUtils]: 4: Hoare triple {2896#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,679 INFO L290 TraceCheckUtils]: 5: Hoare triple {2896#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,679 INFO L290 TraceCheckUtils]: 6: Hoare triple {2896#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {2896#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:47,679 INFO L290 TraceCheckUtils]: 7: Hoare triple {2896#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2895#false} is VALID [2022-02-21 04:21:47,679 INFO L290 TraceCheckUtils]: 8: Hoare triple {2895#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 9: Hoare triple {2895#false} assume !(0 == ~M_E~0); {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 10: Hoare triple {2895#false} assume !(0 == ~T1_E~0); {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 11: Hoare triple {2895#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 12: Hoare triple {2895#false} assume !(0 == ~T3_E~0); {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 13: Hoare triple {2895#false} assume !(0 == ~E_M~0); {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 14: Hoare triple {2895#false} assume !(0 == ~E_1~0); {2895#false} is VALID [2022-02-21 04:21:47,680 INFO L290 TraceCheckUtils]: 15: Hoare triple {2895#false} assume !(0 == ~E_2~0); {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 16: Hoare triple {2895#false} assume !(0 == ~E_3~0); {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 17: Hoare triple {2895#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 18: Hoare triple {2895#false} assume 1 == ~m_pc~0; {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 19: Hoare triple {2895#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 20: Hoare triple {2895#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 21: Hoare triple {2895#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 22: Hoare triple {2895#false} assume !(0 != activate_threads_~tmp~1#1); {2895#false} is VALID [2022-02-21 04:21:47,681 INFO L290 TraceCheckUtils]: 23: Hoare triple {2895#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 24: Hoare triple {2895#false} assume !(1 == ~t1_pc~0); {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 25: Hoare triple {2895#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 26: Hoare triple {2895#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 27: Hoare triple {2895#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 28: Hoare triple {2895#false} assume !(0 != activate_threads_~tmp___0~0#1); {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 29: Hoare triple {2895#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 30: Hoare triple {2895#false} assume 1 == ~t2_pc~0; {2895#false} is VALID [2022-02-21 04:21:47,682 INFO L290 TraceCheckUtils]: 31: Hoare triple {2895#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 32: Hoare triple {2895#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 33: Hoare triple {2895#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 34: Hoare triple {2895#false} assume !(0 != activate_threads_~tmp___1~0#1); {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 35: Hoare triple {2895#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 36: Hoare triple {2895#false} assume !(1 == ~t3_pc~0); {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 37: Hoare triple {2895#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2895#false} is VALID [2022-02-21 04:21:47,683 INFO L290 TraceCheckUtils]: 38: Hoare triple {2895#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 39: Hoare triple {2895#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 40: Hoare triple {2895#false} assume !(0 != activate_threads_~tmp___2~0#1); {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 41: Hoare triple {2895#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 42: Hoare triple {2895#false} assume !(1 == ~M_E~0); {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 43: Hoare triple {2895#false} assume !(1 == ~T1_E~0); {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 44: Hoare triple {2895#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 45: Hoare triple {2895#false} assume !(1 == ~T3_E~0); {2895#false} is VALID [2022-02-21 04:21:47,684 INFO L290 TraceCheckUtils]: 46: Hoare triple {2895#false} assume !(1 == ~E_M~0); {2895#false} is VALID [2022-02-21 04:21:47,685 INFO L290 TraceCheckUtils]: 47: Hoare triple {2895#false} assume !(1 == ~E_1~0); {2895#false} is VALID [2022-02-21 04:21:47,685 INFO L290 TraceCheckUtils]: 48: Hoare triple {2895#false} assume !(1 == ~E_2~0); {2895#false} is VALID [2022-02-21 04:21:47,685 INFO L290 TraceCheckUtils]: 49: Hoare triple {2895#false} assume !(1 == ~E_3~0); {2895#false} is VALID [2022-02-21 04:21:47,685 INFO L290 TraceCheckUtils]: 50: Hoare triple {2895#false} assume { :end_inline_reset_delta_events } true; {2895#false} is VALID [2022-02-21 04:21:47,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,685 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,686 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131124579] [2022-02-21 04:21:47,686 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131124579] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,686 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,686 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:47,686 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [651875910] [2022-02-21 04:21:47,686 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,686 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:47,687 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,687 INFO L85 PathProgramCache]: Analyzing trace with hash -2071506233, now seen corresponding path program 1 times [2022-02-21 04:21:47,687 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,687 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319898444] [2022-02-21 04:21:47,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,725 INFO L290 TraceCheckUtils]: 0: Hoare triple {2897#true} assume !false; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 1: Hoare triple {2897#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 2: Hoare triple {2897#true} assume !false; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 3: Hoare triple {2897#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 4: Hoare triple {2897#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 5: Hoare triple {2897#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 6: Hoare triple {2897#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {2897#true} is VALID [2022-02-21 04:21:47,726 INFO L290 TraceCheckUtils]: 7: Hoare triple {2897#true} assume !(0 != eval_~tmp~0#1); {2897#true} is VALID [2022-02-21 04:21:47,727 INFO L290 TraceCheckUtils]: 8: Hoare triple {2897#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2897#true} is VALID [2022-02-21 04:21:47,727 INFO L290 TraceCheckUtils]: 9: Hoare triple {2897#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2897#true} is VALID [2022-02-21 04:21:47,727 INFO L290 TraceCheckUtils]: 10: Hoare triple {2897#true} assume 0 == ~M_E~0;~M_E~0 := 1; {2897#true} is VALID [2022-02-21 04:21:47,727 INFO L290 TraceCheckUtils]: 11: Hoare triple {2897#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2897#true} is VALID [2022-02-21 04:21:47,727 INFO L290 TraceCheckUtils]: 12: Hoare triple {2897#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,728 INFO L290 TraceCheckUtils]: 13: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,728 INFO L290 TraceCheckUtils]: 14: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,729 INFO L290 TraceCheckUtils]: 15: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,729 INFO L290 TraceCheckUtils]: 16: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,729 INFO L290 TraceCheckUtils]: 17: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_3~0); {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,730 INFO L290 TraceCheckUtils]: 18: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,730 INFO L290 TraceCheckUtils]: 19: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,730 INFO L290 TraceCheckUtils]: 20: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,731 INFO L290 TraceCheckUtils]: 21: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,731 INFO L290 TraceCheckUtils]: 22: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,731 INFO L290 TraceCheckUtils]: 23: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,732 INFO L290 TraceCheckUtils]: 24: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,732 INFO L290 TraceCheckUtils]: 25: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,734 INFO L290 TraceCheckUtils]: 26: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,735 INFO L290 TraceCheckUtils]: 27: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,735 INFO L290 TraceCheckUtils]: 28: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,735 INFO L290 TraceCheckUtils]: 29: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,736 INFO L290 TraceCheckUtils]: 30: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,736 INFO L290 TraceCheckUtils]: 31: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,736 INFO L290 TraceCheckUtils]: 32: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,737 INFO L290 TraceCheckUtils]: 33: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,737 INFO L290 TraceCheckUtils]: 34: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,738 INFO L290 TraceCheckUtils]: 35: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,738 INFO L290 TraceCheckUtils]: 36: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,738 INFO L290 TraceCheckUtils]: 37: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,739 INFO L290 TraceCheckUtils]: 38: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,739 INFO L290 TraceCheckUtils]: 39: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,740 INFO L290 TraceCheckUtils]: 40: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,740 INFO L290 TraceCheckUtils]: 41: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,740 INFO L290 TraceCheckUtils]: 42: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,741 INFO L290 TraceCheckUtils]: 43: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,741 INFO L290 TraceCheckUtils]: 44: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2899#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:47,742 INFO L290 TraceCheckUtils]: 45: Hoare triple {2899#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {2898#false} is VALID [2022-02-21 04:21:47,742 INFO L290 TraceCheckUtils]: 46: Hoare triple {2898#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2898#false} is VALID [2022-02-21 04:21:47,742 INFO L290 TraceCheckUtils]: 47: Hoare triple {2898#false} assume 1 == ~E_M~0;~E_M~0 := 2; {2898#false} is VALID [2022-02-21 04:21:47,742 INFO L290 TraceCheckUtils]: 48: Hoare triple {2898#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2898#false} is VALID [2022-02-21 04:21:47,742 INFO L290 TraceCheckUtils]: 49: Hoare triple {2898#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 50: Hoare triple {2898#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 51: Hoare triple {2898#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 52: Hoare triple {2898#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 53: Hoare triple {2898#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 54: Hoare triple {2898#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {2898#false} is VALID [2022-02-21 04:21:47,743 INFO L290 TraceCheckUtils]: 55: Hoare triple {2898#false} assume !(0 == start_simulation_~tmp~3#1); {2898#false} is VALID [2022-02-21 04:21:47,744 INFO L290 TraceCheckUtils]: 56: Hoare triple {2898#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {2898#false} is VALID [2022-02-21 04:21:47,744 INFO L290 TraceCheckUtils]: 57: Hoare triple {2898#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {2898#false} is VALID [2022-02-21 04:21:47,744 INFO L290 TraceCheckUtils]: 58: Hoare triple {2898#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {2898#false} is VALID [2022-02-21 04:21:47,744 INFO L290 TraceCheckUtils]: 59: Hoare triple {2898#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {2898#false} is VALID [2022-02-21 04:21:47,744 INFO L290 TraceCheckUtils]: 60: Hoare triple {2898#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2898#false} is VALID [2022-02-21 04:21:47,745 INFO L290 TraceCheckUtils]: 61: Hoare triple {2898#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2898#false} is VALID [2022-02-21 04:21:47,745 INFO L290 TraceCheckUtils]: 62: Hoare triple {2898#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {2898#false} is VALID [2022-02-21 04:21:47,745 INFO L290 TraceCheckUtils]: 63: Hoare triple {2898#false} assume !(0 != start_simulation_~tmp___0~1#1); {2898#false} is VALID [2022-02-21 04:21:47,745 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,746 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,746 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319898444] [2022-02-21 04:21:47,746 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319898444] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,746 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,746 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:47,746 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [391388064] [2022-02-21 04:21:47,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,747 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:47,747 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:47,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:47,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:47,748 INFO L87 Difference]: Start difference. First operand 318 states and 475 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,054 INFO L93 Difference]: Finished difference Result 318 states and 474 transitions. [2022-02-21 04:21:48,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:48,055 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,100 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:48,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:48,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 318 states to 318 states and 474 transitions. [2022-02-21 04:21:48,118 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 318 [2022-02-21 04:21:48,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 318 [2022-02-21 04:21:48,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:48,119 INFO L681 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2022-02-21 04:21:48,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 318 to 318. [2022-02-21 04:21:48,129 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:48,130 INFO L82 GeneralOperation]: Start isEquivalent. First operand 318 states and 474 transitions. Second operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,130 INFO L74 IsIncluded]: Start isIncluded. First operand 318 states and 474 transitions. Second operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,131 INFO L87 Difference]: Start difference. First operand 318 states and 474 transitions. Second operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,137 INFO L93 Difference]: Finished difference Result 318 states and 474 transitions. [2022-02-21 04:21:48,137 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,138 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,138 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,139 INFO L74 IsIncluded]: Start isIncluded. First operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 474 transitions. [2022-02-21 04:21:48,140 INFO L87 Difference]: Start difference. First operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 318 states and 474 transitions. [2022-02-21 04:21:48,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,146 INFO L93 Difference]: Finished difference Result 318 states and 474 transitions. [2022-02-21 04:21:48,146 INFO L276 IsEmpty]: Start isEmpty. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,147 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,147 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,147 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,147 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318 states, 318 states have (on average 1.490566037735849) internal successors, (474), 317 states have internal predecessors, (474), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 474 transitions. [2022-02-21 04:21:48,154 INFO L704 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2022-02-21 04:21:48,154 INFO L587 BuchiCegarLoop]: Abstraction has 318 states and 474 transitions. [2022-02-21 04:21:48,154 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:48,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 474 transitions. [2022-02-21 04:21:48,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 263 [2022-02-21 04:21:48,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,159 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,159 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,160 INFO L791 eck$LassoCheckResult]: Stem: 3535#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3504#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3505#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3509#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3409#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3410#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3496#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3481#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3482#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3489#L429 assume !(0 == ~M_E~0); 3318#L429-2 assume !(0 == ~T1_E~0); 3319#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3440#L439-1 assume !(0 == ~T3_E~0); 3462#L444-1 assume !(0 == ~E_M~0); 3463#L449-1 assume !(0 == ~E_1~0); 3324#L454-1 assume !(0 == ~E_2~0); 3325#L459-1 assume !(0 == ~E_3~0); 3285#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3286#L208 assume 1 == ~m_pc~0; 3531#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3533#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3354#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3305#L531 assume !(0 != activate_threads_~tmp~1#1); 3306#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3415#L227 assume !(1 == ~t1_pc~0); 3303#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3304#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3490#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3322#L539 assume !(0 != activate_threads_~tmp___0~0#1); 3323#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3355#L246 assume 1 == ~t2_pc~0; 3356#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3428#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3443#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3495#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3500#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3365#L265 assume !(1 == ~t3_pc~0); 3247#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3220#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3221#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3445#L555 assume !(0 != activate_threads_~tmp___2~0#1); 3337#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3338#L477 assume !(1 == ~M_E~0); 3494#L477-2 assume !(1 == ~T1_E~0); 3506#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3457#L487-1 assume !(1 == ~T3_E~0); 3458#L492-1 assume !(1 == ~E_M~0); 3293#L497-1 assume !(1 == ~E_1~0); 3294#L502-1 assume !(1 == ~E_2~0); 3272#L507-1 assume !(1 == ~E_3~0); 3273#L512-1 assume { :end_inline_reset_delta_events } true; 3362#L678-2 [2022-02-21 04:21:48,161 INFO L793 eck$LassoCheckResult]: Loop: 3362#L678-2 assume !false; 3487#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3251#L404 assume !false; 3414#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3395#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3257#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3289#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3342#L357 assume !(0 != eval_~tmp~0#1); 3222#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3223#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3333#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3524#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3483#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3484#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3331#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3332#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3349#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3381#L459-3 assume !(0 == ~E_3~0); 3326#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3327#L208-15 assume !(1 == ~m_pc~0); 3468#L208-17 is_master_triggered_~__retres1~0#1 := 0; 3469#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3313#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3314#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3350#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3351#L227-15 assume !(1 == ~t1_pc~0); 3526#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 3514#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3248#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3249#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3479#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3464#L246-15 assume 1 == ~t2_pc~0; 3228#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3229#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3520#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3528#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3315#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3316#L265-15 assume 1 == ~t3_pc~0; 3390#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3392#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3373#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3368#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3369#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3502#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3470#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3471#L482-3 assume !(1 == ~T2_E~0); 3380#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3309#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3310#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3434#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3435#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3404#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3276#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3237#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3238#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3317#L697 assume !(0 == start_simulation_~tmp~3#1); 3218#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3219#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3360#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 3345#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 3346#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3491#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3492#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3361#L710 assume !(0 != start_simulation_~tmp___0~1#1); 3362#L678-2 [2022-02-21 04:21:48,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,161 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2022-02-21 04:21:48,162 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,162 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2140847902] [2022-02-21 04:21:48,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,208 INFO L290 TraceCheckUtils]: 0: Hoare triple {4175#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,209 INFO L290 TraceCheckUtils]: 1: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,209 INFO L290 TraceCheckUtils]: 2: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,209 INFO L290 TraceCheckUtils]: 3: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,210 INFO L290 TraceCheckUtils]: 4: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,210 INFO L290 TraceCheckUtils]: 5: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,211 INFO L290 TraceCheckUtils]: 6: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,211 INFO L290 TraceCheckUtils]: 7: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,211 INFO L290 TraceCheckUtils]: 8: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4177#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:48,212 INFO L290 TraceCheckUtils]: 9: Hoare triple {4177#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {4178#(not (= ~T2_E~0 0))} is VALID [2022-02-21 04:21:48,212 INFO L290 TraceCheckUtils]: 10: Hoare triple {4178#(not (= ~T2_E~0 0))} assume !(0 == ~T1_E~0); {4178#(not (= ~T2_E~0 0))} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 11: Hoare triple {4178#(not (= ~T2_E~0 0))} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4176#false} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 12: Hoare triple {4176#false} assume !(0 == ~T3_E~0); {4176#false} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 13: Hoare triple {4176#false} assume !(0 == ~E_M~0); {4176#false} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 14: Hoare triple {4176#false} assume !(0 == ~E_1~0); {4176#false} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 15: Hoare triple {4176#false} assume !(0 == ~E_2~0); {4176#false} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 16: Hoare triple {4176#false} assume !(0 == ~E_3~0); {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 17: Hoare triple {4176#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 18: Hoare triple {4176#false} assume 1 == ~m_pc~0; {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 19: Hoare triple {4176#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 20: Hoare triple {4176#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 21: Hoare triple {4176#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {4176#false} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 22: Hoare triple {4176#false} assume !(0 != activate_threads_~tmp~1#1); {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 23: Hoare triple {4176#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 24: Hoare triple {4176#false} assume !(1 == ~t1_pc~0); {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 25: Hoare triple {4176#false} is_transmit1_triggered_~__retres1~1#1 := 0; {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 26: Hoare triple {4176#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 27: Hoare triple {4176#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {4176#false} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 28: Hoare triple {4176#false} assume !(0 != activate_threads_~tmp___0~0#1); {4176#false} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 29: Hoare triple {4176#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4176#false} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 30: Hoare triple {4176#false} assume 1 == ~t2_pc~0; {4176#false} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 31: Hoare triple {4176#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4176#false} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 32: Hoare triple {4176#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4176#false} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 33: Hoare triple {4176#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 34: Hoare triple {4176#false} assume !(0 != activate_threads_~tmp___1~0#1); {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 35: Hoare triple {4176#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 36: Hoare triple {4176#false} assume !(1 == ~t3_pc~0); {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 37: Hoare triple {4176#false} is_transmit3_triggered_~__retres1~3#1 := 0; {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 38: Hoare triple {4176#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4176#false} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 39: Hoare triple {4176#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 40: Hoare triple {4176#false} assume !(0 != activate_threads_~tmp___2~0#1); {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 41: Hoare triple {4176#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 42: Hoare triple {4176#false} assume !(1 == ~M_E~0); {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 43: Hoare triple {4176#false} assume !(1 == ~T1_E~0); {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 44: Hoare triple {4176#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {4176#false} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 45: Hoare triple {4176#false} assume !(1 == ~T3_E~0); {4176#false} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 46: Hoare triple {4176#false} assume !(1 == ~E_M~0); {4176#false} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 47: Hoare triple {4176#false} assume !(1 == ~E_1~0); {4176#false} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 48: Hoare triple {4176#false} assume !(1 == ~E_2~0); {4176#false} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 49: Hoare triple {4176#false} assume !(1 == ~E_3~0); {4176#false} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 50: Hoare triple {4176#false} assume { :end_inline_reset_delta_events } true; {4176#false} is VALID [2022-02-21 04:21:48,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,220 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,220 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2140847902] [2022-02-21 04:21:48,220 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2140847902] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,220 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,221 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,221 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1565050428] [2022-02-21 04:21:48,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,221 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:48,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,222 INFO L85 PathProgramCache]: Analyzing trace with hash -494948474, now seen corresponding path program 2 times [2022-02-21 04:21:48,222 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,222 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [964750054] [2022-02-21 04:21:48,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,289 INFO L290 TraceCheckUtils]: 0: Hoare triple {4179#true} assume !false; {4179#true} is VALID [2022-02-21 04:21:48,290 INFO L290 TraceCheckUtils]: 1: Hoare triple {4179#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4179#true} is VALID [2022-02-21 04:21:48,290 INFO L290 TraceCheckUtils]: 2: Hoare triple {4179#true} assume !false; {4179#true} is VALID [2022-02-21 04:21:48,290 INFO L290 TraceCheckUtils]: 3: Hoare triple {4179#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {4179#true} is VALID [2022-02-21 04:21:48,290 INFO L290 TraceCheckUtils]: 4: Hoare triple {4179#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 5: Hoare triple {4179#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 6: Hoare triple {4179#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 7: Hoare triple {4179#true} assume !(0 != eval_~tmp~0#1); {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 8: Hoare triple {4179#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 9: Hoare triple {4179#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4179#true} is VALID [2022-02-21 04:21:48,291 INFO L290 TraceCheckUtils]: 10: Hoare triple {4179#true} assume 0 == ~M_E~0;~M_E~0 := 1; {4179#true} is VALID [2022-02-21 04:21:48,292 INFO L290 TraceCheckUtils]: 11: Hoare triple {4179#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {4179#true} is VALID [2022-02-21 04:21:48,292 INFO L290 TraceCheckUtils]: 12: Hoare triple {4179#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,293 INFO L290 TraceCheckUtils]: 13: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,293 INFO L290 TraceCheckUtils]: 14: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,293 INFO L290 TraceCheckUtils]: 15: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,294 INFO L290 TraceCheckUtils]: 16: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,294 INFO L290 TraceCheckUtils]: 17: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_3~0); {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,294 INFO L290 TraceCheckUtils]: 18: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,295 INFO L290 TraceCheckUtils]: 19: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,295 INFO L290 TraceCheckUtils]: 20: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,296 INFO L290 TraceCheckUtils]: 21: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,296 INFO L290 TraceCheckUtils]: 22: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,296 INFO L290 TraceCheckUtils]: 23: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,297 INFO L290 TraceCheckUtils]: 24: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,297 INFO L290 TraceCheckUtils]: 25: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,297 INFO L290 TraceCheckUtils]: 26: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,298 INFO L290 TraceCheckUtils]: 27: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,298 INFO L290 TraceCheckUtils]: 28: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,299 INFO L290 TraceCheckUtils]: 29: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,299 INFO L290 TraceCheckUtils]: 30: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,300 INFO L290 TraceCheckUtils]: 31: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,300 INFO L290 TraceCheckUtils]: 32: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,300 INFO L290 TraceCheckUtils]: 33: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,301 INFO L290 TraceCheckUtils]: 34: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,301 INFO L290 TraceCheckUtils]: 35: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,301 INFO L290 TraceCheckUtils]: 36: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,302 INFO L290 TraceCheckUtils]: 37: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,302 INFO L290 TraceCheckUtils]: 38: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,303 INFO L290 TraceCheckUtils]: 39: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,303 INFO L290 TraceCheckUtils]: 40: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,303 INFO L290 TraceCheckUtils]: 41: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,304 INFO L290 TraceCheckUtils]: 42: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,304 INFO L290 TraceCheckUtils]: 43: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,304 INFO L290 TraceCheckUtils]: 44: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4181#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:48,305 INFO L290 TraceCheckUtils]: 45: Hoare triple {4181#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {4180#false} is VALID [2022-02-21 04:21:48,305 INFO L290 TraceCheckUtils]: 46: Hoare triple {4180#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4180#false} is VALID [2022-02-21 04:21:48,305 INFO L290 TraceCheckUtils]: 47: Hoare triple {4180#false} assume 1 == ~E_M~0;~E_M~0 := 2; {4180#false} is VALID [2022-02-21 04:21:48,305 INFO L290 TraceCheckUtils]: 48: Hoare triple {4180#false} assume 1 == ~E_1~0;~E_1~0 := 2; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 49: Hoare triple {4180#false} assume 1 == ~E_2~0;~E_2~0 := 2; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 50: Hoare triple {4180#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 51: Hoare triple {4180#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 52: Hoare triple {4180#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 53: Hoare triple {4180#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {4180#false} is VALID [2022-02-21 04:21:48,306 INFO L290 TraceCheckUtils]: 54: Hoare triple {4180#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 55: Hoare triple {4180#false} assume !(0 == start_simulation_~tmp~3#1); {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 56: Hoare triple {4180#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 57: Hoare triple {4180#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 58: Hoare triple {4180#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 59: Hoare triple {4180#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {4180#false} is VALID [2022-02-21 04:21:48,307 INFO L290 TraceCheckUtils]: 60: Hoare triple {4180#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4180#false} is VALID [2022-02-21 04:21:48,308 INFO L290 TraceCheckUtils]: 61: Hoare triple {4180#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4180#false} is VALID [2022-02-21 04:21:48,308 INFO L290 TraceCheckUtils]: 62: Hoare triple {4180#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {4180#false} is VALID [2022-02-21 04:21:48,308 INFO L290 TraceCheckUtils]: 63: Hoare triple {4180#false} assume !(0 != start_simulation_~tmp___0~1#1); {4180#false} is VALID [2022-02-21 04:21:48,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,308 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,309 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [964750054] [2022-02-21 04:21:48,309 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [964750054] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,309 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,309 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,309 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641702375] [2022-02-21 04:21:48,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:48,310 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:48,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:48,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:48,311 INFO L87 Difference]: Start difference. First operand 318 states and 474 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,068 INFO L93 Difference]: Finished difference Result 551 states and 816 transitions. [2022-02-21 04:21:49,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:49,068 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,113 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:49,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,140 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2022-02-21 04:21:49,155 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 551 states to 551 states and 816 transitions. [2022-02-21 04:21:49,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 551 [2022-02-21 04:21:49,156 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 551 [2022-02-21 04:21:49,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:49,157 INFO L681 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2022-02-21 04:21:49,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2022-02-21 04:21:49,167 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:49,169 INFO L82 GeneralOperation]: Start isEquivalent. First operand 551 states and 816 transitions. Second operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,170 INFO L74 IsIncluded]: Start isIncluded. First operand 551 states and 816 transitions. Second operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,171 INFO L87 Difference]: Start difference. First operand 551 states and 816 transitions. Second operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,186 INFO L93 Difference]: Finished difference Result 551 states and 816 transitions. [2022-02-21 04:21:49,186 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,187 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:49,187 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:49,189 INFO L74 IsIncluded]: Start isIncluded. First operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 551 states and 816 transitions. [2022-02-21 04:21:49,190 INFO L87 Difference]: Start difference. First operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 551 states and 816 transitions. [2022-02-21 04:21:49,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,205 INFO L93 Difference]: Finished difference Result 551 states and 816 transitions. [2022-02-21 04:21:49,205 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,206 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:49,206 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:49,207 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:49,207 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:49,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 551 states have (on average 1.4809437386569873) internal successors, (816), 550 states have internal predecessors, (816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 816 transitions. [2022-02-21 04:21:49,222 INFO L704 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2022-02-21 04:21:49,222 INFO L587 BuchiCegarLoop]: Abstraction has 551 states and 816 transitions. [2022-02-21 04:21:49,222 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:49,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 551 states and 816 transitions. [2022-02-21 04:21:49,225 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 488 [2022-02-21 04:21:49,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:49,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:49,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:49,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:49,227 INFO L791 eck$LassoCheckResult]: Stem: 5082#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 5037#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 5038#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5043#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4927#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4928#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5029#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5010#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5011#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5020#L429 assume !(0 == ~M_E~0); 4836#L429-2 assume !(0 == ~T1_E~0); 4837#L434-1 assume !(0 == ~T2_E~0); 4965#L439-1 assume !(0 == ~T3_E~0); 4989#L444-1 assume !(0 == ~E_M~0); 4990#L449-1 assume !(0 == ~E_1~0); 4842#L454-1 assume !(0 == ~E_2~0); 4843#L459-1 assume !(0 == ~E_3~0); 4802#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4803#L208 assume 1 == ~m_pc~0; 5076#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5078#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4872#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4823#L531 assume !(0 != activate_threads_~tmp~1#1); 4824#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4937#L227 assume !(1 == ~t1_pc~0); 4821#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4822#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5021#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4840#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4841#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4873#L246 assume 1 == ~t2_pc~0; 4874#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4952#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4969#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5028#L547 assume !(0 != activate_threads_~tmp___1~0#1); 5032#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4882#L265 assume !(1 == ~t3_pc~0); 4764#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4737#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4738#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4971#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4852#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4853#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 5025#L477-2 assume !(1 == ~T1_E~0); 5144#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5040#L487-1 assume !(1 == ~T3_E~0); 5142#L492-1 assume !(1 == ~E_M~0); 5141#L497-1 assume !(1 == ~E_1~0); 5139#L502-1 assume !(1 == ~E_2~0); 5137#L507-1 assume !(1 == ~E_3~0); 4934#L512-1 assume { :end_inline_reset_delta_events } true; 4881#L678-2 [2022-02-21 04:21:49,227 INFO L793 eck$LassoCheckResult]: Loop: 4881#L678-2 assume !false; 5015#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4768#L404 assume !false; 4935#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4936#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4806#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4807#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5070#L357 assume !(0 != eval_~tmp~0#1); 4739#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4740#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4851#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5083#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5013#L434-3 assume !(0 == ~T2_E~0); 5014#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4849#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4850#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4866#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4899#L459-3 assume !(0 == ~E_3~0); 4844#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4845#L208-15 assume 1 == ~m_pc~0; 5056#L209-5 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4998#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4831#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4832#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4867#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4868#L227-15 assume 1 == ~t1_pc~0; 5073#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5050#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4765#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4766#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5009#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4991#L246-15 assume 1 == ~t2_pc~0; 4749#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4750#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5057#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5074#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4833#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4834#L265-15 assume 1 == ~t3_pc~0; 4910#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4912#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4893#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4888#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4889#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5035#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4999#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5000#L482-3 assume !(1 == ~T2_E~0); 4900#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4829#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4830#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4958#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4959#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4925#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4793#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4756#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4757#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4835#L697 assume !(0 == start_simulation_~tmp~3#1); 4735#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4736#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 5159#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 5157#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 5155#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5153#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5151#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 4880#L710 assume !(0 != start_simulation_~tmp___0~1#1); 4881#L678-2 [2022-02-21 04:21:49,228 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:49,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2022-02-21 04:21:49,228 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:49,228 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971464008] [2022-02-21 04:21:49,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:49,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:49,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:49,260 INFO L290 TraceCheckUtils]: 0: Hoare triple {6391#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,261 INFO L290 TraceCheckUtils]: 1: Hoare triple {6393#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,261 INFO L290 TraceCheckUtils]: 2: Hoare triple {6393#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,261 INFO L290 TraceCheckUtils]: 3: Hoare triple {6393#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,262 INFO L290 TraceCheckUtils]: 4: Hoare triple {6393#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,262 INFO L290 TraceCheckUtils]: 5: Hoare triple {6393#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,262 INFO L290 TraceCheckUtils]: 6: Hoare triple {6393#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,263 INFO L290 TraceCheckUtils]: 7: Hoare triple {6393#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,263 INFO L290 TraceCheckUtils]: 8: Hoare triple {6393#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,264 INFO L290 TraceCheckUtils]: 9: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,264 INFO L290 TraceCheckUtils]: 10: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,264 INFO L290 TraceCheckUtils]: 11: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,265 INFO L290 TraceCheckUtils]: 12: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,265 INFO L290 TraceCheckUtils]: 13: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,266 INFO L290 TraceCheckUtils]: 14: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,266 INFO L290 TraceCheckUtils]: 15: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,266 INFO L290 TraceCheckUtils]: 16: Hoare triple {6393#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,267 INFO L290 TraceCheckUtils]: 17: Hoare triple {6393#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6393#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:49,267 INFO L290 TraceCheckUtils]: 18: Hoare triple {6393#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {6392#false} is VALID [2022-02-21 04:21:49,267 INFO L290 TraceCheckUtils]: 19: Hoare triple {6392#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 20: Hoare triple {6392#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 21: Hoare triple {6392#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 22: Hoare triple {6392#false} assume !(0 != activate_threads_~tmp~1#1); {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 23: Hoare triple {6392#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 24: Hoare triple {6392#false} assume !(1 == ~t1_pc~0); {6392#false} is VALID [2022-02-21 04:21:49,268 INFO L290 TraceCheckUtils]: 25: Hoare triple {6392#false} is_transmit1_triggered_~__retres1~1#1 := 0; {6392#false} is VALID [2022-02-21 04:21:49,269 INFO L290 TraceCheckUtils]: 26: Hoare triple {6392#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6392#false} is VALID [2022-02-21 04:21:49,270 INFO L290 TraceCheckUtils]: 27: Hoare triple {6392#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6392#false} is VALID [2022-02-21 04:21:49,270 INFO L290 TraceCheckUtils]: 28: Hoare triple {6392#false} assume !(0 != activate_threads_~tmp___0~0#1); {6392#false} is VALID [2022-02-21 04:21:49,270 INFO L290 TraceCheckUtils]: 29: Hoare triple {6392#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6392#false} is VALID [2022-02-21 04:21:49,270 INFO L290 TraceCheckUtils]: 30: Hoare triple {6392#false} assume 1 == ~t2_pc~0; {6392#false} is VALID [2022-02-21 04:21:49,270 INFO L290 TraceCheckUtils]: 31: Hoare triple {6392#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 32: Hoare triple {6392#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 33: Hoare triple {6392#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 34: Hoare triple {6392#false} assume !(0 != activate_threads_~tmp___1~0#1); {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 35: Hoare triple {6392#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 36: Hoare triple {6392#false} assume !(1 == ~t3_pc~0); {6392#false} is VALID [2022-02-21 04:21:49,271 INFO L290 TraceCheckUtils]: 37: Hoare triple {6392#false} is_transmit3_triggered_~__retres1~3#1 := 0; {6392#false} is VALID [2022-02-21 04:21:49,272 INFO L290 TraceCheckUtils]: 38: Hoare triple {6392#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6392#false} is VALID [2022-02-21 04:21:49,272 INFO L290 TraceCheckUtils]: 39: Hoare triple {6392#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6392#false} is VALID [2022-02-21 04:21:49,272 INFO L290 TraceCheckUtils]: 40: Hoare triple {6392#false} assume !(0 != activate_threads_~tmp___2~0#1); {6392#false} is VALID [2022-02-21 04:21:49,272 INFO L290 TraceCheckUtils]: 41: Hoare triple {6392#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6392#false} is VALID [2022-02-21 04:21:49,274 INFO L290 TraceCheckUtils]: 42: Hoare triple {6392#false} assume 1 == ~M_E~0;~M_E~0 := 2; {6392#false} is VALID [2022-02-21 04:21:49,274 INFO L290 TraceCheckUtils]: 43: Hoare triple {6392#false} assume !(1 == ~T1_E~0); {6392#false} is VALID [2022-02-21 04:21:49,275 INFO L290 TraceCheckUtils]: 44: Hoare triple {6392#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {6392#false} is VALID [2022-02-21 04:21:49,275 INFO L290 TraceCheckUtils]: 45: Hoare triple {6392#false} assume !(1 == ~T3_E~0); {6392#false} is VALID [2022-02-21 04:21:49,275 INFO L290 TraceCheckUtils]: 46: Hoare triple {6392#false} assume !(1 == ~E_M~0); {6392#false} is VALID [2022-02-21 04:21:49,277 INFO L290 TraceCheckUtils]: 47: Hoare triple {6392#false} assume !(1 == ~E_1~0); {6392#false} is VALID [2022-02-21 04:21:49,277 INFO L290 TraceCheckUtils]: 48: Hoare triple {6392#false} assume !(1 == ~E_2~0); {6392#false} is VALID [2022-02-21 04:21:49,277 INFO L290 TraceCheckUtils]: 49: Hoare triple {6392#false} assume !(1 == ~E_3~0); {6392#false} is VALID [2022-02-21 04:21:49,277 INFO L290 TraceCheckUtils]: 50: Hoare triple {6392#false} assume { :end_inline_reset_delta_events } true; {6392#false} is VALID [2022-02-21 04:21:49,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:49,278 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:49,278 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971464008] [2022-02-21 04:21:49,278 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971464008] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:49,279 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:49,279 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:49,279 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775893332] [2022-02-21 04:21:49,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:49,280 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:49,281 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:49,281 INFO L85 PathProgramCache]: Analyzing trace with hash -1421169662, now seen corresponding path program 1 times [2022-02-21 04:21:49,281 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:49,281 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469309796] [2022-02-21 04:21:49,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:49,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:49,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:49,338 INFO L290 TraceCheckUtils]: 0: Hoare triple {6394#true} assume !false; {6394#true} is VALID [2022-02-21 04:21:49,338 INFO L290 TraceCheckUtils]: 1: Hoare triple {6394#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6394#true} is VALID [2022-02-21 04:21:49,338 INFO L290 TraceCheckUtils]: 2: Hoare triple {6394#true} assume !false; {6394#true} is VALID [2022-02-21 04:21:49,339 INFO L290 TraceCheckUtils]: 3: Hoare triple {6394#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {6394#true} is VALID [2022-02-21 04:21:49,341 INFO L290 TraceCheckUtils]: 4: Hoare triple {6394#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {6396#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} is VALID [2022-02-21 04:21:49,341 INFO L290 TraceCheckUtils]: 5: Hoare triple {6396#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {6397#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:49,341 INFO L290 TraceCheckUtils]: 6: Hoare triple {6397#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {6398#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 7: Hoare triple {6398#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 8: Hoare triple {6395#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 9: Hoare triple {6395#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 10: Hoare triple {6395#false} assume 0 == ~M_E~0;~M_E~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 11: Hoare triple {6395#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 12: Hoare triple {6395#false} assume !(0 == ~T2_E~0); {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 13: Hoare triple {6395#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,342 INFO L290 TraceCheckUtils]: 14: Hoare triple {6395#false} assume 0 == ~E_M~0;~E_M~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 15: Hoare triple {6395#false} assume 0 == ~E_1~0;~E_1~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 16: Hoare triple {6395#false} assume 0 == ~E_2~0;~E_2~0 := 1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 17: Hoare triple {6395#false} assume !(0 == ~E_3~0); {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 18: Hoare triple {6395#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 19: Hoare triple {6395#false} assume 1 == ~m_pc~0; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 20: Hoare triple {6395#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 21: Hoare triple {6395#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 22: Hoare triple {6395#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {6395#false} is VALID [2022-02-21 04:21:49,343 INFO L290 TraceCheckUtils]: 23: Hoare triple {6395#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 24: Hoare triple {6395#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 25: Hoare triple {6395#false} assume 1 == ~t1_pc~0; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 26: Hoare triple {6395#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 27: Hoare triple {6395#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 28: Hoare triple {6395#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 29: Hoare triple {6395#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 30: Hoare triple {6395#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 31: Hoare triple {6395#false} assume 1 == ~t2_pc~0; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 32: Hoare triple {6395#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,344 INFO L290 TraceCheckUtils]: 33: Hoare triple {6395#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 34: Hoare triple {6395#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 35: Hoare triple {6395#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 36: Hoare triple {6395#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 37: Hoare triple {6395#false} assume 1 == ~t3_pc~0; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 38: Hoare triple {6395#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 39: Hoare triple {6395#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 40: Hoare triple {6395#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 41: Hoare triple {6395#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 42: Hoare triple {6395#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6395#false} is VALID [2022-02-21 04:21:49,345 INFO L290 TraceCheckUtils]: 43: Hoare triple {6395#false} assume 1 == ~M_E~0;~M_E~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 44: Hoare triple {6395#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 45: Hoare triple {6395#false} assume !(1 == ~T2_E~0); {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 46: Hoare triple {6395#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 47: Hoare triple {6395#false} assume 1 == ~E_M~0;~E_M~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 48: Hoare triple {6395#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 49: Hoare triple {6395#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 50: Hoare triple {6395#false} assume 1 == ~E_3~0;~E_3~0 := 2; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 51: Hoare triple {6395#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 52: Hoare triple {6395#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,346 INFO L290 TraceCheckUtils]: 53: Hoare triple {6395#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 54: Hoare triple {6395#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 55: Hoare triple {6395#false} assume !(0 == start_simulation_~tmp~3#1); {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 56: Hoare triple {6395#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 57: Hoare triple {6395#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 58: Hoare triple {6395#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 59: Hoare triple {6395#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 60: Hoare triple {6395#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 61: Hoare triple {6395#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 62: Hoare triple {6395#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {6395#false} is VALID [2022-02-21 04:21:49,347 INFO L290 TraceCheckUtils]: 63: Hoare triple {6395#false} assume !(0 != start_simulation_~tmp___0~1#1); {6395#false} is VALID [2022-02-21 04:21:49,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:49,348 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:49,348 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469309796] [2022-02-21 04:21:49,348 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469309796] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:49,348 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:49,348 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:49,349 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125390444] [2022-02-21 04:21:49,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:49,349 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:49,349 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:49,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:49,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:49,350 INFO L87 Difference]: Start difference. First operand 551 states and 816 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,807 INFO L93 Difference]: Finished difference Result 1021 states and 1489 transitions. [2022-02-21 04:21:49,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:49,807 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,845 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:49,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1021 states and 1489 transitions. [2022-02-21 04:21:49,920 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 957 [2022-02-21 04:21:49,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1021 states to 1021 states and 1489 transitions. [2022-02-21 04:21:49,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1021 [2022-02-21 04:21:49,962 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1021 [2022-02-21 04:21:49,962 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1021 states and 1489 transitions. [2022-02-21 04:21:49,963 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:49,963 INFO L681 BuchiCegarLoop]: Abstraction has 1021 states and 1489 transitions. [2022-02-21 04:21:49,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1021 states and 1489 transitions. [2022-02-21 04:21:49,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1021 to 967. [2022-02-21 04:21:49,979 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:49,982 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1021 states and 1489 transitions. Second operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,984 INFO L74 IsIncluded]: Start isIncluded. First operand 1021 states and 1489 transitions. Second operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,986 INFO L87 Difference]: Start difference. First operand 1021 states and 1489 transitions. Second operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,027 INFO L93 Difference]: Finished difference Result 1021 states and 1489 transitions. [2022-02-21 04:21:50,027 INFO L276 IsEmpty]: Start isEmpty. Operand 1021 states and 1489 transitions. [2022-02-21 04:21:50,028 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,029 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,031 INFO L74 IsIncluded]: Start isIncluded. First operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1021 states and 1489 transitions. [2022-02-21 04:21:50,033 INFO L87 Difference]: Start difference. First operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1021 states and 1489 transitions. [2022-02-21 04:21:50,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,073 INFO L93 Difference]: Finished difference Result 1021 states and 1489 transitions. [2022-02-21 04:21:50,073 INFO L276 IsEmpty]: Start isEmpty. Operand 1021 states and 1489 transitions. [2022-02-21 04:21:50,075 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,075 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,075 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:50,075 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:50,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 967 states, 967 states have (on average 1.4632885211995863) internal successors, (1415), 966 states have internal predecessors, (1415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 967 states to 967 states and 1415 transitions. [2022-02-21 04:21:50,114 INFO L704 BuchiCegarLoop]: Abstraction has 967 states and 1415 transitions. [2022-02-21 04:21:50,114 INFO L587 BuchiCegarLoop]: Abstraction has 967 states and 1415 transitions. [2022-02-21 04:21:50,114 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:50,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 967 states and 1415 transitions. [2022-02-21 04:21:50,118 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 903 [2022-02-21 04:21:50,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:50,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:50,119 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,120 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,120 INFO L791 eck$LassoCheckResult]: Stem: 7779#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 7725#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7730#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7612#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 7613#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7712#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7692#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7693#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7701#L429 assume !(0 == ~M_E~0); 7521#L429-2 assume !(0 == ~T1_E~0); 7522#L434-1 assume !(0 == ~T2_E~0); 7647#L439-1 assume !(0 == ~T3_E~0); 7670#L444-1 assume !(0 == ~E_M~0); 7671#L449-1 assume !(0 == ~E_1~0); 7527#L454-1 assume !(0 == ~E_2~0); 7528#L459-1 assume !(0 == ~E_3~0); 7487#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7488#L208 assume !(1 == ~m_pc~0); 7772#L208-2 is_master_triggered_~__retres1~0#1 := 0; 7773#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7557#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7508#L531 assume !(0 != activate_threads_~tmp~1#1); 7509#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7619#L227 assume !(1 == ~t1_pc~0); 7506#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7507#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7702#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7525#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7526#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7558#L246 assume 1 == ~t2_pc~0; 7559#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7636#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7651#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7708#L547 assume !(0 != activate_threads_~tmp___1~0#1); 7716#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7568#L265 assume !(1 == ~t3_pc~0); 7449#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7422#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7423#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7653#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7537#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7538#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 7706#L477-2 assume !(1 == ~T1_E~0); 8295#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7727#L487-1 assume !(1 == ~T3_E~0); 8292#L492-1 assume !(1 == ~E_M~0); 8290#L497-1 assume !(1 == ~E_1~0); 8288#L502-1 assume !(1 == ~E_2~0); 8286#L507-1 assume !(1 == ~E_3~0); 8232#L512-1 assume { :end_inline_reset_delta_events } true; 8230#L678-2 [2022-02-21 04:21:50,120 INFO L793 eck$LassoCheckResult]: Loop: 8230#L678-2 assume !false; 8228#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8226#L404 assume !false; 8225#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 8223#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7491#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7492#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7544#L357 assume !(0 != eval_~tmp~0#1); 7546#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8314#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8313#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8312#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8311#L434-3 assume !(0 == ~T2_E~0); 8310#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8309#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8308#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8307#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8306#L459-3 assume !(0 == ~E_3~0); 8305#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8304#L208-15 assume !(1 == ~m_pc~0); 8303#L208-17 is_master_triggered_~__retres1~0#1 := 0; 8302#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8301#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 8300#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8299#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8298#L227-15 assume 1 == ~t1_pc~0; 8296#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8294#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8293#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8291#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8289#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8287#L246-15 assume 1 == ~t2_pc~0; 8284#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8283#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8282#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8281#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8280#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8279#L265-15 assume !(1 == ~t3_pc~0); 8277#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 8276#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8275#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8274#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8273#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8272#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7746#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8271#L482-3 assume !(1 == ~T2_E~0); 7749#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8270#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8269#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7642#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7643#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7609#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7610#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 8258#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 8256#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 8255#L697 assume !(0 == start_simulation_~tmp~3#1); 7420#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7421#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7564#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7565#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 8238#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7703#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7704#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 8233#L710 assume !(0 != start_simulation_~tmp___0~1#1); 8230#L678-2 [2022-02-21 04:21:50,121 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,121 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2022-02-21 04:21:50,121 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,121 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693260302] [2022-02-21 04:21:50,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,166 INFO L290 TraceCheckUtils]: 0: Hoare triple {10432#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,167 INFO L290 TraceCheckUtils]: 1: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,167 INFO L290 TraceCheckUtils]: 2: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,167 INFO L290 TraceCheckUtils]: 3: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,168 INFO L290 TraceCheckUtils]: 4: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,168 INFO L290 TraceCheckUtils]: 5: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,168 INFO L290 TraceCheckUtils]: 6: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,169 INFO L290 TraceCheckUtils]: 7: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,169 INFO L290 TraceCheckUtils]: 8: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,170 INFO L290 TraceCheckUtils]: 9: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,170 INFO L290 TraceCheckUtils]: 10: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,170 INFO L290 TraceCheckUtils]: 11: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,171 INFO L290 TraceCheckUtils]: 12: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,171 INFO L290 TraceCheckUtils]: 13: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_M~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,171 INFO L290 TraceCheckUtils]: 14: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,172 INFO L290 TraceCheckUtils]: 15: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,172 INFO L290 TraceCheckUtils]: 16: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,172 INFO L290 TraceCheckUtils]: 17: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10434#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:50,173 INFO L290 TraceCheckUtils]: 18: Hoare triple {10434#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,173 INFO L290 TraceCheckUtils]: 19: Hoare triple {10435#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,173 INFO L290 TraceCheckUtils]: 20: Hoare triple {10435#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,174 INFO L290 TraceCheckUtils]: 21: Hoare triple {10435#(not (= ~t2_pc~0 1))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,174 INFO L290 TraceCheckUtils]: 22: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,174 INFO L290 TraceCheckUtils]: 23: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,175 INFO L290 TraceCheckUtils]: 24: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,175 INFO L290 TraceCheckUtils]: 25: Hoare triple {10435#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,175 INFO L290 TraceCheckUtils]: 26: Hoare triple {10435#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,176 INFO L290 TraceCheckUtils]: 27: Hoare triple {10435#(not (= ~t2_pc~0 1))} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,176 INFO L290 TraceCheckUtils]: 28: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,176 INFO L290 TraceCheckUtils]: 29: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10435#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 30: Hoare triple {10435#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {10433#false} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 31: Hoare triple {10433#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10433#false} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 32: Hoare triple {10433#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10433#false} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 33: Hoare triple {10433#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10433#false} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 34: Hoare triple {10433#false} assume !(0 != activate_threads_~tmp___1~0#1); {10433#false} is VALID [2022-02-21 04:21:50,177 INFO L290 TraceCheckUtils]: 35: Hoare triple {10433#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 36: Hoare triple {10433#false} assume !(1 == ~t3_pc~0); {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 37: Hoare triple {10433#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 38: Hoare triple {10433#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 39: Hoare triple {10433#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 40: Hoare triple {10433#false} assume !(0 != activate_threads_~tmp___2~0#1); {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 41: Hoare triple {10433#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10433#false} is VALID [2022-02-21 04:21:50,178 INFO L290 TraceCheckUtils]: 42: Hoare triple {10433#false} assume 1 == ~M_E~0;~M_E~0 := 2; {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 43: Hoare triple {10433#false} assume !(1 == ~T1_E~0); {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 44: Hoare triple {10433#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 45: Hoare triple {10433#false} assume !(1 == ~T3_E~0); {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 46: Hoare triple {10433#false} assume !(1 == ~E_M~0); {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 47: Hoare triple {10433#false} assume !(1 == ~E_1~0); {10433#false} is VALID [2022-02-21 04:21:50,179 INFO L290 TraceCheckUtils]: 48: Hoare triple {10433#false} assume !(1 == ~E_2~0); {10433#false} is VALID [2022-02-21 04:21:50,180 INFO L290 TraceCheckUtils]: 49: Hoare triple {10433#false} assume !(1 == ~E_3~0); {10433#false} is VALID [2022-02-21 04:21:50,180 INFO L290 TraceCheckUtils]: 50: Hoare triple {10433#false} assume { :end_inline_reset_delta_events } true; {10433#false} is VALID [2022-02-21 04:21:50,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,181 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,181 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1693260302] [2022-02-21 04:21:50,181 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1693260302] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,181 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,182 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:50,182 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [161474610] [2022-02-21 04:21:50,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,183 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:50,183 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,183 INFO L85 PathProgramCache]: Analyzing trace with hash 327802308, now seen corresponding path program 1 times [2022-02-21 04:21:50,183 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,187 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56406556] [2022-02-21 04:21:50,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,230 INFO L290 TraceCheckUtils]: 0: Hoare triple {10436#true} assume !false; {10436#true} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 1: Hoare triple {10436#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10436#true} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 2: Hoare triple {10436#true} assume !false; {10436#true} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 3: Hoare triple {10436#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {10436#true} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 4: Hoare triple {10436#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {10438#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} is VALID [2022-02-21 04:21:50,232 INFO L290 TraceCheckUtils]: 5: Hoare triple {10438#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {10439#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:50,232 INFO L290 TraceCheckUtils]: 6: Hoare triple {10439#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {10440#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 7: Hoare triple {10440#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 8: Hoare triple {10437#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 9: Hoare triple {10437#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 10: Hoare triple {10437#false} assume 0 == ~M_E~0;~M_E~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {10437#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 12: Hoare triple {10437#false} assume !(0 == ~T2_E~0); {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 13: Hoare triple {10437#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 14: Hoare triple {10437#false} assume 0 == ~E_M~0;~E_M~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 15: Hoare triple {10437#false} assume 0 == ~E_1~0;~E_1~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 16: Hoare triple {10437#false} assume 0 == ~E_2~0;~E_2~0 := 1; {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 17: Hoare triple {10437#false} assume !(0 == ~E_3~0); {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 18: Hoare triple {10437#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 19: Hoare triple {10437#false} assume !(1 == ~m_pc~0); {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 20: Hoare triple {10437#false} is_master_triggered_~__retres1~0#1 := 0; {10437#false} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 21: Hoare triple {10437#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10437#false} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 22: Hoare triple {10437#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {10437#false} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 23: Hoare triple {10437#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10437#false} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 24: Hoare triple {10437#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10437#false} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 25: Hoare triple {10437#false} assume 1 == ~t1_pc~0; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 26: Hoare triple {10437#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 27: Hoare triple {10437#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 28: Hoare triple {10437#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 29: Hoare triple {10437#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 30: Hoare triple {10437#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10437#false} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 31: Hoare triple {10437#false} assume 1 == ~t2_pc~0; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 32: Hoare triple {10437#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 33: Hoare triple {10437#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 34: Hoare triple {10437#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 35: Hoare triple {10437#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 36: Hoare triple {10437#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 37: Hoare triple {10437#false} assume !(1 == ~t3_pc~0); {10437#false} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 38: Hoare triple {10437#false} is_transmit3_triggered_~__retres1~3#1 := 0; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 39: Hoare triple {10437#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 40: Hoare triple {10437#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 41: Hoare triple {10437#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 42: Hoare triple {10437#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 43: Hoare triple {10437#false} assume 1 == ~M_E~0;~M_E~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 44: Hoare triple {10437#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 45: Hoare triple {10437#false} assume !(1 == ~T2_E~0); {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 46: Hoare triple {10437#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 47: Hoare triple {10437#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 48: Hoare triple {10437#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 49: Hoare triple {10437#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 50: Hoare triple {10437#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 51: Hoare triple {10437#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {10437#false} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 52: Hoare triple {10437#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 53: Hoare triple {10437#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 54: Hoare triple {10437#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 55: Hoare triple {10437#false} assume !(0 == start_simulation_~tmp~3#1); {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 56: Hoare triple {10437#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 57: Hoare triple {10437#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {10437#false} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 58: Hoare triple {10437#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {10437#false} is VALID [2022-02-21 04:21:50,243 INFO L290 TraceCheckUtils]: 59: Hoare triple {10437#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {10437#false} is VALID [2022-02-21 04:21:50,243 INFO L290 TraceCheckUtils]: 60: Hoare triple {10437#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10437#false} is VALID [2022-02-21 04:21:50,243 INFO L290 TraceCheckUtils]: 61: Hoare triple {10437#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10437#false} is VALID [2022-02-21 04:21:50,244 INFO L290 TraceCheckUtils]: 62: Hoare triple {10437#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {10437#false} is VALID [2022-02-21 04:21:50,244 INFO L290 TraceCheckUtils]: 63: Hoare triple {10437#false} assume !(0 != start_simulation_~tmp___0~1#1); {10437#false} is VALID [2022-02-21 04:21:50,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,244 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,244 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56406556] [2022-02-21 04:21:50,245 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56406556] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,245 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,245 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:50,245 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615011815] [2022-02-21 04:21:50,245 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,246 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:50,246 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:50,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:50,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:50,247 INFO L87 Difference]: Start difference. First operand 967 states and 1415 transitions. cyclomatic complexity: 452 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,314 INFO L93 Difference]: Finished difference Result 2187 states and 3150 transitions. [2022-02-21 04:21:51,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:51,314 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,356 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:51,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2187 states and 3150 transitions. [2022-02-21 04:21:51,537 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2054 [2022-02-21 04:21:51,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2187 states to 2187 states and 3150 transitions. [2022-02-21 04:21:51,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2187 [2022-02-21 04:21:51,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2187 [2022-02-21 04:21:51,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2187 states and 3150 transitions. [2022-02-21 04:21:51,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:51,719 INFO L681 BuchiCegarLoop]: Abstraction has 2187 states and 3150 transitions. [2022-02-21 04:21:51,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2187 states and 3150 transitions. [2022-02-21 04:21:51,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2187 to 1725. [2022-02-21 04:21:51,749 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:51,753 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2187 states and 3150 transitions. Second operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,756 INFO L74 IsIncluded]: Start isIncluded. First operand 2187 states and 3150 transitions. Second operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,759 INFO L87 Difference]: Start difference. First operand 2187 states and 3150 transitions. Second operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,915 INFO L93 Difference]: Finished difference Result 2187 states and 3150 transitions. [2022-02-21 04:21:51,915 INFO L276 IsEmpty]: Start isEmpty. Operand 2187 states and 3150 transitions. [2022-02-21 04:21:51,919 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:51,919 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:51,923 INFO L74 IsIncluded]: Start isIncluded. First operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2187 states and 3150 transitions. [2022-02-21 04:21:51,927 INFO L87 Difference]: Start difference. First operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2187 states and 3150 transitions. [2022-02-21 04:21:52,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,115 INFO L93 Difference]: Finished difference Result 2187 states and 3150 transitions. [2022-02-21 04:21:52,116 INFO L276 IsEmpty]: Start isEmpty. Operand 2187 states and 3150 transitions. [2022-02-21 04:21:52,119 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,119 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:52,120 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:52,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1725 states, 1725 states have (on average 1.4533333333333334) internal successors, (2507), 1724 states have internal predecessors, (2507), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1725 states to 1725 states and 2507 transitions. [2022-02-21 04:21:52,233 INFO L704 BuchiCegarLoop]: Abstraction has 1725 states and 2507 transitions. [2022-02-21 04:21:52,233 INFO L587 BuchiCegarLoop]: Abstraction has 1725 states and 2507 transitions. [2022-02-21 04:21:52,233 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:52,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1725 states and 2507 transitions. [2022-02-21 04:21:52,240 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1660 [2022-02-21 04:21:52,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:52,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:52,242 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,242 INFO L791 eck$LassoCheckResult]: Stem: 13001#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12937#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12943#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12822#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 12823#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12927#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12907#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12908#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12916#L429 assume !(0 == ~M_E~0); 12731#L429-2 assume !(0 == ~T1_E~0); 12732#L434-1 assume !(0 == ~T2_E~0); 12859#L439-1 assume !(0 == ~T3_E~0); 12884#L444-1 assume !(0 == ~E_M~0); 12885#L449-1 assume !(0 == ~E_1~0); 12737#L454-1 assume !(0 == ~E_2~0); 12738#L459-1 assume !(0 == ~E_3~0); 12698#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12699#L208 assume !(1 == ~m_pc~0); 12990#L208-2 is_master_triggered_~__retres1~0#1 := 0; 12991#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12769#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12718#L531 assume !(0 != activate_threads_~tmp~1#1); 12719#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12828#L227 assume !(1 == ~t1_pc~0); 12716#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12717#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12917#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12735#L539 assume !(0 != activate_threads_~tmp___0~0#1); 12736#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12770#L246 assume !(1 == ~t2_pc~0); 12771#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12864#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12865#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12925#L547 assume !(0 != activate_threads_~tmp___1~0#1); 12932#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12779#L265 assume !(1 == ~t3_pc~0); 12661#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12632#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12633#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12867#L555 assume !(0 != activate_threads_~tmp___2~0#1); 12747#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12748#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 12923#L477-2 assume !(1 == ~T1_E~0); 12938#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12939#L487-1 assume !(1 == ~T3_E~0); 12961#L492-1 assume !(1 == ~E_M~0); 12962#L497-1 assume !(1 == ~E_1~0); 12852#L502-1 assume !(1 == ~E_2~0); 12853#L507-1 assume !(1 == ~E_3~0); 12826#L512-1 assume { :end_inline_reset_delta_events } true; 12776#L678-2 [2022-02-21 04:21:52,242 INFO L793 eck$LassoCheckResult]: Loop: 12776#L678-2 assume !false; 12911#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12665#L404 assume !false; 12827#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12808#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12671#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12702#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12754#L357 assume !(0 != eval_~tmp~0#1); 12756#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14294#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14292#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14290#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14288#L434-3 assume !(0 == ~T2_E~0); 14286#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14284#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 14283#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14281#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14279#L459-3 assume !(0 == ~E_3~0); 14277#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14275#L208-15 assume !(1 == ~m_pc~0); 14273#L208-17 is_master_triggered_~__retres1~0#1 := 0; 14270#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14268#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14266#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14265#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14264#L227-15 assume 1 == ~t1_pc~0; 14262#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14261#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14259#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14255#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14252#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14250#L246-15 assume !(1 == ~t2_pc~0); 13719#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 14246#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14243#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14239#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14236#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14234#L265-15 assume 1 == ~t3_pc~0; 12803#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12805#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12786#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12782#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12783#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12934#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12963#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12966#L482-3 assume !(1 == ~T2_E~0); 12793#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12722#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12723#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12850#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12851#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12817#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12690#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12649#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12650#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 12730#L697 assume !(0 == start_simulation_~tmp~3#1); 12630#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12631#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12774#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12760#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 12761#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13002#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12978#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12775#L710 assume !(0 != start_simulation_~tmp___0~1#1); 12776#L678-2 [2022-02-21 04:21:52,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,243 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2022-02-21 04:21:52,243 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,243 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104711202] [2022-02-21 04:21:52,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,276 INFO L290 TraceCheckUtils]: 0: Hoare triple {18732#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,277 INFO L290 TraceCheckUtils]: 1: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,277 INFO L290 TraceCheckUtils]: 2: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,278 INFO L290 TraceCheckUtils]: 3: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,278 INFO L290 TraceCheckUtils]: 4: Hoare triple {18734#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,278 INFO L290 TraceCheckUtils]: 5: Hoare triple {18734#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,279 INFO L290 TraceCheckUtils]: 6: Hoare triple {18734#(= ~M_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,279 INFO L290 TraceCheckUtils]: 7: Hoare triple {18734#(= ~M_E~0 2)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,279 INFO L290 TraceCheckUtils]: 8: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,280 INFO L290 TraceCheckUtils]: 9: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~M_E~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,280 INFO L290 TraceCheckUtils]: 10: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~T1_E~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,280 INFO L290 TraceCheckUtils]: 11: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~T2_E~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,281 INFO L290 TraceCheckUtils]: 12: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~T3_E~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,296 INFO L290 TraceCheckUtils]: 13: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~E_M~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,297 INFO L290 TraceCheckUtils]: 14: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~E_1~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,297 INFO L290 TraceCheckUtils]: 15: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~E_2~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,298 INFO L290 TraceCheckUtils]: 16: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 == ~E_3~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,298 INFO L290 TraceCheckUtils]: 17: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,298 INFO L290 TraceCheckUtils]: 18: Hoare triple {18734#(= ~M_E~0 2)} assume !(1 == ~m_pc~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,299 INFO L290 TraceCheckUtils]: 19: Hoare triple {18734#(= ~M_E~0 2)} is_master_triggered_~__retres1~0#1 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,299 INFO L290 TraceCheckUtils]: 20: Hoare triple {18734#(= ~M_E~0 2)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,299 INFO L290 TraceCheckUtils]: 21: Hoare triple {18734#(= ~M_E~0 2)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,300 INFO L290 TraceCheckUtils]: 22: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp~1#1); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,300 INFO L290 TraceCheckUtils]: 23: Hoare triple {18734#(= ~M_E~0 2)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,300 INFO L290 TraceCheckUtils]: 24: Hoare triple {18734#(= ~M_E~0 2)} assume !(1 == ~t1_pc~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,301 INFO L290 TraceCheckUtils]: 25: Hoare triple {18734#(= ~M_E~0 2)} is_transmit1_triggered_~__retres1~1#1 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,301 INFO L290 TraceCheckUtils]: 26: Hoare triple {18734#(= ~M_E~0 2)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,302 INFO L290 TraceCheckUtils]: 27: Hoare triple {18734#(= ~M_E~0 2)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,315 INFO L290 TraceCheckUtils]: 28: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___0~0#1); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,316 INFO L290 TraceCheckUtils]: 29: Hoare triple {18734#(= ~M_E~0 2)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,316 INFO L290 TraceCheckUtils]: 30: Hoare triple {18734#(= ~M_E~0 2)} assume !(1 == ~t2_pc~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,317 INFO L290 TraceCheckUtils]: 31: Hoare triple {18734#(= ~M_E~0 2)} is_transmit2_triggered_~__retres1~2#1 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,317 INFO L290 TraceCheckUtils]: 32: Hoare triple {18734#(= ~M_E~0 2)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,318 INFO L290 TraceCheckUtils]: 33: Hoare triple {18734#(= ~M_E~0 2)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,318 INFO L290 TraceCheckUtils]: 34: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___1~0#1); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,318 INFO L290 TraceCheckUtils]: 35: Hoare triple {18734#(= ~M_E~0 2)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,319 INFO L290 TraceCheckUtils]: 36: Hoare triple {18734#(= ~M_E~0 2)} assume !(1 == ~t3_pc~0); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,319 INFO L290 TraceCheckUtils]: 37: Hoare triple {18734#(= ~M_E~0 2)} is_transmit3_triggered_~__retres1~3#1 := 0; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,319 INFO L290 TraceCheckUtils]: 38: Hoare triple {18734#(= ~M_E~0 2)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,320 INFO L290 TraceCheckUtils]: 39: Hoare triple {18734#(= ~M_E~0 2)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,320 INFO L290 TraceCheckUtils]: 40: Hoare triple {18734#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___2~0#1); {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,321 INFO L290 TraceCheckUtils]: 41: Hoare triple {18734#(= ~M_E~0 2)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18734#(= ~M_E~0 2)} is VALID [2022-02-21 04:21:52,321 INFO L290 TraceCheckUtils]: 42: Hoare triple {18734#(= ~M_E~0 2)} assume 1 == ~M_E~0;~M_E~0 := 2; {18733#false} is VALID [2022-02-21 04:21:52,321 INFO L290 TraceCheckUtils]: 43: Hoare triple {18733#false} assume !(1 == ~T1_E~0); {18733#false} is VALID [2022-02-21 04:21:52,321 INFO L290 TraceCheckUtils]: 44: Hoare triple {18733#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {18733#false} is VALID [2022-02-21 04:21:52,321 INFO L290 TraceCheckUtils]: 45: Hoare triple {18733#false} assume !(1 == ~T3_E~0); {18733#false} is VALID [2022-02-21 04:21:52,322 INFO L290 TraceCheckUtils]: 46: Hoare triple {18733#false} assume !(1 == ~E_M~0); {18733#false} is VALID [2022-02-21 04:21:52,322 INFO L290 TraceCheckUtils]: 47: Hoare triple {18733#false} assume !(1 == ~E_1~0); {18733#false} is VALID [2022-02-21 04:21:52,322 INFO L290 TraceCheckUtils]: 48: Hoare triple {18733#false} assume !(1 == ~E_2~0); {18733#false} is VALID [2022-02-21 04:21:52,322 INFO L290 TraceCheckUtils]: 49: Hoare triple {18733#false} assume !(1 == ~E_3~0); {18733#false} is VALID [2022-02-21 04:21:52,322 INFO L290 TraceCheckUtils]: 50: Hoare triple {18733#false} assume { :end_inline_reset_delta_events } true; {18733#false} is VALID [2022-02-21 04:21:52,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,323 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,323 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [104711202] [2022-02-21 04:21:52,323 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [104711202] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,323 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,324 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:52,324 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666874336] [2022-02-21 04:21:52,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,324 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:52,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,325 INFO L85 PathProgramCache]: Analyzing trace with hash 423762180, now seen corresponding path program 1 times [2022-02-21 04:21:52,325 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,325 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1290807749] [2022-02-21 04:21:52,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,365 INFO L290 TraceCheckUtils]: 0: Hoare triple {18735#true} assume !false; {18735#true} is VALID [2022-02-21 04:21:52,366 INFO L290 TraceCheckUtils]: 1: Hoare triple {18735#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {18735#true} is VALID [2022-02-21 04:21:52,366 INFO L290 TraceCheckUtils]: 2: Hoare triple {18735#true} assume !false; {18735#true} is VALID [2022-02-21 04:21:52,366 INFO L290 TraceCheckUtils]: 3: Hoare triple {18735#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {18735#true} is VALID [2022-02-21 04:21:52,366 INFO L290 TraceCheckUtils]: 4: Hoare triple {18735#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {18737#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} is VALID [2022-02-21 04:21:52,367 INFO L290 TraceCheckUtils]: 5: Hoare triple {18737#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {18738#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:52,367 INFO L290 TraceCheckUtils]: 6: Hoare triple {18738#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {18739#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 7: Hoare triple {18739#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {18736#false} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 8: Hoare triple {18736#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {18736#false} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 9: Hoare triple {18736#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {18736#false} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 10: Hoare triple {18736#false} assume 0 == ~M_E~0;~M_E~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 11: Hoare triple {18736#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,368 INFO L290 TraceCheckUtils]: 12: Hoare triple {18736#false} assume !(0 == ~T2_E~0); {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 13: Hoare triple {18736#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 14: Hoare triple {18736#false} assume 0 == ~E_M~0;~E_M~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 15: Hoare triple {18736#false} assume 0 == ~E_1~0;~E_1~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 16: Hoare triple {18736#false} assume 0 == ~E_2~0;~E_2~0 := 1; {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 17: Hoare triple {18736#false} assume !(0 == ~E_3~0); {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 18: Hoare triple {18736#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {18736#false} is VALID [2022-02-21 04:21:52,369 INFO L290 TraceCheckUtils]: 19: Hoare triple {18736#false} assume !(1 == ~m_pc~0); {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 20: Hoare triple {18736#false} is_master_triggered_~__retres1~0#1 := 0; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 21: Hoare triple {18736#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 22: Hoare triple {18736#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 23: Hoare triple {18736#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 24: Hoare triple {18736#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 25: Hoare triple {18736#false} assume 1 == ~t1_pc~0; {18736#false} is VALID [2022-02-21 04:21:52,370 INFO L290 TraceCheckUtils]: 26: Hoare triple {18736#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 27: Hoare triple {18736#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 28: Hoare triple {18736#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 29: Hoare triple {18736#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 30: Hoare triple {18736#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 31: Hoare triple {18736#false} assume !(1 == ~t2_pc~0); {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 32: Hoare triple {18736#false} is_transmit2_triggered_~__retres1~2#1 := 0; {18736#false} is VALID [2022-02-21 04:21:52,371 INFO L290 TraceCheckUtils]: 33: Hoare triple {18736#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 34: Hoare triple {18736#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 35: Hoare triple {18736#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 36: Hoare triple {18736#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 37: Hoare triple {18736#false} assume 1 == ~t3_pc~0; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 38: Hoare triple {18736#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 39: Hoare triple {18736#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {18736#false} is VALID [2022-02-21 04:21:52,372 INFO L290 TraceCheckUtils]: 40: Hoare triple {18736#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 41: Hoare triple {18736#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 42: Hoare triple {18736#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 43: Hoare triple {18736#false} assume 1 == ~M_E~0;~M_E~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 44: Hoare triple {18736#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 45: Hoare triple {18736#false} assume !(1 == ~T2_E~0); {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 46: Hoare triple {18736#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,373 INFO L290 TraceCheckUtils]: 47: Hoare triple {18736#false} assume 1 == ~E_M~0;~E_M~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 48: Hoare triple {18736#false} assume 1 == ~E_1~0;~E_1~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 49: Hoare triple {18736#false} assume 1 == ~E_2~0;~E_2~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 50: Hoare triple {18736#false} assume 1 == ~E_3~0;~E_3~0 := 2; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 51: Hoare triple {18736#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 52: Hoare triple {18736#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 53: Hoare triple {18736#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {18736#false} is VALID [2022-02-21 04:21:52,374 INFO L290 TraceCheckUtils]: 54: Hoare triple {18736#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 55: Hoare triple {18736#false} assume !(0 == start_simulation_~tmp~3#1); {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 56: Hoare triple {18736#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 57: Hoare triple {18736#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 58: Hoare triple {18736#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 59: Hoare triple {18736#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 60: Hoare triple {18736#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {18736#false} is VALID [2022-02-21 04:21:52,375 INFO L290 TraceCheckUtils]: 61: Hoare triple {18736#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {18736#false} is VALID [2022-02-21 04:21:52,376 INFO L290 TraceCheckUtils]: 62: Hoare triple {18736#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {18736#false} is VALID [2022-02-21 04:21:52,376 INFO L290 TraceCheckUtils]: 63: Hoare triple {18736#false} assume !(0 != start_simulation_~tmp___0~1#1); {18736#false} is VALID [2022-02-21 04:21:52,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,376 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,376 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1290807749] [2022-02-21 04:21:52,377 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1290807749] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,377 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,377 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:52,377 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091312066] [2022-02-21 04:21:52,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,377 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:52,378 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:52,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:52,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:52,379 INFO L87 Difference]: Start difference. First operand 1725 states and 2507 transitions. cyclomatic complexity: 786 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,958 INFO L93 Difference]: Finished difference Result 2513 states and 3650 transitions. [2022-02-21 04:21:52,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:52,958 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,992 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:52,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,169 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2448 [2022-02-21 04:21:53,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2513 states to 2513 states and 3650 transitions. [2022-02-21 04:21:53,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2513 [2022-02-21 04:21:53,320 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2513 [2022-02-21 04:21:53,320 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:53,323 INFO L681 BuchiCegarLoop]: Abstraction has 2513 states and 3650 transitions. [2022-02-21 04:21:53,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2513 to 1749. [2022-02-21 04:21:53,348 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:53,350 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2513 states and 3650 transitions. Second operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,352 INFO L74 IsIncluded]: Start isIncluded. First operand 2513 states and 3650 transitions. Second operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,354 INFO L87 Difference]: Start difference. First operand 2513 states and 3650 transitions. Second operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,507 INFO L93 Difference]: Finished difference Result 2513 states and 3650 transitions. [2022-02-21 04:21:53,507 INFO L276 IsEmpty]: Start isEmpty. Operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,511 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,511 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,514 INFO L74 IsIncluded]: Start isIncluded. First operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,516 INFO L87 Difference]: Start difference. First operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,660 INFO L93 Difference]: Finished difference Result 2513 states and 3650 transitions. [2022-02-21 04:21:53,660 INFO L276 IsEmpty]: Start isEmpty. Operand 2513 states and 3650 transitions. [2022-02-21 04:21:53,664 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,664 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,665 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:53,665 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:53,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1749 states, 1749 states have (on average 1.4562607204116638) internal successors, (2547), 1748 states have internal predecessors, (2547), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 1749 states and 2547 transitions. [2022-02-21 04:21:53,743 INFO L704 BuchiCegarLoop]: Abstraction has 1749 states and 2547 transitions. [2022-02-21 04:21:53,743 INFO L587 BuchiCegarLoop]: Abstraction has 1749 states and 2547 transitions. [2022-02-21 04:21:53,743 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:53,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1749 states and 2547 transitions. [2022-02-21 04:21:53,749 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1692 [2022-02-21 04:21:53,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:53,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:53,751 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,751 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,751 INFO L791 eck$LassoCheckResult]: Stem: 21611#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 21561#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21562#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21566#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21451#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 21452#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21550#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21531#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21532#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21541#L429 assume !(0 == ~M_E~0); 21353#L429-2 assume !(0 == ~T1_E~0); 21354#L434-1 assume !(0 == ~T2_E~0); 21483#L439-1 assume !(0 == ~T3_E~0); 21508#L444-1 assume !(0 == ~E_M~0); 21509#L449-1 assume !(0 == ~E_1~0); 21361#L454-1 assume !(0 == ~E_2~0); 21362#L459-1 assume !(0 == ~E_3~0); 21319#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21320#L208 assume !(1 == ~m_pc~0); 21601#L208-2 is_master_triggered_~__retres1~0#1 := 0; 21602#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21391#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 21340#L531 assume !(0 != activate_threads_~tmp~1#1); 21341#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21456#L227 assume !(1 == ~t1_pc~0); 21338#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21339#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21542#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21357#L539 assume !(0 != activate_threads_~tmp___0~0#1); 21358#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21392#L246 assume !(1 == ~t2_pc~0); 21393#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21487#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21488#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21548#L547 assume !(0 != activate_threads_~tmp___1~0#1); 21555#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21401#L265 assume !(1 == ~t3_pc~0); 21282#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21255#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21256#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21491#L555 assume !(0 != activate_threads_~tmp___2~0#1); 21375#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21376#L477 assume !(1 == ~M_E~0); 21546#L477-2 assume !(1 == ~T1_E~0); 21563#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21506#L487-1 assume !(1 == ~T3_E~0); 21507#L492-1 assume !(1 == ~E_M~0); 21325#L497-1 assume !(1 == ~E_1~0); 21326#L502-1 assume !(1 == ~E_2~0); 21309#L507-1 assume !(1 == ~E_3~0); 21310#L512-1 assume { :end_inline_reset_delta_events } true; 21453#L678-2 [2022-02-21 04:21:53,752 INFO L793 eck$LassoCheckResult]: Loop: 21453#L678-2 assume !false; 22276#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22271#L404 assume !false; 22269#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22265#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22261#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22260#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22257#L357 assume !(0 != eval_~tmp~0#1); 22258#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22435#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22434#L429-3 assume !(0 == ~M_E~0); 22433#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22432#L434-3 assume !(0 == ~T2_E~0); 22431#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22430#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22429#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22428#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22427#L459-3 assume !(0 == ~E_3~0); 22426#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22425#L208-15 assume !(1 == ~m_pc~0); 22424#L208-17 is_master_triggered_~__retres1~0#1 := 0; 22423#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22422#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22421#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22420#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22419#L227-15 assume 1 == ~t1_pc~0; 22417#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22416#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22415#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22414#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22413#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22412#L246-15 assume !(1 == ~t2_pc~0); 22175#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 22411#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22410#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22409#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22408#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22407#L265-15 assume !(1 == ~t3_pc~0); 22405#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 22404#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22403#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22402#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22401#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22400#L477-3 assume !(1 == ~M_E~0); 22054#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22399#L482-3 assume !(1 == ~T2_E~0); 22398#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22397#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22396#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22395#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22394#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22393#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22390#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22388#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22387#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 21552#L697 assume !(0 == start_simulation_~tmp~3#1); 21553#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22359#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22354#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22350#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 22345#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22340#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22336#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 22332#L710 assume !(0 != start_simulation_~tmp___0~1#1); 21453#L678-2 [2022-02-21 04:21:53,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,752 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2022-02-21 04:21:53,752 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,752 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002002397] [2022-02-21 04:21:53,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,777 INFO L290 TraceCheckUtils]: 0: Hoare triple {28031#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 1: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 2: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 3: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 4: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 5: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 6: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 7: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 8: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 9: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 10: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~T1_E~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 11: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~T2_E~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 12: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~T3_E~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 13: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~E_M~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 14: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~E_1~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 15: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~E_2~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 16: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 == ~E_3~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,788 INFO L290 TraceCheckUtils]: 17: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,792 INFO L290 TraceCheckUtils]: 18: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(1 == ~m_pc~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,792 INFO L290 TraceCheckUtils]: 19: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_master_triggered_~__retres1~0#1 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,793 INFO L290 TraceCheckUtils]: 20: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,793 INFO L290 TraceCheckUtils]: 21: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,793 INFO L290 TraceCheckUtils]: 22: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 != activate_threads_~tmp~1#1); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,794 INFO L290 TraceCheckUtils]: 23: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,794 INFO L290 TraceCheckUtils]: 24: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(1 == ~t1_pc~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,794 INFO L290 TraceCheckUtils]: 25: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,795 INFO L290 TraceCheckUtils]: 26: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,795 INFO L290 TraceCheckUtils]: 27: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,795 INFO L290 TraceCheckUtils]: 28: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___0~0#1); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,796 INFO L290 TraceCheckUtils]: 29: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,796 INFO L290 TraceCheckUtils]: 30: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(1 == ~t2_pc~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,797 INFO L290 TraceCheckUtils]: 31: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,797 INFO L290 TraceCheckUtils]: 32: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,797 INFO L290 TraceCheckUtils]: 33: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,798 INFO L290 TraceCheckUtils]: 34: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___1~0#1); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,798 INFO L290 TraceCheckUtils]: 35: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,798 INFO L290 TraceCheckUtils]: 36: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(1 == ~t3_pc~0); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,799 INFO L290 TraceCheckUtils]: 37: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,799 INFO L290 TraceCheckUtils]: 38: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,799 INFO L290 TraceCheckUtils]: 39: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,800 INFO L290 TraceCheckUtils]: 40: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___2~0#1); {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,800 INFO L290 TraceCheckUtils]: 41: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28033#(= ~T2_E~0 ~M_E~0)} is VALID [2022-02-21 04:21:53,800 INFO L290 TraceCheckUtils]: 42: Hoare triple {28033#(= ~T2_E~0 ~M_E~0)} assume !(1 == ~M_E~0); {28034#(not (= ~T2_E~0 1))} is VALID [2022-02-21 04:21:53,801 INFO L290 TraceCheckUtils]: 43: Hoare triple {28034#(not (= ~T2_E~0 1))} assume !(1 == ~T1_E~0); {28034#(not (= ~T2_E~0 1))} is VALID [2022-02-21 04:21:53,801 INFO L290 TraceCheckUtils]: 44: Hoare triple {28034#(not (= ~T2_E~0 1))} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28032#false} is VALID [2022-02-21 04:21:53,801 INFO L290 TraceCheckUtils]: 45: Hoare triple {28032#false} assume !(1 == ~T3_E~0); {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L290 TraceCheckUtils]: 46: Hoare triple {28032#false} assume !(1 == ~E_M~0); {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L290 TraceCheckUtils]: 47: Hoare triple {28032#false} assume !(1 == ~E_1~0); {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L290 TraceCheckUtils]: 48: Hoare triple {28032#false} assume !(1 == ~E_2~0); {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L290 TraceCheckUtils]: 49: Hoare triple {28032#false} assume !(1 == ~E_3~0); {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L290 TraceCheckUtils]: 50: Hoare triple {28032#false} assume { :end_inline_reset_delta_events } true; {28032#false} is VALID [2022-02-21 04:21:53,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,803 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,803 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002002397] [2022-02-21 04:21:53,803 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002002397] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,804 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,804 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:53,805 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861926523] [2022-02-21 04:21:53,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,805 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:53,806 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,806 INFO L85 PathProgramCache]: Analyzing trace with hash 49965381, now seen corresponding path program 1 times [2022-02-21 04:21:53,806 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,809 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447883436] [2022-02-21 04:21:53,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 0: Hoare triple {28035#true} assume !false; {28035#true} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 1: Hoare triple {28035#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28035#true} is VALID [2022-02-21 04:21:53,842 INFO L290 TraceCheckUtils]: 2: Hoare triple {28035#true} assume !false; {28035#true} is VALID [2022-02-21 04:21:53,842 INFO L290 TraceCheckUtils]: 3: Hoare triple {28035#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {28035#true} is VALID [2022-02-21 04:21:53,842 INFO L290 TraceCheckUtils]: 4: Hoare triple {28035#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {28037#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} is VALID [2022-02-21 04:21:53,843 INFO L290 TraceCheckUtils]: 5: Hoare triple {28037#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {28038#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:53,843 INFO L290 TraceCheckUtils]: 6: Hoare triple {28038#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {28039#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 7: Hoare triple {28039#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 8: Hoare triple {28036#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 9: Hoare triple {28036#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 10: Hoare triple {28036#false} assume !(0 == ~M_E~0); {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 11: Hoare triple {28036#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 12: Hoare triple {28036#false} assume !(0 == ~T2_E~0); {28036#false} is VALID [2022-02-21 04:21:53,844 INFO L290 TraceCheckUtils]: 13: Hoare triple {28036#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 14: Hoare triple {28036#false} assume 0 == ~E_M~0;~E_M~0 := 1; {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 15: Hoare triple {28036#false} assume 0 == ~E_1~0;~E_1~0 := 1; {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 16: Hoare triple {28036#false} assume 0 == ~E_2~0;~E_2~0 := 1; {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 17: Hoare triple {28036#false} assume !(0 == ~E_3~0); {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 18: Hoare triple {28036#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {28036#false} assume !(1 == ~m_pc~0); {28036#false} is VALID [2022-02-21 04:21:53,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {28036#false} is_master_triggered_~__retres1~0#1 := 0; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 21: Hoare triple {28036#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 22: Hoare triple {28036#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 23: Hoare triple {28036#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 24: Hoare triple {28036#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 25: Hoare triple {28036#false} assume 1 == ~t1_pc~0; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 26: Hoare triple {28036#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {28036#false} is VALID [2022-02-21 04:21:53,846 INFO L290 TraceCheckUtils]: 27: Hoare triple {28036#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 28: Hoare triple {28036#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 29: Hoare triple {28036#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 30: Hoare triple {28036#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 31: Hoare triple {28036#false} assume !(1 == ~t2_pc~0); {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 32: Hoare triple {28036#false} is_transmit2_triggered_~__retres1~2#1 := 0; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 33: Hoare triple {28036#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28036#false} is VALID [2022-02-21 04:21:53,847 INFO L290 TraceCheckUtils]: 34: Hoare triple {28036#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 35: Hoare triple {28036#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 36: Hoare triple {28036#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 37: Hoare triple {28036#false} assume !(1 == ~t3_pc~0); {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 38: Hoare triple {28036#false} is_transmit3_triggered_~__retres1~3#1 := 0; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 39: Hoare triple {28036#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 40: Hoare triple {28036#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28036#false} is VALID [2022-02-21 04:21:53,848 INFO L290 TraceCheckUtils]: 41: Hoare triple {28036#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 42: Hoare triple {28036#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 43: Hoare triple {28036#false} assume !(1 == ~M_E~0); {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 44: Hoare triple {28036#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 45: Hoare triple {28036#false} assume !(1 == ~T2_E~0); {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 46: Hoare triple {28036#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 47: Hoare triple {28036#false} assume 1 == ~E_M~0;~E_M~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,849 INFO L290 TraceCheckUtils]: 48: Hoare triple {28036#false} assume 1 == ~E_1~0;~E_1~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 49: Hoare triple {28036#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 50: Hoare triple {28036#false} assume 1 == ~E_3~0;~E_3~0 := 2; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 51: Hoare triple {28036#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 52: Hoare triple {28036#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 53: Hoare triple {28036#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {28036#false} is VALID [2022-02-21 04:21:53,850 INFO L290 TraceCheckUtils]: 54: Hoare triple {28036#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 55: Hoare triple {28036#false} assume !(0 == start_simulation_~tmp~3#1); {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 56: Hoare triple {28036#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 57: Hoare triple {28036#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 58: Hoare triple {28036#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 59: Hoare triple {28036#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 60: Hoare triple {28036#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28036#false} is VALID [2022-02-21 04:21:53,851 INFO L290 TraceCheckUtils]: 61: Hoare triple {28036#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28036#false} is VALID [2022-02-21 04:21:53,852 INFO L290 TraceCheckUtils]: 62: Hoare triple {28036#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {28036#false} is VALID [2022-02-21 04:21:53,852 INFO L290 TraceCheckUtils]: 63: Hoare triple {28036#false} assume !(0 != start_simulation_~tmp___0~1#1); {28036#false} is VALID [2022-02-21 04:21:53,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,852 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,852 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447883436] [2022-02-21 04:21:53,853 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447883436] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,853 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,853 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:53,853 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753590986] [2022-02-21 04:21:53,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:53,854 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:53,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:53,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:53,854 INFO L87 Difference]: Start difference. First operand 1749 states and 2547 transitions. cyclomatic complexity: 800 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,632 INFO L93 Difference]: Finished difference Result 2507 states and 3618 transitions. [2022-02-21 04:21:54,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:54,632 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,666 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:54,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2507 states and 3618 transitions. [2022-02-21 04:21:54,866 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2448 [2022-02-21 04:21:55,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2507 states to 2507 states and 3618 transitions. [2022-02-21 04:21:55,010 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2507 [2022-02-21 04:21:55,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2507 [2022-02-21 04:21:55,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:55,013 INFO L681 BuchiCegarLoop]: Abstraction has 2507 states and 3618 transitions. [2022-02-21 04:21:55,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2507 to 1749. [2022-02-21 04:21:55,035 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:55,037 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2507 states and 3618 transitions. Second operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,039 INFO L74 IsIncluded]: Start isIncluded. First operand 2507 states and 3618 transitions. Second operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,041 INFO L87 Difference]: Start difference. First operand 2507 states and 3618 transitions. Second operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,190 INFO L93 Difference]: Finished difference Result 2507 states and 3618 transitions. [2022-02-21 04:21:55,190 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,193 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,193 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,196 INFO L74 IsIncluded]: Start isIncluded. First operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,197 INFO L87 Difference]: Start difference. First operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,362 INFO L93 Difference]: Finished difference Result 2507 states and 3618 transitions. [2022-02-21 04:21:55,362 INFO L276 IsEmpty]: Start isEmpty. Operand 2507 states and 3618 transitions. [2022-02-21 04:21:55,365 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,365 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,365 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:55,365 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:55,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1749 states, 1749 states have (on average 1.4465408805031446) internal successors, (2530), 1748 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1749 states to 1749 states and 2530 transitions. [2022-02-21 04:21:55,439 INFO L704 BuchiCegarLoop]: Abstraction has 1749 states and 2530 transitions. [2022-02-21 04:21:55,439 INFO L587 BuchiCegarLoop]: Abstraction has 1749 states and 2530 transitions. [2022-02-21 04:21:55,439 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:55,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1749 states and 2530 transitions. [2022-02-21 04:21:55,445 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1692 [2022-02-21 04:21:55,445 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:55,445 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:55,446 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,446 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,447 INFO L791 eck$LassoCheckResult]: Stem: 30911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 30853#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 30854#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30859#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30748#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 30749#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30841#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30823#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30824#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30831#L429 assume !(0 == ~M_E~0); 30651#L429-2 assume !(0 == ~T1_E~0); 30652#L434-1 assume !(0 == ~T2_E~0); 30777#L439-1 assume !(0 == ~T3_E~0); 30802#L444-1 assume !(0 == ~E_M~0); 30803#L449-1 assume !(0 == ~E_1~0); 30659#L454-1 assume !(0 == ~E_2~0); 30660#L459-1 assume !(0 == ~E_3~0); 30618#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30619#L208 assume !(1 == ~m_pc~0); 30901#L208-2 is_master_triggered_~__retres1~0#1 := 0; 30902#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30688#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30638#L531 assume !(0 != activate_threads_~tmp~1#1); 30639#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30752#L227 assume !(1 == ~t1_pc~0); 30636#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30637#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30832#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30655#L539 assume !(0 != activate_threads_~tmp___0~0#1); 30656#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30689#L246 assume !(1 == ~t2_pc~0); 30690#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 30781#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30782#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30840#L547 assume !(0 != activate_threads_~tmp___1~0#1); 30848#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30698#L265 assume !(1 == ~t3_pc~0); 30580#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30551#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30552#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30786#L555 assume !(0 != activate_threads_~tmp___2~0#1); 30672#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30673#L477 assume !(1 == ~M_E~0); 30836#L477-2 assume !(1 == ~T1_E~0); 30855#L482-1 assume !(1 == ~T2_E~0); 30800#L487-1 assume !(1 == ~T3_E~0); 30801#L492-1 assume !(1 == ~E_M~0); 30626#L497-1 assume !(1 == ~E_1~0); 30627#L502-1 assume !(1 == ~E_2~0); 30607#L507-1 assume !(1 == ~E_3~0); 30608#L512-1 assume { :end_inline_reset_delta_events } true; 30750#L678-2 [2022-02-21 04:21:55,447 INFO L793 eck$LassoCheckResult]: Loop: 30750#L678-2 assume !false; 32222#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32218#L404 assume !false; 30751#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30729#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30590#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30622#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30674#L357 assume !(0 != eval_~tmp~0#1); 30553#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30554#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30666#L429-3 assume !(0 == ~M_E~0); 30880#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30825#L434-3 assume !(0 == ~T2_E~0); 30826#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30664#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 30665#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30685#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30715#L459-3 assume !(0 == ~E_3~0); 30657#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30658#L208-15 assume !(1 == ~m_pc~0); 30808#L208-17 is_master_triggered_~__retres1~0#1 := 0; 30809#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30646#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 30647#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30681#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30682#L227-15 assume 1 == ~t1_pc~0; 30896#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30866#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30581#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 30582#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30821#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30804#L246-15 assume !(1 == ~t2_pc~0); 30572#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 30573#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30876#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30897#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30649#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30650#L265-15 assume 1 == ~t3_pc~0; 30726#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30728#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30705#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30700#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30701#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30850#L477-3 assume !(1 == ~M_E~0); 30810#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30811#L482-3 assume !(1 == ~T2_E~0); 30713#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30714#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30895#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30770#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30771#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30739#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30609#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30568#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30569#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 30648#L697 assume !(0 == start_simulation_~tmp~3#1); 30842#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32240#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 32236#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 32234#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 32232#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32230#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32228#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 32226#L710 assume !(0 != start_simulation_~tmp___0~1#1); 30750#L678-2 [2022-02-21 04:21:55,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2022-02-21 04:21:55,448 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,448 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936518017] [2022-02-21 04:21:55,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:55,456 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:55,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:55,491 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:55,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1722483012, now seen corresponding path program 1 times [2022-02-21 04:21:55,492 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,493 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961526706] [2022-02-21 04:21:55,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,535 INFO L290 TraceCheckUtils]: 0: Hoare triple {37317#true} assume !false; {37317#true} is VALID [2022-02-21 04:21:55,535 INFO L290 TraceCheckUtils]: 1: Hoare triple {37317#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {37317#true} is VALID [2022-02-21 04:21:55,535 INFO L290 TraceCheckUtils]: 2: Hoare triple {37317#true} assume !false; {37317#true} is VALID [2022-02-21 04:21:55,535 INFO L290 TraceCheckUtils]: 3: Hoare triple {37317#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {37317#true} is VALID [2022-02-21 04:21:55,536 INFO L290 TraceCheckUtils]: 4: Hoare triple {37317#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {37319#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} is VALID [2022-02-21 04:21:55,536 INFO L290 TraceCheckUtils]: 5: Hoare triple {37319#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~4#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {37320#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:21:55,537 INFO L290 TraceCheckUtils]: 6: Hoare triple {37320#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {37321#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:21:55,537 INFO L290 TraceCheckUtils]: 7: Hoare triple {37321#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {37318#false} is VALID [2022-02-21 04:21:55,537 INFO L290 TraceCheckUtils]: 8: Hoare triple {37318#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {37318#false} is VALID [2022-02-21 04:21:55,537 INFO L290 TraceCheckUtils]: 9: Hoare triple {37318#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {37318#false} is VALID [2022-02-21 04:21:55,537 INFO L290 TraceCheckUtils]: 10: Hoare triple {37318#false} assume !(0 == ~M_E~0); {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 11: Hoare triple {37318#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 12: Hoare triple {37318#false} assume !(0 == ~T2_E~0); {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 13: Hoare triple {37318#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 14: Hoare triple {37318#false} assume 0 == ~E_M~0;~E_M~0 := 1; {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 15: Hoare triple {37318#false} assume 0 == ~E_1~0;~E_1~0 := 1; {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 16: Hoare triple {37318#false} assume 0 == ~E_2~0;~E_2~0 := 1; {37318#false} is VALID [2022-02-21 04:21:55,538 INFO L290 TraceCheckUtils]: 17: Hoare triple {37318#false} assume !(0 == ~E_3~0); {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 18: Hoare triple {37318#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 19: Hoare triple {37318#false} assume !(1 == ~m_pc~0); {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 20: Hoare triple {37318#false} is_master_triggered_~__retres1~0#1 := 0; {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 21: Hoare triple {37318#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 22: Hoare triple {37318#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 23: Hoare triple {37318#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {37318#false} is VALID [2022-02-21 04:21:55,539 INFO L290 TraceCheckUtils]: 24: Hoare triple {37318#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 25: Hoare triple {37318#false} assume 1 == ~t1_pc~0; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 26: Hoare triple {37318#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 27: Hoare triple {37318#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 28: Hoare triple {37318#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 29: Hoare triple {37318#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {37318#false} is VALID [2022-02-21 04:21:55,540 INFO L290 TraceCheckUtils]: 30: Hoare triple {37318#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 31: Hoare triple {37318#false} assume !(1 == ~t2_pc~0); {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 32: Hoare triple {37318#false} is_transmit2_triggered_~__retres1~2#1 := 0; {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 33: Hoare triple {37318#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 34: Hoare triple {37318#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 35: Hoare triple {37318#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {37318#false} is VALID [2022-02-21 04:21:55,541 INFO L290 TraceCheckUtils]: 36: Hoare triple {37318#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 37: Hoare triple {37318#false} assume 1 == ~t3_pc~0; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 38: Hoare triple {37318#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 39: Hoare triple {37318#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 40: Hoare triple {37318#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 41: Hoare triple {37318#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 42: Hoare triple {37318#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {37318#false} is VALID [2022-02-21 04:21:55,542 INFO L290 TraceCheckUtils]: 43: Hoare triple {37318#false} assume !(1 == ~M_E~0); {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 44: Hoare triple {37318#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 45: Hoare triple {37318#false} assume !(1 == ~T2_E~0); {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 46: Hoare triple {37318#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 47: Hoare triple {37318#false} assume 1 == ~E_M~0;~E_M~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 48: Hoare triple {37318#false} assume 1 == ~E_1~0;~E_1~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,543 INFO L290 TraceCheckUtils]: 49: Hoare triple {37318#false} assume 1 == ~E_2~0;~E_2~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 50: Hoare triple {37318#false} assume 1 == ~E_3~0;~E_3~0 := 2; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 51: Hoare triple {37318#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 52: Hoare triple {37318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 53: Hoare triple {37318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 54: Hoare triple {37318#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {37318#false} is VALID [2022-02-21 04:21:55,544 INFO L290 TraceCheckUtils]: 55: Hoare triple {37318#false} assume !(0 == start_simulation_~tmp~3#1); {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 56: Hoare triple {37318#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 57: Hoare triple {37318#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 58: Hoare triple {37318#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 59: Hoare triple {37318#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 60: Hoare triple {37318#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 61: Hoare triple {37318#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {37318#false} is VALID [2022-02-21 04:21:55,545 INFO L290 TraceCheckUtils]: 62: Hoare triple {37318#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {37318#false} is VALID [2022-02-21 04:21:55,546 INFO L290 TraceCheckUtils]: 63: Hoare triple {37318#false} assume !(0 != start_simulation_~tmp___0~1#1); {37318#false} is VALID [2022-02-21 04:21:55,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,546 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,546 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961526706] [2022-02-21 04:21:55,546 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961526706] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,547 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,547 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:55,547 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320176445] [2022-02-21 04:21:55,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:55,547 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:55,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:55,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:55,548 INFO L87 Difference]: Start difference. First operand 1749 states and 2530 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,785 INFO L93 Difference]: Finished difference Result 3053 states and 4338 transitions. [2022-02-21 04:21:56,785 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:21:56,786 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,835 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:56,837 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,088 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2992 [2022-02-21 04:21:57,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3053 states to 3053 states and 4338 transitions. [2022-02-21 04:21:57,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3053 [2022-02-21 04:21:57,319 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3053 [2022-02-21 04:21:57,319 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:57,323 INFO L681 BuchiCegarLoop]: Abstraction has 3053 states and 4338 transitions. [2022-02-21 04:21:57,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3053 to 1773. [2022-02-21 04:21:57,349 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:57,351 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3053 states and 4338 transitions. Second operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,352 INFO L74 IsIncluded]: Start isIncluded. First operand 3053 states and 4338 transitions. Second operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,354 INFO L87 Difference]: Start difference. First operand 3053 states and 4338 transitions. Second operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,600 INFO L93 Difference]: Finished difference Result 3053 states and 4338 transitions. [2022-02-21 04:21:57,600 INFO L276 IsEmpty]: Start isEmpty. Operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,602 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:57,602 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:57,604 INFO L74 IsIncluded]: Start isIncluded. First operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,605 INFO L87 Difference]: Start difference. First operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,861 INFO L93 Difference]: Finished difference Result 3053 states and 4338 transitions. [2022-02-21 04:21:57,861 INFO L276 IsEmpty]: Start isEmpty. Operand 3053 states and 4338 transitions. [2022-02-21 04:21:57,863 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:57,863 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:57,863 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:57,863 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:57,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1773 states, 1773 states have (on average 1.440496333897349) internal successors, (2554), 1772 states have internal predecessors, (2554), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 2554 transitions. [2022-02-21 04:21:57,934 INFO L704 BuchiCegarLoop]: Abstraction has 1773 states and 2554 transitions. [2022-02-21 04:21:57,934 INFO L587 BuchiCegarLoop]: Abstraction has 1773 states and 2554 transitions. [2022-02-21 04:21:57,934 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:57,934 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1773 states and 2554 transitions. [2022-02-21 04:21:57,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1716 [2022-02-21 04:21:57,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:57,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:57,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:57,939 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:57,939 INFO L791 eck$LassoCheckResult]: Stem: 40768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 40696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 40697#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40701#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40578#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 40579#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40684#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40664#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40665#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40673#L429 assume !(0 == ~M_E~0); 40485#L429-2 assume !(0 == ~T1_E~0); 40486#L434-1 assume !(0 == ~T2_E~0); 40613#L439-1 assume !(0 == ~T3_E~0); 40640#L444-1 assume !(0 == ~E_M~0); 40641#L449-1 assume !(0 == ~E_1~0); 40491#L454-1 assume !(0 == ~E_2~0); 40492#L459-1 assume !(0 == ~E_3~0); 40451#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40452#L208 assume !(1 == ~m_pc~0); 40758#L208-2 is_master_triggered_~__retres1~0#1 := 0; 40759#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40523#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40472#L531 assume !(0 != activate_threads_~tmp~1#1); 40473#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40586#L227 assume !(1 == ~t1_pc~0); 40470#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40471#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40674#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40489#L539 assume !(0 != activate_threads_~tmp___0~0#1); 40490#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40524#L246 assume !(1 == ~t2_pc~0); 40525#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40617#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40618#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40680#L547 assume !(0 != activate_threads_~tmp___1~0#1); 40689#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40532#L265 assume !(1 == ~t3_pc~0); 40414#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 40385#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40386#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40621#L555 assume !(0 != activate_threads_~tmp___2~0#1); 40502#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40503#L477 assume !(1 == ~M_E~0); 40678#L477-2 assume !(1 == ~T1_E~0); 40698#L482-1 assume !(1 == ~T2_E~0); 40635#L487-1 assume !(1 == ~T3_E~0); 40636#L492-1 assume !(1 == ~E_M~0); 40457#L497-1 assume !(1 == ~E_1~0); 40458#L502-1 assume !(1 == ~E_2~0); 40439#L507-1 assume !(1 == ~E_3~0); 40440#L512-1 assume { :end_inline_reset_delta_events } true; 40531#L678-2 [2022-02-21 04:21:57,939 INFO L793 eck$LassoCheckResult]: Loop: 40531#L678-2 assume !false; 40669#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40418#L404 assume !false; 40585#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40560#L320 assume !(0 == ~m_st~0); 40422#L324 assume !(0 == ~t1_st~0); 40423#L328 assume !(0 == ~t2_st~0); 40677#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 40455#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40456#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40743#L357 assume !(0 != eval_~tmp~0#1); 40387#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40388#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40735#L429-3 assume !(0 == ~M_E~0); 40736#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40770#L434-3 assume !(0 == ~T2_E~0); 40705#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40706#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40516#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40517#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 40708#L459-3 assume !(0 == ~E_3~0); 40709#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40721#L208-15 assume !(1 == ~m_pc~0); 40722#L208-17 is_master_triggered_~__retres1~0#1 := 0; 40718#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40719#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 40622#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40623#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40751#L227-15 assume 1 == ~t1_pc~0; 40752#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40739#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40415#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 40416#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42006#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40642#L246-15 assume !(1 == ~t2_pc~0); 40643#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 40725#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40726#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 42005#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 40482#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40483#L265-15 assume !(1 == ~t3_pc~0); 42003#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 42002#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42001#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40536#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40537#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40728#L477-3 assume !(1 == ~M_E~0); 40650#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40651#L482-3 assume !(1 == ~T2_E~0); 40550#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40551#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40749#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40750#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40657#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40658#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40443#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40404#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40405#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 40484#L697 assume !(0 == start_simulation_~tmp~3#1); 42090#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 40727#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 40529#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 40514#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 40515#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40675#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40676#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 40530#L710 assume !(0 != start_simulation_~tmp___0~1#1); 40531#L678-2 [2022-02-21 04:21:57,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:57,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2022-02-21 04:21:57,940 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:57,940 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658297278] [2022-02-21 04:21:57,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:57,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:57,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:57,958 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:21:57,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:21:57,975 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:21:57,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:57,976 INFO L85 PathProgramCache]: Analyzing trace with hash 1720384587, now seen corresponding path program 1 times [2022-02-21 04:21:57,976 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:57,977 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2057436478] [2022-02-21 04:21:57,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:57,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:57,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,046 INFO L290 TraceCheckUtils]: 0: Hoare triple {48267#true} assume !false; {48267#true} is VALID [2022-02-21 04:21:58,047 INFO L290 TraceCheckUtils]: 1: Hoare triple {48267#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {48267#true} is VALID [2022-02-21 04:21:58,047 INFO L290 TraceCheckUtils]: 2: Hoare triple {48267#true} assume !false; {48267#true} is VALID [2022-02-21 04:21:58,047 INFO L290 TraceCheckUtils]: 3: Hoare triple {48267#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {48267#true} is VALID [2022-02-21 04:21:58,047 INFO L290 TraceCheckUtils]: 4: Hoare triple {48267#true} assume !(0 == ~m_st~0); {48267#true} is VALID [2022-02-21 04:21:58,047 INFO L290 TraceCheckUtils]: 5: Hoare triple {48267#true} assume !(0 == ~t1_st~0); {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 6: Hoare triple {48267#true} assume !(0 == ~t2_st~0); {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 7: Hoare triple {48267#true} assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 8: Hoare triple {48267#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 9: Hoare triple {48267#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 10: Hoare triple {48267#true} assume !(0 != eval_~tmp~0#1); {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 11: Hoare triple {48267#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {48267#true} is VALID [2022-02-21 04:21:58,048 INFO L290 TraceCheckUtils]: 12: Hoare triple {48267#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 13: Hoare triple {48267#true} assume !(0 == ~M_E~0); {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 14: Hoare triple {48267#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 15: Hoare triple {48267#true} assume !(0 == ~T2_E~0); {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 16: Hoare triple {48267#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 17: Hoare triple {48267#true} assume 0 == ~E_M~0;~E_M~0 := 1; {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 18: Hoare triple {48267#true} assume 0 == ~E_1~0;~E_1~0 := 1; {48267#true} is VALID [2022-02-21 04:21:58,049 INFO L290 TraceCheckUtils]: 19: Hoare triple {48267#true} assume 0 == ~E_2~0;~E_2~0 := 1; {48267#true} is VALID [2022-02-21 04:21:58,050 INFO L290 TraceCheckUtils]: 20: Hoare triple {48267#true} assume !(0 == ~E_3~0); {48267#true} is VALID [2022-02-21 04:21:58,050 INFO L290 TraceCheckUtils]: 21: Hoare triple {48267#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {48267#true} is VALID [2022-02-21 04:21:58,050 INFO L290 TraceCheckUtils]: 22: Hoare triple {48267#true} assume !(1 == ~m_pc~0); {48267#true} is VALID [2022-02-21 04:21:58,050 INFO L290 TraceCheckUtils]: 23: Hoare triple {48267#true} is_master_triggered_~__retres1~0#1 := 0; {48269#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:21:58,051 INFO L290 TraceCheckUtils]: 24: Hoare triple {48269#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {48270#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:21:58,052 INFO L290 TraceCheckUtils]: 25: Hoare triple {48270#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {48271#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:21:58,053 INFO L290 TraceCheckUtils]: 26: Hoare triple {48271#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {48268#false} is VALID [2022-02-21 04:21:58,053 INFO L290 TraceCheckUtils]: 27: Hoare triple {48268#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {48268#false} is VALID [2022-02-21 04:21:58,053 INFO L290 TraceCheckUtils]: 28: Hoare triple {48268#false} assume 1 == ~t1_pc~0; {48268#false} is VALID [2022-02-21 04:21:58,053 INFO L290 TraceCheckUtils]: 29: Hoare triple {48268#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {48268#false} is VALID [2022-02-21 04:21:58,053 INFO L290 TraceCheckUtils]: 30: Hoare triple {48268#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 31: Hoare triple {48268#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 32: Hoare triple {48268#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 33: Hoare triple {48268#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 34: Hoare triple {48268#false} assume !(1 == ~t2_pc~0); {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 35: Hoare triple {48268#false} is_transmit2_triggered_~__retres1~2#1 := 0; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 36: Hoare triple {48268#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {48268#false} is VALID [2022-02-21 04:21:58,054 INFO L290 TraceCheckUtils]: 37: Hoare triple {48268#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 38: Hoare triple {48268#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 39: Hoare triple {48268#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 40: Hoare triple {48268#false} assume !(1 == ~t3_pc~0); {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 41: Hoare triple {48268#false} is_transmit3_triggered_~__retres1~3#1 := 0; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 42: Hoare triple {48268#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 43: Hoare triple {48268#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {48268#false} is VALID [2022-02-21 04:21:58,055 INFO L290 TraceCheckUtils]: 44: Hoare triple {48268#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 45: Hoare triple {48268#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 46: Hoare triple {48268#false} assume !(1 == ~M_E~0); {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 47: Hoare triple {48268#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 48: Hoare triple {48268#false} assume !(1 == ~T2_E~0); {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 49: Hoare triple {48268#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,056 INFO L290 TraceCheckUtils]: 50: Hoare triple {48268#false} assume 1 == ~E_M~0;~E_M~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 51: Hoare triple {48268#false} assume 1 == ~E_1~0;~E_1~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 52: Hoare triple {48268#false} assume 1 == ~E_2~0;~E_2~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 53: Hoare triple {48268#false} assume 1 == ~E_3~0;~E_3~0 := 2; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 54: Hoare triple {48268#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 55: Hoare triple {48268#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 56: Hoare triple {48268#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {48268#false} is VALID [2022-02-21 04:21:58,057 INFO L290 TraceCheckUtils]: 57: Hoare triple {48268#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 58: Hoare triple {48268#false} assume !(0 == start_simulation_~tmp~3#1); {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 59: Hoare triple {48268#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 60: Hoare triple {48268#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 61: Hoare triple {48268#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 62: Hoare triple {48268#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 63: Hoare triple {48268#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {48268#false} is VALID [2022-02-21 04:21:58,058 INFO L290 TraceCheckUtils]: 64: Hoare triple {48268#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {48268#false} is VALID [2022-02-21 04:21:58,059 INFO L290 TraceCheckUtils]: 65: Hoare triple {48268#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {48268#false} is VALID [2022-02-21 04:21:58,059 INFO L290 TraceCheckUtils]: 66: Hoare triple {48268#false} assume !(0 != start_simulation_~tmp___0~1#1); {48268#false} is VALID [2022-02-21 04:21:58,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,059 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,059 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2057436478] [2022-02-21 04:21:58,059 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2057436478] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,060 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,060 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:58,060 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1535390788] [2022-02-21 04:21:58,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,060 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:58,061 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:58,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:58,061 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:58,061 INFO L87 Difference]: Start difference. First operand 1773 states and 2554 transitions. cyclomatic complexity: 783 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,851 INFO L93 Difference]: Finished difference Result 3467 states and 4955 transitions. [2022-02-21 04:21:59,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:59,852 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,892 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:59,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3467 states and 4955 transitions. [2022-02-21 04:22:00,160 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3410 [2022-02-21 04:22:00,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3467 states to 3467 states and 4955 transitions. [2022-02-21 04:22:00,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3467 [2022-02-21 04:22:00,446 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3467 [2022-02-21 04:22:00,446 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3467 states and 4955 transitions. [2022-02-21 04:22:00,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:00,450 INFO L681 BuchiCegarLoop]: Abstraction has 3467 states and 4955 transitions. [2022-02-21 04:22:00,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3467 states and 4955 transitions. [2022-02-21 04:22:00,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3467 to 1833. [2022-02-21 04:22:00,484 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:00,486 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3467 states and 4955 transitions. Second operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,487 INFO L74 IsIncluded]: Start isIncluded. First operand 3467 states and 4955 transitions. Second operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,489 INFO L87 Difference]: Start difference. First operand 3467 states and 4955 transitions. Second operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,759 INFO L93 Difference]: Finished difference Result 3467 states and 4955 transitions. [2022-02-21 04:22:00,759 INFO L276 IsEmpty]: Start isEmpty. Operand 3467 states and 4955 transitions. [2022-02-21 04:22:00,762 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,762 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,764 INFO L74 IsIncluded]: Start isIncluded. First operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3467 states and 4955 transitions. [2022-02-21 04:22:00,766 INFO L87 Difference]: Start difference. First operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3467 states and 4955 transitions. [2022-02-21 04:22:01,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,101 INFO L93 Difference]: Finished difference Result 3467 states and 4955 transitions. [2022-02-21 04:22:01,101 INFO L276 IsEmpty]: Start isEmpty. Operand 3467 states and 4955 transitions. [2022-02-21 04:22:01,103 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:01,104 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:01,104 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:01,104 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:01,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1833 states, 1833 states have (on average 1.4168030551009274) internal successors, (2597), 1832 states have internal predecessors, (2597), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1833 states to 1833 states and 2597 transitions. [2022-02-21 04:22:01,183 INFO L704 BuchiCegarLoop]: Abstraction has 1833 states and 2597 transitions. [2022-02-21 04:22:01,183 INFO L587 BuchiCegarLoop]: Abstraction has 1833 states and 2597 transitions. [2022-02-21 04:22:01,183 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:01,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1833 states and 2597 transitions. [2022-02-21 04:22:01,187 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1776 [2022-02-21 04:22:01,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:01,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:01,188 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,188 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,189 INFO L791 eck$LassoCheckResult]: Stem: 52133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 52062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 52063#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52067#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51948#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 51949#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52050#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52030#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52031#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52039#L429 assume !(0 == ~M_E~0); 51849#L429-2 assume !(0 == ~T1_E~0); 51850#L434-1 assume !(0 == ~T2_E~0); 51980#L439-1 assume !(0 == ~T3_E~0); 52007#L444-1 assume !(0 == ~E_M~0); 52008#L449-1 assume !(0 == ~E_1~0); 51857#L454-1 assume !(0 == ~E_2~0); 51858#L459-1 assume !(0 == ~E_3~0); 51815#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51816#L208 assume !(1 == ~m_pc~0); 52122#L208-2 is_master_triggered_~__retres1~0#1 := 0; 52123#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51887#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 51836#L531 assume !(0 != activate_threads_~tmp~1#1); 51837#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51953#L227 assume !(1 == ~t1_pc~0); 51834#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 51835#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52040#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 51853#L539 assume !(0 != activate_threads_~tmp___0~0#1); 51854#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51888#L246 assume !(1 == ~t2_pc~0); 51889#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 51984#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51985#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52048#L547 assume !(0 != activate_threads_~tmp___1~0#1); 52057#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51897#L265 assume !(1 == ~t3_pc~0); 51775#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 51746#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51747#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 51989#L555 assume !(0 != activate_threads_~tmp___2~0#1); 51870#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51871#L477 assume !(1 == ~M_E~0); 52045#L477-2 assume !(1 == ~T1_E~0); 52064#L482-1 assume !(1 == ~T2_E~0); 52005#L487-1 assume !(1 == ~T3_E~0); 52006#L492-1 assume !(1 == ~E_M~0); 51824#L497-1 assume !(1 == ~E_1~0); 51825#L502-1 assume !(1 == ~E_2~0); 51803#L507-1 assume !(1 == ~E_3~0); 51804#L512-1 assume { :end_inline_reset_delta_events } true; 51950#L678-2 [2022-02-21 04:22:01,189 INFO L793 eck$LassoCheckResult]: Loop: 51950#L678-2 assume !false; 52839#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52835#L404 assume !false; 52834#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52832#L320 assume !(0 == ~m_st~0); 52833#L324 assume !(0 == ~t1_st~0); 52829#L328 assume !(0 == ~t2_st~0); 52830#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 52831#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52683#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 52684#L357 assume !(0 != eval_~tmp~0#1); 52912#L419 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52911#L285-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52910#L429-3 assume !(0 == ~M_E~0); 52908#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52907#L434-3 assume !(0 == ~T2_E~0); 52906#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52905#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52904#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 52903#L454-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52902#L459-3 assume !(0 == ~E_3~0); 51855#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51856#L208-15 assume !(1 == ~m_pc~0); 52080#L208-17 is_master_triggered_~__retres1~0#1 := 0; 52965#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52964#L220-5 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 52963#L531-15 assume !(0 != activate_threads_~tmp~1#1); 52962#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52961#L227-15 assume !(1 == ~t1_pc~0); 52960#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 52958#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52957#L239-5 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 52956#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52955#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52954#L246-15 assume !(1 == ~t2_pc~0); 52486#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 52953#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52952#L258-5 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52951#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52950#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52949#L265-15 assume !(1 == ~t3_pc~0); 52947#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 52946#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52945#L277-5 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52944#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52943#L555-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52942#L477-3 assume !(1 == ~M_E~0); 52767#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52941#L482-3 assume !(1 == ~T2_E~0); 52940#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52939#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 52938#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 52937#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 52936#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 52935#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52932#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52930#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52929#L343-1 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 52051#L697 assume !(0 == start_simulation_~tmp~3#1); 52052#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 52857#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 52853#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 52851#L343-2 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 52849#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 52847#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52845#L660 start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 52842#L710 assume !(0 != start_simulation_~tmp___0~1#1); 51950#L678-2 [2022-02-21 04:22:01,189 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,189 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2022-02-21 04:22:01,190 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,190 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2030026133] [2022-02-21 04:22:01,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:01,197 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:01,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:01,208 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:01,209 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1187102926, now seen corresponding path program 1 times [2022-02-21 04:22:01,209 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,209 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39121143] [2022-02-21 04:22:01,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,228 INFO L290 TraceCheckUtils]: 0: Hoare triple {60516#true} assume !false; {60516#true} is VALID [2022-02-21 04:22:01,229 INFO L290 TraceCheckUtils]: 1: Hoare triple {60516#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {60516#true} is VALID [2022-02-21 04:22:01,229 INFO L290 TraceCheckUtils]: 2: Hoare triple {60516#true} assume !false; {60516#true} is VALID [2022-02-21 04:22:01,229 INFO L290 TraceCheckUtils]: 3: Hoare triple {60516#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {60516#true} is VALID [2022-02-21 04:22:01,229 INFO L290 TraceCheckUtils]: 4: Hoare triple {60516#true} assume !(0 == ~m_st~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,230 INFO L290 TraceCheckUtils]: 5: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,230 INFO L290 TraceCheckUtils]: 6: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~t2_st~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,230 INFO L290 TraceCheckUtils]: 7: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,231 INFO L290 TraceCheckUtils]: 8: Hoare triple {60518#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,231 INFO L290 TraceCheckUtils]: 9: Hoare triple {60518#(not (= ~m_st~0 0))} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,231 INFO L290 TraceCheckUtils]: 10: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,232 INFO L290 TraceCheckUtils]: 11: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,232 INFO L290 TraceCheckUtils]: 12: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,232 INFO L290 TraceCheckUtils]: 13: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~M_E~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,233 INFO L290 TraceCheckUtils]: 14: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~T1_E~0;~T1_E~0 := 1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,233 INFO L290 TraceCheckUtils]: 15: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~T2_E~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,233 INFO L290 TraceCheckUtils]: 16: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,234 INFO L290 TraceCheckUtils]: 17: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,234 INFO L290 TraceCheckUtils]: 18: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,234 INFO L290 TraceCheckUtils]: 19: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~E_2~0;~E_2~0 := 1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,235 INFO L290 TraceCheckUtils]: 20: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 == ~E_3~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,235 INFO L290 TraceCheckUtils]: 21: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,235 INFO L290 TraceCheckUtils]: 22: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,236 INFO L290 TraceCheckUtils]: 23: Hoare triple {60518#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,236 INFO L290 TraceCheckUtils]: 24: Hoare triple {60518#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,236 INFO L290 TraceCheckUtils]: 25: Hoare triple {60518#(not (= ~m_st~0 0))} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,237 INFO L290 TraceCheckUtils]: 26: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,237 INFO L290 TraceCheckUtils]: 27: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,237 INFO L290 TraceCheckUtils]: 28: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,238 INFO L290 TraceCheckUtils]: 29: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,238 INFO L290 TraceCheckUtils]: 30: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,238 INFO L290 TraceCheckUtils]: 31: Hoare triple {60518#(not (= ~m_st~0 0))} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,239 INFO L290 TraceCheckUtils]: 32: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,239 INFO L290 TraceCheckUtils]: 33: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,239 INFO L290 TraceCheckUtils]: 34: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~t2_pc~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,240 INFO L290 TraceCheckUtils]: 35: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit2_triggered_~__retres1~2#1 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,240 INFO L290 TraceCheckUtils]: 36: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,240 INFO L290 TraceCheckUtils]: 37: Hoare triple {60518#(not (= ~m_st~0 0))} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,241 INFO L290 TraceCheckUtils]: 38: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,241 INFO L290 TraceCheckUtils]: 39: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,241 INFO L290 TraceCheckUtils]: 40: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~t3_pc~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,242 INFO L290 TraceCheckUtils]: 41: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit3_triggered_~__retres1~3#1 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,242 INFO L290 TraceCheckUtils]: 42: Hoare triple {60518#(not (= ~m_st~0 0))} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,242 INFO L290 TraceCheckUtils]: 43: Hoare triple {60518#(not (= ~m_st~0 0))} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,243 INFO L290 TraceCheckUtils]: 44: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,243 INFO L290 TraceCheckUtils]: 45: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,243 INFO L290 TraceCheckUtils]: 46: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~M_E~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,244 INFO L290 TraceCheckUtils]: 47: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~T1_E~0;~T1_E~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,244 INFO L290 TraceCheckUtils]: 48: Hoare triple {60518#(not (= ~m_st~0 0))} assume !(1 == ~T2_E~0); {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,244 INFO L290 TraceCheckUtils]: 49: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~T3_E~0;~T3_E~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,245 INFO L290 TraceCheckUtils]: 50: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~E_M~0;~E_M~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,245 INFO L290 TraceCheckUtils]: 51: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~E_1~0;~E_1~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,245 INFO L290 TraceCheckUtils]: 52: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~E_2~0;~E_2~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,246 INFO L290 TraceCheckUtils]: 53: Hoare triple {60518#(not (= ~m_st~0 0))} assume 1 == ~E_3~0;~E_3~0 := 2; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,246 INFO L290 TraceCheckUtils]: 54: Hoare triple {60518#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {60518#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:01,246 INFO L290 TraceCheckUtils]: 55: Hoare triple {60518#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {60517#false} is VALID [2022-02-21 04:22:01,246 INFO L290 TraceCheckUtils]: 56: Hoare triple {60517#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {60517#false} is VALID [2022-02-21 04:22:01,246 INFO L290 TraceCheckUtils]: 57: Hoare triple {60517#false} start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 58: Hoare triple {60517#false} assume !(0 == start_simulation_~tmp~3#1); {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 59: Hoare triple {60517#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 60: Hoare triple {60517#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 61: Hoare triple {60517#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 62: Hoare triple {60517#false} stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 63: Hoare triple {60517#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {60517#false} is VALID [2022-02-21 04:22:01,247 INFO L290 TraceCheckUtils]: 64: Hoare triple {60517#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {60517#false} is VALID [2022-02-21 04:22:01,248 INFO L290 TraceCheckUtils]: 65: Hoare triple {60517#false} start_simulation_#t~ret16#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; {60517#false} is VALID [2022-02-21 04:22:01,248 INFO L290 TraceCheckUtils]: 66: Hoare triple {60517#false} assume !(0 != start_simulation_~tmp___0~1#1); {60517#false} is VALID [2022-02-21 04:22:01,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,248 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,248 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39121143] [2022-02-21 04:22:01,249 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39121143] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,249 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,249 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,249 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514657224] [2022-02-21 04:22:01,249 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,249 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:01,250 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:01,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:01,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:01,250 INFO L87 Difference]: Start difference. First operand 1833 states and 2597 transitions. cyclomatic complexity: 766 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,863 INFO L93 Difference]: Finished difference Result 2824 states and 3942 transitions. [2022-02-21 04:22:01,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:01,864 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,904 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:01,905 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,079 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2767 [2022-02-21 04:22:02,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2824 states to 2824 states and 3942 transitions. [2022-02-21 04:22:02,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2824 [2022-02-21 04:22:02,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2824 [2022-02-21 04:22:02,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:02,289 INFO L681 BuchiCegarLoop]: Abstraction has 2824 states and 3942 transitions. [2022-02-21 04:22:02,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2824 to 2734. [2022-02-21 04:22:02,321 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:02,324 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2824 states and 3942 transitions. Second operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,327 INFO L74 IsIncluded]: Start isIncluded. First operand 2824 states and 3942 transitions. Second operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,330 INFO L87 Difference]: Start difference. First operand 2824 states and 3942 transitions. Second operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,593 INFO L93 Difference]: Finished difference Result 2824 states and 3942 transitions. [2022-02-21 04:22:02,594 INFO L276 IsEmpty]: Start isEmpty. Operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,596 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:02,597 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:02,600 INFO L74 IsIncluded]: Start isIncluded. First operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,601 INFO L87 Difference]: Start difference. First operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,792 INFO L93 Difference]: Finished difference Result 2824 states and 3942 transitions. [2022-02-21 04:22:02,792 INFO L276 IsEmpty]: Start isEmpty. Operand 2824 states and 3942 transitions. [2022-02-21 04:22:02,794 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:02,795 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:02,795 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:02,795 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:02,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2734 states, 2734 states have (on average 1.3972201901975128) internal successors, (3820), 2733 states have internal predecessors, (3820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2734 states to 2734 states and 3820 transitions. [2022-02-21 04:22:02,982 INFO L704 BuchiCegarLoop]: Abstraction has 2734 states and 3820 transitions. [2022-02-21 04:22:02,982 INFO L587 BuchiCegarLoop]: Abstraction has 2734 states and 3820 transitions. [2022-02-21 04:22:02,982 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:22:02,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2734 states and 3820 transitions. [2022-02-21 04:22:02,987 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2677 [2022-02-21 04:22:02,987 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:02,987 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:02,990 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,990 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,990 INFO L791 eck$LassoCheckResult]: Stem: 63716#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 63652#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 63653#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63659#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63541#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 63542#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63640#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63621#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63622#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63629#L429 assume !(0 == ~M_E~0); 63444#L429-2 assume !(0 == ~T1_E~0); 63445#L434-1 assume !(0 == ~T2_E~0); 63573#L439-1 assume !(0 == ~T3_E~0); 63597#L444-1 assume !(0 == ~E_M~0); 63598#L449-1 assume !(0 == ~E_1~0); 63452#L454-1 assume !(0 == ~E_2~0); 63453#L459-1 assume !(0 == ~E_3~0); 63410#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63411#L208 assume !(1 == ~m_pc~0); 63702#L208-2 is_master_triggered_~__retres1~0#1 := 0; 63703#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63482#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 63431#L531 assume !(0 != activate_threads_~tmp~1#1); 63432#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63545#L227 assume !(1 == ~t1_pc~0); 63429#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63430#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63630#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63448#L539 assume !(0 != activate_threads_~tmp___0~0#1); 63449#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63483#L246 assume !(1 == ~t2_pc~0); 63484#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63576#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63577#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63639#L547 assume !(0 != activate_threads_~tmp___1~0#1); 63647#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63493#L265 assume !(1 == ~t3_pc~0); 63372#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63345#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63346#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63580#L555 assume !(0 != activate_threads_~tmp___2~0#1); 63465#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63466#L477 assume !(1 == ~M_E~0); 63635#L477-2 assume !(1 == ~T1_E~0); 63654#L482-1 assume !(1 == ~T2_E~0); 63595#L487-1 assume !(1 == ~T3_E~0); 63596#L492-1 assume !(1 == ~E_M~0); 63418#L497-1 assume !(1 == ~E_1~0); 63419#L502-1 assume !(1 == ~E_2~0); 63400#L507-1 assume !(1 == ~E_3~0); 63401#L512-1 assume { :end_inline_reset_delta_events } true; 63543#L678-2 assume !false; 65323#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65318#L404 [2022-02-21 04:22:02,991 INFO L793 eck$LassoCheckResult]: Loop: 65318#L404 assume !false; 65314#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 65311#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 65309#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 65305#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65303#L357 assume 0 != eval_~tmp~0#1; 65298#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 63454#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 63455#L362 assume !(0 == ~t1_st~0); 65304#L376 assume !(0 == ~t2_st~0); 65301#L390 assume !(0 == ~t3_st~0); 65318#L404 [2022-02-21 04:22:02,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:02,991 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2022-02-21 04:22:02,991 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:02,992 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789636398] [2022-02-21 04:22:02,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:02,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:03,000 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:03,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:03,010 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:03,011 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,011 INFO L85 PathProgramCache]: Analyzing trace with hash 257277008, now seen corresponding path program 1 times [2022-02-21 04:22:03,011 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,011 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453213586] [2022-02-21 04:22:03,011 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:03,014 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:03,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:03,025 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:03,027 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1138955338, now seen corresponding path program 1 times [2022-02-21 04:22:03,028 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,028 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605004650] [2022-02-21 04:22:03,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:03,055 INFO L290 TraceCheckUtils]: 0: Hoare triple {71732#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {71732#true} is VALID [2022-02-21 04:22:03,056 INFO L290 TraceCheckUtils]: 1: Hoare triple {71732#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {71732#true} is VALID [2022-02-21 04:22:03,056 INFO L290 TraceCheckUtils]: 2: Hoare triple {71732#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {71732#true} is VALID [2022-02-21 04:22:03,056 INFO L290 TraceCheckUtils]: 3: Hoare triple {71732#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {71732#true} is VALID [2022-02-21 04:22:03,056 INFO L290 TraceCheckUtils]: 4: Hoare triple {71732#true} assume 1 == ~m_i~0;~m_st~0 := 0; {71732#true} is VALID [2022-02-21 04:22:03,057 INFO L290 TraceCheckUtils]: 5: Hoare triple {71732#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,057 INFO L290 TraceCheckUtils]: 6: Hoare triple {71734#(= ~t1_st~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,057 INFO L290 TraceCheckUtils]: 7: Hoare triple {71734#(= ~t1_st~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,058 INFO L290 TraceCheckUtils]: 8: Hoare triple {71734#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,058 INFO L290 TraceCheckUtils]: 9: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,059 INFO L290 TraceCheckUtils]: 11: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~T2_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,059 INFO L290 TraceCheckUtils]: 12: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~T3_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,059 INFO L290 TraceCheckUtils]: 13: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~E_M~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,060 INFO L290 TraceCheckUtils]: 14: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,060 INFO L290 TraceCheckUtils]: 15: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~E_2~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,060 INFO L290 TraceCheckUtils]: 16: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~E_3~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,061 INFO L290 TraceCheckUtils]: 17: Hoare triple {71734#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,061 INFO L290 TraceCheckUtils]: 18: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,061 INFO L290 TraceCheckUtils]: 19: Hoare triple {71734#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,062 INFO L290 TraceCheckUtils]: 20: Hoare triple {71734#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,062 INFO L290 TraceCheckUtils]: 21: Hoare triple {71734#(= ~t1_st~0 0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,062 INFO L290 TraceCheckUtils]: 22: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,063 INFO L290 TraceCheckUtils]: 23: Hoare triple {71734#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,063 INFO L290 TraceCheckUtils]: 24: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,063 INFO L290 TraceCheckUtils]: 25: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,064 INFO L290 TraceCheckUtils]: 26: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,064 INFO L290 TraceCheckUtils]: 27: Hoare triple {71734#(= ~t1_st~0 0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,064 INFO L290 TraceCheckUtils]: 28: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,065 INFO L290 TraceCheckUtils]: 29: Hoare triple {71734#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,065 INFO L290 TraceCheckUtils]: 30: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~t2_pc~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,065 INFO L290 TraceCheckUtils]: 31: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,066 INFO L290 TraceCheckUtils]: 32: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,066 INFO L290 TraceCheckUtils]: 33: Hoare triple {71734#(= ~t1_st~0 0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,066 INFO L290 TraceCheckUtils]: 34: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,067 INFO L290 TraceCheckUtils]: 35: Hoare triple {71734#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,067 INFO L290 TraceCheckUtils]: 36: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~t3_pc~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,067 INFO L290 TraceCheckUtils]: 37: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,068 INFO L290 TraceCheckUtils]: 38: Hoare triple {71734#(= ~t1_st~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,068 INFO L290 TraceCheckUtils]: 39: Hoare triple {71734#(= ~t1_st~0 0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,068 INFO L290 TraceCheckUtils]: 40: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,069 INFO L290 TraceCheckUtils]: 41: Hoare triple {71734#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,069 INFO L290 TraceCheckUtils]: 42: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,069 INFO L290 TraceCheckUtils]: 43: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,070 INFO L290 TraceCheckUtils]: 44: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~T2_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,070 INFO L290 TraceCheckUtils]: 45: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~T3_E~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,070 INFO L290 TraceCheckUtils]: 46: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~E_M~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,071 INFO L290 TraceCheckUtils]: 47: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,071 INFO L290 TraceCheckUtils]: 48: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~E_2~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,071 INFO L290 TraceCheckUtils]: 49: Hoare triple {71734#(= ~t1_st~0 0)} assume !(1 == ~E_3~0); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,072 INFO L290 TraceCheckUtils]: 50: Hoare triple {71734#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,072 INFO L290 TraceCheckUtils]: 51: Hoare triple {71734#(= ~t1_st~0 0)} assume !false; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,072 INFO L290 TraceCheckUtils]: 52: Hoare triple {71734#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,073 INFO L290 TraceCheckUtils]: 53: Hoare triple {71734#(= ~t1_st~0 0)} assume !false; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,073 INFO L290 TraceCheckUtils]: 54: Hoare triple {71734#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,074 INFO L290 TraceCheckUtils]: 55: Hoare triple {71734#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,074 INFO L290 TraceCheckUtils]: 56: Hoare triple {71734#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,074 INFO L290 TraceCheckUtils]: 57: Hoare triple {71734#(= ~t1_st~0 0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,075 INFO L290 TraceCheckUtils]: 58: Hoare triple {71734#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,075 INFO L290 TraceCheckUtils]: 59: Hoare triple {71734#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,075 INFO L290 TraceCheckUtils]: 60: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {71734#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:03,076 INFO L290 TraceCheckUtils]: 61: Hoare triple {71734#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {71733#false} is VALID [2022-02-21 04:22:03,076 INFO L290 TraceCheckUtils]: 62: Hoare triple {71733#false} assume !(0 == ~t2_st~0); {71733#false} is VALID [2022-02-21 04:22:03,076 INFO L290 TraceCheckUtils]: 63: Hoare triple {71733#false} assume !(0 == ~t3_st~0); {71733#false} is VALID [2022-02-21 04:22:03,076 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:03,076 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:03,077 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605004650] [2022-02-21 04:22:03,077 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605004650] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:03,077 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:03,077 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:03,077 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596762854] [2022-02-21 04:22:03,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:03,168 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:03,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:03,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:03,168 INFO L87 Difference]: Start difference. First operand 2734 states and 3820 transitions. cyclomatic complexity: 1089 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,200 INFO L93 Difference]: Finished difference Result 4892 states and 6761 transitions. [2022-02-21 04:22:04,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:04,200 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,250 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:04,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4892 states and 6761 transitions. [2022-02-21 04:22:04,796 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4784 [2022-02-21 04:22:05,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4892 states to 4892 states and 6761 transitions. [2022-02-21 04:22:05,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4892 [2022-02-21 04:22:05,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4892 [2022-02-21 04:22:05,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4892 states and 6761 transitions. [2022-02-21 04:22:05,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:05,310 INFO L681 BuchiCegarLoop]: Abstraction has 4892 states and 6761 transitions. [2022-02-21 04:22:05,312 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4892 states and 6761 transitions. [2022-02-21 04:22:05,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4892 to 4647. [2022-02-21 04:22:05,363 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:05,368 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4892 states and 6761 transitions. Second operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,373 INFO L74 IsIncluded]: Start isIncluded. First operand 4892 states and 6761 transitions. Second operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,376 INFO L87 Difference]: Start difference. First operand 4892 states and 6761 transitions. Second operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:05,890 INFO L93 Difference]: Finished difference Result 4892 states and 6761 transitions. [2022-02-21 04:22:05,890 INFO L276 IsEmpty]: Start isEmpty. Operand 4892 states and 6761 transitions. [2022-02-21 04:22:05,895 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:05,895 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:05,899 INFO L74 IsIncluded]: Start isIncluded. First operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4892 states and 6761 transitions. [2022-02-21 04:22:05,904 INFO L87 Difference]: Start difference. First operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4892 states and 6761 transitions. [2022-02-21 04:22:06,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:06,419 INFO L93 Difference]: Finished difference Result 4892 states and 6761 transitions. [2022-02-21 04:22:06,419 INFO L276 IsEmpty]: Start isEmpty. Operand 4892 states and 6761 transitions. [2022-02-21 04:22:06,424 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:06,424 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:06,424 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:06,424 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:06,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4647 states, 4647 states have (on average 1.3871314826769958) internal successors, (6446), 4646 states have internal predecessors, (6446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4647 states to 4647 states and 6446 transitions. [2022-02-21 04:22:06,923 INFO L704 BuchiCegarLoop]: Abstraction has 4647 states and 6446 transitions. [2022-02-21 04:22:06,923 INFO L587 BuchiCegarLoop]: Abstraction has 4647 states and 6446 transitions. [2022-02-21 04:22:06,923 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:22:06,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4647 states and 6446 transitions. [2022-02-21 04:22:06,942 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2022-02-21 04:22:06,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:06,942 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:06,943 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:06,943 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:06,943 INFO L791 eck$LassoCheckResult]: Stem: 77024#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 76949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 76950#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76954#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76829#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 76830#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 76955#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78849#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 78848#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 78847#L429 assume !(0 == ~M_E~0); 78846#L429-2 assume !(0 == ~T1_E~0); 78845#L434-1 assume !(0 == ~T2_E~0); 78844#L439-1 assume !(0 == ~T3_E~0); 78843#L444-1 assume !(0 == ~E_M~0); 78842#L449-1 assume !(0 == ~E_1~0); 78841#L454-1 assume !(0 == ~E_2~0); 78840#L459-1 assume !(0 == ~E_3~0); 78839#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78838#L208 assume !(1 == ~m_pc~0); 78837#L208-2 is_master_triggered_~__retres1~0#1 := 0; 78836#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78835#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 78834#L531 assume !(0 != activate_threads_~tmp~1#1); 78833#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78832#L227 assume !(1 == ~t1_pc~0); 78830#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 78829#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 78828#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 78827#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76735#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76769#L246 assume !(1 == ~t2_pc~0); 76770#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76868#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76869#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76936#L547 assume !(0 != activate_threads_~tmp___1~0#1); 76945#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76779#L265 assume !(1 == ~t3_pc~0); 76780#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 78017#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76872#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76873#L555 assume !(0 != activate_threads_~tmp___2~0#1); 76751#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76752#L477 assume !(1 == ~M_E~0); 76991#L477-2 assume !(1 == ~T1_E~0); 76951#L482-1 assume !(1 == ~T2_E~0); 76890#L487-1 assume !(1 == ~T3_E~0); 76891#L492-1 assume !(1 == ~E_M~0); 77946#L497-1 assume !(1 == ~E_1~0); 77944#L502-1 assume !(1 == ~E_2~0); 76685#L507-1 assume !(1 == ~E_3~0); 76686#L512-1 assume { :end_inline_reset_delta_events } true; 76831#L678-2 assume !false; 77899#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 77894#L404 [2022-02-21 04:22:06,943 INFO L793 eck$LassoCheckResult]: Loop: 77894#L404 assume !false; 77893#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 77692#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 77693#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 78296#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 78294#L357 assume 0 != eval_~tmp~0#1; 78291#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 77677#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 77678#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 77903#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 77900#L376 assume !(0 == ~t2_st~0); 77898#L390 assume !(0 == ~t3_st~0); 77894#L404 [2022-02-21 04:22:06,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:06,944 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2022-02-21 04:22:06,944 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:06,944 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1766932771] [2022-02-21 04:22:06,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:06,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:06,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:06,960 INFO L290 TraceCheckUtils]: 0: Hoare triple {91061#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {91061#true} is VALID [2022-02-21 04:22:06,960 INFO L290 TraceCheckUtils]: 1: Hoare triple {91061#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {91063#(= ~t1_i~0 1)} is VALID [2022-02-21 04:22:06,961 INFO L290 TraceCheckUtils]: 2: Hoare triple {91063#(= ~t1_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {91063#(= ~t1_i~0 1)} is VALID [2022-02-21 04:22:06,961 INFO L290 TraceCheckUtils]: 3: Hoare triple {91063#(= ~t1_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {91063#(= ~t1_i~0 1)} is VALID [2022-02-21 04:22:06,961 INFO L290 TraceCheckUtils]: 4: Hoare triple {91063#(= ~t1_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {91063#(= ~t1_i~0 1)} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 5: Hoare triple {91063#(= ~t1_i~0 1)} assume !(1 == ~t1_i~0);~t1_st~0 := 2; {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 6: Hoare triple {91062#false} assume 1 == ~t2_i~0;~t2_st~0 := 0; {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 7: Hoare triple {91062#false} assume 1 == ~t3_i~0;~t3_st~0 := 0; {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 8: Hoare triple {91062#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 9: Hoare triple {91062#false} assume !(0 == ~M_E~0); {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 10: Hoare triple {91062#false} assume !(0 == ~T1_E~0); {91062#false} is VALID [2022-02-21 04:22:06,962 INFO L290 TraceCheckUtils]: 11: Hoare triple {91062#false} assume !(0 == ~T2_E~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 12: Hoare triple {91062#false} assume !(0 == ~T3_E~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 13: Hoare triple {91062#false} assume !(0 == ~E_M~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 14: Hoare triple {91062#false} assume !(0 == ~E_1~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 15: Hoare triple {91062#false} assume !(0 == ~E_2~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 16: Hoare triple {91062#false} assume !(0 == ~E_3~0); {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 17: Hoare triple {91062#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {91062#false} is VALID [2022-02-21 04:22:06,963 INFO L290 TraceCheckUtils]: 18: Hoare triple {91062#false} assume !(1 == ~m_pc~0); {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 19: Hoare triple {91062#false} is_master_triggered_~__retres1~0#1 := 0; {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 20: Hoare triple {91062#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 21: Hoare triple {91062#false} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 22: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp~1#1); {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 23: Hoare triple {91062#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 24: Hoare triple {91062#false} assume !(1 == ~t1_pc~0); {91062#false} is VALID [2022-02-21 04:22:06,964 INFO L290 TraceCheckUtils]: 25: Hoare triple {91062#false} is_transmit1_triggered_~__retres1~1#1 := 0; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 26: Hoare triple {91062#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 27: Hoare triple {91062#false} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 28: Hoare triple {91062#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 29: Hoare triple {91062#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 30: Hoare triple {91062#false} assume !(1 == ~t2_pc~0); {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 31: Hoare triple {91062#false} is_transmit2_triggered_~__retres1~2#1 := 0; {91062#false} is VALID [2022-02-21 04:22:06,965 INFO L290 TraceCheckUtils]: 32: Hoare triple {91062#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 33: Hoare triple {91062#false} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 34: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___1~0#1); {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 35: Hoare triple {91062#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 36: Hoare triple {91062#false} assume !(1 == ~t3_pc~0); {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 37: Hoare triple {91062#false} is_transmit3_triggered_~__retres1~3#1 := 0; {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 38: Hoare triple {91062#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {91062#false} is VALID [2022-02-21 04:22:06,966 INFO L290 TraceCheckUtils]: 39: Hoare triple {91062#false} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 40: Hoare triple {91062#false} assume !(0 != activate_threads_~tmp___2~0#1); {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 41: Hoare triple {91062#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 42: Hoare triple {91062#false} assume !(1 == ~M_E~0); {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 43: Hoare triple {91062#false} assume !(1 == ~T1_E~0); {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 44: Hoare triple {91062#false} assume !(1 == ~T2_E~0); {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 45: Hoare triple {91062#false} assume !(1 == ~T3_E~0); {91062#false} is VALID [2022-02-21 04:22:06,967 INFO L290 TraceCheckUtils]: 46: Hoare triple {91062#false} assume !(1 == ~E_M~0); {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 47: Hoare triple {91062#false} assume !(1 == ~E_1~0); {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 48: Hoare triple {91062#false} assume !(1 == ~E_2~0); {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 49: Hoare triple {91062#false} assume !(1 == ~E_3~0); {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 50: Hoare triple {91062#false} assume { :end_inline_reset_delta_events } true; {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 51: Hoare triple {91062#false} assume !false; {91062#false} is VALID [2022-02-21 04:22:06,968 INFO L290 TraceCheckUtils]: 52: Hoare triple {91062#false} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {91062#false} is VALID [2022-02-21 04:22:06,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:06,969 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:06,969 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1766932771] [2022-02-21 04:22:06,969 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1766932771] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:06,969 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:06,969 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:06,970 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215630678] [2022-02-21 04:22:06,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:06,970 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:06,970 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:06,971 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 1 times [2022-02-21 04:22:06,971 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:06,971 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976131757] [2022-02-21 04:22:06,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:06,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:06,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:06,974 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:06,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:06,977 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:07,056 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:07,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:07,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:07,057 INFO L87 Difference]: Start difference. First operand 4647 states and 6446 transitions. cyclomatic complexity: 1802 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,899 INFO L93 Difference]: Finished difference Result 4598 states and 6377 transitions. [2022-02-21 04:22:07,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:07,899 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,937 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 53 edges. 53 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:07,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:08,405 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2022-02-21 04:22:08,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4598 states to 4598 states and 6377 transitions. [2022-02-21 04:22:08,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4598 [2022-02-21 04:22:08,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4598 [2022-02-21 04:22:08,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:08,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:08,918 INFO L681 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2022-02-21 04:22:08,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:08,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4598 to 4598. [2022-02-21 04:22:08,991 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:08,997 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4598 states and 6377 transitions. Second operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,003 INFO L74 IsIncluded]: Start isIncluded. First operand 4598 states and 6377 transitions. Second operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,008 INFO L87 Difference]: Start difference. First operand 4598 states and 6377 transitions. Second operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,453 INFO L93 Difference]: Finished difference Result 4598 states and 6377 transitions. [2022-02-21 04:22:09,453 INFO L276 IsEmpty]: Start isEmpty. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:09,457 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,457 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,461 INFO L74 IsIncluded]: Start isIncluded. First operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4598 states and 6377 transitions. [2022-02-21 04:22:09,465 INFO L87 Difference]: Start difference. First operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4598 states and 6377 transitions. [2022-02-21 04:22:09,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,918 INFO L93 Difference]: Finished difference Result 4598 states and 6377 transitions. [2022-02-21 04:22:09,918 INFO L276 IsEmpty]: Start isEmpty. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:09,922 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,922 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,922 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:09,922 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:09,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4598 states, 4598 states have (on average 1.3869073510221837) internal successors, (6377), 4597 states have internal predecessors, (6377), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4598 states to 4598 states and 6377 transitions. [2022-02-21 04:22:10,411 INFO L704 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2022-02-21 04:22:10,412 INFO L587 BuchiCegarLoop]: Abstraction has 4598 states and 6377 transitions. [2022-02-21 04:22:10,412 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:22:10,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4598 states and 6377 transitions. [2022-02-21 04:22:10,420 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4539 [2022-02-21 04:22:10,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:10,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:10,421 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,421 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,421 INFO L791 eck$LassoCheckResult]: Stem: 96043#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 95981#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 95982#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95987#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95861#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 95862#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95968#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95949#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95950#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95958#L429 assume !(0 == ~M_E~0); 95766#L429-2 assume !(0 == ~T1_E~0); 95767#L434-1 assume !(0 == ~T2_E~0); 95899#L439-1 assume !(0 == ~T3_E~0); 95928#L444-1 assume !(0 == ~E_M~0); 95929#L449-1 assume !(0 == ~E_1~0); 95772#L454-1 assume !(0 == ~E_2~0); 95773#L459-1 assume !(0 == ~E_3~0); 95731#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95732#L208 assume !(1 == ~m_pc~0); 96033#L208-2 is_master_triggered_~__retres1~0#1 := 0; 96034#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95804#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 95753#L531 assume !(0 != activate_threads_~tmp~1#1); 95754#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95871#L227 assume !(1 == ~t1_pc~0); 95751#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95752#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95959#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 95770#L539 assume !(0 != activate_threads_~tmp___0~0#1); 95771#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95805#L246 assume !(1 == ~t2_pc~0); 95806#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95903#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95904#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95966#L547 assume !(0 != activate_threads_~tmp___1~0#1); 95972#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95813#L265 assume !(1 == ~t3_pc~0); 95694#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95666#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95667#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95907#L555 assume !(0 != activate_threads_~tmp___2~0#1); 95782#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95783#L477 assume !(1 == ~M_E~0); 95965#L477-2 assume !(1 == ~T1_E~0); 95983#L482-1 assume !(1 == ~T2_E~0); 95923#L487-1 assume !(1 == ~T3_E~0); 95924#L492-1 assume !(1 == ~E_M~0); 95737#L497-1 assume !(1 == ~E_1~0); 95738#L502-1 assume !(1 == ~E_2~0); 95718#L507-1 assume !(1 == ~E_3~0); 95719#L512-1 assume { :end_inline_reset_delta_events } true; 95869#L678-2 assume !false; 97532#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97525#L404 [2022-02-21 04:22:10,421 INFO L793 eck$LassoCheckResult]: Loop: 97525#L404 assume !false; 97523#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 97520#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 97518#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 97517#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97515#L357 assume 0 != eval_~tmp~0#1; 97507#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 97501#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 97496#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 97044#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 97489#L376 assume !(0 == ~t2_st~0); 97531#L390 assume !(0 == ~t3_st~0); 97525#L404 [2022-02-21 04:22:10,421 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2022-02-21 04:22:10,421 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,422 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136846057] [2022-02-21 04:22:10,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:10,429 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:10,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:10,438 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:10,439 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,439 INFO L85 PathProgramCache]: Analyzing trace with hash -618385943, now seen corresponding path program 2 times [2022-02-21 04:22:10,439 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,439 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756275588] [2022-02-21 04:22:10,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:10,442 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:10,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:10,445 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:10,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,446 INFO L85 PathProgramCache]: Analyzing trace with hash 943838511, now seen corresponding path program 1 times [2022-02-21 04:22:10,446 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,446 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003081595] [2022-02-21 04:22:10,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,446 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,466 INFO L290 TraceCheckUtils]: 0: Hoare triple {109465#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {109465#true} is VALID [2022-02-21 04:22:10,466 INFO L290 TraceCheckUtils]: 1: Hoare triple {109465#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {109465#true} is VALID [2022-02-21 04:22:10,467 INFO L290 TraceCheckUtils]: 2: Hoare triple {109465#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {109465#true} is VALID [2022-02-21 04:22:10,467 INFO L290 TraceCheckUtils]: 3: Hoare triple {109465#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {109465#true} is VALID [2022-02-21 04:22:10,467 INFO L290 TraceCheckUtils]: 4: Hoare triple {109465#true} assume 1 == ~m_i~0;~m_st~0 := 0; {109465#true} is VALID [2022-02-21 04:22:10,467 INFO L290 TraceCheckUtils]: 5: Hoare triple {109465#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {109465#true} is VALID [2022-02-21 04:22:10,468 INFO L290 TraceCheckUtils]: 6: Hoare triple {109465#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,468 INFO L290 TraceCheckUtils]: 7: Hoare triple {109467#(= 0 ~t2_st~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,468 INFO L290 TraceCheckUtils]: 8: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,469 INFO L290 TraceCheckUtils]: 9: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~M_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,469 INFO L290 TraceCheckUtils]: 10: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~T1_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,469 INFO L290 TraceCheckUtils]: 11: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~T2_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,470 INFO L290 TraceCheckUtils]: 12: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~T3_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,470 INFO L290 TraceCheckUtils]: 13: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~E_M~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,470 INFO L290 TraceCheckUtils]: 14: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~E_1~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,471 INFO L290 TraceCheckUtils]: 15: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~E_2~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,471 INFO L290 TraceCheckUtils]: 16: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~E_3~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,472 INFO L290 TraceCheckUtils]: 17: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,472 INFO L290 TraceCheckUtils]: 18: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~m_pc~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,472 INFO L290 TraceCheckUtils]: 19: Hoare triple {109467#(= 0 ~t2_st~0)} is_master_triggered_~__retres1~0#1 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,473 INFO L290 TraceCheckUtils]: 20: Hoare triple {109467#(= 0 ~t2_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,473 INFO L290 TraceCheckUtils]: 21: Hoare triple {109467#(= 0 ~t2_st~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,473 INFO L290 TraceCheckUtils]: 22: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp~1#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,474 INFO L290 TraceCheckUtils]: 23: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,474 INFO L290 TraceCheckUtils]: 24: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~t1_pc~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,474 INFO L290 TraceCheckUtils]: 25: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,475 INFO L290 TraceCheckUtils]: 26: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,475 INFO L290 TraceCheckUtils]: 27: Hoare triple {109467#(= 0 ~t2_st~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,476 INFO L290 TraceCheckUtils]: 28: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,476 INFO L290 TraceCheckUtils]: 29: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,476 INFO L290 TraceCheckUtils]: 30: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~t2_pc~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,477 INFO L290 TraceCheckUtils]: 31: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,477 INFO L290 TraceCheckUtils]: 32: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,477 INFO L290 TraceCheckUtils]: 33: Hoare triple {109467#(= 0 ~t2_st~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,478 INFO L290 TraceCheckUtils]: 34: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,478 INFO L290 TraceCheckUtils]: 35: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,478 INFO L290 TraceCheckUtils]: 36: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~t3_pc~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,479 INFO L290 TraceCheckUtils]: 37: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,479 INFO L290 TraceCheckUtils]: 38: Hoare triple {109467#(= 0 ~t2_st~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,479 INFO L290 TraceCheckUtils]: 39: Hoare triple {109467#(= 0 ~t2_st~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,480 INFO L290 TraceCheckUtils]: 40: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != activate_threads_~tmp___2~0#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,480 INFO L290 TraceCheckUtils]: 41: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,481 INFO L290 TraceCheckUtils]: 42: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~M_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,481 INFO L290 TraceCheckUtils]: 43: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~T1_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,481 INFO L290 TraceCheckUtils]: 44: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~T2_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,482 INFO L290 TraceCheckUtils]: 45: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~T3_E~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,482 INFO L290 TraceCheckUtils]: 46: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~E_M~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,482 INFO L290 TraceCheckUtils]: 47: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~E_1~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,483 INFO L290 TraceCheckUtils]: 48: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~E_2~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,483 INFO L290 TraceCheckUtils]: 49: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(1 == ~E_3~0); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,483 INFO L290 TraceCheckUtils]: 50: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :end_inline_reset_delta_events } true; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,484 INFO L290 TraceCheckUtils]: 51: Hoare triple {109467#(= 0 ~t2_st~0)} assume !false; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,484 INFO L290 TraceCheckUtils]: 52: Hoare triple {109467#(= 0 ~t2_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,485 INFO L290 TraceCheckUtils]: 53: Hoare triple {109467#(= 0 ~t2_st~0)} assume !false; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,485 INFO L290 TraceCheckUtils]: 54: Hoare triple {109467#(= 0 ~t2_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,485 INFO L290 TraceCheckUtils]: 55: Hoare triple {109467#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,486 INFO L290 TraceCheckUtils]: 56: Hoare triple {109467#(= 0 ~t2_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,486 INFO L290 TraceCheckUtils]: 57: Hoare triple {109467#(= 0 ~t2_st~0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,486 INFO L290 TraceCheckUtils]: 58: Hoare triple {109467#(= 0 ~t2_st~0)} assume 0 != eval_~tmp~0#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,487 INFO L290 TraceCheckUtils]: 59: Hoare triple {109467#(= 0 ~t2_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,487 INFO L290 TraceCheckUtils]: 60: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,487 INFO L290 TraceCheckUtils]: 61: Hoare triple {109467#(= 0 ~t2_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,488 INFO L290 TraceCheckUtils]: 62: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {109467#(= 0 ~t2_st~0)} is VALID [2022-02-21 04:22:10,488 INFO L290 TraceCheckUtils]: 63: Hoare triple {109467#(= 0 ~t2_st~0)} assume !(0 == ~t2_st~0); {109466#false} is VALID [2022-02-21 04:22:10,488 INFO L290 TraceCheckUtils]: 64: Hoare triple {109466#false} assume !(0 == ~t3_st~0); {109466#false} is VALID [2022-02-21 04:22:10,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,489 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,489 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003081595] [2022-02-21 04:22:10,489 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003081595] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,489 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,489 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,489 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933005260] [2022-02-21 04:22:10,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,564 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:10,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:10,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:10,565 INFO L87 Difference]: Start difference. First operand 4598 states and 6377 transitions. cyclomatic complexity: 1782 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,602 INFO L93 Difference]: Finished difference Result 8299 states and 11428 transitions. [2022-02-21 04:22:12,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:12,603 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,652 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:12,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8299 states and 11428 transitions. [2022-02-21 04:22:14,212 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8236 [2022-02-21 04:22:15,685 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8299 states to 8299 states and 11428 transitions. [2022-02-21 04:22:15,685 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8299 [2022-02-21 04:22:15,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8299 [2022-02-21 04:22:15,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8299 states and 11428 transitions. [2022-02-21 04:22:15,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:15,691 INFO L681 BuchiCegarLoop]: Abstraction has 8299 states and 11428 transitions. [2022-02-21 04:22:15,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8299 states and 11428 transitions. [2022-02-21 04:22:15,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8299 to 8145. [2022-02-21 04:22:15,751 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:15,759 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8299 states and 11428 transitions. Second operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,767 INFO L74 IsIncluded]: Start isIncluded. First operand 8299 states and 11428 transitions. Second operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,773 INFO L87 Difference]: Start difference. First operand 8299 states and 11428 transitions. Second operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:17,189 INFO L93 Difference]: Finished difference Result 8299 states and 11428 transitions. [2022-02-21 04:22:17,189 INFO L276 IsEmpty]: Start isEmpty. Operand 8299 states and 11428 transitions. [2022-02-21 04:22:17,195 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:17,196 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:17,201 INFO L74 IsIncluded]: Start isIncluded. First operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8299 states and 11428 transitions. [2022-02-21 04:22:17,206 INFO L87 Difference]: Start difference. First operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8299 states and 11428 transitions. [2022-02-21 04:22:18,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,651 INFO L93 Difference]: Finished difference Result 8299 states and 11428 transitions. [2022-02-21 04:22:18,651 INFO L276 IsEmpty]: Start isEmpty. Operand 8299 states and 11428 transitions. [2022-02-21 04:22:18,657 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,657 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,657 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:18,657 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:18,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8145 states, 8145 states have (on average 1.3790055248618784) internal successors, (11232), 8144 states have internal predecessors, (11232), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:19,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8145 states to 8145 states and 11232 transitions. [2022-02-21 04:22:19,938 INFO L704 BuchiCegarLoop]: Abstraction has 8145 states and 11232 transitions. [2022-02-21 04:22:19,938 INFO L587 BuchiCegarLoop]: Abstraction has 8145 states and 11232 transitions. [2022-02-21 04:22:19,938 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:22:19,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8145 states and 11232 transitions. [2022-02-21 04:22:19,950 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8082 [2022-02-21 04:22:19,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:19,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:19,951 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:19,951 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:19,951 INFO L791 eck$LassoCheckResult]: Stem: 118169#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 118097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 118098#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118103#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117969#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 117970#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118086#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118066#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118067#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118074#L429 assume !(0 == ~M_E~0); 117868#L429-2 assume !(0 == ~T1_E~0); 117869#L434-1 assume !(0 == ~T2_E~0); 118009#L439-1 assume !(0 == ~T3_E~0); 118040#L444-1 assume !(0 == ~E_M~0); 118041#L449-1 assume !(0 == ~E_1~0); 117876#L454-1 assume !(0 == ~E_2~0); 117877#L459-1 assume !(0 == ~E_3~0); 117832#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 117833#L208 assume !(1 == ~m_pc~0); 118157#L208-2 is_master_triggered_~__retres1~0#1 := 0; 118158#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117906#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 117854#L531 assume !(0 != activate_threads_~tmp~1#1); 117855#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117978#L227 assume !(1 == ~t1_pc~0); 117852#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117853#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118075#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 117872#L539 assume !(0 != activate_threads_~tmp___0~0#1); 117873#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117907#L246 assume !(1 == ~t2_pc~0); 117908#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118013#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118014#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118083#L547 assume !(0 != activate_threads_~tmp___1~0#1); 118090#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 117918#L265 assume !(1 == ~t3_pc~0); 117796#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 117769#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 117770#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118018#L555 assume !(0 != activate_threads_~tmp___2~0#1); 117889#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117890#L477 assume !(1 == ~M_E~0); 118081#L477-2 assume !(1 == ~T1_E~0); 118099#L482-1 assume !(1 == ~T2_E~0); 118038#L487-1 assume !(1 == ~T3_E~0); 118039#L492-1 assume !(1 == ~E_M~0); 117838#L497-1 assume !(1 == ~E_1~0); 117839#L502-1 assume !(1 == ~E_2~0); 117822#L507-1 assume !(1 == ~E_3~0); 117823#L512-1 assume { :end_inline_reset_delta_events } true; 117974#L678-2 assume !false; 120584#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 120542#L404 [2022-02-21 04:22:19,951 INFO L793 eck$LassoCheckResult]: Loop: 120542#L404 assume !false; 120534#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 120527#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 120518#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 120510#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 120505#L357 assume 0 != eval_~tmp~0#1; 120362#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 120359#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 120329#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 120330#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 120176#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 120051#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 120053#L390 assume !(0 == ~t3_st~0); 120542#L404 [2022-02-21 04:22:19,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:19,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2022-02-21 04:22:19,952 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:19,952 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281164674] [2022-02-21 04:22:19,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:19,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:19,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:19,960 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:19,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:19,971 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:19,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:19,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1990224393, now seen corresponding path program 1 times [2022-02-21 04:22:19,972 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:19,972 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999313929] [2022-02-21 04:22:19,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:19,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:19,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:19,975 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:19,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:19,978 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:19,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:19,979 INFO L85 PathProgramCache]: Analyzing trace with hash -805906575, now seen corresponding path program 1 times [2022-02-21 04:22:19,979 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:19,979 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678409142] [2022-02-21 04:22:19,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:19,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:19,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:20,019 INFO L290 TraceCheckUtils]: 0: Hoare triple {142517#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 1: Hoare triple {142517#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 2: Hoare triple {142517#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 3: Hoare triple {142517#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 4: Hoare triple {142517#true} assume 1 == ~m_i~0;~m_st~0 := 0; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 5: Hoare triple {142517#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {142517#true} is VALID [2022-02-21 04:22:20,020 INFO L290 TraceCheckUtils]: 6: Hoare triple {142517#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {142517#true} is VALID [2022-02-21 04:22:20,021 INFO L290 TraceCheckUtils]: 7: Hoare triple {142517#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,021 INFO L290 TraceCheckUtils]: 8: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,022 INFO L290 TraceCheckUtils]: 9: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~M_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,022 INFO L290 TraceCheckUtils]: 10: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~T1_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,023 INFO L290 TraceCheckUtils]: 11: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~T2_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,023 INFO L290 TraceCheckUtils]: 12: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~T3_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,023 INFO L290 TraceCheckUtils]: 13: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~E_M~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,024 INFO L290 TraceCheckUtils]: 14: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~E_1~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,024 INFO L290 TraceCheckUtils]: 15: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~E_2~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,025 INFO L290 TraceCheckUtils]: 16: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~E_3~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,025 INFO L290 TraceCheckUtils]: 17: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,025 INFO L290 TraceCheckUtils]: 18: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~m_pc~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,026 INFO L290 TraceCheckUtils]: 19: Hoare triple {142519#(= 0 ~t3_st~0)} is_master_triggered_~__retres1~0#1 := 0; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,026 INFO L290 TraceCheckUtils]: 20: Hoare triple {142519#(= 0 ~t3_st~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,026 INFO L290 TraceCheckUtils]: 21: Hoare triple {142519#(= 0 ~t3_st~0)} activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,027 INFO L290 TraceCheckUtils]: 22: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp~1#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,027 INFO L290 TraceCheckUtils]: 23: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,028 INFO L290 TraceCheckUtils]: 24: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~t1_pc~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,028 INFO L290 TraceCheckUtils]: 25: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,028 INFO L290 TraceCheckUtils]: 26: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,029 INFO L290 TraceCheckUtils]: 27: Hoare triple {142519#(= 0 ~t3_st~0)} activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,029 INFO L290 TraceCheckUtils]: 28: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___0~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,030 INFO L290 TraceCheckUtils]: 29: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,030 INFO L290 TraceCheckUtils]: 30: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~t2_pc~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,030 INFO L290 TraceCheckUtils]: 31: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,031 INFO L290 TraceCheckUtils]: 32: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,031 INFO L290 TraceCheckUtils]: 33: Hoare triple {142519#(= 0 ~t3_st~0)} activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,032 INFO L290 TraceCheckUtils]: 34: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___1~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,032 INFO L290 TraceCheckUtils]: 35: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,032 INFO L290 TraceCheckUtils]: 36: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~t3_pc~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,033 INFO L290 TraceCheckUtils]: 37: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,033 INFO L290 TraceCheckUtils]: 38: Hoare triple {142519#(= 0 ~t3_st~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,034 INFO L290 TraceCheckUtils]: 39: Hoare triple {142519#(= 0 ~t3_st~0)} activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,034 INFO L290 TraceCheckUtils]: 40: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != activate_threads_~tmp___2~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,034 INFO L290 TraceCheckUtils]: 41: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,035 INFO L290 TraceCheckUtils]: 42: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~M_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,035 INFO L290 TraceCheckUtils]: 43: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~T1_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,036 INFO L290 TraceCheckUtils]: 44: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~T2_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,036 INFO L290 TraceCheckUtils]: 45: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~T3_E~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,036 INFO L290 TraceCheckUtils]: 46: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~E_M~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,037 INFO L290 TraceCheckUtils]: 47: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~E_1~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,037 INFO L290 TraceCheckUtils]: 48: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~E_2~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,037 INFO L290 TraceCheckUtils]: 49: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(1 == ~E_3~0); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,038 INFO L290 TraceCheckUtils]: 50: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :end_inline_reset_delta_events } true; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,038 INFO L290 TraceCheckUtils]: 51: Hoare triple {142519#(= 0 ~t3_st~0)} assume !false; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,039 INFO L290 TraceCheckUtils]: 52: Hoare triple {142519#(= 0 ~t3_st~0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,039 INFO L290 TraceCheckUtils]: 53: Hoare triple {142519#(= 0 ~t3_st~0)} assume !false; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,039 INFO L290 TraceCheckUtils]: 54: Hoare triple {142519#(= 0 ~t3_st~0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,040 INFO L290 TraceCheckUtils]: 55: Hoare triple {142519#(= 0 ~t3_st~0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,040 INFO L290 TraceCheckUtils]: 56: Hoare triple {142519#(= 0 ~t3_st~0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,041 INFO L290 TraceCheckUtils]: 57: Hoare triple {142519#(= 0 ~t3_st~0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,041 INFO L290 TraceCheckUtils]: 58: Hoare triple {142519#(= 0 ~t3_st~0)} assume 0 != eval_~tmp~0#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,041 INFO L290 TraceCheckUtils]: 59: Hoare triple {142519#(= 0 ~t3_st~0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,042 INFO L290 TraceCheckUtils]: 60: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_1~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,042 INFO L290 TraceCheckUtils]: 61: Hoare triple {142519#(= 0 ~t3_st~0)} assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,043 INFO L290 TraceCheckUtils]: 62: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_2~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,043 INFO L290 TraceCheckUtils]: 63: Hoare triple {142519#(= 0 ~t3_st~0)} assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,043 INFO L290 TraceCheckUtils]: 64: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 != eval_~tmp_ndt_3~0#1); {142519#(= 0 ~t3_st~0)} is VALID [2022-02-21 04:22:20,044 INFO L290 TraceCheckUtils]: 65: Hoare triple {142519#(= 0 ~t3_st~0)} assume !(0 == ~t3_st~0); {142518#false} is VALID [2022-02-21 04:22:20,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:20,044 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:20,044 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678409142] [2022-02-21 04:22:20,045 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678409142] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:20,045 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:20,045 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:20,045 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [706950424] [2022-02-21 04:22:20,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:20,137 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:20,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:20,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:20,138 INFO L87 Difference]: Start difference. First operand 8145 states and 11232 transitions. cyclomatic complexity: 3090 Second operand has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:24,825 INFO L93 Difference]: Finished difference Result 13631 states and 18694 transitions. [2022-02-21 04:22:24,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:24,825 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 2 states have (on average 33.0) internal successors, (66), 3 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,876 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 66 edges. 66 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:24,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13631 states and 18694 transitions. [2022-02-21 04:22:28,738 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13560 [2022-02-21 04:22:32,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13631 states to 13631 states and 18694 transitions. [2022-02-21 04:22:32,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13631 [2022-02-21 04:22:32,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13631 [2022-02-21 04:22:32,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13631 states and 18694 transitions. [2022-02-21 04:22:32,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:32,641 INFO L681 BuchiCegarLoop]: Abstraction has 13631 states and 18694 transitions. [2022-02-21 04:22:32,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13631 states and 18694 transitions. [2022-02-21 04:22:32,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13631 to 13407. [2022-02-21 04:22:32,759 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:32,774 INFO L82 GeneralOperation]: Start isEquivalent. First operand 13631 states and 18694 transitions. Second operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:32,790 INFO L74 IsIncluded]: Start isIncluded. First operand 13631 states and 18694 transitions. Second operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:32,806 INFO L87 Difference]: Start difference. First operand 13631 states and 18694 transitions. Second operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:36,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:36,605 INFO L93 Difference]: Finished difference Result 13631 states and 18694 transitions. [2022-02-21 04:22:36,605 INFO L276 IsEmpty]: Start isEmpty. Operand 13631 states and 18694 transitions. [2022-02-21 04:22:36,615 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:36,615 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:36,626 INFO L74 IsIncluded]: Start isIncluded. First operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 13631 states and 18694 transitions. [2022-02-21 04:22:36,637 INFO L87 Difference]: Start difference. First operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 13631 states and 18694 transitions. [2022-02-21 04:22:40,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:40,270 INFO L93 Difference]: Finished difference Result 13631 states and 18694 transitions. [2022-02-21 04:22:40,270 INFO L276 IsEmpty]: Start isEmpty. Operand 13631 states and 18694 transitions. [2022-02-21 04:22:40,278 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:40,278 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:40,278 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:40,278 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:40,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13407 states, 13407 states have (on average 1.3776385470276722) internal successors, (18470), 13406 states have internal predecessors, (18470), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:44,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13407 states to 13407 states and 18470 transitions. [2022-02-21 04:22:44,131 INFO L704 BuchiCegarLoop]: Abstraction has 13407 states and 18470 transitions. [2022-02-21 04:22:44,131 INFO L587 BuchiCegarLoop]: Abstraction has 13407 states and 18470 transitions. [2022-02-21 04:22:44,131 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:22:44,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13407 states and 18470 transitions. [2022-02-21 04:22:44,151 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13336 [2022-02-21 04:22:44,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:44,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:44,152 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:44,152 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:44,152 INFO L791 eck$LassoCheckResult]: Stem: 156540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 156477#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 156478#L641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 156483#L285 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 156351#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 156352#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 156464#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156446#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156447#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 156455#L429 assume !(0 == ~M_E~0); 156255#L429-2 assume !(0 == ~T1_E~0); 156256#L434-1 assume !(0 == ~T2_E~0); 156392#L439-1 assume !(0 == ~T3_E~0); 156420#L444-1 assume !(0 == ~E_M~0); 156421#L449-1 assume !(0 == ~E_1~0); 156261#L454-1 assume !(0 == ~E_2~0); 156262#L459-1 assume !(0 == ~E_3~0); 156220#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156221#L208 assume !(1 == ~m_pc~0); 156529#L208-2 is_master_triggered_~__retres1~0#1 := 0; 156530#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156292#L220 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 156241#L531 assume !(0 != activate_threads_~tmp~1#1); 156242#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156361#L227 assume !(1 == ~t1_pc~0); 156239#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 156240#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 156456#L239 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 156259#L539 assume !(0 != activate_threads_~tmp___0~0#1); 156260#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156293#L246 assume !(1 == ~t2_pc~0); 156294#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 156398#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156399#L258 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 156462#L547 assume !(0 != activate_threads_~tmp___1~0#1); 156469#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156301#L265 assume !(1 == ~t3_pc~0); 156182#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 156153#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 156154#L277 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156401#L555 assume !(0 != activate_threads_~tmp___2~0#1); 156271#L555-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156272#L477 assume !(1 == ~M_E~0); 156461#L477-2 assume !(1 == ~T1_E~0); 156479#L482-1 assume !(1 == ~T2_E~0); 156415#L487-1 assume !(1 == ~T3_E~0); 156416#L492-1 assume !(1 == ~E_M~0); 156225#L497-1 assume !(1 == ~E_1~0); 156226#L502-1 assume !(1 == ~E_2~0); 156206#L507-1 assume !(1 == ~E_3~0); 156207#L512-1 assume { :end_inline_reset_delta_events } true; 156359#L678-2 assume !false; 160089#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 160086#L404 [2022-02-21 04:22:44,152 INFO L793 eck$LassoCheckResult]: Loop: 160086#L404 assume !false; 160084#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 160081#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 160080#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 160058#L343 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 160057#L357 assume 0 != eval_~tmp~0#1; 160053#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 160048#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 160049#L362 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 160493#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 160126#L376 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 160106#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 160107#L390 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 160087#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 160086#L404 [2022-02-21 04:22:44,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2022-02-21 04:22:44,153 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,153 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068944225] [2022-02-21 04:22:44,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,173 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:44,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,187 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:44,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,195 INFO L85 PathProgramCache]: Analyzing trace with hash -1567417278, now seen corresponding path program 1 times [2022-02-21 04:22:44,196 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,196 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460505850] [2022-02-21 04:22:44,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,200 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:44,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,203 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:44,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,205 INFO L85 PathProgramCache]: Analyzing trace with hash 786696712, now seen corresponding path program 1 times [2022-02-21 04:22:44,205 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,205 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046120008] [2022-02-21 04:22:44,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,214 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:44,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,227 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:45,196 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 21.02 04:22:45 BoogieIcfgContainer [2022-02-21 04:22:45,196 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2022-02-21 04:22:45,196 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-02-21 04:22:45,196 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-02-21 04:22:45,196 INFO L275 PluginConnector]: Witness Printer initialized [2022-02-21 04:22:45,197 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:45" (3/4) ... [2022-02-21 04:22:45,199 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2022-02-21 04:22:45,234 INFO L141 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2022-02-21 04:22:45,234 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-02-21 04:22:45,236 INFO L158 Benchmark]: Toolchain (without parser) took 60936.80ms. Allocated memory was 107.0MB in the beginning and 272.6MB in the end (delta: 165.7MB). Free memory was 75.7MB in the beginning and 114.1MB in the end (delta: -38.4MB). Peak memory consumption was 126.7MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,236 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 83.9MB. Free memory was 39.0MB in the beginning and 39.0MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-02-21 04:22:45,236 INFO L158 Benchmark]: CACSL2BoogieTranslator took 318.84ms. Allocated memory is still 107.0MB. Free memory was 75.7MB in the beginning and 77.4MB in the end (delta: -1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,236 INFO L158 Benchmark]: Boogie Procedure Inliner took 70.59ms. Allocated memory is still 107.0MB. Free memory was 77.4MB in the beginning and 72.8MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,237 INFO L158 Benchmark]: Boogie Preprocessor took 55.64ms. Allocated memory is still 107.0MB. Free memory was 72.8MB in the beginning and 69.5MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,237 INFO L158 Benchmark]: RCFGBuilder took 966.51ms. Allocated memory is still 107.0MB. Free memory was 69.5MB in the beginning and 61.9MB in the end (delta: 7.6MB). Peak memory consumption was 22.2MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,237 INFO L158 Benchmark]: BuchiAutomizer took 59477.79ms. Allocated memory was 107.0MB in the beginning and 272.6MB in the end (delta: 165.7MB). Free memory was 61.4MB in the beginning and 118.3MB in the end (delta: -56.9MB). Peak memory consumption was 159.6MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,238 INFO L158 Benchmark]: Witness Printer took 38.33ms. Allocated memory is still 272.6MB. Free memory was 118.3MB in the beginning and 114.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-02-21 04:22:45,239 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 83.9MB. Free memory was 39.0MB in the beginning and 39.0MB in the end (delta: 83.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 318.84ms. Allocated memory is still 107.0MB. Free memory was 75.7MB in the beginning and 77.4MB in the end (delta: -1.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 70.59ms. Allocated memory is still 107.0MB. Free memory was 77.4MB in the beginning and 72.8MB in the end (delta: 4.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 55.64ms. Allocated memory is still 107.0MB. Free memory was 72.8MB in the beginning and 69.5MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 966.51ms. Allocated memory is still 107.0MB. Free memory was 69.5MB in the beginning and 61.9MB in the end (delta: 7.6MB). Peak memory consumption was 22.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 59477.79ms. Allocated memory was 107.0MB in the beginning and 272.6MB in the end (delta: 165.7MB). Free memory was 61.4MB in the beginning and 118.3MB in the end (delta: -56.9MB). Peak memory consumption was 159.6MB. Max. memory is 16.1GB. * Witness Printer took 38.33ms. Allocated memory is still 272.6MB. Free memory was 118.3MB in the beginning and 114.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (15 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13407 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 59.4s and 16 iterations. TraceHistogramMax:1. Analysis of lassos took 3.2s. Construction of modules took 0.3s. Büchi inclusion checks took 17.2s. Highest rank in rank-based complementation 0. Minimization of det autom 15. Minimization of nondet autom 0. Automata minimization 22.7s AutomataMinimizationTime, 15 MinimizatonAttempts, 5665 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 15.4s Buchi closure took 0.0s. Biggest automaton had 13407 states and ocurred in iteration 15. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9253 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9253 mSDsluCounter, 14655 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7271 mSDsCounter, 152 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 351 IncrementalHoareTripleChecker+Invalid, 503 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 152 mSolverCounterUnsat, 7384 mSDtfsCounter, 351 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc3 concLT0 SILN1 SILU0 SILI8 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=1} State at position 1 is {tmp_ndt_3=0, NULL=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4b6d4e73=0, token=0, NULL=1, tmp=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70148424=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49bba55e=0, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@450a72dd=0, tmp_ndt_2=0, E_3=2, E_1=2, tmp_ndt_1=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4942aa8b=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@493a0a6c=0, m_st=0, NULL=0, t3_pc=0, __retres1=0, tmp___0=0, tmp___2=0, m_pc=0, \result=0, \result=1, \result=0, \result=0, tmp___1=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@741ea836=0, tmp=0, t1_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44a6b25=0, E_2=2, tmp___0=0, T1_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44507974=0, __retres1=0, M_E=2, __retres1=1, t2_i=1, \result=0, t3_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5dffbdfc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32572f84=0, t1_st=0, __retres1=0, local=0, t2_pc=0, __retres1=0, tmp_ndt_4=0, E_M=2, kernel_st=1, T3_E=2, t1_i=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) [L434] COND FALSE !(T1_E == 0) [L439] COND FALSE !(T2_E == 0) [L444] COND FALSE !(T3_E == 0) [L449] COND FALSE !(E_M == 0) [L454] COND FALSE !(E_1 == 0) [L459] COND FALSE !(E_2 == 0) [L464] COND FALSE !(E_3 == 0) [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; [L208] COND FALSE !(m_pc == 1) [L218] __retres1 = 0 [L220] return (__retres1); [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; [L227] COND FALSE !(t1_pc == 1) [L237] __retres1 = 0 [L239] return (__retres1); [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; [L246] COND FALSE !(t2_pc == 1) [L256] __retres1 = 0 [L258] return (__retres1); [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; [L265] COND FALSE !(t3_pc == 1) [L275] __retres1 = 0 [L277] return (__retres1); [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) [L482] COND FALSE !(T1_E == 1) [L487] COND FALSE !(T2_E == 1) [L492] COND FALSE !(T3_E == 1) [L497] COND FALSE !(E_M == 1) [L502] COND FALSE !(E_1 == 1) [L507] COND FALSE !(E_2 == 1) [L512] COND FALSE !(E_3 == 1) [L675] RET reset_delta_events() [L678] COND TRUE 1 [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE !(\read(tmp_ndt_1)) [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE !(\read(tmp_ndt_2)) [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE !(\read(tmp_ndt_3)) [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2022-02-21 04:22:45,277 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)