./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:44,433 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:44,435 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:44,479 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:44,479 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:44,482 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:44,484 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:44,486 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:44,490 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:44,494 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:44,495 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:44,496 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:44,497 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:44,499 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:44,500 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:44,503 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:44,504 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:44,505 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:44,507 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:44,512 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:44,513 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:44,514 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:44,515 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:44,516 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:44,522 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:44,522 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:44,523 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:44,524 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:44,525 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:44,525 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:44,526 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:44,527 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:44,528 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:44,529 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:44,530 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:44,530 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:44,531 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:44,531 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:44,532 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:44,533 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:44,534 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:44,535 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:44,555 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:44,556 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:44,556 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:44,557 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:44,558 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:44,558 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:44,558 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:44,558 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:44,559 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:44,559 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:44,559 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:44,560 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:44,560 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:44,560 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:44,560 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:44,560 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:44,561 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:44,561 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:44,561 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:44,561 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:44,561 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:44,562 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:44,562 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:44,562 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:44,562 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:44,562 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:44,563 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:44,563 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:44,563 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:44,563 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:44,564 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:44,564 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:44,565 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2022-02-21 04:21:44,781 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:44,803 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:44,805 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:44,806 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:44,807 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:44,808 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-02-21 04:21:44,868 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/29c051ea7/0d6969141147412e8a2cefe0a32a3319/FLAG5ac3cd2ed [2022-02-21 04:21:45,259 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:45,259 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2022-02-21 04:21:45,272 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/29c051ea7/0d6969141147412e8a2cefe0a32a3319/FLAG5ac3cd2ed [2022-02-21 04:21:45,283 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/29c051ea7/0d6969141147412e8a2cefe0a32a3319 [2022-02-21 04:21:45,285 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:45,287 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:45,290 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:45,290 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:45,292 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:45,293 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,295 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7e14c4f4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45, skipping insertion in model container [2022-02-21 04:21:45,295 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,300 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:45,330 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:45,453 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-02-21 04:21:45,516 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:45,525 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:45,534 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c[671,684] [2022-02-21 04:21:45,574 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:45,594 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:45,594 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45 WrapperNode [2022-02-21 04:21:45,594 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:45,601 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:45,601 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:45,601 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:45,607 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,624 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,714 INFO L137 Inliner]: procedures = 36, calls = 43, calls flagged for inlining = 38, calls inlined = 77, statements flattened = 1062 [2022-02-21 04:21:45,716 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:45,717 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:45,718 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:45,718 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:45,724 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,724 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,736 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,738 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,755 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,767 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,769 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,790 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:45,791 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:45,791 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:45,791 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:45,805 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (1/1) ... [2022-02-21 04:21:45,811 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:45,823 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:45,836 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:45,863 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:45,881 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:45,881 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:45,881 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:45,881 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:46,009 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:46,011 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:46,790 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:46,800 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:46,800 INFO L299 CfgBuilder]: Removed 7 assume(true) statements. [2022-02-21 04:21:46,802 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:46 BoogieIcfgContainer [2022-02-21 04:21:46,803 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:46,807 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:46,807 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:46,810 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:46,811 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:46,811 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:45" (1/3) ... [2022-02-21 04:21:46,811 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c88d9cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:46, skipping insertion in model container [2022-02-21 04:21:46,811 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:46,812 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:45" (2/3) ... [2022-02-21 04:21:46,812 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6c88d9cd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:46, skipping insertion in model container [2022-02-21 04:21:46,812 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:46,812 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:46" (3/3) ... [2022-02-21 04:21:46,813 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2022-02-21 04:21:46,864 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:46,865 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:46,865 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:46,865 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:46,865 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:46,865 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:46,866 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:46,866 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:46,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-02-21 04:21:47,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:47,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:47,027 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,027 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,027 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:47,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 360 [2022-02-21 04:21:47,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:47,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:47,085 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,085 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:47,092 INFO L791 eck$LassoCheckResult]: Stem: 425#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 219#L766true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 45#L346true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 298#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 368#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 48#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 411#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 123#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65#L514true assume !(0 == ~M_E~0); 382#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 327#L519-1true assume !(0 == ~T2_E~0); 40#L524-1true assume !(0 == ~T3_E~0); 106#L529-1true assume !(0 == ~T4_E~0); 330#L534-1true assume !(0 == ~E_M~0); 267#L539-1true assume !(0 == ~E_1~0); 296#L544-1true assume !(0 == ~E_2~0); 297#L549-1true assume !(0 == ~E_3~0); 335#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 38#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 328#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#L262true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 300#L637true assume !(0 != activate_threads_~tmp~1#1); 41#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56#L269true assume !(1 == ~t1_pc~0); 103#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 181#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 120#L281true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 329#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238#L288true assume 1 == ~t2_pc~0; 359#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 251#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157#L300true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 260#L653true assume !(0 != activate_threads_~tmp___1~0#1); 313#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164#L307true assume !(1 == ~t3_pc~0); 226#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 210#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 432#L319true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308#L661true assume !(0 != activate_threads_~tmp___2~0#1); 130#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 352#L326true assume 1 == ~t4_pc~0; 345#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 162#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 266#L338true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 309#L669true assume !(0 != activate_threads_~tmp___3~0#1); 264#L669-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 304#L572true assume !(1 == ~M_E~0); 346#L572-2true assume !(1 == ~T1_E~0); 46#L577-1true assume !(1 == ~T2_E~0); 247#L582-1true assume !(1 == ~T3_E~0); 254#L587-1true assume !(1 == ~T4_E~0); 372#L592-1true assume !(1 == ~E_M~0); 14#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 412#L602-1true assume !(1 == ~E_2~0); 141#L607-1true assume !(1 == ~E_3~0); 416#L612-1true assume !(1 == ~E_4~0); 105#L617-1true assume { :end_inline_reset_delta_events } true; 430#L803-2true [2022-02-21 04:21:47,099 INFO L793 eck$LassoCheckResult]: Loop: 430#L803-2true assume !false; 220#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 201#L489true assume !true; 389#L504true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232#L346-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198#L514-3true assume 0 == ~M_E~0;~M_E~0 := 1; 153#L514-5true assume !(0 == ~T1_E~0); 318#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 244#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 173#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 9#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 333#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 400#L549-3true assume 0 == ~E_3~0;~E_3~0 := 1; 119#L554-3true assume !(0 == ~E_4~0); 194#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274#L250-18true assume 1 == ~m_pc~0; 231#L251-6true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 208#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#L262-6true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32#L269-18true assume !(1 == ~t1_pc~0); 353#L269-20true is_transmit1_triggered_~__retres1~1#1 := 0; 72#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102#L281-6true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 185#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 13#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62#L300-6true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316#L307-18true assume !(1 == ~t3_pc~0); 81#L307-20true is_transmit3_triggered_~__retres1~3#1 := 0; 122#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 125#L319-6true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 85#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 275#L326-18true assume !(1 == ~t4_pc~0); 361#L326-20true is_transmit4_triggered_~__retres1~4#1 := 0; 286#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 246#L338-6true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 369#L669-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 94#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 111#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 37#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 371#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 193#L592-3true assume 1 == ~E_M~0;~E_M~0 := 2; 252#L597-3true assume !(1 == ~E_1~0); 134#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 324#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 196#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 128#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 373#L414-1true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 163#L822true assume !(0 == start_simulation_~tmp~3#1); 271#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 405#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165#L414-2true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 24#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 203#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 213#L785true start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 317#L835true assume !(0 != start_simulation_~tmp___0~1#1); 430#L803-2true [2022-02-21 04:21:47,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2022-02-21 04:21:47,115 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,116 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1978113777] [2022-02-21 04:21:47,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,314 INFO L290 TraceCheckUtils]: 0: Hoare triple {435#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {435#true} is VALID [2022-02-21 04:21:47,316 INFO L290 TraceCheckUtils]: 1: Hoare triple {435#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {437#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:47,316 INFO L290 TraceCheckUtils]: 2: Hoare triple {437#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {437#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:47,317 INFO L290 TraceCheckUtils]: 3: Hoare triple {437#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {437#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:47,317 INFO L290 TraceCheckUtils]: 4: Hoare triple {437#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {436#false} is VALID [2022-02-21 04:21:47,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {436#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {436#false} is VALID [2022-02-21 04:21:47,318 INFO L290 TraceCheckUtils]: 6: Hoare triple {436#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {436#false} is VALID [2022-02-21 04:21:47,318 INFO L290 TraceCheckUtils]: 7: Hoare triple {436#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {436#false} is VALID [2022-02-21 04:21:47,318 INFO L290 TraceCheckUtils]: 8: Hoare triple {436#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {436#false} is VALID [2022-02-21 04:21:47,318 INFO L290 TraceCheckUtils]: 9: Hoare triple {436#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {436#false} is VALID [2022-02-21 04:21:47,319 INFO L290 TraceCheckUtils]: 10: Hoare triple {436#false} assume !(0 == ~M_E~0); {436#false} is VALID [2022-02-21 04:21:47,319 INFO L290 TraceCheckUtils]: 11: Hoare triple {436#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {436#false} is VALID [2022-02-21 04:21:47,319 INFO L290 TraceCheckUtils]: 12: Hoare triple {436#false} assume !(0 == ~T2_E~0); {436#false} is VALID [2022-02-21 04:21:47,319 INFO L290 TraceCheckUtils]: 13: Hoare triple {436#false} assume !(0 == ~T3_E~0); {436#false} is VALID [2022-02-21 04:21:47,319 INFO L290 TraceCheckUtils]: 14: Hoare triple {436#false} assume !(0 == ~T4_E~0); {436#false} is VALID [2022-02-21 04:21:47,320 INFO L290 TraceCheckUtils]: 15: Hoare triple {436#false} assume !(0 == ~E_M~0); {436#false} is VALID [2022-02-21 04:21:47,320 INFO L290 TraceCheckUtils]: 16: Hoare triple {436#false} assume !(0 == ~E_1~0); {436#false} is VALID [2022-02-21 04:21:47,320 INFO L290 TraceCheckUtils]: 17: Hoare triple {436#false} assume !(0 == ~E_2~0); {436#false} is VALID [2022-02-21 04:21:47,320 INFO L290 TraceCheckUtils]: 18: Hoare triple {436#false} assume !(0 == ~E_3~0); {436#false} is VALID [2022-02-21 04:21:47,320 INFO L290 TraceCheckUtils]: 19: Hoare triple {436#false} assume 0 == ~E_4~0;~E_4~0 := 1; {436#false} is VALID [2022-02-21 04:21:47,321 INFO L290 TraceCheckUtils]: 20: Hoare triple {436#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {436#false} is VALID [2022-02-21 04:21:47,321 INFO L290 TraceCheckUtils]: 21: Hoare triple {436#false} assume 1 == ~m_pc~0; {436#false} is VALID [2022-02-21 04:21:47,321 INFO L290 TraceCheckUtils]: 22: Hoare triple {436#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {436#false} is VALID [2022-02-21 04:21:47,321 INFO L290 TraceCheckUtils]: 23: Hoare triple {436#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {436#false} is VALID [2022-02-21 04:21:47,322 INFO L290 TraceCheckUtils]: 24: Hoare triple {436#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {436#false} is VALID [2022-02-21 04:21:47,322 INFO L290 TraceCheckUtils]: 25: Hoare triple {436#false} assume !(0 != activate_threads_~tmp~1#1); {436#false} is VALID [2022-02-21 04:21:47,322 INFO L290 TraceCheckUtils]: 26: Hoare triple {436#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {436#false} is VALID [2022-02-21 04:21:47,322 INFO L290 TraceCheckUtils]: 27: Hoare triple {436#false} assume !(1 == ~t1_pc~0); {436#false} is VALID [2022-02-21 04:21:47,323 INFO L290 TraceCheckUtils]: 28: Hoare triple {436#false} is_transmit1_triggered_~__retres1~1#1 := 0; {436#false} is VALID [2022-02-21 04:21:47,323 INFO L290 TraceCheckUtils]: 29: Hoare triple {436#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {436#false} is VALID [2022-02-21 04:21:47,323 INFO L290 TraceCheckUtils]: 30: Hoare triple {436#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {436#false} is VALID [2022-02-21 04:21:47,323 INFO L290 TraceCheckUtils]: 31: Hoare triple {436#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {436#false} is VALID [2022-02-21 04:21:47,323 INFO L290 TraceCheckUtils]: 32: Hoare triple {436#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {436#false} is VALID [2022-02-21 04:21:47,324 INFO L290 TraceCheckUtils]: 33: Hoare triple {436#false} assume 1 == ~t2_pc~0; {436#false} is VALID [2022-02-21 04:21:47,324 INFO L290 TraceCheckUtils]: 34: Hoare triple {436#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {436#false} is VALID [2022-02-21 04:21:47,324 INFO L290 TraceCheckUtils]: 35: Hoare triple {436#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {436#false} is VALID [2022-02-21 04:21:47,324 INFO L290 TraceCheckUtils]: 36: Hoare triple {436#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {436#false} is VALID [2022-02-21 04:21:47,325 INFO L290 TraceCheckUtils]: 37: Hoare triple {436#false} assume !(0 != activate_threads_~tmp___1~0#1); {436#false} is VALID [2022-02-21 04:21:47,325 INFO L290 TraceCheckUtils]: 38: Hoare triple {436#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {436#false} is VALID [2022-02-21 04:21:47,325 INFO L290 TraceCheckUtils]: 39: Hoare triple {436#false} assume !(1 == ~t3_pc~0); {436#false} is VALID [2022-02-21 04:21:47,325 INFO L290 TraceCheckUtils]: 40: Hoare triple {436#false} is_transmit3_triggered_~__retres1~3#1 := 0; {436#false} is VALID [2022-02-21 04:21:47,325 INFO L290 TraceCheckUtils]: 41: Hoare triple {436#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {436#false} is VALID [2022-02-21 04:21:47,326 INFO L290 TraceCheckUtils]: 42: Hoare triple {436#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {436#false} is VALID [2022-02-21 04:21:47,326 INFO L290 TraceCheckUtils]: 43: Hoare triple {436#false} assume !(0 != activate_threads_~tmp___2~0#1); {436#false} is VALID [2022-02-21 04:21:47,326 INFO L290 TraceCheckUtils]: 44: Hoare triple {436#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {436#false} is VALID [2022-02-21 04:21:47,326 INFO L290 TraceCheckUtils]: 45: Hoare triple {436#false} assume 1 == ~t4_pc~0; {436#false} is VALID [2022-02-21 04:21:47,327 INFO L290 TraceCheckUtils]: 46: Hoare triple {436#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {436#false} is VALID [2022-02-21 04:21:47,327 INFO L290 TraceCheckUtils]: 47: Hoare triple {436#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {436#false} is VALID [2022-02-21 04:21:47,327 INFO L290 TraceCheckUtils]: 48: Hoare triple {436#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {436#false} is VALID [2022-02-21 04:21:47,327 INFO L290 TraceCheckUtils]: 49: Hoare triple {436#false} assume !(0 != activate_threads_~tmp___3~0#1); {436#false} is VALID [2022-02-21 04:21:47,327 INFO L290 TraceCheckUtils]: 50: Hoare triple {436#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {436#false} is VALID [2022-02-21 04:21:47,328 INFO L290 TraceCheckUtils]: 51: Hoare triple {436#false} assume !(1 == ~M_E~0); {436#false} is VALID [2022-02-21 04:21:47,328 INFO L290 TraceCheckUtils]: 52: Hoare triple {436#false} assume !(1 == ~T1_E~0); {436#false} is VALID [2022-02-21 04:21:47,328 INFO L290 TraceCheckUtils]: 53: Hoare triple {436#false} assume !(1 == ~T2_E~0); {436#false} is VALID [2022-02-21 04:21:47,328 INFO L290 TraceCheckUtils]: 54: Hoare triple {436#false} assume !(1 == ~T3_E~0); {436#false} is VALID [2022-02-21 04:21:47,329 INFO L290 TraceCheckUtils]: 55: Hoare triple {436#false} assume !(1 == ~T4_E~0); {436#false} is VALID [2022-02-21 04:21:47,329 INFO L290 TraceCheckUtils]: 56: Hoare triple {436#false} assume !(1 == ~E_M~0); {436#false} is VALID [2022-02-21 04:21:47,329 INFO L290 TraceCheckUtils]: 57: Hoare triple {436#false} assume 1 == ~E_1~0;~E_1~0 := 2; {436#false} is VALID [2022-02-21 04:21:47,329 INFO L290 TraceCheckUtils]: 58: Hoare triple {436#false} assume !(1 == ~E_2~0); {436#false} is VALID [2022-02-21 04:21:47,330 INFO L290 TraceCheckUtils]: 59: Hoare triple {436#false} assume !(1 == ~E_3~0); {436#false} is VALID [2022-02-21 04:21:47,330 INFO L290 TraceCheckUtils]: 60: Hoare triple {436#false} assume !(1 == ~E_4~0); {436#false} is VALID [2022-02-21 04:21:47,330 INFO L290 TraceCheckUtils]: 61: Hoare triple {436#false} assume { :end_inline_reset_delta_events } true; {436#false} is VALID [2022-02-21 04:21:47,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,332 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,332 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1978113777] [2022-02-21 04:21:47,333 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1978113777] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,333 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,333 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:47,335 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714432264] [2022-02-21 04:21:47,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,338 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:47,339 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:47,339 INFO L85 PathProgramCache]: Analyzing trace with hash -1756395876, now seen corresponding path program 1 times [2022-02-21 04:21:47,339 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:47,340 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411585826] [2022-02-21 04:21:47,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:47,340 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:47,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:47,360 INFO L290 TraceCheckUtils]: 0: Hoare triple {438#true} assume !false; {438#true} is VALID [2022-02-21 04:21:47,361 INFO L290 TraceCheckUtils]: 1: Hoare triple {438#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {438#true} is VALID [2022-02-21 04:21:47,361 INFO L290 TraceCheckUtils]: 2: Hoare triple {438#true} assume !true; {439#false} is VALID [2022-02-21 04:21:47,361 INFO L290 TraceCheckUtils]: 3: Hoare triple {439#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {439#false} is VALID [2022-02-21 04:21:47,362 INFO L290 TraceCheckUtils]: 4: Hoare triple {439#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {439#false} is VALID [2022-02-21 04:21:47,362 INFO L290 TraceCheckUtils]: 5: Hoare triple {439#false} assume 0 == ~M_E~0;~M_E~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,362 INFO L290 TraceCheckUtils]: 6: Hoare triple {439#false} assume !(0 == ~T1_E~0); {439#false} is VALID [2022-02-21 04:21:47,362 INFO L290 TraceCheckUtils]: 7: Hoare triple {439#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,363 INFO L290 TraceCheckUtils]: 8: Hoare triple {439#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,363 INFO L290 TraceCheckUtils]: 9: Hoare triple {439#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,363 INFO L290 TraceCheckUtils]: 10: Hoare triple {439#false} assume 0 == ~E_M~0;~E_M~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,363 INFO L290 TraceCheckUtils]: 11: Hoare triple {439#false} assume 0 == ~E_1~0;~E_1~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,363 INFO L290 TraceCheckUtils]: 12: Hoare triple {439#false} assume 0 == ~E_2~0;~E_2~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,364 INFO L290 TraceCheckUtils]: 13: Hoare triple {439#false} assume 0 == ~E_3~0;~E_3~0 := 1; {439#false} is VALID [2022-02-21 04:21:47,364 INFO L290 TraceCheckUtils]: 14: Hoare triple {439#false} assume !(0 == ~E_4~0); {439#false} is VALID [2022-02-21 04:21:47,364 INFO L290 TraceCheckUtils]: 15: Hoare triple {439#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {439#false} is VALID [2022-02-21 04:21:47,364 INFO L290 TraceCheckUtils]: 16: Hoare triple {439#false} assume 1 == ~m_pc~0; {439#false} is VALID [2022-02-21 04:21:47,364 INFO L290 TraceCheckUtils]: 17: Hoare triple {439#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {439#false} is VALID [2022-02-21 04:21:47,365 INFO L290 TraceCheckUtils]: 18: Hoare triple {439#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {439#false} is VALID [2022-02-21 04:21:47,365 INFO L290 TraceCheckUtils]: 19: Hoare triple {439#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {439#false} is VALID [2022-02-21 04:21:47,365 INFO L290 TraceCheckUtils]: 20: Hoare triple {439#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {439#false} is VALID [2022-02-21 04:21:47,365 INFO L290 TraceCheckUtils]: 21: Hoare triple {439#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {439#false} is VALID [2022-02-21 04:21:47,366 INFO L290 TraceCheckUtils]: 22: Hoare triple {439#false} assume !(1 == ~t1_pc~0); {439#false} is VALID [2022-02-21 04:21:47,366 INFO L290 TraceCheckUtils]: 23: Hoare triple {439#false} is_transmit1_triggered_~__retres1~1#1 := 0; {439#false} is VALID [2022-02-21 04:21:47,366 INFO L290 TraceCheckUtils]: 24: Hoare triple {439#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {439#false} is VALID [2022-02-21 04:21:47,366 INFO L290 TraceCheckUtils]: 25: Hoare triple {439#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {439#false} is VALID [2022-02-21 04:21:47,366 INFO L290 TraceCheckUtils]: 26: Hoare triple {439#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {439#false} is VALID [2022-02-21 04:21:47,367 INFO L290 TraceCheckUtils]: 27: Hoare triple {439#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {439#false} is VALID [2022-02-21 04:21:47,367 INFO L290 TraceCheckUtils]: 28: Hoare triple {439#false} assume !(1 == ~t2_pc~0); {439#false} is VALID [2022-02-21 04:21:47,367 INFO L290 TraceCheckUtils]: 29: Hoare triple {439#false} is_transmit2_triggered_~__retres1~2#1 := 0; {439#false} is VALID [2022-02-21 04:21:47,367 INFO L290 TraceCheckUtils]: 30: Hoare triple {439#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {439#false} is VALID [2022-02-21 04:21:47,367 INFO L290 TraceCheckUtils]: 31: Hoare triple {439#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {439#false} is VALID [2022-02-21 04:21:47,368 INFO L290 TraceCheckUtils]: 32: Hoare triple {439#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {439#false} is VALID [2022-02-21 04:21:47,368 INFO L290 TraceCheckUtils]: 33: Hoare triple {439#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {439#false} is VALID [2022-02-21 04:21:47,368 INFO L290 TraceCheckUtils]: 34: Hoare triple {439#false} assume !(1 == ~t3_pc~0); {439#false} is VALID [2022-02-21 04:21:47,368 INFO L290 TraceCheckUtils]: 35: Hoare triple {439#false} is_transmit3_triggered_~__retres1~3#1 := 0; {439#false} is VALID [2022-02-21 04:21:47,369 INFO L290 TraceCheckUtils]: 36: Hoare triple {439#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {439#false} is VALID [2022-02-21 04:21:47,369 INFO L290 TraceCheckUtils]: 37: Hoare triple {439#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {439#false} is VALID [2022-02-21 04:21:47,369 INFO L290 TraceCheckUtils]: 38: Hoare triple {439#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {439#false} is VALID [2022-02-21 04:21:47,369 INFO L290 TraceCheckUtils]: 39: Hoare triple {439#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {439#false} is VALID [2022-02-21 04:21:47,369 INFO L290 TraceCheckUtils]: 40: Hoare triple {439#false} assume !(1 == ~t4_pc~0); {439#false} is VALID [2022-02-21 04:21:47,370 INFO L290 TraceCheckUtils]: 41: Hoare triple {439#false} is_transmit4_triggered_~__retres1~4#1 := 0; {439#false} is VALID [2022-02-21 04:21:47,370 INFO L290 TraceCheckUtils]: 42: Hoare triple {439#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {439#false} is VALID [2022-02-21 04:21:47,370 INFO L290 TraceCheckUtils]: 43: Hoare triple {439#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {439#false} is VALID [2022-02-21 04:21:47,370 INFO L290 TraceCheckUtils]: 44: Hoare triple {439#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {439#false} is VALID [2022-02-21 04:21:47,370 INFO L290 TraceCheckUtils]: 45: Hoare triple {439#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {439#false} is VALID [2022-02-21 04:21:47,371 INFO L290 TraceCheckUtils]: 46: Hoare triple {439#false} assume 1 == ~M_E~0;~M_E~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,371 INFO L290 TraceCheckUtils]: 47: Hoare triple {439#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,371 INFO L290 TraceCheckUtils]: 48: Hoare triple {439#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,371 INFO L290 TraceCheckUtils]: 49: Hoare triple {439#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 50: Hoare triple {439#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 51: Hoare triple {439#false} assume 1 == ~E_M~0;~E_M~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 52: Hoare triple {439#false} assume !(1 == ~E_1~0); {439#false} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 53: Hoare triple {439#false} assume 1 == ~E_2~0;~E_2~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,372 INFO L290 TraceCheckUtils]: 54: Hoare triple {439#false} assume 1 == ~E_3~0;~E_3~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 55: Hoare triple {439#false} assume 1 == ~E_4~0;~E_4~0 := 2; {439#false} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 56: Hoare triple {439#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {439#false} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 57: Hoare triple {439#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {439#false} is VALID [2022-02-21 04:21:47,373 INFO L290 TraceCheckUtils]: 58: Hoare triple {439#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {439#false} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 59: Hoare triple {439#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {439#false} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 60: Hoare triple {439#false} assume !(0 == start_simulation_~tmp~3#1); {439#false} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 61: Hoare triple {439#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {439#false} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 62: Hoare triple {439#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {439#false} is VALID [2022-02-21 04:21:47,374 INFO L290 TraceCheckUtils]: 63: Hoare triple {439#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {439#false} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 64: Hoare triple {439#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {439#false} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 65: Hoare triple {439#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {439#false} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 66: Hoare triple {439#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {439#false} is VALID [2022-02-21 04:21:47,375 INFO L290 TraceCheckUtils]: 67: Hoare triple {439#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {439#false} is VALID [2022-02-21 04:21:47,376 INFO L290 TraceCheckUtils]: 68: Hoare triple {439#false} assume !(0 != start_simulation_~tmp___0~1#1); {439#false} is VALID [2022-02-21 04:21:47,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:47,376 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:47,377 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411585826] [2022-02-21 04:21:47,377 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411585826] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:47,377 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:47,377 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:47,377 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1929268259] [2022-02-21 04:21:47,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:47,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:47,380 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:47,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:47,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:47,404 INFO L87 Difference]: Start difference. First operand has 431 states, 430 states have (on average 1.5325581395348837) internal successors, (659), 430 states have internal predecessors, (659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:47,856 INFO L93 Difference]: Finished difference Result 430 states and 642 transitions. [2022-02-21 04:21:47,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:47,858 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:47,909 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:47,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 642 transitions. [2022-02-21 04:21:47,942 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:47,961 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 425 states and 637 transitions. [2022-02-21 04:21:47,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-02-21 04:21:47,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-02-21 04:21:47,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 637 transitions. [2022-02-21 04:21:47,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:47,968 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-02-21 04:21:47,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 637 transitions. [2022-02-21 04:21:48,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-02-21 04:21:48,015 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:48,017 INFO L82 GeneralOperation]: Start isEquivalent. First operand 425 states and 637 transitions. Second operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,020 INFO L74 IsIncluded]: Start isIncluded. First operand 425 states and 637 transitions. Second operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,023 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. Second operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,038 INFO L93 Difference]: Finished difference Result 425 states and 637 transitions. [2022-02-21 04:21:48,039 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 637 transitions. [2022-02-21 04:21:48,041 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,041 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,042 INFO L74 IsIncluded]: Start isIncluded. First operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 637 transitions. [2022-02-21 04:21:48,044 INFO L87 Difference]: Start difference. First operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 637 transitions. [2022-02-21 04:21:48,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,059 INFO L93 Difference]: Finished difference Result 425 states and 637 transitions. [2022-02-21 04:21:48,059 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 637 transitions. [2022-02-21 04:21:48,061 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,061 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,061 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,062 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4988235294117647) internal successors, (637), 424 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 637 transitions. [2022-02-21 04:21:48,079 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-02-21 04:21:48,079 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 637 transitions. [2022-02-21 04:21:48,079 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:48,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 637 transitions. [2022-02-21 04:21:48,081 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:48,081 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,081 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,083 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,083 INFO L791 eck$LassoCheckResult]: Stem: 1294#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1205#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 958#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 959#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1014#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1260#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 964#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 965#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1087#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996#L514 assume !(0 == ~M_E~0); 997#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1276#L519-1 assume !(0 == ~T2_E~0); 950#L524-1 assume !(0 == ~T3_E~0); 951#L529-1 assume !(0 == ~T4_E~0); 1066#L534-1 assume !(0 == ~E_M~0); 1242#L539-1 assume !(0 == ~E_1~0); 1243#L544-1 assume !(0 == ~E_2~0); 1258#L549-1 assume !(0 == ~E_3~0); 1259#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 945#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 946#L250 assume 1 == ~m_pc~0; 1155#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1264#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1120#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1121#L637 assume !(0 != activate_threads_~tmp~1#1); 952#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 953#L269 assume !(1 == ~t1_pc~0); 890#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 889#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1084#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1085#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1117#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1118#L288 assume 1 == ~t2_pc~0; 1220#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1114#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1130#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1131#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1237#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1144#L307 assume !(1 == ~t3_pc~0); 1078#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1079#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1269#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1093#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1094#L326 assume 1 == ~t4_pc~0; 1283#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 904#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1140#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1241#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1238#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L572 assume !(1 == ~M_E~0); 1265#L572-2 assume !(1 == ~T1_E~0); 960#L577-1 assume !(1 == ~T2_E~0); 961#L582-1 assume !(1 == ~T3_E~0); 1226#L587-1 assume !(1 == ~T4_E~0); 1233#L592-1 assume !(1 == ~E_M~0); 895#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 896#L602-1 assume !(1 == ~E_2~0); 1110#L607-1 assume !(1 == ~E_3~0); 1111#L612-1 assume !(1 == ~E_4~0); 1064#L617-1 assume { :end_inline_reset_delta_events } true; 1065#L803-2 [2022-02-21 04:21:48,084 INFO L793 eck$LassoCheckResult]: Loop: 1065#L803-2 assume !false; 1206#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 988#L489 assume !false; 1183#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1146#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1004#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1060#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1293#L428 assume !(0 != eval_~tmp~0#1); 1291#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1216#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1182#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1124#L514-5 assume !(0 == ~T1_E~0); 1125#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1224#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1034#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1035#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 884#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 885#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1278#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1082#L554-3 assume !(0 == ~E_4~0); 1083#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1180#L250-18 assume 1 == ~m_pc~0; 1214#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1192#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 976#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1044#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 932#L269-18 assume !(1 == ~t1_pc~0); 933#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1006#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1007#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1061#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1168#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1070#L288-18 assume 1 == ~t2_pc~0; 1056#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 893#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 894#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 991#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1051#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052#L307-18 assume 1 == ~t3_pc~0; 1112#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1024#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1086#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1032#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1033#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1247#L326-18 assume 1 == ~t4_pc~0; 1248#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1254#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1225#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 880#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 881#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1288#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1049#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1050#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 943#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 944#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1178#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1179#L597-3 assume !(1 == ~E_1~0); 1099#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1100#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1058#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1059#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1105#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1074#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1091#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1141#L822 assume !(0 == start_simulation_~tmp~3#1); 1143#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1245#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1187#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1145#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 916#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 917#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1185#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1201#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1065#L803-2 [2022-02-21 04:21:48,084 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2022-02-21 04:21:48,085 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,085 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131987019] [2022-02-21 04:21:48,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,120 INFO L290 TraceCheckUtils]: 0: Hoare triple {2148#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {2148#true} is VALID [2022-02-21 04:21:48,120 INFO L290 TraceCheckUtils]: 1: Hoare triple {2148#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {2150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:48,121 INFO L290 TraceCheckUtils]: 2: Hoare triple {2150#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {2150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:48,121 INFO L290 TraceCheckUtils]: 3: Hoare triple {2150#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {2150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:48,122 INFO L290 TraceCheckUtils]: 4: Hoare triple {2150#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {2150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:48,122 INFO L290 TraceCheckUtils]: 5: Hoare triple {2150#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {2150#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:48,122 INFO L290 TraceCheckUtils]: 6: Hoare triple {2150#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {2149#false} is VALID [2022-02-21 04:21:48,123 INFO L290 TraceCheckUtils]: 7: Hoare triple {2149#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {2149#false} is VALID [2022-02-21 04:21:48,123 INFO L290 TraceCheckUtils]: 8: Hoare triple {2149#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {2149#false} is VALID [2022-02-21 04:21:48,123 INFO L290 TraceCheckUtils]: 9: Hoare triple {2149#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {2149#false} is VALID [2022-02-21 04:21:48,123 INFO L290 TraceCheckUtils]: 10: Hoare triple {2149#false} assume !(0 == ~M_E~0); {2149#false} is VALID [2022-02-21 04:21:48,123 INFO L290 TraceCheckUtils]: 11: Hoare triple {2149#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {2149#false} is VALID [2022-02-21 04:21:48,124 INFO L290 TraceCheckUtils]: 12: Hoare triple {2149#false} assume !(0 == ~T2_E~0); {2149#false} is VALID [2022-02-21 04:21:48,124 INFO L290 TraceCheckUtils]: 13: Hoare triple {2149#false} assume !(0 == ~T3_E~0); {2149#false} is VALID [2022-02-21 04:21:48,124 INFO L290 TraceCheckUtils]: 14: Hoare triple {2149#false} assume !(0 == ~T4_E~0); {2149#false} is VALID [2022-02-21 04:21:48,124 INFO L290 TraceCheckUtils]: 15: Hoare triple {2149#false} assume !(0 == ~E_M~0); {2149#false} is VALID [2022-02-21 04:21:48,124 INFO L290 TraceCheckUtils]: 16: Hoare triple {2149#false} assume !(0 == ~E_1~0); {2149#false} is VALID [2022-02-21 04:21:48,125 INFO L290 TraceCheckUtils]: 17: Hoare triple {2149#false} assume !(0 == ~E_2~0); {2149#false} is VALID [2022-02-21 04:21:48,125 INFO L290 TraceCheckUtils]: 18: Hoare triple {2149#false} assume !(0 == ~E_3~0); {2149#false} is VALID [2022-02-21 04:21:48,125 INFO L290 TraceCheckUtils]: 19: Hoare triple {2149#false} assume 0 == ~E_4~0;~E_4~0 := 1; {2149#false} is VALID [2022-02-21 04:21:48,125 INFO L290 TraceCheckUtils]: 20: Hoare triple {2149#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2149#false} is VALID [2022-02-21 04:21:48,125 INFO L290 TraceCheckUtils]: 21: Hoare triple {2149#false} assume 1 == ~m_pc~0; {2149#false} is VALID [2022-02-21 04:21:48,126 INFO L290 TraceCheckUtils]: 22: Hoare triple {2149#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2149#false} is VALID [2022-02-21 04:21:48,126 INFO L290 TraceCheckUtils]: 23: Hoare triple {2149#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2149#false} is VALID [2022-02-21 04:21:48,126 INFO L290 TraceCheckUtils]: 24: Hoare triple {2149#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2149#false} is VALID [2022-02-21 04:21:48,126 INFO L290 TraceCheckUtils]: 25: Hoare triple {2149#false} assume !(0 != activate_threads_~tmp~1#1); {2149#false} is VALID [2022-02-21 04:21:48,126 INFO L290 TraceCheckUtils]: 26: Hoare triple {2149#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2149#false} is VALID [2022-02-21 04:21:48,127 INFO L290 TraceCheckUtils]: 27: Hoare triple {2149#false} assume !(1 == ~t1_pc~0); {2149#false} is VALID [2022-02-21 04:21:48,127 INFO L290 TraceCheckUtils]: 28: Hoare triple {2149#false} is_transmit1_triggered_~__retres1~1#1 := 0; {2149#false} is VALID [2022-02-21 04:21:48,127 INFO L290 TraceCheckUtils]: 29: Hoare triple {2149#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2149#false} is VALID [2022-02-21 04:21:48,127 INFO L290 TraceCheckUtils]: 30: Hoare triple {2149#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2149#false} is VALID [2022-02-21 04:21:48,127 INFO L290 TraceCheckUtils]: 31: Hoare triple {2149#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2149#false} is VALID [2022-02-21 04:21:48,128 INFO L290 TraceCheckUtils]: 32: Hoare triple {2149#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2149#false} is VALID [2022-02-21 04:21:48,128 INFO L290 TraceCheckUtils]: 33: Hoare triple {2149#false} assume 1 == ~t2_pc~0; {2149#false} is VALID [2022-02-21 04:21:48,128 INFO L290 TraceCheckUtils]: 34: Hoare triple {2149#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2149#false} is VALID [2022-02-21 04:21:48,128 INFO L290 TraceCheckUtils]: 35: Hoare triple {2149#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2149#false} is VALID [2022-02-21 04:21:48,128 INFO L290 TraceCheckUtils]: 36: Hoare triple {2149#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2149#false} is VALID [2022-02-21 04:21:48,129 INFO L290 TraceCheckUtils]: 37: Hoare triple {2149#false} assume !(0 != activate_threads_~tmp___1~0#1); {2149#false} is VALID [2022-02-21 04:21:48,129 INFO L290 TraceCheckUtils]: 38: Hoare triple {2149#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2149#false} is VALID [2022-02-21 04:21:48,129 INFO L290 TraceCheckUtils]: 39: Hoare triple {2149#false} assume !(1 == ~t3_pc~0); {2149#false} is VALID [2022-02-21 04:21:48,129 INFO L290 TraceCheckUtils]: 40: Hoare triple {2149#false} is_transmit3_triggered_~__retres1~3#1 := 0; {2149#false} is VALID [2022-02-21 04:21:48,129 INFO L290 TraceCheckUtils]: 41: Hoare triple {2149#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2149#false} is VALID [2022-02-21 04:21:48,130 INFO L290 TraceCheckUtils]: 42: Hoare triple {2149#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {2149#false} is VALID [2022-02-21 04:21:48,130 INFO L290 TraceCheckUtils]: 43: Hoare triple {2149#false} assume !(0 != activate_threads_~tmp___2~0#1); {2149#false} is VALID [2022-02-21 04:21:48,130 INFO L290 TraceCheckUtils]: 44: Hoare triple {2149#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2149#false} is VALID [2022-02-21 04:21:48,130 INFO L290 TraceCheckUtils]: 45: Hoare triple {2149#false} assume 1 == ~t4_pc~0; {2149#false} is VALID [2022-02-21 04:21:48,130 INFO L290 TraceCheckUtils]: 46: Hoare triple {2149#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2149#false} is VALID [2022-02-21 04:21:48,131 INFO L290 TraceCheckUtils]: 47: Hoare triple {2149#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2149#false} is VALID [2022-02-21 04:21:48,131 INFO L290 TraceCheckUtils]: 48: Hoare triple {2149#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {2149#false} is VALID [2022-02-21 04:21:48,131 INFO L290 TraceCheckUtils]: 49: Hoare triple {2149#false} assume !(0 != activate_threads_~tmp___3~0#1); {2149#false} is VALID [2022-02-21 04:21:48,131 INFO L290 TraceCheckUtils]: 50: Hoare triple {2149#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2149#false} is VALID [2022-02-21 04:21:48,131 INFO L290 TraceCheckUtils]: 51: Hoare triple {2149#false} assume !(1 == ~M_E~0); {2149#false} is VALID [2022-02-21 04:21:48,132 INFO L290 TraceCheckUtils]: 52: Hoare triple {2149#false} assume !(1 == ~T1_E~0); {2149#false} is VALID [2022-02-21 04:21:48,132 INFO L290 TraceCheckUtils]: 53: Hoare triple {2149#false} assume !(1 == ~T2_E~0); {2149#false} is VALID [2022-02-21 04:21:48,132 INFO L290 TraceCheckUtils]: 54: Hoare triple {2149#false} assume !(1 == ~T3_E~0); {2149#false} is VALID [2022-02-21 04:21:48,132 INFO L290 TraceCheckUtils]: 55: Hoare triple {2149#false} assume !(1 == ~T4_E~0); {2149#false} is VALID [2022-02-21 04:21:48,132 INFO L290 TraceCheckUtils]: 56: Hoare triple {2149#false} assume !(1 == ~E_M~0); {2149#false} is VALID [2022-02-21 04:21:48,133 INFO L290 TraceCheckUtils]: 57: Hoare triple {2149#false} assume 1 == ~E_1~0;~E_1~0 := 2; {2149#false} is VALID [2022-02-21 04:21:48,133 INFO L290 TraceCheckUtils]: 58: Hoare triple {2149#false} assume !(1 == ~E_2~0); {2149#false} is VALID [2022-02-21 04:21:48,133 INFO L290 TraceCheckUtils]: 59: Hoare triple {2149#false} assume !(1 == ~E_3~0); {2149#false} is VALID [2022-02-21 04:21:48,133 INFO L290 TraceCheckUtils]: 60: Hoare triple {2149#false} assume !(1 == ~E_4~0); {2149#false} is VALID [2022-02-21 04:21:48,133 INFO L290 TraceCheckUtils]: 61: Hoare triple {2149#false} assume { :end_inline_reset_delta_events } true; {2149#false} is VALID [2022-02-21 04:21:48,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,134 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,134 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131987019] [2022-02-21 04:21:48,134 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131987019] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,135 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,135 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,135 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997875531] [2022-02-21 04:21:48,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,136 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:48,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,136 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 1 times [2022-02-21 04:21:48,136 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,137 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125131821] [2022-02-21 04:21:48,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,193 INFO L290 TraceCheckUtils]: 0: Hoare triple {2151#true} assume !false; {2151#true} is VALID [2022-02-21 04:21:48,193 INFO L290 TraceCheckUtils]: 1: Hoare triple {2151#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {2151#true} is VALID [2022-02-21 04:21:48,193 INFO L290 TraceCheckUtils]: 2: Hoare triple {2151#true} assume !false; {2151#true} is VALID [2022-02-21 04:21:48,193 INFO L290 TraceCheckUtils]: 3: Hoare triple {2151#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {2151#true} is VALID [2022-02-21 04:21:48,193 INFO L290 TraceCheckUtils]: 4: Hoare triple {2151#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 5: Hoare triple {2151#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 6: Hoare triple {2151#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 7: Hoare triple {2151#true} assume !(0 != eval_~tmp~0#1); {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 8: Hoare triple {2151#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 9: Hoare triple {2151#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {2151#true} is VALID [2022-02-21 04:21:48,194 INFO L290 TraceCheckUtils]: 10: Hoare triple {2151#true} assume 0 == ~M_E~0;~M_E~0 := 1; {2151#true} is VALID [2022-02-21 04:21:48,195 INFO L290 TraceCheckUtils]: 11: Hoare triple {2151#true} assume !(0 == ~T1_E~0); {2151#true} is VALID [2022-02-21 04:21:48,195 INFO L290 TraceCheckUtils]: 12: Hoare triple {2151#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {2151#true} is VALID [2022-02-21 04:21:48,195 INFO L290 TraceCheckUtils]: 13: Hoare triple {2151#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {2151#true} is VALID [2022-02-21 04:21:48,195 INFO L290 TraceCheckUtils]: 14: Hoare triple {2151#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {2151#true} is VALID [2022-02-21 04:21:48,195 INFO L290 TraceCheckUtils]: 15: Hoare triple {2151#true} assume 0 == ~E_M~0;~E_M~0 := 1; {2151#true} is VALID [2022-02-21 04:21:48,196 INFO L290 TraceCheckUtils]: 16: Hoare triple {2151#true} assume 0 == ~E_1~0;~E_1~0 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,196 INFO L290 TraceCheckUtils]: 17: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,204 INFO L290 TraceCheckUtils]: 18: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,204 INFO L290 TraceCheckUtils]: 19: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,205 INFO L290 TraceCheckUtils]: 20: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,205 INFO L290 TraceCheckUtils]: 21: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,206 INFO L290 TraceCheckUtils]: 22: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,206 INFO L290 TraceCheckUtils]: 23: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,207 INFO L290 TraceCheckUtils]: 24: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,207 INFO L290 TraceCheckUtils]: 25: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,208 INFO L290 TraceCheckUtils]: 26: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,208 INFO L290 TraceCheckUtils]: 27: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,208 INFO L290 TraceCheckUtils]: 28: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,209 INFO L290 TraceCheckUtils]: 29: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,209 INFO L290 TraceCheckUtils]: 30: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,210 INFO L290 TraceCheckUtils]: 31: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,210 INFO L290 TraceCheckUtils]: 32: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,211 INFO L290 TraceCheckUtils]: 33: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,211 INFO L290 TraceCheckUtils]: 34: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,212 INFO L290 TraceCheckUtils]: 35: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,212 INFO L290 TraceCheckUtils]: 36: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 37: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,213 INFO L290 TraceCheckUtils]: 38: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 39: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,214 INFO L290 TraceCheckUtils]: 40: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 41: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 42: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,215 INFO L290 TraceCheckUtils]: 43: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 44: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,216 INFO L290 TraceCheckUtils]: 45: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 46: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,217 INFO L290 TraceCheckUtils]: 47: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 48: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,218 INFO L290 TraceCheckUtils]: 49: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 50: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,219 INFO L290 TraceCheckUtils]: 51: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,220 INFO L290 TraceCheckUtils]: 52: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,220 INFO L290 TraceCheckUtils]: 53: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,220 INFO L290 TraceCheckUtils]: 54: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,221 INFO L290 TraceCheckUtils]: 55: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,221 INFO L290 TraceCheckUtils]: 56: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {2153#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,222 INFO L290 TraceCheckUtils]: 57: Hoare triple {2153#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {2152#false} is VALID [2022-02-21 04:21:48,222 INFO L290 TraceCheckUtils]: 58: Hoare triple {2152#false} assume 1 == ~E_2~0;~E_2~0 := 2; {2152#false} is VALID [2022-02-21 04:21:48,222 INFO L290 TraceCheckUtils]: 59: Hoare triple {2152#false} assume 1 == ~E_3~0;~E_3~0 := 2; {2152#false} is VALID [2022-02-21 04:21:48,222 INFO L290 TraceCheckUtils]: 60: Hoare triple {2152#false} assume 1 == ~E_4~0;~E_4~0 := 2; {2152#false} is VALID [2022-02-21 04:21:48,223 INFO L290 TraceCheckUtils]: 61: Hoare triple {2152#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {2152#false} is VALID [2022-02-21 04:21:48,223 INFO L290 TraceCheckUtils]: 62: Hoare triple {2152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {2152#false} is VALID [2022-02-21 04:21:48,223 INFO L290 TraceCheckUtils]: 63: Hoare triple {2152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {2152#false} is VALID [2022-02-21 04:21:48,223 INFO L290 TraceCheckUtils]: 64: Hoare triple {2152#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {2152#false} is VALID [2022-02-21 04:21:48,223 INFO L290 TraceCheckUtils]: 65: Hoare triple {2152#false} assume !(0 == start_simulation_~tmp~3#1); {2152#false} is VALID [2022-02-21 04:21:48,224 INFO L290 TraceCheckUtils]: 66: Hoare triple {2152#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {2152#false} is VALID [2022-02-21 04:21:48,224 INFO L290 TraceCheckUtils]: 67: Hoare triple {2152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {2152#false} is VALID [2022-02-21 04:21:48,224 INFO L290 TraceCheckUtils]: 68: Hoare triple {2152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {2152#false} is VALID [2022-02-21 04:21:48,224 INFO L290 TraceCheckUtils]: 69: Hoare triple {2152#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {2152#false} is VALID [2022-02-21 04:21:48,224 INFO L290 TraceCheckUtils]: 70: Hoare triple {2152#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {2152#false} is VALID [2022-02-21 04:21:48,225 INFO L290 TraceCheckUtils]: 71: Hoare triple {2152#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {2152#false} is VALID [2022-02-21 04:21:48,225 INFO L290 TraceCheckUtils]: 72: Hoare triple {2152#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {2152#false} is VALID [2022-02-21 04:21:48,225 INFO L290 TraceCheckUtils]: 73: Hoare triple {2152#false} assume !(0 != start_simulation_~tmp___0~1#1); {2152#false} is VALID [2022-02-21 04:21:48,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,226 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,226 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125131821] [2022-02-21 04:21:48,226 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125131821] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,226 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,227 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,227 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067926272] [2022-02-21 04:21:48,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,227 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:48,228 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:48,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:48,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:48,229 INFO L87 Difference]: Start difference. First operand 425 states and 637 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,648 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2022-02-21 04:21:48,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:48,648 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,694 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:48,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,710 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:48,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 636 transitions. [2022-02-21 04:21:48,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-02-21 04:21:48,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-02-21 04:21:48,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:48,726 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-02-21 04:21:48,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-02-21 04:21:48,736 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:48,737 INFO L82 GeneralOperation]: Start isEquivalent. First operand 425 states and 636 transitions. Second operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,738 INFO L74 IsIncluded]: Start isIncluded. First operand 425 states and 636 transitions. Second operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,739 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. Second operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,752 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2022-02-21 04:21:48,752 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,753 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,753 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,754 INFO L74 IsIncluded]: Start isIncluded. First operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 636 transitions. [2022-02-21 04:21:48,755 INFO L87 Difference]: Start difference. First operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 636 transitions. [2022-02-21 04:21:48,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:48,768 INFO L93 Difference]: Finished difference Result 425 states and 636 transitions. [2022-02-21 04:21:48,768 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,769 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:48,769 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:48,770 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:48,770 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:48,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4964705882352942) internal successors, (636), 424 states have internal predecessors, (636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:48,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 636 transitions. [2022-02-21 04:21:48,783 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-02-21 04:21:48,783 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 636 transitions. [2022-02-21 04:21:48,783 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:48,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 636 transitions. [2022-02-21 04:21:48,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:48,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:48,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:48,786 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,787 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:48,787 INFO L791 eck$LassoCheckResult]: Stem: 3003#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2996#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2914#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2667#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2668#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2723#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2969#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2673#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2674#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2796#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2705#L514 assume !(0 == ~M_E~0); 2706#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2985#L519-1 assume !(0 == ~T2_E~0); 2659#L524-1 assume !(0 == ~T3_E~0); 2660#L529-1 assume !(0 == ~T4_E~0); 2775#L534-1 assume !(0 == ~E_M~0); 2951#L539-1 assume !(0 == ~E_1~0); 2952#L544-1 assume !(0 == ~E_2~0); 2967#L549-1 assume !(0 == ~E_3~0); 2968#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2654#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2655#L250 assume 1 == ~m_pc~0; 2864#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2973#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2829#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2830#L637 assume !(0 != activate_threads_~tmp~1#1); 2661#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2662#L269 assume !(1 == ~t1_pc~0); 2599#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2598#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2793#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2794#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2826#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2827#L288 assume 1 == ~t2_pc~0; 2929#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2823#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2839#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2840#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2946#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2853#L307 assume !(1 == ~t3_pc~0); 2787#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2788#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2904#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2978#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2802#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2803#L326 assume 1 == ~t4_pc~0; 2992#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2613#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2849#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2950#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2947#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2948#L572 assume !(1 == ~M_E~0); 2974#L572-2 assume !(1 == ~T1_E~0); 2669#L577-1 assume !(1 == ~T2_E~0); 2670#L582-1 assume !(1 == ~T3_E~0); 2935#L587-1 assume !(1 == ~T4_E~0); 2942#L592-1 assume !(1 == ~E_M~0); 2604#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2605#L602-1 assume !(1 == ~E_2~0); 2819#L607-1 assume !(1 == ~E_3~0); 2820#L612-1 assume !(1 == ~E_4~0); 2773#L617-1 assume { :end_inline_reset_delta_events } true; 2774#L803-2 [2022-02-21 04:21:48,787 INFO L793 eck$LassoCheckResult]: Loop: 2774#L803-2 assume !false; 2915#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2697#L489 assume !false; 2892#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2855#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2713#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2769#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3002#L428 assume !(0 != eval_~tmp~0#1); 3000#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2925#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2891#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2833#L514-5 assume !(0 == ~T1_E~0); 2834#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2933#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2743#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2744#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2593#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2594#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2987#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2791#L554-3 assume !(0 == ~E_4~0); 2792#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2889#L250-18 assume 1 == ~m_pc~0; 2923#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2901#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2684#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2685#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2641#L269-18 assume !(1 == ~t1_pc~0); 2642#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2715#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2716#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2770#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2877#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2779#L288-18 assume 1 == ~t2_pc~0; 2765#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2602#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2603#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2700#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2760#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2761#L307-18 assume 1 == ~t3_pc~0; 2821#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2733#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2795#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2741#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2742#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2956#L326-18 assume 1 == ~t4_pc~0; 2957#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2963#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2934#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2589#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2590#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2997#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2758#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2759#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2652#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2653#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2887#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2888#L597-3 assume !(1 == ~E_1~0); 2808#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2809#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2767#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2768#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2814#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2783#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2800#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2850#L822 assume !(0 == start_simulation_~tmp~3#1); 2852#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2954#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2896#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2854#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2625#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2626#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2894#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2910#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2774#L803-2 [2022-02-21 04:21:48,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2022-02-21 04:21:48,788 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,788 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093158067] [2022-02-21 04:21:48,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,821 INFO L290 TraceCheckUtils]: 0: Hoare triple {3857#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {3857#true} is VALID [2022-02-21 04:21:48,821 INFO L290 TraceCheckUtils]: 1: Hoare triple {3857#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,822 INFO L290 TraceCheckUtils]: 2: Hoare triple {3859#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,822 INFO L290 TraceCheckUtils]: 3: Hoare triple {3859#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,823 INFO L290 TraceCheckUtils]: 4: Hoare triple {3859#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,823 INFO L290 TraceCheckUtils]: 5: Hoare triple {3859#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,823 INFO L290 TraceCheckUtils]: 6: Hoare triple {3859#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {3859#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:48,824 INFO L290 TraceCheckUtils]: 7: Hoare triple {3859#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {3858#false} is VALID [2022-02-21 04:21:48,824 INFO L290 TraceCheckUtils]: 8: Hoare triple {3858#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {3858#false} is VALID [2022-02-21 04:21:48,824 INFO L290 TraceCheckUtils]: 9: Hoare triple {3858#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3858#false} is VALID [2022-02-21 04:21:48,824 INFO L290 TraceCheckUtils]: 10: Hoare triple {3858#false} assume !(0 == ~M_E~0); {3858#false} is VALID [2022-02-21 04:21:48,824 INFO L290 TraceCheckUtils]: 11: Hoare triple {3858#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3858#false} is VALID [2022-02-21 04:21:48,825 INFO L290 TraceCheckUtils]: 12: Hoare triple {3858#false} assume !(0 == ~T2_E~0); {3858#false} is VALID [2022-02-21 04:21:48,825 INFO L290 TraceCheckUtils]: 13: Hoare triple {3858#false} assume !(0 == ~T3_E~0); {3858#false} is VALID [2022-02-21 04:21:48,825 INFO L290 TraceCheckUtils]: 14: Hoare triple {3858#false} assume !(0 == ~T4_E~0); {3858#false} is VALID [2022-02-21 04:21:48,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {3858#false} assume !(0 == ~E_M~0); {3858#false} is VALID [2022-02-21 04:21:48,844 INFO L290 TraceCheckUtils]: 16: Hoare triple {3858#false} assume !(0 == ~E_1~0); {3858#false} is VALID [2022-02-21 04:21:48,844 INFO L290 TraceCheckUtils]: 17: Hoare triple {3858#false} assume !(0 == ~E_2~0); {3858#false} is VALID [2022-02-21 04:21:48,844 INFO L290 TraceCheckUtils]: 18: Hoare triple {3858#false} assume !(0 == ~E_3~0); {3858#false} is VALID [2022-02-21 04:21:48,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {3858#false} assume 0 == ~E_4~0;~E_4~0 := 1; {3858#false} is VALID [2022-02-21 04:21:48,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {3858#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3858#false} is VALID [2022-02-21 04:21:48,845 INFO L290 TraceCheckUtils]: 21: Hoare triple {3858#false} assume 1 == ~m_pc~0; {3858#false} is VALID [2022-02-21 04:21:48,845 INFO L290 TraceCheckUtils]: 22: Hoare triple {3858#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {3858#false} is VALID [2022-02-21 04:21:48,845 INFO L290 TraceCheckUtils]: 23: Hoare triple {3858#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3858#false} is VALID [2022-02-21 04:21:48,846 INFO L290 TraceCheckUtils]: 24: Hoare triple {3858#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3858#false} is VALID [2022-02-21 04:21:48,846 INFO L290 TraceCheckUtils]: 25: Hoare triple {3858#false} assume !(0 != activate_threads_~tmp~1#1); {3858#false} is VALID [2022-02-21 04:21:48,846 INFO L290 TraceCheckUtils]: 26: Hoare triple {3858#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3858#false} is VALID [2022-02-21 04:21:48,848 INFO L290 TraceCheckUtils]: 27: Hoare triple {3858#false} assume !(1 == ~t1_pc~0); {3858#false} is VALID [2022-02-21 04:21:48,848 INFO L290 TraceCheckUtils]: 28: Hoare triple {3858#false} is_transmit1_triggered_~__retres1~1#1 := 0; {3858#false} is VALID [2022-02-21 04:21:48,849 INFO L290 TraceCheckUtils]: 29: Hoare triple {3858#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3858#false} is VALID [2022-02-21 04:21:48,849 INFO L290 TraceCheckUtils]: 30: Hoare triple {3858#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3858#false} is VALID [2022-02-21 04:21:48,849 INFO L290 TraceCheckUtils]: 31: Hoare triple {3858#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3858#false} is VALID [2022-02-21 04:21:48,849 INFO L290 TraceCheckUtils]: 32: Hoare triple {3858#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3858#false} is VALID [2022-02-21 04:21:48,849 INFO L290 TraceCheckUtils]: 33: Hoare triple {3858#false} assume 1 == ~t2_pc~0; {3858#false} is VALID [2022-02-21 04:21:48,852 INFO L290 TraceCheckUtils]: 34: Hoare triple {3858#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3858#false} is VALID [2022-02-21 04:21:48,852 INFO L290 TraceCheckUtils]: 35: Hoare triple {3858#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3858#false} is VALID [2022-02-21 04:21:48,853 INFO L290 TraceCheckUtils]: 36: Hoare triple {3858#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3858#false} is VALID [2022-02-21 04:21:48,853 INFO L290 TraceCheckUtils]: 37: Hoare triple {3858#false} assume !(0 != activate_threads_~tmp___1~0#1); {3858#false} is VALID [2022-02-21 04:21:48,853 INFO L290 TraceCheckUtils]: 38: Hoare triple {3858#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3858#false} is VALID [2022-02-21 04:21:48,853 INFO L290 TraceCheckUtils]: 39: Hoare triple {3858#false} assume !(1 == ~t3_pc~0); {3858#false} is VALID [2022-02-21 04:21:48,853 INFO L290 TraceCheckUtils]: 40: Hoare triple {3858#false} is_transmit3_triggered_~__retres1~3#1 := 0; {3858#false} is VALID [2022-02-21 04:21:48,854 INFO L290 TraceCheckUtils]: 41: Hoare triple {3858#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3858#false} is VALID [2022-02-21 04:21:48,854 INFO L290 TraceCheckUtils]: 42: Hoare triple {3858#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3858#false} is VALID [2022-02-21 04:21:48,855 INFO L290 TraceCheckUtils]: 43: Hoare triple {3858#false} assume !(0 != activate_threads_~tmp___2~0#1); {3858#false} is VALID [2022-02-21 04:21:48,856 INFO L290 TraceCheckUtils]: 44: Hoare triple {3858#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3858#false} is VALID [2022-02-21 04:21:48,856 INFO L290 TraceCheckUtils]: 45: Hoare triple {3858#false} assume 1 == ~t4_pc~0; {3858#false} is VALID [2022-02-21 04:21:48,856 INFO L290 TraceCheckUtils]: 46: Hoare triple {3858#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3858#false} is VALID [2022-02-21 04:21:48,856 INFO L290 TraceCheckUtils]: 47: Hoare triple {3858#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3858#false} is VALID [2022-02-21 04:21:48,856 INFO L290 TraceCheckUtils]: 48: Hoare triple {3858#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3858#false} is VALID [2022-02-21 04:21:48,857 INFO L290 TraceCheckUtils]: 49: Hoare triple {3858#false} assume !(0 != activate_threads_~tmp___3~0#1); {3858#false} is VALID [2022-02-21 04:21:48,857 INFO L290 TraceCheckUtils]: 50: Hoare triple {3858#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3858#false} is VALID [2022-02-21 04:21:48,857 INFO L290 TraceCheckUtils]: 51: Hoare triple {3858#false} assume !(1 == ~M_E~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 52: Hoare triple {3858#false} assume !(1 == ~T1_E~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 53: Hoare triple {3858#false} assume !(1 == ~T2_E~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 54: Hoare triple {3858#false} assume !(1 == ~T3_E~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 55: Hoare triple {3858#false} assume !(1 == ~T4_E~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 56: Hoare triple {3858#false} assume !(1 == ~E_M~0); {3858#false} is VALID [2022-02-21 04:21:48,858 INFO L290 TraceCheckUtils]: 57: Hoare triple {3858#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3858#false} is VALID [2022-02-21 04:21:48,859 INFO L290 TraceCheckUtils]: 58: Hoare triple {3858#false} assume !(1 == ~E_2~0); {3858#false} is VALID [2022-02-21 04:21:48,859 INFO L290 TraceCheckUtils]: 59: Hoare triple {3858#false} assume !(1 == ~E_3~0); {3858#false} is VALID [2022-02-21 04:21:48,859 INFO L290 TraceCheckUtils]: 60: Hoare triple {3858#false} assume !(1 == ~E_4~0); {3858#false} is VALID [2022-02-21 04:21:48,859 INFO L290 TraceCheckUtils]: 61: Hoare triple {3858#false} assume { :end_inline_reset_delta_events } true; {3858#false} is VALID [2022-02-21 04:21:48,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,860 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,860 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093158067] [2022-02-21 04:21:48,861 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093158067] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,861 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,861 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,861 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798130046] [2022-02-21 04:21:48,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,862 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:48,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:48,863 INFO L85 PathProgramCache]: Analyzing trace with hash -387617298, now seen corresponding path program 2 times [2022-02-21 04:21:48,863 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:48,863 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812737541] [2022-02-21 04:21:48,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:48,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:48,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:48,945 INFO L290 TraceCheckUtils]: 0: Hoare triple {3860#true} assume !false; {3860#true} is VALID [2022-02-21 04:21:48,945 INFO L290 TraceCheckUtils]: 1: Hoare triple {3860#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3860#true} is VALID [2022-02-21 04:21:48,945 INFO L290 TraceCheckUtils]: 2: Hoare triple {3860#true} assume !false; {3860#true} is VALID [2022-02-21 04:21:48,946 INFO L290 TraceCheckUtils]: 3: Hoare triple {3860#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3860#true} is VALID [2022-02-21 04:21:48,946 INFO L290 TraceCheckUtils]: 4: Hoare triple {3860#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3860#true} is VALID [2022-02-21 04:21:48,946 INFO L290 TraceCheckUtils]: 5: Hoare triple {3860#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3860#true} is VALID [2022-02-21 04:21:48,946 INFO L290 TraceCheckUtils]: 6: Hoare triple {3860#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {3860#true} is VALID [2022-02-21 04:21:48,946 INFO L290 TraceCheckUtils]: 7: Hoare triple {3860#true} assume !(0 != eval_~tmp~0#1); {3860#true} is VALID [2022-02-21 04:21:48,947 INFO L290 TraceCheckUtils]: 8: Hoare triple {3860#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3860#true} is VALID [2022-02-21 04:21:48,947 INFO L290 TraceCheckUtils]: 9: Hoare triple {3860#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3860#true} is VALID [2022-02-21 04:21:48,947 INFO L290 TraceCheckUtils]: 10: Hoare triple {3860#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3860#true} is VALID [2022-02-21 04:21:48,947 INFO L290 TraceCheckUtils]: 11: Hoare triple {3860#true} assume !(0 == ~T1_E~0); {3860#true} is VALID [2022-02-21 04:21:48,947 INFO L290 TraceCheckUtils]: 12: Hoare triple {3860#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {3860#true} is VALID [2022-02-21 04:21:48,948 INFO L290 TraceCheckUtils]: 13: Hoare triple {3860#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {3860#true} is VALID [2022-02-21 04:21:48,948 INFO L290 TraceCheckUtils]: 14: Hoare triple {3860#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {3860#true} is VALID [2022-02-21 04:21:48,948 INFO L290 TraceCheckUtils]: 15: Hoare triple {3860#true} assume 0 == ~E_M~0;~E_M~0 := 1; {3860#true} is VALID [2022-02-21 04:21:48,949 INFO L290 TraceCheckUtils]: 16: Hoare triple {3860#true} assume 0 == ~E_1~0;~E_1~0 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,949 INFO L290 TraceCheckUtils]: 17: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,950 INFO L290 TraceCheckUtils]: 18: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,950 INFO L290 TraceCheckUtils]: 19: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,950 INFO L290 TraceCheckUtils]: 20: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,951 INFO L290 TraceCheckUtils]: 21: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,951 INFO L290 TraceCheckUtils]: 22: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,952 INFO L290 TraceCheckUtils]: 23: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,952 INFO L290 TraceCheckUtils]: 24: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,953 INFO L290 TraceCheckUtils]: 25: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,953 INFO L290 TraceCheckUtils]: 26: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,954 INFO L290 TraceCheckUtils]: 27: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,954 INFO L290 TraceCheckUtils]: 28: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,955 INFO L290 TraceCheckUtils]: 29: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,955 INFO L290 TraceCheckUtils]: 30: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,956 INFO L290 TraceCheckUtils]: 31: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,956 INFO L290 TraceCheckUtils]: 32: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,957 INFO L290 TraceCheckUtils]: 33: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,957 INFO L290 TraceCheckUtils]: 34: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,958 INFO L290 TraceCheckUtils]: 35: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,958 INFO L290 TraceCheckUtils]: 36: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,959 INFO L290 TraceCheckUtils]: 37: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,959 INFO L290 TraceCheckUtils]: 38: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,960 INFO L290 TraceCheckUtils]: 39: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,960 INFO L290 TraceCheckUtils]: 40: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,961 INFO L290 TraceCheckUtils]: 41: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,961 INFO L290 TraceCheckUtils]: 42: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,962 INFO L290 TraceCheckUtils]: 43: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,962 INFO L290 TraceCheckUtils]: 44: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,963 INFO L290 TraceCheckUtils]: 45: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,963 INFO L290 TraceCheckUtils]: 46: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,964 INFO L290 TraceCheckUtils]: 47: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,964 INFO L290 TraceCheckUtils]: 48: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,965 INFO L290 TraceCheckUtils]: 49: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,965 INFO L290 TraceCheckUtils]: 50: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,965 INFO L290 TraceCheckUtils]: 51: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,966 INFO L290 TraceCheckUtils]: 52: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,966 INFO L290 TraceCheckUtils]: 53: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,967 INFO L290 TraceCheckUtils]: 54: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,967 INFO L290 TraceCheckUtils]: 55: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,968 INFO L290 TraceCheckUtils]: 56: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {3862#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:48,968 INFO L290 TraceCheckUtils]: 57: Hoare triple {3862#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {3861#false} is VALID [2022-02-21 04:21:48,969 INFO L290 TraceCheckUtils]: 58: Hoare triple {3861#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3861#false} is VALID [2022-02-21 04:21:48,969 INFO L290 TraceCheckUtils]: 59: Hoare triple {3861#false} assume 1 == ~E_3~0;~E_3~0 := 2; {3861#false} is VALID [2022-02-21 04:21:48,969 INFO L290 TraceCheckUtils]: 60: Hoare triple {3861#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3861#false} is VALID [2022-02-21 04:21:48,969 INFO L290 TraceCheckUtils]: 61: Hoare triple {3861#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3861#false} is VALID [2022-02-21 04:21:48,969 INFO L290 TraceCheckUtils]: 62: Hoare triple {3861#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3861#false} is VALID [2022-02-21 04:21:48,970 INFO L290 TraceCheckUtils]: 63: Hoare triple {3861#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3861#false} is VALID [2022-02-21 04:21:48,970 INFO L290 TraceCheckUtils]: 64: Hoare triple {3861#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {3861#false} is VALID [2022-02-21 04:21:48,970 INFO L290 TraceCheckUtils]: 65: Hoare triple {3861#false} assume !(0 == start_simulation_~tmp~3#1); {3861#false} is VALID [2022-02-21 04:21:48,970 INFO L290 TraceCheckUtils]: 66: Hoare triple {3861#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {3861#false} is VALID [2022-02-21 04:21:48,970 INFO L290 TraceCheckUtils]: 67: Hoare triple {3861#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {3861#false} is VALID [2022-02-21 04:21:48,971 INFO L290 TraceCheckUtils]: 68: Hoare triple {3861#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {3861#false} is VALID [2022-02-21 04:21:48,971 INFO L290 TraceCheckUtils]: 69: Hoare triple {3861#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {3861#false} is VALID [2022-02-21 04:21:48,971 INFO L290 TraceCheckUtils]: 70: Hoare triple {3861#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3861#false} is VALID [2022-02-21 04:21:48,971 INFO L290 TraceCheckUtils]: 71: Hoare triple {3861#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3861#false} is VALID [2022-02-21 04:21:48,971 INFO L290 TraceCheckUtils]: 72: Hoare triple {3861#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {3861#false} is VALID [2022-02-21 04:21:48,972 INFO L290 TraceCheckUtils]: 73: Hoare triple {3861#false} assume !(0 != start_simulation_~tmp___0~1#1); {3861#false} is VALID [2022-02-21 04:21:48,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:48,972 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:48,973 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812737541] [2022-02-21 04:21:48,973 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812737541] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:48,973 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:48,973 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:48,973 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719719833] [2022-02-21 04:21:48,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:48,974 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:48,974 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:48,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:48,975 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:48,975 INFO L87 Difference]: Start difference. First operand 425 states and 636 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,396 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2022-02-21 04:21:49,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:49,396 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,443 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:49,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:49,475 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 635 transitions. [2022-02-21 04:21:49,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-02-21 04:21:49,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-02-21 04:21:49,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,476 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:49,477 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-02-21 04:21:49,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-02-21 04:21:49,482 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:49,483 INFO L82 GeneralOperation]: Start isEquivalent. First operand 425 states and 635 transitions. Second operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,484 INFO L74 IsIncluded]: Start isIncluded. First operand 425 states and 635 transitions. Second operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,485 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. Second operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,495 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2022-02-21 04:21:49,495 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,496 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:49,496 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:49,497 INFO L74 IsIncluded]: Start isIncluded. First operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 635 transitions. [2022-02-21 04:21:49,498 INFO L87 Difference]: Start difference. First operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 635 transitions. [2022-02-21 04:21:49,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:49,508 INFO L93 Difference]: Finished difference Result 425 states and 635 transitions. [2022-02-21 04:21:49,509 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,509 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:49,509 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:49,509 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:49,510 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:49,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4941176470588236) internal successors, (635), 424 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:49,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 635 transitions. [2022-02-21 04:21:49,521 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-02-21 04:21:49,521 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 635 transitions. [2022-02-21 04:21:49,521 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:49,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 635 transitions. [2022-02-21 04:21:49,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:49,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:49,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:49,525 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:49,525 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:49,525 INFO L791 eck$LassoCheckResult]: Stem: 4712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4623#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4376#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4377#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4432#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4678#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4382#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4383#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4506#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4414#L514 assume !(0 == ~M_E~0); 4415#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4694#L519-1 assume !(0 == ~T2_E~0); 4368#L524-1 assume !(0 == ~T3_E~0); 4369#L529-1 assume !(0 == ~T4_E~0); 4484#L534-1 assume !(0 == ~E_M~0); 4660#L539-1 assume !(0 == ~E_1~0); 4661#L544-1 assume !(0 == ~E_2~0); 4676#L549-1 assume !(0 == ~E_3~0); 4677#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4363#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4364#L250 assume 1 == ~m_pc~0; 4576#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4682#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4538#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4539#L637 assume !(0 != activate_threads_~tmp~1#1); 4370#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4371#L269 assume !(1 == ~t1_pc~0); 4308#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4307#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4502#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4503#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4535#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4536#L288 assume 1 == ~t2_pc~0; 4638#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4532#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4548#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4549#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4655#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4563#L307 assume !(1 == ~t3_pc~0); 4496#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4497#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4615#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4687#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4511#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4512#L326 assume 1 == ~t4_pc~0; 4701#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4322#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4561#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4659#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4656#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4657#L572 assume !(1 == ~M_E~0); 4683#L572-2 assume !(1 == ~T1_E~0); 4378#L577-1 assume !(1 == ~T2_E~0); 4379#L582-1 assume !(1 == ~T3_E~0); 4645#L587-1 assume !(1 == ~T4_E~0); 4651#L592-1 assume !(1 == ~E_M~0); 4313#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4314#L602-1 assume !(1 == ~E_2~0); 4528#L607-1 assume !(1 == ~E_3~0); 4529#L612-1 assume !(1 == ~E_4~0); 4482#L617-1 assume { :end_inline_reset_delta_events } true; 4483#L803-2 [2022-02-21 04:21:49,525 INFO L793 eck$LassoCheckResult]: Loop: 4483#L803-2 assume !false; 4625#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4406#L489 assume !false; 4601#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4564#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4422#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4479#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4711#L428 assume !(0 != eval_~tmp~0#1); 4709#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4634#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4600#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4543#L514-5 assume !(0 == ~T1_E~0); 4544#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4643#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4452#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4453#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4302#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4303#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4696#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4500#L554-3 assume !(0 == ~E_4~0); 4501#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4598#L250-18 assume 1 == ~m_pc~0; 4632#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4610#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4393#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4394#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4462#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4350#L269-18 assume 1 == ~t1_pc~0; 4352#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4424#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4425#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4478#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4586#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4488#L288-18 assume 1 == ~t2_pc~0; 4471#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4311#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4312#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4409#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4469#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4470#L307-18 assume 1 == ~t3_pc~0; 4530#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4440#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4504#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4450#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4451#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4665#L326-18 assume 1 == ~t4_pc~0; 4666#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4672#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4642#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4298#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4299#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4706#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4465#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4466#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4361#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4362#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4596#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4597#L597-3 assume !(1 == ~E_1~0); 4517#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4518#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4476#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4477#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4523#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4492#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4509#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4558#L822 assume !(0 == start_simulation_~tmp~3#1); 4560#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4662#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4605#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4562#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4334#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4335#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4602#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4619#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4483#L803-2 [2022-02-21 04:21:49,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:49,526 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2022-02-21 04:21:49,527 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:49,527 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295480977] [2022-02-21 04:21:49,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:49,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:49,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:49,563 INFO L290 TraceCheckUtils]: 0: Hoare triple {5566#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {5566#true} is VALID [2022-02-21 04:21:49,564 INFO L290 TraceCheckUtils]: 1: Hoare triple {5566#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,564 INFO L290 TraceCheckUtils]: 2: Hoare triple {5568#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,565 INFO L290 TraceCheckUtils]: 3: Hoare triple {5568#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,565 INFO L290 TraceCheckUtils]: 4: Hoare triple {5568#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,565 INFO L290 TraceCheckUtils]: 5: Hoare triple {5568#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,566 INFO L290 TraceCheckUtils]: 6: Hoare triple {5568#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,566 INFO L290 TraceCheckUtils]: 7: Hoare triple {5568#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {5568#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:49,566 INFO L290 TraceCheckUtils]: 8: Hoare triple {5568#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {5567#false} is VALID [2022-02-21 04:21:49,567 INFO L290 TraceCheckUtils]: 9: Hoare triple {5567#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {5567#false} is VALID [2022-02-21 04:21:49,567 INFO L290 TraceCheckUtils]: 10: Hoare triple {5567#false} assume !(0 == ~M_E~0); {5567#false} is VALID [2022-02-21 04:21:49,567 INFO L290 TraceCheckUtils]: 11: Hoare triple {5567#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {5567#false} is VALID [2022-02-21 04:21:49,567 INFO L290 TraceCheckUtils]: 12: Hoare triple {5567#false} assume !(0 == ~T2_E~0); {5567#false} is VALID [2022-02-21 04:21:49,567 INFO L290 TraceCheckUtils]: 13: Hoare triple {5567#false} assume !(0 == ~T3_E~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 14: Hoare triple {5567#false} assume !(0 == ~T4_E~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 15: Hoare triple {5567#false} assume !(0 == ~E_M~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 16: Hoare triple {5567#false} assume !(0 == ~E_1~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 17: Hoare triple {5567#false} assume !(0 == ~E_2~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 18: Hoare triple {5567#false} assume !(0 == ~E_3~0); {5567#false} is VALID [2022-02-21 04:21:49,568 INFO L290 TraceCheckUtils]: 19: Hoare triple {5567#false} assume 0 == ~E_4~0;~E_4~0 := 1; {5567#false} is VALID [2022-02-21 04:21:49,569 INFO L290 TraceCheckUtils]: 20: Hoare triple {5567#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5567#false} is VALID [2022-02-21 04:21:49,569 INFO L290 TraceCheckUtils]: 21: Hoare triple {5567#false} assume 1 == ~m_pc~0; {5567#false} is VALID [2022-02-21 04:21:49,569 INFO L290 TraceCheckUtils]: 22: Hoare triple {5567#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {5567#false} is VALID [2022-02-21 04:21:49,569 INFO L290 TraceCheckUtils]: 23: Hoare triple {5567#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5567#false} is VALID [2022-02-21 04:21:49,569 INFO L290 TraceCheckUtils]: 24: Hoare triple {5567#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 25: Hoare triple {5567#false} assume !(0 != activate_threads_~tmp~1#1); {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 26: Hoare triple {5567#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 27: Hoare triple {5567#false} assume !(1 == ~t1_pc~0); {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 28: Hoare triple {5567#false} is_transmit1_triggered_~__retres1~1#1 := 0; {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 29: Hoare triple {5567#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5567#false} is VALID [2022-02-21 04:21:49,570 INFO L290 TraceCheckUtils]: 30: Hoare triple {5567#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 31: Hoare triple {5567#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 32: Hoare triple {5567#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 33: Hoare triple {5567#false} assume 1 == ~t2_pc~0; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 34: Hoare triple {5567#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 35: Hoare triple {5567#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5567#false} is VALID [2022-02-21 04:21:49,571 INFO L290 TraceCheckUtils]: 36: Hoare triple {5567#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 37: Hoare triple {5567#false} assume !(0 != activate_threads_~tmp___1~0#1); {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 38: Hoare triple {5567#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 39: Hoare triple {5567#false} assume !(1 == ~t3_pc~0); {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 40: Hoare triple {5567#false} is_transmit3_triggered_~__retres1~3#1 := 0; {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 41: Hoare triple {5567#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5567#false} is VALID [2022-02-21 04:21:49,572 INFO L290 TraceCheckUtils]: 42: Hoare triple {5567#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 43: Hoare triple {5567#false} assume !(0 != activate_threads_~tmp___2~0#1); {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 44: Hoare triple {5567#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 45: Hoare triple {5567#false} assume 1 == ~t4_pc~0; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 46: Hoare triple {5567#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 47: Hoare triple {5567#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 48: Hoare triple {5567#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5567#false} is VALID [2022-02-21 04:21:49,573 INFO L290 TraceCheckUtils]: 49: Hoare triple {5567#false} assume !(0 != activate_threads_~tmp___3~0#1); {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 50: Hoare triple {5567#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 51: Hoare triple {5567#false} assume !(1 == ~M_E~0); {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 52: Hoare triple {5567#false} assume !(1 == ~T1_E~0); {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 53: Hoare triple {5567#false} assume !(1 == ~T2_E~0); {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 54: Hoare triple {5567#false} assume !(1 == ~T3_E~0); {5567#false} is VALID [2022-02-21 04:21:49,574 INFO L290 TraceCheckUtils]: 55: Hoare triple {5567#false} assume !(1 == ~T4_E~0); {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 56: Hoare triple {5567#false} assume !(1 == ~E_M~0); {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 57: Hoare triple {5567#false} assume 1 == ~E_1~0;~E_1~0 := 2; {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 58: Hoare triple {5567#false} assume !(1 == ~E_2~0); {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 59: Hoare triple {5567#false} assume !(1 == ~E_3~0); {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 60: Hoare triple {5567#false} assume !(1 == ~E_4~0); {5567#false} is VALID [2022-02-21 04:21:49,575 INFO L290 TraceCheckUtils]: 61: Hoare triple {5567#false} assume { :end_inline_reset_delta_events } true; {5567#false} is VALID [2022-02-21 04:21:49,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:49,576 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:49,576 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295480977] [2022-02-21 04:21:49,576 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295480977] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:49,577 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:49,577 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:49,577 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1364149393] [2022-02-21 04:21:49,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:49,577 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:49,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:49,578 INFO L85 PathProgramCache]: Analyzing trace with hash 1505824877, now seen corresponding path program 1 times [2022-02-21 04:21:49,578 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:49,578 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655447280] [2022-02-21 04:21:49,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:49,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:49,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:49,610 INFO L290 TraceCheckUtils]: 0: Hoare triple {5569#true} assume !false; {5569#true} is VALID [2022-02-21 04:21:49,611 INFO L290 TraceCheckUtils]: 1: Hoare triple {5569#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {5569#true} is VALID [2022-02-21 04:21:49,611 INFO L290 TraceCheckUtils]: 2: Hoare triple {5569#true} assume !false; {5569#true} is VALID [2022-02-21 04:21:49,611 INFO L290 TraceCheckUtils]: 3: Hoare triple {5569#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5569#true} is VALID [2022-02-21 04:21:49,611 INFO L290 TraceCheckUtils]: 4: Hoare triple {5569#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5569#true} is VALID [2022-02-21 04:21:49,611 INFO L290 TraceCheckUtils]: 5: Hoare triple {5569#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 6: Hoare triple {5569#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 7: Hoare triple {5569#true} assume !(0 != eval_~tmp~0#1); {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 8: Hoare triple {5569#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 9: Hoare triple {5569#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 10: Hoare triple {5569#true} assume 0 == ~M_E~0;~M_E~0 := 1; {5569#true} is VALID [2022-02-21 04:21:49,612 INFO L290 TraceCheckUtils]: 11: Hoare triple {5569#true} assume !(0 == ~T1_E~0); {5569#true} is VALID [2022-02-21 04:21:49,613 INFO L290 TraceCheckUtils]: 12: Hoare triple {5569#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {5569#true} is VALID [2022-02-21 04:21:49,613 INFO L290 TraceCheckUtils]: 13: Hoare triple {5569#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {5569#true} is VALID [2022-02-21 04:21:49,613 INFO L290 TraceCheckUtils]: 14: Hoare triple {5569#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {5569#true} is VALID [2022-02-21 04:21:49,613 INFO L290 TraceCheckUtils]: 15: Hoare triple {5569#true} assume 0 == ~E_M~0;~E_M~0 := 1; {5569#true} is VALID [2022-02-21 04:21:49,613 INFO L290 TraceCheckUtils]: 16: Hoare triple {5569#true} assume 0 == ~E_1~0;~E_1~0 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,617 INFO L290 TraceCheckUtils]: 17: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,618 INFO L290 TraceCheckUtils]: 18: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,618 INFO L290 TraceCheckUtils]: 19: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,619 INFO L290 TraceCheckUtils]: 20: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,619 INFO L290 TraceCheckUtils]: 21: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,620 INFO L290 TraceCheckUtils]: 22: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,620 INFO L290 TraceCheckUtils]: 23: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,620 INFO L290 TraceCheckUtils]: 24: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,621 INFO L290 TraceCheckUtils]: 25: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,621 INFO L290 TraceCheckUtils]: 26: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,622 INFO L290 TraceCheckUtils]: 27: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t1_pc~0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,622 INFO L290 TraceCheckUtils]: 28: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,622 INFO L290 TraceCheckUtils]: 29: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,623 INFO L290 TraceCheckUtils]: 30: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,623 INFO L290 TraceCheckUtils]: 31: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,624 INFO L290 TraceCheckUtils]: 32: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,624 INFO L290 TraceCheckUtils]: 33: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,624 INFO L290 TraceCheckUtils]: 34: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,625 INFO L290 TraceCheckUtils]: 35: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,626 INFO L290 TraceCheckUtils]: 36: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,627 INFO L290 TraceCheckUtils]: 37: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,628 INFO L290 TraceCheckUtils]: 38: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,632 INFO L290 TraceCheckUtils]: 39: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t3_pc~0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,633 INFO L290 TraceCheckUtils]: 40: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,633 INFO L290 TraceCheckUtils]: 41: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,633 INFO L290 TraceCheckUtils]: 42: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,634 INFO L290 TraceCheckUtils]: 43: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,635 INFO L290 TraceCheckUtils]: 44: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,636 INFO L290 TraceCheckUtils]: 45: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,636 INFO L290 TraceCheckUtils]: 46: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,639 INFO L290 TraceCheckUtils]: 47: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,640 INFO L290 TraceCheckUtils]: 48: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,640 INFO L290 TraceCheckUtils]: 49: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,641 INFO L290 TraceCheckUtils]: 50: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,641 INFO L290 TraceCheckUtils]: 51: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,642 INFO L290 TraceCheckUtils]: 52: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,642 INFO L290 TraceCheckUtils]: 53: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,642 INFO L290 TraceCheckUtils]: 54: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,643 INFO L290 TraceCheckUtils]: 55: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,643 INFO L290 TraceCheckUtils]: 56: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {5571#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 57: Hoare triple {5571#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 58: Hoare triple {5570#false} assume 1 == ~E_2~0;~E_2~0 := 2; {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 59: Hoare triple {5570#false} assume 1 == ~E_3~0;~E_3~0 := 2; {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 60: Hoare triple {5570#false} assume 1 == ~E_4~0;~E_4~0 := 2; {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 61: Hoare triple {5570#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 62: Hoare triple {5570#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5570#false} is VALID [2022-02-21 04:21:49,644 INFO L290 TraceCheckUtils]: 63: Hoare triple {5570#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 64: Hoare triple {5570#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 65: Hoare triple {5570#false} assume !(0 == start_simulation_~tmp~3#1); {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 66: Hoare triple {5570#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 67: Hoare triple {5570#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 68: Hoare triple {5570#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {5570#false} is VALID [2022-02-21 04:21:49,645 INFO L290 TraceCheckUtils]: 69: Hoare triple {5570#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {5570#false} is VALID [2022-02-21 04:21:49,646 INFO L290 TraceCheckUtils]: 70: Hoare triple {5570#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {5570#false} is VALID [2022-02-21 04:21:49,646 INFO L290 TraceCheckUtils]: 71: Hoare triple {5570#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {5570#false} is VALID [2022-02-21 04:21:49,646 INFO L290 TraceCheckUtils]: 72: Hoare triple {5570#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {5570#false} is VALID [2022-02-21 04:21:49,646 INFO L290 TraceCheckUtils]: 73: Hoare triple {5570#false} assume !(0 != start_simulation_~tmp___0~1#1); {5570#false} is VALID [2022-02-21 04:21:49,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:49,647 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:49,647 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [655447280] [2022-02-21 04:21:49,647 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [655447280] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:49,647 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:49,647 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:49,647 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1830281718] [2022-02-21 04:21:49,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:49,648 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:49,648 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:49,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:49,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:49,649 INFO L87 Difference]: Start difference. First operand 425 states and 635 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,029 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2022-02-21 04:21:50,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:50,029 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,079 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:50,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:50,103 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 634 transitions. [2022-02-21 04:21:50,104 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-02-21 04:21:50,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-02-21 04:21:50,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,105 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:50,105 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-02-21 04:21:50,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-02-21 04:21:50,110 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:50,111 INFO L82 GeneralOperation]: Start isEquivalent. First operand 425 states and 634 transitions. Second operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,112 INFO L74 IsIncluded]: Start isIncluded. First operand 425 states and 634 transitions. Second operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,113 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. Second operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,123 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2022-02-21 04:21:50,123 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,123 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,124 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,125 INFO L74 IsIncluded]: Start isIncluded. First operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 634 transitions. [2022-02-21 04:21:50,125 INFO L87 Difference]: Start difference. First operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 634 transitions. [2022-02-21 04:21:50,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,136 INFO L93 Difference]: Finished difference Result 425 states and 634 transitions. [2022-02-21 04:21:50,136 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,137 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,138 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,138 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:50,138 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:50,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.4917647058823529) internal successors, (634), 424 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 634 transitions. [2022-02-21 04:21:50,149 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-02-21 04:21:50,149 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 634 transitions. [2022-02-21 04:21:50,149 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:50,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 634 transitions. [2022-02-21 04:21:50,151 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:50,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:50,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:50,152 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,152 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,153 INFO L791 eck$LassoCheckResult]: Stem: 6421#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 6414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 6332#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6085#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6086#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 6141#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6387#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6091#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6092#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6214#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6123#L514 assume !(0 == ~M_E~0); 6124#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6403#L519-1 assume !(0 == ~T2_E~0); 6077#L524-1 assume !(0 == ~T3_E~0); 6078#L529-1 assume !(0 == ~T4_E~0); 6193#L534-1 assume !(0 == ~E_M~0); 6369#L539-1 assume !(0 == ~E_1~0); 6370#L544-1 assume !(0 == ~E_2~0); 6385#L549-1 assume !(0 == ~E_3~0); 6386#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 6072#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6073#L250 assume 1 == ~m_pc~0; 6282#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6391#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6247#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6248#L637 assume !(0 != activate_threads_~tmp~1#1); 6079#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6080#L269 assume !(1 == ~t1_pc~0); 6017#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6016#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6211#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6212#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6244#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6245#L288 assume 1 == ~t2_pc~0; 6347#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6241#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6257#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6258#L653 assume !(0 != activate_threads_~tmp___1~0#1); 6364#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6271#L307 assume !(1 == ~t3_pc~0); 6205#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6206#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6322#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6396#L661 assume !(0 != activate_threads_~tmp___2~0#1); 6220#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6221#L326 assume 1 == ~t4_pc~0; 6410#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6031#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6267#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6368#L669 assume !(0 != activate_threads_~tmp___3~0#1); 6365#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6366#L572 assume !(1 == ~M_E~0); 6392#L572-2 assume !(1 == ~T1_E~0); 6087#L577-1 assume !(1 == ~T2_E~0); 6088#L582-1 assume !(1 == ~T3_E~0); 6353#L587-1 assume !(1 == ~T4_E~0); 6360#L592-1 assume !(1 == ~E_M~0); 6022#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6023#L602-1 assume !(1 == ~E_2~0); 6237#L607-1 assume !(1 == ~E_3~0); 6238#L612-1 assume !(1 == ~E_4~0); 6191#L617-1 assume { :end_inline_reset_delta_events } true; 6192#L803-2 [2022-02-21 04:21:50,153 INFO L793 eck$LassoCheckResult]: Loop: 6192#L803-2 assume !false; 6333#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6115#L489 assume !false; 6310#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6273#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6131#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6187#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6420#L428 assume !(0 != eval_~tmp~0#1); 6418#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6343#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6309#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6251#L514-5 assume !(0 == ~T1_E~0); 6252#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6351#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6161#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6162#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6011#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6012#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6405#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6209#L554-3 assume !(0 == ~E_4~0); 6210#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6307#L250-18 assume 1 == ~m_pc~0; 6341#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6319#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6102#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6103#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6171#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6059#L269-18 assume !(1 == ~t1_pc~0); 6060#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6133#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6134#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6188#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6295#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6197#L288-18 assume 1 == ~t2_pc~0; 6183#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6020#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6021#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6118#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6178#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6179#L307-18 assume !(1 == ~t3_pc~0); 6150#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 6151#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6213#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6159#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6160#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6374#L326-18 assume 1 == ~t4_pc~0; 6375#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6381#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6352#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6007#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6008#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6415#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6176#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6177#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6070#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6071#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6305#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6306#L597-3 assume !(1 == ~E_1~0); 6226#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6227#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6185#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6186#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6232#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6201#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6218#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 6268#L822 assume !(0 == start_simulation_~tmp~3#1); 6270#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6372#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 6314#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 6272#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 6043#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6044#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6312#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6328#L835 assume !(0 != start_simulation_~tmp___0~1#1); 6192#L803-2 [2022-02-21 04:21:50,153 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2022-02-21 04:21:50,154 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,154 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803824865] [2022-02-21 04:21:50,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,183 INFO L290 TraceCheckUtils]: 0: Hoare triple {7275#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,183 INFO L290 TraceCheckUtils]: 1: Hoare triple {7277#(<= 2 ~T1_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,184 INFO L290 TraceCheckUtils]: 2: Hoare triple {7277#(<= 2 ~T1_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,184 INFO L290 TraceCheckUtils]: 3: Hoare triple {7277#(<= 2 ~T1_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,184 INFO L290 TraceCheckUtils]: 4: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,185 INFO L290 TraceCheckUtils]: 5: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,185 INFO L290 TraceCheckUtils]: 6: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,185 INFO L290 TraceCheckUtils]: 7: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,186 INFO L290 TraceCheckUtils]: 8: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,186 INFO L290 TraceCheckUtils]: 9: Hoare triple {7277#(<= 2 ~T1_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,186 INFO L290 TraceCheckUtils]: 10: Hoare triple {7277#(<= 2 ~T1_E~0)} assume !(0 == ~M_E~0); {7277#(<= 2 ~T1_E~0)} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 11: Hoare triple {7277#(<= 2 ~T1_E~0)} assume 0 == ~T1_E~0;~T1_E~0 := 1; {7276#false} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 12: Hoare triple {7276#false} assume !(0 == ~T2_E~0); {7276#false} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 13: Hoare triple {7276#false} assume !(0 == ~T3_E~0); {7276#false} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 14: Hoare triple {7276#false} assume !(0 == ~T4_E~0); {7276#false} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 15: Hoare triple {7276#false} assume !(0 == ~E_M~0); {7276#false} is VALID [2022-02-21 04:21:50,187 INFO L290 TraceCheckUtils]: 16: Hoare triple {7276#false} assume !(0 == ~E_1~0); {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 17: Hoare triple {7276#false} assume !(0 == ~E_2~0); {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 18: Hoare triple {7276#false} assume !(0 == ~E_3~0); {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 19: Hoare triple {7276#false} assume 0 == ~E_4~0;~E_4~0 := 1; {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 20: Hoare triple {7276#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 21: Hoare triple {7276#false} assume 1 == ~m_pc~0; {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 22: Hoare triple {7276#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {7276#false} is VALID [2022-02-21 04:21:50,188 INFO L290 TraceCheckUtils]: 23: Hoare triple {7276#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 24: Hoare triple {7276#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 25: Hoare triple {7276#false} assume !(0 != activate_threads_~tmp~1#1); {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 26: Hoare triple {7276#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 27: Hoare triple {7276#false} assume !(1 == ~t1_pc~0); {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 28: Hoare triple {7276#false} is_transmit1_triggered_~__retres1~1#1 := 0; {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 29: Hoare triple {7276#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7276#false} is VALID [2022-02-21 04:21:50,189 INFO L290 TraceCheckUtils]: 30: Hoare triple {7276#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 31: Hoare triple {7276#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 32: Hoare triple {7276#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 33: Hoare triple {7276#false} assume 1 == ~t2_pc~0; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 34: Hoare triple {7276#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 35: Hoare triple {7276#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 36: Hoare triple {7276#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {7276#false} is VALID [2022-02-21 04:21:50,190 INFO L290 TraceCheckUtils]: 37: Hoare triple {7276#false} assume !(0 != activate_threads_~tmp___1~0#1); {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 38: Hoare triple {7276#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 39: Hoare triple {7276#false} assume !(1 == ~t3_pc~0); {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 40: Hoare triple {7276#false} is_transmit3_triggered_~__retres1~3#1 := 0; {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 41: Hoare triple {7276#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 42: Hoare triple {7276#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {7276#false} is VALID [2022-02-21 04:21:50,191 INFO L290 TraceCheckUtils]: 43: Hoare triple {7276#false} assume !(0 != activate_threads_~tmp___2~0#1); {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 44: Hoare triple {7276#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 45: Hoare triple {7276#false} assume 1 == ~t4_pc~0; {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 46: Hoare triple {7276#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 47: Hoare triple {7276#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 48: Hoare triple {7276#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 49: Hoare triple {7276#false} assume !(0 != activate_threads_~tmp___3~0#1); {7276#false} is VALID [2022-02-21 04:21:50,192 INFO L290 TraceCheckUtils]: 50: Hoare triple {7276#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 51: Hoare triple {7276#false} assume !(1 == ~M_E~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 52: Hoare triple {7276#false} assume !(1 == ~T1_E~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 53: Hoare triple {7276#false} assume !(1 == ~T2_E~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 54: Hoare triple {7276#false} assume !(1 == ~T3_E~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 55: Hoare triple {7276#false} assume !(1 == ~T4_E~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 56: Hoare triple {7276#false} assume !(1 == ~E_M~0); {7276#false} is VALID [2022-02-21 04:21:50,193 INFO L290 TraceCheckUtils]: 57: Hoare triple {7276#false} assume 1 == ~E_1~0;~E_1~0 := 2; {7276#false} is VALID [2022-02-21 04:21:50,194 INFO L290 TraceCheckUtils]: 58: Hoare triple {7276#false} assume !(1 == ~E_2~0); {7276#false} is VALID [2022-02-21 04:21:50,194 INFO L290 TraceCheckUtils]: 59: Hoare triple {7276#false} assume !(1 == ~E_3~0); {7276#false} is VALID [2022-02-21 04:21:50,194 INFO L290 TraceCheckUtils]: 60: Hoare triple {7276#false} assume !(1 == ~E_4~0); {7276#false} is VALID [2022-02-21 04:21:50,194 INFO L290 TraceCheckUtils]: 61: Hoare triple {7276#false} assume { :end_inline_reset_delta_events } true; {7276#false} is VALID [2022-02-21 04:21:50,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,195 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,195 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803824865] [2022-02-21 04:21:50,195 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803824865] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,195 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,195 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:50,195 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156212237] [2022-02-21 04:21:50,196 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,196 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:50,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,197 INFO L85 PathProgramCache]: Analyzing trace with hash 663831791, now seen corresponding path program 1 times [2022-02-21 04:21:50,197 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,197 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1540159537] [2022-02-21 04:21:50,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,223 INFO L290 TraceCheckUtils]: 0: Hoare triple {7278#true} assume !false; {7278#true} is VALID [2022-02-21 04:21:50,223 INFO L290 TraceCheckUtils]: 1: Hoare triple {7278#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7278#true} is VALID [2022-02-21 04:21:50,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {7278#true} assume !false; {7278#true} is VALID [2022-02-21 04:21:50,223 INFO L290 TraceCheckUtils]: 3: Hoare triple {7278#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {7278#true} is VALID [2022-02-21 04:21:50,223 INFO L290 TraceCheckUtils]: 4: Hoare triple {7278#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {7278#true} is VALID [2022-02-21 04:21:50,224 INFO L290 TraceCheckUtils]: 5: Hoare triple {7278#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {7278#true} is VALID [2022-02-21 04:21:50,227 INFO L290 TraceCheckUtils]: 6: Hoare triple {7278#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 7: Hoare triple {7278#true} assume !(0 != eval_~tmp~0#1); {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 8: Hoare triple {7278#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 9: Hoare triple {7278#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 10: Hoare triple {7278#true} assume 0 == ~M_E~0;~M_E~0 := 1; {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 11: Hoare triple {7278#true} assume !(0 == ~T1_E~0); {7278#true} is VALID [2022-02-21 04:21:50,228 INFO L290 TraceCheckUtils]: 12: Hoare triple {7278#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {7278#true} is VALID [2022-02-21 04:21:50,229 INFO L290 TraceCheckUtils]: 13: Hoare triple {7278#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {7278#true} is VALID [2022-02-21 04:21:50,229 INFO L290 TraceCheckUtils]: 14: Hoare triple {7278#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {7278#true} is VALID [2022-02-21 04:21:50,229 INFO L290 TraceCheckUtils]: 15: Hoare triple {7278#true} assume 0 == ~E_M~0;~E_M~0 := 1; {7278#true} is VALID [2022-02-21 04:21:50,229 INFO L290 TraceCheckUtils]: 16: Hoare triple {7278#true} assume 0 == ~E_1~0;~E_1~0 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,230 INFO L290 TraceCheckUtils]: 17: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,230 INFO L290 TraceCheckUtils]: 18: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 19: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 20: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,231 INFO L290 TraceCheckUtils]: 21: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,232 INFO L290 TraceCheckUtils]: 22: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,232 INFO L290 TraceCheckUtils]: 23: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 24: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 25: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,233 INFO L290 TraceCheckUtils]: 26: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 27: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,234 INFO L290 TraceCheckUtils]: 28: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 29: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 30: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,235 INFO L290 TraceCheckUtils]: 31: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 32: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,236 INFO L290 TraceCheckUtils]: 33: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 34: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 35: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,237 INFO L290 TraceCheckUtils]: 36: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 37: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,238 INFO L290 TraceCheckUtils]: 38: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 39: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 40: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,239 INFO L290 TraceCheckUtils]: 41: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 42: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,240 INFO L290 TraceCheckUtils]: 43: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,241 INFO L290 TraceCheckUtils]: 44: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,241 INFO L290 TraceCheckUtils]: 45: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,241 INFO L290 TraceCheckUtils]: 46: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,242 INFO L290 TraceCheckUtils]: 47: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,242 INFO L290 TraceCheckUtils]: 48: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,242 INFO L290 TraceCheckUtils]: 49: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,243 INFO L290 TraceCheckUtils]: 50: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,243 INFO L290 TraceCheckUtils]: 51: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,244 INFO L290 TraceCheckUtils]: 52: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,244 INFO L290 TraceCheckUtils]: 53: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,244 INFO L290 TraceCheckUtils]: 54: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,245 INFO L290 TraceCheckUtils]: 55: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,245 INFO L290 TraceCheckUtils]: 56: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {7280#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 57: Hoare triple {7280#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 58: Hoare triple {7279#false} assume 1 == ~E_2~0;~E_2~0 := 2; {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 59: Hoare triple {7279#false} assume 1 == ~E_3~0;~E_3~0 := 2; {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 60: Hoare triple {7279#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 61: Hoare triple {7279#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 62: Hoare triple {7279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {7279#false} is VALID [2022-02-21 04:21:50,246 INFO L290 TraceCheckUtils]: 63: Hoare triple {7279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 64: Hoare triple {7279#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 65: Hoare triple {7279#false} assume !(0 == start_simulation_~tmp~3#1); {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 66: Hoare triple {7279#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 67: Hoare triple {7279#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 68: Hoare triple {7279#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {7279#false} is VALID [2022-02-21 04:21:50,247 INFO L290 TraceCheckUtils]: 69: Hoare triple {7279#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {7279#false} is VALID [2022-02-21 04:21:50,248 INFO L290 TraceCheckUtils]: 70: Hoare triple {7279#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {7279#false} is VALID [2022-02-21 04:21:50,248 INFO L290 TraceCheckUtils]: 71: Hoare triple {7279#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7279#false} is VALID [2022-02-21 04:21:50,248 INFO L290 TraceCheckUtils]: 72: Hoare triple {7279#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {7279#false} is VALID [2022-02-21 04:21:50,248 INFO L290 TraceCheckUtils]: 73: Hoare triple {7279#false} assume !(0 != start_simulation_~tmp___0~1#1); {7279#false} is VALID [2022-02-21 04:21:50,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,249 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,249 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1540159537] [2022-02-21 04:21:50,249 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1540159537] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,249 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,250 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:50,250 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503611009] [2022-02-21 04:21:50,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,258 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:50,258 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:50,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:50,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:50,259 INFO L87 Difference]: Start difference. First operand 425 states and 634 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,634 INFO L93 Difference]: Finished difference Result 425 states and 629 transitions. [2022-02-21 04:21:50,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:50,634 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,676 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:50,679 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:50,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 425 states to 425 states and 629 transitions. [2022-02-21 04:21:50,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 425 [2022-02-21 04:21:50,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 425 [2022-02-21 04:21:50,702 INFO L73 IsDeterministic]: Start isDeterministic. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:50,703 INFO L681 BuchiCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-02-21 04:21:50,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 425 to 425. [2022-02-21 04:21:50,708 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:50,709 INFO L82 GeneralOperation]: Start isEquivalent. First operand 425 states and 629 transitions. Second operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,709 INFO L74 IsIncluded]: Start isIncluded. First operand 425 states and 629 transitions. Second operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,710 INFO L87 Difference]: Start difference. First operand 425 states and 629 transitions. Second operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,720 INFO L93 Difference]: Finished difference Result 425 states and 629 transitions. [2022-02-21 04:21:50,720 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,722 INFO L74 IsIncluded]: Start isIncluded. First operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 629 transitions. [2022-02-21 04:21:50,723 INFO L87 Difference]: Start difference. First operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 425 states and 629 transitions. [2022-02-21 04:21:50,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:50,735 INFO L93 Difference]: Finished difference Result 425 states and 629 transitions. [2022-02-21 04:21:50,735 INFO L276 IsEmpty]: Start isEmpty. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,735 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:50,736 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:50,736 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:50,736 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:50,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 425 states, 425 states have (on average 1.48) internal successors, (629), 424 states have internal predecessors, (629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:50,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 425 states to 425 states and 629 transitions. [2022-02-21 04:21:50,747 INFO L704 BuchiCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-02-21 04:21:50,747 INFO L587 BuchiCegarLoop]: Abstraction has 425 states and 629 transitions. [2022-02-21 04:21:50,747 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:50,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 425 states and 629 transitions. [2022-02-21 04:21:50,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 358 [2022-02-21 04:21:50,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:50,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:50,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:50,752 INFO L791 eck$LassoCheckResult]: Stem: 8130#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 8123#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8041#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7794#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7795#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7850#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8096#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7800#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7801#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7923#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7832#L514 assume !(0 == ~M_E~0); 7833#L514-2 assume !(0 == ~T1_E~0); 8112#L519-1 assume !(0 == ~T2_E~0); 7786#L524-1 assume !(0 == ~T3_E~0); 7787#L529-1 assume !(0 == ~T4_E~0); 7902#L534-1 assume !(0 == ~E_M~0); 8078#L539-1 assume !(0 == ~E_1~0); 8079#L544-1 assume !(0 == ~E_2~0); 8094#L549-1 assume !(0 == ~E_3~0); 8095#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7781#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7782#L250 assume 1 == ~m_pc~0; 7991#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8100#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7956#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7957#L637 assume !(0 != activate_threads_~tmp~1#1); 7788#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7789#L269 assume !(1 == ~t1_pc~0); 7726#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7725#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7920#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7921#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7953#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7954#L288 assume 1 == ~t2_pc~0; 8056#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7950#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7966#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7967#L653 assume !(0 != activate_threads_~tmp___1~0#1); 8073#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7980#L307 assume !(1 == ~t3_pc~0); 7914#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7915#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8031#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8105#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7929#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7930#L326 assume 1 == ~t4_pc~0; 8119#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7740#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7976#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8077#L669 assume !(0 != activate_threads_~tmp___3~0#1); 8074#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8075#L572 assume !(1 == ~M_E~0); 8101#L572-2 assume !(1 == ~T1_E~0); 7796#L577-1 assume !(1 == ~T2_E~0); 7797#L582-1 assume !(1 == ~T3_E~0); 8062#L587-1 assume !(1 == ~T4_E~0); 8069#L592-1 assume !(1 == ~E_M~0); 7731#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7732#L602-1 assume !(1 == ~E_2~0); 7946#L607-1 assume !(1 == ~E_3~0); 7947#L612-1 assume !(1 == ~E_4~0); 7900#L617-1 assume { :end_inline_reset_delta_events } true; 7901#L803-2 [2022-02-21 04:21:50,753 INFO L793 eck$LassoCheckResult]: Loop: 7901#L803-2 assume !false; 8042#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7824#L489 assume !false; 8019#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7982#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7840#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7896#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8129#L428 assume !(0 != eval_~tmp~0#1); 8127#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8052#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8018#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7960#L514-5 assume !(0 == ~T1_E~0); 7961#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8060#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7870#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7871#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7720#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7721#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8114#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7918#L554-3 assume !(0 == ~E_4~0); 7919#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8016#L250-18 assume 1 == ~m_pc~0; 8050#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8028#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7811#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7812#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7880#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7768#L269-18 assume !(1 == ~t1_pc~0); 7769#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 7842#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7843#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7897#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8004#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7906#L288-18 assume 1 == ~t2_pc~0; 7892#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7729#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7730#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7827#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7887#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7888#L307-18 assume !(1 == ~t3_pc~0); 7859#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7860#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7922#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7868#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7869#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8083#L326-18 assume 1 == ~t4_pc~0; 8084#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8090#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8061#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7716#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7717#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8124#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7885#L572-5 assume !(1 == ~T1_E~0); 7886#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7779#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7780#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8014#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8015#L597-3 assume !(1 == ~E_1~0); 7935#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7936#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7894#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7895#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7941#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7910#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7927#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7977#L822 assume !(0 == start_simulation_~tmp~3#1); 7979#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8081#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8023#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7981#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 7752#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7753#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8021#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8037#L835 assume !(0 != start_simulation_~tmp___0~1#1); 7901#L803-2 [2022-02-21 04:21:50,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,753 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2022-02-21 04:21:50,754 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,754 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [877864224] [2022-02-21 04:21:50,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,800 INFO L290 TraceCheckUtils]: 0: Hoare triple {8984#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,801 INFO L290 TraceCheckUtils]: 1: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,802 INFO L290 TraceCheckUtils]: 2: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,802 INFO L290 TraceCheckUtils]: 3: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,802 INFO L290 TraceCheckUtils]: 4: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,803 INFO L290 TraceCheckUtils]: 5: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,803 INFO L290 TraceCheckUtils]: 6: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,803 INFO L290 TraceCheckUtils]: 7: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,804 INFO L290 TraceCheckUtils]: 8: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,805 INFO L290 TraceCheckUtils]: 9: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8986#(= ~E_4~0 ~M_E~0)} is VALID [2022-02-21 04:21:50,806 INFO L290 TraceCheckUtils]: 10: Hoare triple {8986#(= ~E_4~0 ~M_E~0)} assume !(0 == ~M_E~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,806 INFO L290 TraceCheckUtils]: 11: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~T1_E~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,806 INFO L290 TraceCheckUtils]: 12: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~T2_E~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,807 INFO L290 TraceCheckUtils]: 13: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~T3_E~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,807 INFO L290 TraceCheckUtils]: 14: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~T4_E~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,808 INFO L290 TraceCheckUtils]: 15: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~E_M~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,810 INFO L290 TraceCheckUtils]: 16: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~E_1~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,810 INFO L290 TraceCheckUtils]: 17: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~E_2~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,811 INFO L290 TraceCheckUtils]: 18: Hoare triple {8987#(not (= ~E_4~0 0))} assume !(0 == ~E_3~0); {8987#(not (= ~E_4~0 0))} is VALID [2022-02-21 04:21:50,811 INFO L290 TraceCheckUtils]: 19: Hoare triple {8987#(not (= ~E_4~0 0))} assume 0 == ~E_4~0;~E_4~0 := 1; {8985#false} is VALID [2022-02-21 04:21:50,811 INFO L290 TraceCheckUtils]: 20: Hoare triple {8985#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8985#false} is VALID [2022-02-21 04:21:50,811 INFO L290 TraceCheckUtils]: 21: Hoare triple {8985#false} assume 1 == ~m_pc~0; {8985#false} is VALID [2022-02-21 04:21:50,811 INFO L290 TraceCheckUtils]: 22: Hoare triple {8985#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 23: Hoare triple {8985#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 24: Hoare triple {8985#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 25: Hoare triple {8985#false} assume !(0 != activate_threads_~tmp~1#1); {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 26: Hoare triple {8985#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 27: Hoare triple {8985#false} assume !(1 == ~t1_pc~0); {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 28: Hoare triple {8985#false} is_transmit1_triggered_~__retres1~1#1 := 0; {8985#false} is VALID [2022-02-21 04:21:50,812 INFO L290 TraceCheckUtils]: 29: Hoare triple {8985#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 30: Hoare triple {8985#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 31: Hoare triple {8985#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 32: Hoare triple {8985#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 33: Hoare triple {8985#false} assume 1 == ~t2_pc~0; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 34: Hoare triple {8985#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8985#false} is VALID [2022-02-21 04:21:50,813 INFO L290 TraceCheckUtils]: 35: Hoare triple {8985#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 36: Hoare triple {8985#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 37: Hoare triple {8985#false} assume !(0 != activate_threads_~tmp___1~0#1); {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 38: Hoare triple {8985#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 39: Hoare triple {8985#false} assume !(1 == ~t3_pc~0); {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 40: Hoare triple {8985#false} is_transmit3_triggered_~__retres1~3#1 := 0; {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 41: Hoare triple {8985#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8985#false} is VALID [2022-02-21 04:21:50,814 INFO L290 TraceCheckUtils]: 42: Hoare triple {8985#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 43: Hoare triple {8985#false} assume !(0 != activate_threads_~tmp___2~0#1); {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 44: Hoare triple {8985#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 45: Hoare triple {8985#false} assume 1 == ~t4_pc~0; {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 46: Hoare triple {8985#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 47: Hoare triple {8985#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8985#false} is VALID [2022-02-21 04:21:50,815 INFO L290 TraceCheckUtils]: 48: Hoare triple {8985#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 49: Hoare triple {8985#false} assume !(0 != activate_threads_~tmp___3~0#1); {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 50: Hoare triple {8985#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 51: Hoare triple {8985#false} assume !(1 == ~M_E~0); {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 52: Hoare triple {8985#false} assume !(1 == ~T1_E~0); {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 53: Hoare triple {8985#false} assume !(1 == ~T2_E~0); {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 54: Hoare triple {8985#false} assume !(1 == ~T3_E~0); {8985#false} is VALID [2022-02-21 04:21:50,816 INFO L290 TraceCheckUtils]: 55: Hoare triple {8985#false} assume !(1 == ~T4_E~0); {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 56: Hoare triple {8985#false} assume !(1 == ~E_M~0); {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 57: Hoare triple {8985#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 58: Hoare triple {8985#false} assume !(1 == ~E_2~0); {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 59: Hoare triple {8985#false} assume !(1 == ~E_3~0); {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 60: Hoare triple {8985#false} assume !(1 == ~E_4~0); {8985#false} is VALID [2022-02-21 04:21:50,817 INFO L290 TraceCheckUtils]: 61: Hoare triple {8985#false} assume { :end_inline_reset_delta_events } true; {8985#false} is VALID [2022-02-21 04:21:50,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,818 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,818 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [877864224] [2022-02-21 04:21:50,818 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [877864224] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,818 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,819 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:50,819 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461892255] [2022-02-21 04:21:50,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:50,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:50,820 INFO L85 PathProgramCache]: Analyzing trace with hash 882686509, now seen corresponding path program 1 times [2022-02-21 04:21:50,820 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:50,820 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101763644] [2022-02-21 04:21:50,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:50,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:50,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:50,852 INFO L290 TraceCheckUtils]: 0: Hoare triple {8988#true} assume !false; {8988#true} is VALID [2022-02-21 04:21:50,852 INFO L290 TraceCheckUtils]: 1: Hoare triple {8988#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8988#true} is VALID [2022-02-21 04:21:50,852 INFO L290 TraceCheckUtils]: 2: Hoare triple {8988#true} assume !false; {8988#true} is VALID [2022-02-21 04:21:50,852 INFO L290 TraceCheckUtils]: 3: Hoare triple {8988#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8988#true} is VALID [2022-02-21 04:21:50,852 INFO L290 TraceCheckUtils]: 4: Hoare triple {8988#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 5: Hoare triple {8988#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 6: Hoare triple {8988#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 7: Hoare triple {8988#true} assume !(0 != eval_~tmp~0#1); {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 8: Hoare triple {8988#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 9: Hoare triple {8988#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8988#true} is VALID [2022-02-21 04:21:50,853 INFO L290 TraceCheckUtils]: 10: Hoare triple {8988#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 11: Hoare triple {8988#true} assume !(0 == ~T1_E~0); {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 12: Hoare triple {8988#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 13: Hoare triple {8988#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 14: Hoare triple {8988#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 15: Hoare triple {8988#true} assume 0 == ~E_M~0;~E_M~0 := 1; {8988#true} is VALID [2022-02-21 04:21:50,854 INFO L290 TraceCheckUtils]: 16: Hoare triple {8988#true} assume 0 == ~E_1~0;~E_1~0 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,855 INFO L290 TraceCheckUtils]: 17: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,855 INFO L290 TraceCheckUtils]: 18: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,856 INFO L290 TraceCheckUtils]: 19: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,856 INFO L290 TraceCheckUtils]: 20: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,857 INFO L290 TraceCheckUtils]: 21: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,857 INFO L290 TraceCheckUtils]: 22: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,858 INFO L290 TraceCheckUtils]: 23: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,858 INFO L290 TraceCheckUtils]: 24: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,858 INFO L290 TraceCheckUtils]: 25: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,859 INFO L290 TraceCheckUtils]: 26: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,859 INFO L290 TraceCheckUtils]: 27: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,860 INFO L290 TraceCheckUtils]: 28: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,860 INFO L290 TraceCheckUtils]: 29: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,860 INFO L290 TraceCheckUtils]: 30: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,861 INFO L290 TraceCheckUtils]: 31: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,861 INFO L290 TraceCheckUtils]: 32: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,862 INFO L290 TraceCheckUtils]: 33: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,862 INFO L290 TraceCheckUtils]: 34: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,862 INFO L290 TraceCheckUtils]: 35: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,863 INFO L290 TraceCheckUtils]: 36: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,863 INFO L290 TraceCheckUtils]: 37: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,863 INFO L290 TraceCheckUtils]: 38: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,864 INFO L290 TraceCheckUtils]: 39: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,864 INFO L290 TraceCheckUtils]: 40: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,865 INFO L290 TraceCheckUtils]: 41: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,865 INFO L290 TraceCheckUtils]: 42: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,865 INFO L290 TraceCheckUtils]: 43: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,866 INFO L290 TraceCheckUtils]: 44: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,866 INFO L290 TraceCheckUtils]: 45: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,867 INFO L290 TraceCheckUtils]: 46: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,867 INFO L290 TraceCheckUtils]: 47: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,867 INFO L290 TraceCheckUtils]: 48: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,868 INFO L290 TraceCheckUtils]: 49: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,868 INFO L290 TraceCheckUtils]: 50: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,868 INFO L290 TraceCheckUtils]: 51: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,869 INFO L290 TraceCheckUtils]: 52: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,869 INFO L290 TraceCheckUtils]: 53: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,870 INFO L290 TraceCheckUtils]: 54: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,870 INFO L290 TraceCheckUtils]: 55: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,870 INFO L290 TraceCheckUtils]: 56: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {8990#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:50,871 INFO L290 TraceCheckUtils]: 57: Hoare triple {8990#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {8989#false} is VALID [2022-02-21 04:21:50,871 INFO L290 TraceCheckUtils]: 58: Hoare triple {8989#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8989#false} is VALID [2022-02-21 04:21:50,871 INFO L290 TraceCheckUtils]: 59: Hoare triple {8989#false} assume 1 == ~E_3~0;~E_3~0 := 2; {8989#false} is VALID [2022-02-21 04:21:50,871 INFO L290 TraceCheckUtils]: 60: Hoare triple {8989#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8989#false} is VALID [2022-02-21 04:21:50,871 INFO L290 TraceCheckUtils]: 61: Hoare triple {8989#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 62: Hoare triple {8989#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 63: Hoare triple {8989#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 64: Hoare triple {8989#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 65: Hoare triple {8989#false} assume !(0 == start_simulation_~tmp~3#1); {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 66: Hoare triple {8989#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {8989#false} is VALID [2022-02-21 04:21:50,872 INFO L290 TraceCheckUtils]: 67: Hoare triple {8989#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 68: Hoare triple {8989#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 69: Hoare triple {8989#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 70: Hoare triple {8989#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 71: Hoare triple {8989#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 72: Hoare triple {8989#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {8989#false} is VALID [2022-02-21 04:21:50,873 INFO L290 TraceCheckUtils]: 73: Hoare triple {8989#false} assume !(0 != start_simulation_~tmp___0~1#1); {8989#false} is VALID [2022-02-21 04:21:50,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:50,874 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:50,875 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101763644] [2022-02-21 04:21:50,875 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101763644] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:50,875 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:50,875 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:50,875 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912837517] [2022-02-21 04:21:50,875 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:50,876 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:50,876 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:50,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:50,877 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:50,877 INFO L87 Difference]: Start difference. First operand 425 states and 629 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,834 INFO L93 Difference]: Finished difference Result 710 states and 1048 transitions. [2022-02-21 04:21:51,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:51,835 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,877 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:51,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 710 states and 1048 transitions. [2022-02-21 04:21:51,903 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-02-21 04:21:51,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 710 states to 710 states and 1048 transitions. [2022-02-21 04:21:51,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 710 [2022-02-21 04:21:51,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 710 [2022-02-21 04:21:51,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 710 states and 1048 transitions. [2022-02-21 04:21:51,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:51,929 INFO L681 BuchiCegarLoop]: Abstraction has 710 states and 1048 transitions. [2022-02-21 04:21:51,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 710 states and 1048 transitions. [2022-02-21 04:21:51,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 710 to 709. [2022-02-21 04:21:51,943 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:51,945 INFO L82 GeneralOperation]: Start isEquivalent. First operand 710 states and 1048 transitions. Second operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,946 INFO L74 IsIncluded]: Start isIncluded. First operand 710 states and 1048 transitions. Second operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,947 INFO L87 Difference]: Start difference. First operand 710 states and 1048 transitions. Second operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,970 INFO L93 Difference]: Finished difference Result 710 states and 1048 transitions. [2022-02-21 04:21:51,970 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 1048 transitions. [2022-02-21 04:21:51,971 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:51,971 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:51,973 INFO L74 IsIncluded]: Start isIncluded. First operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 710 states and 1048 transitions. [2022-02-21 04:21:51,974 INFO L87 Difference]: Start difference. First operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 710 states and 1048 transitions. [2022-02-21 04:21:51,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:51,997 INFO L93 Difference]: Finished difference Result 710 states and 1048 transitions. [2022-02-21 04:21:51,997 INFO L276 IsEmpty]: Start isEmpty. Operand 710 states and 1048 transitions. [2022-02-21 04:21:51,998 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:51,998 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:51,998 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:51,999 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:52,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 709 states, 709 states have (on average 1.4767277856135401) internal successors, (1047), 708 states have internal predecessors, (1047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 709 states to 709 states and 1047 transitions. [2022-02-21 04:21:52,023 INFO L704 BuchiCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-02-21 04:21:52,024 INFO L587 BuchiCegarLoop]: Abstraction has 709 states and 1047 transitions. [2022-02-21 04:21:52,024 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:52,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 709 states and 1047 transitions. [2022-02-21 04:21:52,027 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 632 [2022-02-21 04:21:52,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:52,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:52,030 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,030 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,030 INFO L791 eck$LassoCheckResult]: Stem: 10169#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10050#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9791#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9792#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 9847#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10113#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9797#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9798#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9923#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9829#L514 assume !(0 == ~M_E~0); 9830#L514-2 assume !(0 == ~T1_E~0); 10132#L519-1 assume !(0 == ~T2_E~0); 9783#L524-1 assume !(0 == ~T3_E~0); 9784#L529-1 assume !(0 == ~T4_E~0); 9901#L534-1 assume !(0 == ~E_M~0); 10091#L539-1 assume !(0 == ~E_1~0); 10092#L544-1 assume !(0 == ~E_2~0); 10109#L549-1 assume !(0 == ~E_3~0); 10110#L554-1 assume !(0 == ~E_4~0); 9778#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9779#L250 assume 1 == ~m_pc~0; 9997#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10116#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9955#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9956#L637 assume !(0 != activate_threads_~tmp~1#1); 9785#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9786#L269 assume !(1 == ~t1_pc~0); 9723#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9722#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9919#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9920#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9952#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9953#L288 assume 1 == ~t2_pc~0; 10068#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9949#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9965#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9966#L653 assume !(0 != activate_threads_~tmp___1~0#1); 10085#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9981#L307 assume !(1 == ~t3_pc~0); 9913#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9914#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10040#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10123#L661 assume !(0 != activate_threads_~tmp___2~0#1); 9928#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9929#L326 assume 1 == ~t4_pc~0; 10140#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9737#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9978#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10090#L669 assume !(0 != activate_threads_~tmp___3~0#1); 10087#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10088#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 10117#L572-2 assume !(1 == ~T1_E~0); 9793#L577-1 assume !(1 == ~T2_E~0); 9794#L582-1 assume !(1 == ~T3_E~0); 10075#L587-1 assume !(1 == ~T4_E~0); 10081#L592-1 assume !(1 == ~E_M~0); 9734#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9735#L602-1 assume !(1 == ~E_2~0); 9945#L607-1 assume !(1 == ~E_3~0); 9946#L612-1 assume !(1 == ~E_4~0); 9899#L617-1 assume { :end_inline_reset_delta_events } true; 9900#L803-2 [2022-02-21 04:21:52,031 INFO L793 eck$LassoCheckResult]: Loop: 9900#L803-2 assume !false; 10052#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9821#L489 assume !false; 10165#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10166#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 9895#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 9896#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10163#L428 assume !(0 != eval_~tmp~0#1); 10164#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10063#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10064#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10174#L514-5 assume !(0 == ~T1_E~0); 10329#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10328#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10327#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10326#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10325#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10324#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10323#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10322#L554-3 assume !(0 == ~E_4~0); 10321#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10320#L250-18 assume 1 == ~m_pc~0; 10318#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10317#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10316#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10315#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10314#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10313#L269-18 assume 1 == ~t1_pc~0; 10311#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10310#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10309#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10308#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10307#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10306#L288-18 assume 1 == ~t2_pc~0; 10304#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10303#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10302#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10301#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10300#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10299#L307-18 assume !(1 == ~t3_pc~0); 10297#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 10296#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10295#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10294#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10293#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10292#L326-18 assume 1 == ~t4_pc~0; 10290#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10289#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10288#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10287#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10286#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10285#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10167#L572-5 assume !(1 == ~T1_E~0); 10284#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10283#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10282#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10281#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10280#L597-3 assume !(1 == ~E_1~0); 10279#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10278#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10277#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9892#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10240#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10235#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10152#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 10153#L822 assume !(0 == start_simulation_~tmp~3#1); 10086#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 10093#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 10161#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 10162#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 9749#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9750#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10044#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 10045#L835 assume !(0 != start_simulation_~tmp___0~1#1); 9900#L803-2 [2022-02-21 04:21:52,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,031 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2022-02-21 04:21:52,032 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,032 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117968500] [2022-02-21 04:21:52,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,066 INFO L290 TraceCheckUtils]: 0: Hoare triple {11835#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,066 INFO L290 TraceCheckUtils]: 1: Hoare triple {11837#(= ~m_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,067 INFO L290 TraceCheckUtils]: 2: Hoare triple {11837#(= ~m_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,067 INFO L290 TraceCheckUtils]: 3: Hoare triple {11837#(= ~m_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,068 INFO L290 TraceCheckUtils]: 4: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,069 INFO L290 TraceCheckUtils]: 5: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,069 INFO L290 TraceCheckUtils]: 6: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,070 INFO L290 TraceCheckUtils]: 7: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,070 INFO L290 TraceCheckUtils]: 8: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,070 INFO L290 TraceCheckUtils]: 9: Hoare triple {11837#(= ~m_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,071 INFO L290 TraceCheckUtils]: 10: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~M_E~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,071 INFO L290 TraceCheckUtils]: 11: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~T1_E~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,090 INFO L290 TraceCheckUtils]: 12: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~T2_E~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,091 INFO L290 TraceCheckUtils]: 13: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~T3_E~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,091 INFO L290 TraceCheckUtils]: 14: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~T4_E~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,092 INFO L290 TraceCheckUtils]: 15: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~E_M~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,092 INFO L290 TraceCheckUtils]: 16: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~E_1~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,092 INFO L290 TraceCheckUtils]: 17: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~E_2~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,093 INFO L290 TraceCheckUtils]: 18: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~E_3~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,096 INFO L290 TraceCheckUtils]: 19: Hoare triple {11837#(= ~m_pc~0 0)} assume !(0 == ~E_4~0); {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,097 INFO L290 TraceCheckUtils]: 20: Hoare triple {11837#(= ~m_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11837#(= ~m_pc~0 0)} is VALID [2022-02-21 04:21:52,097 INFO L290 TraceCheckUtils]: 21: Hoare triple {11837#(= ~m_pc~0 0)} assume 1 == ~m_pc~0; {11836#false} is VALID [2022-02-21 04:21:52,097 INFO L290 TraceCheckUtils]: 22: Hoare triple {11836#false} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {11836#false} is VALID [2022-02-21 04:21:52,097 INFO L290 TraceCheckUtils]: 23: Hoare triple {11836#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11836#false} is VALID [2022-02-21 04:21:52,097 INFO L290 TraceCheckUtils]: 24: Hoare triple {11836#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 25: Hoare triple {11836#false} assume !(0 != activate_threads_~tmp~1#1); {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 26: Hoare triple {11836#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 27: Hoare triple {11836#false} assume !(1 == ~t1_pc~0); {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 28: Hoare triple {11836#false} is_transmit1_triggered_~__retres1~1#1 := 0; {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 29: Hoare triple {11836#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11836#false} is VALID [2022-02-21 04:21:52,098 INFO L290 TraceCheckUtils]: 30: Hoare triple {11836#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 31: Hoare triple {11836#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 32: Hoare triple {11836#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 33: Hoare triple {11836#false} assume 1 == ~t2_pc~0; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 34: Hoare triple {11836#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 35: Hoare triple {11836#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11836#false} is VALID [2022-02-21 04:21:52,099 INFO L290 TraceCheckUtils]: 36: Hoare triple {11836#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 37: Hoare triple {11836#false} assume !(0 != activate_threads_~tmp___1~0#1); {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 38: Hoare triple {11836#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 39: Hoare triple {11836#false} assume !(1 == ~t3_pc~0); {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 40: Hoare triple {11836#false} is_transmit3_triggered_~__retres1~3#1 := 0; {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 41: Hoare triple {11836#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11836#false} is VALID [2022-02-21 04:21:52,100 INFO L290 TraceCheckUtils]: 42: Hoare triple {11836#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 43: Hoare triple {11836#false} assume !(0 != activate_threads_~tmp___2~0#1); {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 44: Hoare triple {11836#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 45: Hoare triple {11836#false} assume 1 == ~t4_pc~0; {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 46: Hoare triple {11836#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 47: Hoare triple {11836#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11836#false} is VALID [2022-02-21 04:21:52,101 INFO L290 TraceCheckUtils]: 48: Hoare triple {11836#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 49: Hoare triple {11836#false} assume !(0 != activate_threads_~tmp___3~0#1); {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 50: Hoare triple {11836#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 51: Hoare triple {11836#false} assume 1 == ~M_E~0;~M_E~0 := 2; {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 52: Hoare triple {11836#false} assume !(1 == ~T1_E~0); {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 53: Hoare triple {11836#false} assume !(1 == ~T2_E~0); {11836#false} is VALID [2022-02-21 04:21:52,102 INFO L290 TraceCheckUtils]: 54: Hoare triple {11836#false} assume !(1 == ~T3_E~0); {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 55: Hoare triple {11836#false} assume !(1 == ~T4_E~0); {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 56: Hoare triple {11836#false} assume !(1 == ~E_M~0); {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 57: Hoare triple {11836#false} assume 1 == ~E_1~0;~E_1~0 := 2; {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 58: Hoare triple {11836#false} assume !(1 == ~E_2~0); {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 59: Hoare triple {11836#false} assume !(1 == ~E_3~0); {11836#false} is VALID [2022-02-21 04:21:52,103 INFO L290 TraceCheckUtils]: 60: Hoare triple {11836#false} assume !(1 == ~E_4~0); {11836#false} is VALID [2022-02-21 04:21:52,104 INFO L290 TraceCheckUtils]: 61: Hoare triple {11836#false} assume { :end_inline_reset_delta_events } true; {11836#false} is VALID [2022-02-21 04:21:52,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,104 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,104 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117968500] [2022-02-21 04:21:52,105 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117968500] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,105 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,105 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:52,105 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265141049] [2022-02-21 04:21:52,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,106 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:52,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,106 INFO L85 PathProgramCache]: Analyzing trace with hash -1518838612, now seen corresponding path program 1 times [2022-02-21 04:21:52,106 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,106 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829646194] [2022-02-21 04:21:52,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,130 INFO L290 TraceCheckUtils]: 0: Hoare triple {11838#true} assume !false; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {11838#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 2: Hoare triple {11838#true} assume !false; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 3: Hoare triple {11838#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 4: Hoare triple {11838#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 5: Hoare triple {11838#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {11838#true} is VALID [2022-02-21 04:21:52,131 INFO L290 TraceCheckUtils]: 6: Hoare triple {11838#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 7: Hoare triple {11838#true} assume !(0 != eval_~tmp~0#1); {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 8: Hoare triple {11838#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 9: Hoare triple {11838#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 10: Hoare triple {11838#true} assume 0 == ~M_E~0;~M_E~0 := 1; {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 11: Hoare triple {11838#true} assume !(0 == ~T1_E~0); {11838#true} is VALID [2022-02-21 04:21:52,132 INFO L290 TraceCheckUtils]: 12: Hoare triple {11838#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {11838#true} is VALID [2022-02-21 04:21:52,133 INFO L290 TraceCheckUtils]: 13: Hoare triple {11838#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {11838#true} is VALID [2022-02-21 04:21:52,133 INFO L290 TraceCheckUtils]: 14: Hoare triple {11838#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {11838#true} is VALID [2022-02-21 04:21:52,133 INFO L290 TraceCheckUtils]: 15: Hoare triple {11838#true} assume 0 == ~E_M~0;~E_M~0 := 1; {11838#true} is VALID [2022-02-21 04:21:52,133 INFO L290 TraceCheckUtils]: 16: Hoare triple {11838#true} assume 0 == ~E_1~0;~E_1~0 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,134 INFO L290 TraceCheckUtils]: 17: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,134 INFO L290 TraceCheckUtils]: 18: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,134 INFO L290 TraceCheckUtils]: 19: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,135 INFO L290 TraceCheckUtils]: 20: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,135 INFO L290 TraceCheckUtils]: 21: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~m_pc~0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,136 INFO L290 TraceCheckUtils]: 22: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,136 INFO L290 TraceCheckUtils]: 23: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,137 INFO L290 TraceCheckUtils]: 24: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,137 INFO L290 TraceCheckUtils]: 25: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,137 INFO L290 TraceCheckUtils]: 26: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,138 INFO L290 TraceCheckUtils]: 27: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t1_pc~0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,138 INFO L290 TraceCheckUtils]: 28: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,139 INFO L290 TraceCheckUtils]: 29: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,140 INFO L290 TraceCheckUtils]: 31: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,140 INFO L290 TraceCheckUtils]: 32: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,140 INFO L290 TraceCheckUtils]: 33: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,141 INFO L290 TraceCheckUtils]: 34: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,141 INFO L290 TraceCheckUtils]: 35: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,142 INFO L290 TraceCheckUtils]: 36: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,142 INFO L290 TraceCheckUtils]: 37: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,142 INFO L290 TraceCheckUtils]: 38: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,143 INFO L290 TraceCheckUtils]: 39: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,143 INFO L290 TraceCheckUtils]: 40: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,144 INFO L290 TraceCheckUtils]: 41: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,144 INFO L290 TraceCheckUtils]: 42: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,145 INFO L290 TraceCheckUtils]: 43: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,145 INFO L290 TraceCheckUtils]: 44: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,146 INFO L290 TraceCheckUtils]: 45: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,146 INFO L290 TraceCheckUtils]: 46: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,146 INFO L290 TraceCheckUtils]: 47: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,147 INFO L290 TraceCheckUtils]: 48: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,147 INFO L290 TraceCheckUtils]: 49: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,148 INFO L290 TraceCheckUtils]: 50: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,148 INFO L290 TraceCheckUtils]: 51: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,148 INFO L290 TraceCheckUtils]: 52: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,149 INFO L290 TraceCheckUtils]: 53: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,149 INFO L290 TraceCheckUtils]: 54: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,150 INFO L290 TraceCheckUtils]: 55: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,150 INFO L290 TraceCheckUtils]: 56: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {11840#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:52,150 INFO L290 TraceCheckUtils]: 57: Hoare triple {11840#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 58: Hoare triple {11839#false} assume 1 == ~E_2~0;~E_2~0 := 2; {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 59: Hoare triple {11839#false} assume 1 == ~E_3~0;~E_3~0 := 2; {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 60: Hoare triple {11839#false} assume 1 == ~E_4~0;~E_4~0 := 2; {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 61: Hoare triple {11839#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 62: Hoare triple {11839#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {11839#false} is VALID [2022-02-21 04:21:52,151 INFO L290 TraceCheckUtils]: 63: Hoare triple {11839#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 64: Hoare triple {11839#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 65: Hoare triple {11839#false} assume !(0 == start_simulation_~tmp~3#1); {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 66: Hoare triple {11839#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 67: Hoare triple {11839#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 68: Hoare triple {11839#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {11839#false} is VALID [2022-02-21 04:21:52,152 INFO L290 TraceCheckUtils]: 69: Hoare triple {11839#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {11839#false} is VALID [2022-02-21 04:21:52,153 INFO L290 TraceCheckUtils]: 70: Hoare triple {11839#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {11839#false} is VALID [2022-02-21 04:21:52,153 INFO L290 TraceCheckUtils]: 71: Hoare triple {11839#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {11839#false} is VALID [2022-02-21 04:21:52,153 INFO L290 TraceCheckUtils]: 72: Hoare triple {11839#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {11839#false} is VALID [2022-02-21 04:21:52,153 INFO L290 TraceCheckUtils]: 73: Hoare triple {11839#false} assume !(0 != start_simulation_~tmp___0~1#1); {11839#false} is VALID [2022-02-21 04:21:52,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,154 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,154 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829646194] [2022-02-21 04:21:52,154 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829646194] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,154 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,154 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:52,155 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300944168] [2022-02-21 04:21:52,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,155 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:52,155 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:52,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:52,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:52,156 INFO L87 Difference]: Start difference. First operand 709 states and 1047 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,797 INFO L93 Difference]: Finished difference Result 1322 states and 1928 transitions. [2022-02-21 04:21:52,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:52,798 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,837 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:52,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1322 states and 1928 transitions. [2022-02-21 04:21:52,917 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1244 [2022-02-21 04:21:52,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1322 states to 1322 states and 1928 transitions. [2022-02-21 04:21:52,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1322 [2022-02-21 04:21:52,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1322 [2022-02-21 04:21:52,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1322 states and 1928 transitions. [2022-02-21 04:21:52,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:52,997 INFO L681 BuchiCegarLoop]: Abstraction has 1322 states and 1928 transitions. [2022-02-21 04:21:52,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1322 states and 1928 transitions. [2022-02-21 04:21:53,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1322 to 1254. [2022-02-21 04:21:53,015 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:53,017 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1322 states and 1928 transitions. Second operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,019 INFO L74 IsIncluded]: Start isIncluded. First operand 1322 states and 1928 transitions. Second operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,021 INFO L87 Difference]: Start difference. First operand 1322 states and 1928 transitions. Second operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,093 INFO L93 Difference]: Finished difference Result 1322 states and 1928 transitions. [2022-02-21 04:21:53,093 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1928 transitions. [2022-02-21 04:21:53,095 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,095 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,098 INFO L74 IsIncluded]: Start isIncluded. First operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1322 states and 1928 transitions. [2022-02-21 04:21:53,100 INFO L87 Difference]: Start difference. First operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1322 states and 1928 transitions. [2022-02-21 04:21:53,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,170 INFO L93 Difference]: Finished difference Result 1322 states and 1928 transitions. [2022-02-21 04:21:53,170 INFO L276 IsEmpty]: Start isEmpty. Operand 1322 states and 1928 transitions. [2022-02-21 04:21:53,172 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,172 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,172 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:53,173 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:53,176 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1254 states, 1254 states have (on average 1.4625199362041468) internal successors, (1834), 1253 states have internal predecessors, (1834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1254 states to 1254 states and 1834 transitions. [2022-02-21 04:21:53,264 INFO L704 BuchiCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-02-21 04:21:53,264 INFO L587 BuchiCegarLoop]: Abstraction has 1254 states and 1834 transitions. [2022-02-21 04:21:53,264 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:53,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1254 states and 1834 transitions. [2022-02-21 04:21:53,270 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1176 [2022-02-21 04:21:53,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:53,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:53,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,271 INFO L791 eck$LassoCheckResult]: Stem: 13650#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 13625#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 13513#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13251#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13252#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 13308#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13580#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13257#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13258#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13383#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13290#L514 assume !(0 == ~M_E~0); 13291#L514-2 assume !(0 == ~T1_E~0); 13608#L519-1 assume !(0 == ~T2_E~0); 13243#L524-1 assume !(0 == ~T3_E~0); 13244#L529-1 assume !(0 == ~T4_E~0); 13360#L534-1 assume !(0 == ~E_M~0); 13559#L539-1 assume !(0 == ~E_1~0); 13560#L544-1 assume !(0 == ~E_2~0); 13577#L549-1 assume !(0 == ~E_3~0); 13578#L554-1 assume !(0 == ~E_4~0); 13238#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13239#L250 assume !(1 == ~m_pc~0); 13458#L250-2 is_master_triggered_~__retres1~0#1 := 0; 13585#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13417#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13418#L637 assume !(0 != activate_threads_~tmp~1#1); 13245#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13246#L269 assume !(1 == ~t1_pc~0); 13183#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13182#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13379#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13380#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13414#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13415#L288 assume 1 == ~t2_pc~0; 13532#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13409#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13428#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13429#L653 assume !(0 != activate_threads_~tmp___1~0#1); 13551#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13443#L307 assume !(1 == ~t3_pc~0); 13373#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13374#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13506#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13593#L661 assume !(0 != activate_threads_~tmp___2~0#1); 13388#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13389#L326 assume 1 == ~t4_pc~0; 13620#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13197#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13441#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13558#L669 assume !(0 != activate_threads_~tmp___3~0#1); 13555#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13556#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 13586#L572-2 assume !(1 == ~T1_E~0); 14088#L577-1 assume !(1 == ~T2_E~0); 14081#L582-1 assume !(1 == ~T3_E~0); 14076#L587-1 assume !(1 == ~T4_E~0); 13629#L592-1 assume !(1 == ~E_M~0); 13194#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13195#L602-1 assume !(1 == ~E_2~0); 13405#L607-1 assume !(1 == ~E_3~0); 13406#L612-1 assume !(1 == ~E_4~0); 13643#L617-1 assume { :end_inline_reset_delta_events } true; 13826#L803-2 [2022-02-21 04:21:53,272 INFO L793 eck$LassoCheckResult]: Loop: 13826#L803-2 assume !false; 13821#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13820#L489 assume !false; 13819#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13818#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13813#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13812#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13810#L428 assume !(0 != eval_~tmp~0#1); 13809#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13807#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13804#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13805#L514-5 assume !(0 == ~T1_E~0); 13962#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13961#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13960#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13959#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13958#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13957#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13956#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13955#L554-3 assume !(0 == ~E_4~0); 13954#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13953#L250-18 assume !(1 == ~m_pc~0); 13952#L250-20 is_master_triggered_~__retres1~0#1 := 0; 13951#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13950#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13949#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13948#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13947#L269-18 assume 1 == ~t1_pc~0; 13945#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13944#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13943#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13942#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13941#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13940#L288-18 assume 1 == ~t2_pc~0; 13938#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13937#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13936#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13935#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13934#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13933#L307-18 assume !(1 == ~t3_pc~0); 13735#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 13733#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13731#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13729#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13730#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13926#L326-18 assume 1 == ~t4_pc~0; 13924#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13923#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13922#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13921#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13920#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13919#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13714#L572-5 assume !(1 == ~T1_E~0); 13702#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13699#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13700#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13911#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13909#L597-3 assume !(1 == ~E_1~0); 13682#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13678#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13673#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13671#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13667#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13661#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13662#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 13879#L822 assume !(0 == start_simulation_~tmp~3#1); 13877#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 13864#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 13861#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 13859#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 13857#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13855#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13838#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 13831#L835 assume !(0 != start_simulation_~tmp___0~1#1); 13826#L803-2 [2022-02-21 04:21:53,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,272 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2022-02-21 04:21:53,272 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,273 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575177096] [2022-02-21 04:21:53,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,301 INFO L290 TraceCheckUtils]: 0: Hoare triple {17064#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,301 INFO L290 TraceCheckUtils]: 1: Hoare triple {17064#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {17064#true} is VALID [2022-02-21 04:21:53,301 INFO L290 TraceCheckUtils]: 2: Hoare triple {17064#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17064#true} is VALID [2022-02-21 04:21:53,301 INFO L290 TraceCheckUtils]: 3: Hoare triple {17064#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 4: Hoare triple {17064#true} assume 1 == ~m_i~0;~m_st~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 5: Hoare triple {17064#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 6: Hoare triple {17064#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 7: Hoare triple {17064#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 8: Hoare triple {17064#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 9: Hoare triple {17064#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 10: Hoare triple {17064#true} assume !(0 == ~M_E~0); {17064#true} is VALID [2022-02-21 04:21:53,302 INFO L290 TraceCheckUtils]: 11: Hoare triple {17064#true} assume !(0 == ~T1_E~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 12: Hoare triple {17064#true} assume !(0 == ~T2_E~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 13: Hoare triple {17064#true} assume !(0 == ~T3_E~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 14: Hoare triple {17064#true} assume !(0 == ~T4_E~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 15: Hoare triple {17064#true} assume !(0 == ~E_M~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 16: Hoare triple {17064#true} assume !(0 == ~E_1~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 17: Hoare triple {17064#true} assume !(0 == ~E_2~0); {17064#true} is VALID [2022-02-21 04:21:53,303 INFO L290 TraceCheckUtils]: 18: Hoare triple {17064#true} assume !(0 == ~E_3~0); {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 19: Hoare triple {17064#true} assume !(0 == ~E_4~0); {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 20: Hoare triple {17064#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 21: Hoare triple {17064#true} assume !(1 == ~m_pc~0); {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 22: Hoare triple {17064#true} is_master_triggered_~__retres1~0#1 := 0; {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 23: Hoare triple {17064#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 24: Hoare triple {17064#true} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {17064#true} is VALID [2022-02-21 04:21:53,304 INFO L290 TraceCheckUtils]: 25: Hoare triple {17064#true} assume !(0 != activate_threads_~tmp~1#1); {17064#true} is VALID [2022-02-21 04:21:53,305 INFO L290 TraceCheckUtils]: 26: Hoare triple {17064#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17064#true} is VALID [2022-02-21 04:21:53,305 INFO L290 TraceCheckUtils]: 27: Hoare triple {17064#true} assume !(1 == ~t1_pc~0); {17064#true} is VALID [2022-02-21 04:21:53,305 INFO L290 TraceCheckUtils]: 28: Hoare triple {17064#true} is_transmit1_triggered_~__retres1~1#1 := 0; {17066#(= |ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1| 0)} is VALID [2022-02-21 04:21:53,306 INFO L290 TraceCheckUtils]: 29: Hoare triple {17066#(= |ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1| 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17067#(= |ULTIMATE.start_is_transmit1_triggered_#res#1| 0)} is VALID [2022-02-21 04:21:53,306 INFO L290 TraceCheckUtils]: 30: Hoare triple {17067#(= |ULTIMATE.start_is_transmit1_triggered_#res#1| 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {17068#(= |ULTIMATE.start_activate_threads_~tmp___0~0#1| 0)} is VALID [2022-02-21 04:21:53,306 INFO L290 TraceCheckUtils]: 31: Hoare triple {17068#(= |ULTIMATE.start_activate_threads_~tmp___0~0#1| 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17065#false} is VALID [2022-02-21 04:21:53,306 INFO L290 TraceCheckUtils]: 32: Hoare triple {17065#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 33: Hoare triple {17065#false} assume 1 == ~t2_pc~0; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 34: Hoare triple {17065#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 35: Hoare triple {17065#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 36: Hoare triple {17065#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 37: Hoare triple {17065#false} assume !(0 != activate_threads_~tmp___1~0#1); {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 38: Hoare triple {17065#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17065#false} is VALID [2022-02-21 04:21:53,307 INFO L290 TraceCheckUtils]: 39: Hoare triple {17065#false} assume !(1 == ~t3_pc~0); {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 40: Hoare triple {17065#false} is_transmit3_triggered_~__retres1~3#1 := 0; {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 41: Hoare triple {17065#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 42: Hoare triple {17065#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 43: Hoare triple {17065#false} assume !(0 != activate_threads_~tmp___2~0#1); {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 44: Hoare triple {17065#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 45: Hoare triple {17065#false} assume 1 == ~t4_pc~0; {17065#false} is VALID [2022-02-21 04:21:53,308 INFO L290 TraceCheckUtils]: 46: Hoare triple {17065#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 47: Hoare triple {17065#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 48: Hoare triple {17065#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 49: Hoare triple {17065#false} assume !(0 != activate_threads_~tmp___3~0#1); {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 50: Hoare triple {17065#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 51: Hoare triple {17065#false} assume 1 == ~M_E~0;~M_E~0 := 2; {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 52: Hoare triple {17065#false} assume !(1 == ~T1_E~0); {17065#false} is VALID [2022-02-21 04:21:53,309 INFO L290 TraceCheckUtils]: 53: Hoare triple {17065#false} assume !(1 == ~T2_E~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 54: Hoare triple {17065#false} assume !(1 == ~T3_E~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 55: Hoare triple {17065#false} assume !(1 == ~T4_E~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 56: Hoare triple {17065#false} assume !(1 == ~E_M~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 57: Hoare triple {17065#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 58: Hoare triple {17065#false} assume !(1 == ~E_2~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 59: Hoare triple {17065#false} assume !(1 == ~E_3~0); {17065#false} is VALID [2022-02-21 04:21:53,310 INFO L290 TraceCheckUtils]: 60: Hoare triple {17065#false} assume !(1 == ~E_4~0); {17065#false} is VALID [2022-02-21 04:21:53,311 INFO L290 TraceCheckUtils]: 61: Hoare triple {17065#false} assume { :end_inline_reset_delta_events } true; {17065#false} is VALID [2022-02-21 04:21:53,311 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,311 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,311 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575177096] [2022-02-21 04:21:53,311 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575177096] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,312 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,312 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:21:53,312 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681351732] [2022-02-21 04:21:53,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,312 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:53,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,313 INFO L85 PathProgramCache]: Analyzing trace with hash -1792617107, now seen corresponding path program 1 times [2022-02-21 04:21:53,313 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,313 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008518554] [2022-02-21 04:21:53,313 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,334 INFO L290 TraceCheckUtils]: 0: Hoare triple {17069#true} assume !false; {17069#true} is VALID [2022-02-21 04:21:53,334 INFO L290 TraceCheckUtils]: 1: Hoare triple {17069#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17069#true} is VALID [2022-02-21 04:21:53,334 INFO L290 TraceCheckUtils]: 2: Hoare triple {17069#true} assume !false; {17069#true} is VALID [2022-02-21 04:21:53,334 INFO L290 TraceCheckUtils]: 3: Hoare triple {17069#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 4: Hoare triple {17069#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 5: Hoare triple {17069#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 6: Hoare triple {17069#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 7: Hoare triple {17069#true} assume !(0 != eval_~tmp~0#1); {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 8: Hoare triple {17069#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17069#true} is VALID [2022-02-21 04:21:53,335 INFO L290 TraceCheckUtils]: 9: Hoare triple {17069#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 10: Hoare triple {17069#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 11: Hoare triple {17069#true} assume !(0 == ~T1_E~0); {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 12: Hoare triple {17069#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 13: Hoare triple {17069#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 14: Hoare triple {17069#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17069#true} is VALID [2022-02-21 04:21:53,336 INFO L290 TraceCheckUtils]: 15: Hoare triple {17069#true} assume 0 == ~E_M~0;~E_M~0 := 1; {17069#true} is VALID [2022-02-21 04:21:53,337 INFO L290 TraceCheckUtils]: 16: Hoare triple {17069#true} assume 0 == ~E_1~0;~E_1~0 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,337 INFO L290 TraceCheckUtils]: 17: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,337 INFO L290 TraceCheckUtils]: 18: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,338 INFO L290 TraceCheckUtils]: 19: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,338 INFO L290 TraceCheckUtils]: 20: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,338 INFO L290 TraceCheckUtils]: 21: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,339 INFO L290 TraceCheckUtils]: 22: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,339 INFO L290 TraceCheckUtils]: 23: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,340 INFO L290 TraceCheckUtils]: 24: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,340 INFO L290 TraceCheckUtils]: 25: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,340 INFO L290 TraceCheckUtils]: 26: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,341 INFO L290 TraceCheckUtils]: 27: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t1_pc~0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,341 INFO L290 TraceCheckUtils]: 28: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,341 INFO L290 TraceCheckUtils]: 29: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,342 INFO L290 TraceCheckUtils]: 30: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,342 INFO L290 TraceCheckUtils]: 31: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,343 INFO L290 TraceCheckUtils]: 32: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,343 INFO L290 TraceCheckUtils]: 33: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t2_pc~0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,343 INFO L290 TraceCheckUtils]: 34: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,344 INFO L290 TraceCheckUtils]: 35: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,344 INFO L290 TraceCheckUtils]: 36: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,344 INFO L290 TraceCheckUtils]: 37: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,345 INFO L290 TraceCheckUtils]: 38: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,345 INFO L290 TraceCheckUtils]: 39: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,345 INFO L290 TraceCheckUtils]: 40: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,346 INFO L290 TraceCheckUtils]: 41: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,346 INFO L290 TraceCheckUtils]: 42: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,347 INFO L290 TraceCheckUtils]: 43: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,347 INFO L290 TraceCheckUtils]: 44: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,347 INFO L290 TraceCheckUtils]: 45: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,348 INFO L290 TraceCheckUtils]: 46: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,348 INFO L290 TraceCheckUtils]: 47: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,348 INFO L290 TraceCheckUtils]: 48: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,349 INFO L290 TraceCheckUtils]: 49: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,349 INFO L290 TraceCheckUtils]: 50: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,349 INFO L290 TraceCheckUtils]: 51: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,350 INFO L290 TraceCheckUtils]: 52: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,350 INFO L290 TraceCheckUtils]: 53: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,351 INFO L290 TraceCheckUtils]: 54: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,351 INFO L290 TraceCheckUtils]: 55: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,351 INFO L290 TraceCheckUtils]: 56: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {17071#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 57: Hoare triple {17071#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {17070#false} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 58: Hoare triple {17070#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17070#false} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 59: Hoare triple {17070#false} assume 1 == ~E_3~0;~E_3~0 := 2; {17070#false} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 60: Hoare triple {17070#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17070#false} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 61: Hoare triple {17070#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {17070#false} is VALID [2022-02-21 04:21:53,352 INFO L290 TraceCheckUtils]: 62: Hoare triple {17070#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 63: Hoare triple {17070#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 64: Hoare triple {17070#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 65: Hoare triple {17070#false} assume !(0 == start_simulation_~tmp~3#1); {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 66: Hoare triple {17070#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 67: Hoare triple {17070#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 68: Hoare triple {17070#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 69: Hoare triple {17070#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {17070#false} is VALID [2022-02-21 04:21:53,353 INFO L290 TraceCheckUtils]: 70: Hoare triple {17070#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17070#false} is VALID [2022-02-21 04:21:53,354 INFO L290 TraceCheckUtils]: 71: Hoare triple {17070#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17070#false} is VALID [2022-02-21 04:21:53,354 INFO L290 TraceCheckUtils]: 72: Hoare triple {17070#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {17070#false} is VALID [2022-02-21 04:21:53,354 INFO L290 TraceCheckUtils]: 73: Hoare triple {17070#false} assume !(0 != start_simulation_~tmp___0~1#1); {17070#false} is VALID [2022-02-21 04:21:53,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,355 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,355 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008518554] [2022-02-21 04:21:53,355 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008518554] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,355 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,355 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:53,355 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1082759682] [2022-02-21 04:21:53,355 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,356 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:53,356 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:53,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:21:53,356 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:21:53,357 INFO L87 Difference]: Start difference. First operand 1254 states and 1834 transitions. cyclomatic complexity: 584 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,431 INFO L93 Difference]: Finished difference Result 3355 states and 4893 transitions. [2022-02-21 04:21:55,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:21:55,431 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,472 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:55,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3355 states and 4893 transitions. [2022-02-21 04:21:55,699 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3184 [2022-02-21 04:21:55,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3355 states to 3355 states and 4893 transitions. [2022-02-21 04:21:55,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3355 [2022-02-21 04:21:55,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3355 [2022-02-21 04:21:55,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3355 states and 4893 transitions. [2022-02-21 04:21:55,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:55,930 INFO L681 BuchiCegarLoop]: Abstraction has 3355 states and 4893 transitions. [2022-02-21 04:21:55,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3355 states and 4893 transitions. [2022-02-21 04:21:55,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3355 to 1323. [2022-02-21 04:21:55,959 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:55,961 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3355 states and 4893 transitions. Second operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,962 INFO L74 IsIncluded]: Start isIncluded. First operand 3355 states and 4893 transitions. Second operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,963 INFO L87 Difference]: Start difference. First operand 3355 states and 4893 transitions. Second operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,266 INFO L93 Difference]: Finished difference Result 3355 states and 4893 transitions. [2022-02-21 04:21:56,266 INFO L276 IsEmpty]: Start isEmpty. Operand 3355 states and 4893 transitions. [2022-02-21 04:21:56,271 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,271 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,273 INFO L74 IsIncluded]: Start isIncluded. First operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3355 states and 4893 transitions. [2022-02-21 04:21:56,275 INFO L87 Difference]: Start difference. First operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3355 states and 4893 transitions. [2022-02-21 04:21:56,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,557 INFO L93 Difference]: Finished difference Result 3355 states and 4893 transitions. [2022-02-21 04:21:56,558 INFO L276 IsEmpty]: Start isEmpty. Operand 3355 states and 4893 transitions. [2022-02-21 04:21:56,562 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,562 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,562 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:56,562 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:56,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1323 states, 1323 states have (on average 1.438397581254724) internal successors, (1903), 1322 states have internal predecessors, (1903), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1323 states to 1323 states and 1903 transitions. [2022-02-21 04:21:56,610 INFO L704 BuchiCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-02-21 04:21:56,610 INFO L587 BuchiCegarLoop]: Abstraction has 1323 states and 1903 transitions. [2022-02-21 04:21:56,611 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:21:56,611 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1323 states and 1903 transitions. [2022-02-21 04:21:56,616 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1242 [2022-02-21 04:21:56,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,617 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,617 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,618 INFO L791 eck$LassoCheckResult]: Stem: 21002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 20966#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 20805#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20522#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20523#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 20581#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20901#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20528#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20529#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20659#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20563#L514 assume !(0 == ~M_E~0); 20564#L514-2 assume !(0 == ~T1_E~0); 20930#L519-1 assume !(0 == ~T2_E~0); 20514#L524-1 assume !(0 == ~T3_E~0); 20515#L529-1 assume !(0 == ~T4_E~0); 20637#L534-1 assume !(0 == ~E_M~0); 20855#L539-1 assume !(0 == ~E_1~0); 20856#L544-1 assume !(0 == ~E_2~0); 20899#L549-1 assume !(0 == ~E_3~0); 20900#L554-1 assume !(0 == ~E_4~0); 20509#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20510#L250 assume !(1 == ~m_pc~0); 20738#L250-2 is_master_triggered_~__retres1~0#1 := 0; 20906#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20698#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20699#L637 assume !(0 != activate_threads_~tmp~1#1); 20516#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20517#L269 assume !(1 == ~t1_pc~0); 20451#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20632#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20746#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20931#L645 assume !(0 != activate_threads_~tmp___0~0#1); 20695#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20696#L288 assume 1 == ~t2_pc~0; 20826#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20689#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20712#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20713#L653 assume !(0 != activate_threads_~tmp___1~0#1); 20847#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20726#L307 assume !(1 == ~t3_pc~0); 20650#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20651#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20793#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20912#L661 assume !(0 != activate_threads_~tmp___2~0#1); 20665#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20666#L326 assume 1 == ~t4_pc~0; 20949#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20467#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20722#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20854#L669 assume !(0 != activate_threads_~tmp___3~0#1); 20850#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20851#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 20907#L572-2 assume !(1 == ~T1_E~0); 20524#L577-1 assume !(1 == ~T2_E~0); 20525#L582-1 assume !(1 == ~T3_E~0); 20835#L587-1 assume !(1 == ~T4_E~0); 20842#L592-1 assume !(1 == ~E_M~0); 20456#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20457#L602-1 assume !(1 == ~E_2~0); 20685#L607-1 assume !(1 == ~E_3~0); 20686#L612-1 assume !(1 == ~E_4~0); 20635#L617-1 assume { :end_inline_reset_delta_events } true; 20636#L803-2 [2022-02-21 04:21:56,618 INFO L793 eck$LassoCheckResult]: Loop: 20636#L803-2 assume !false; 21005#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21152#L489 assume !false; 21150#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 21148#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 21056#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21055#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21053#L428 assume !(0 != eval_~tmp~0#1); 21054#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21753#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21752#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21751#L514-5 assume !(0 == ~T1_E~0); 21750#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21749#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21748#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21747#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21746#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21745#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21744#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21743#L554-3 assume !(0 == ~E_4~0); 21742#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20866#L250-18 assume !(1 == ~m_pc~0); 20867#L250-20 is_master_triggered_~__retres1~0#1 := 0; 20788#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20789#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20863#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20864#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21167#L269-18 assume 1 == ~t1_pc~0; 21168#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21292#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21293#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21289#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20750#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20642#L288-18 assume !(1 == ~t2_pc~0); 20624#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 20454#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20455#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20558#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20619#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20620#L307-18 assume !(1 == ~t3_pc~0); 20590#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 20591#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20658#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20599#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20600#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20868#L326-18 assume 1 == ~t4_pc~0; 20869#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20886#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20834#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20441#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20442#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20968#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20617#L572-5 assume !(1 == ~T1_E~0); 20618#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20507#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20508#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20764#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20765#L597-3 assume !(1 == ~E_1~0); 20672#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20673#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20626#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20627#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20679#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20646#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20663#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 20970#L822 assume !(0 == start_simulation_~tmp~3#1); 20849#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 20862#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20781#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 20727#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 20479#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20480#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20779#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 20799#L835 assume !(0 != start_simulation_~tmp___0~1#1); 20636#L803-2 [2022-02-21 04:21:56,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,618 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2022-02-21 04:21:56,619 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,619 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170291340] [2022-02-21 04:21:56,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,643 INFO L290 TraceCheckUtils]: 0: Hoare triple {28467#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,644 INFO L290 TraceCheckUtils]: 1: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,644 INFO L290 TraceCheckUtils]: 2: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,645 INFO L290 TraceCheckUtils]: 3: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,645 INFO L290 TraceCheckUtils]: 4: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,645 INFO L290 TraceCheckUtils]: 5: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,646 INFO L290 TraceCheckUtils]: 6: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,646 INFO L290 TraceCheckUtils]: 7: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,646 INFO L290 TraceCheckUtils]: 8: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,647 INFO L290 TraceCheckUtils]: 9: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,647 INFO L290 TraceCheckUtils]: 10: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~M_E~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,647 INFO L290 TraceCheckUtils]: 11: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T1_E~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,648 INFO L290 TraceCheckUtils]: 12: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T2_E~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,648 INFO L290 TraceCheckUtils]: 13: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T3_E~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,648 INFO L290 TraceCheckUtils]: 14: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~T4_E~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,649 INFO L290 TraceCheckUtils]: 15: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_M~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,649 INFO L290 TraceCheckUtils]: 16: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_1~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,649 INFO L290 TraceCheckUtils]: 17: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_2~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,650 INFO L290 TraceCheckUtils]: 18: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_3~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,650 INFO L290 TraceCheckUtils]: 19: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(0 == ~E_4~0); {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,650 INFO L290 TraceCheckUtils]: 20: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28469#(= ~m_pc~0 ~t2_pc~0)} is VALID [2022-02-21 04:21:56,651 INFO L290 TraceCheckUtils]: 21: Hoare triple {28469#(= ~m_pc~0 ~t2_pc~0)} assume !(1 == ~m_pc~0); {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,651 INFO L290 TraceCheckUtils]: 22: Hoare triple {28470#(not (= ~t2_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,651 INFO L290 TraceCheckUtils]: 23: Hoare triple {28470#(not (= ~t2_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,652 INFO L290 TraceCheckUtils]: 24: Hoare triple {28470#(not (= ~t2_pc~0 1))} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,652 INFO L290 TraceCheckUtils]: 25: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,652 INFO L290 TraceCheckUtils]: 26: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,653 INFO L290 TraceCheckUtils]: 27: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume !(1 == ~t1_pc~0); {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,653 INFO L290 TraceCheckUtils]: 28: Hoare triple {28470#(not (= ~t2_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,653 INFO L290 TraceCheckUtils]: 29: Hoare triple {28470#(not (= ~t2_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,654 INFO L290 TraceCheckUtils]: 30: Hoare triple {28470#(not (= ~t2_pc~0 1))} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,654 INFO L290 TraceCheckUtils]: 31: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,654 INFO L290 TraceCheckUtils]: 32: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28470#(not (= ~t2_pc~0 1))} is VALID [2022-02-21 04:21:56,655 INFO L290 TraceCheckUtils]: 33: Hoare triple {28470#(not (= ~t2_pc~0 1))} assume 1 == ~t2_pc~0; {28468#false} is VALID [2022-02-21 04:21:56,655 INFO L290 TraceCheckUtils]: 34: Hoare triple {28468#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {28468#false} is VALID [2022-02-21 04:21:56,655 INFO L290 TraceCheckUtils]: 35: Hoare triple {28468#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28468#false} is VALID [2022-02-21 04:21:56,655 INFO L290 TraceCheckUtils]: 36: Hoare triple {28468#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28468#false} is VALID [2022-02-21 04:21:56,655 INFO L290 TraceCheckUtils]: 37: Hoare triple {28468#false} assume !(0 != activate_threads_~tmp___1~0#1); {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 38: Hoare triple {28468#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 39: Hoare triple {28468#false} assume !(1 == ~t3_pc~0); {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 40: Hoare triple {28468#false} is_transmit3_triggered_~__retres1~3#1 := 0; {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 41: Hoare triple {28468#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 42: Hoare triple {28468#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 43: Hoare triple {28468#false} assume !(0 != activate_threads_~tmp___2~0#1); {28468#false} is VALID [2022-02-21 04:21:56,656 INFO L290 TraceCheckUtils]: 44: Hoare triple {28468#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 45: Hoare triple {28468#false} assume 1 == ~t4_pc~0; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 46: Hoare triple {28468#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 47: Hoare triple {28468#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 48: Hoare triple {28468#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 49: Hoare triple {28468#false} assume !(0 != activate_threads_~tmp___3~0#1); {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 50: Hoare triple {28468#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28468#false} is VALID [2022-02-21 04:21:56,657 INFO L290 TraceCheckUtils]: 51: Hoare triple {28468#false} assume 1 == ~M_E~0;~M_E~0 := 2; {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 52: Hoare triple {28468#false} assume !(1 == ~T1_E~0); {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 53: Hoare triple {28468#false} assume !(1 == ~T2_E~0); {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 54: Hoare triple {28468#false} assume !(1 == ~T3_E~0); {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 55: Hoare triple {28468#false} assume !(1 == ~T4_E~0); {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 56: Hoare triple {28468#false} assume !(1 == ~E_M~0); {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 57: Hoare triple {28468#false} assume 1 == ~E_1~0;~E_1~0 := 2; {28468#false} is VALID [2022-02-21 04:21:56,658 INFO L290 TraceCheckUtils]: 58: Hoare triple {28468#false} assume !(1 == ~E_2~0); {28468#false} is VALID [2022-02-21 04:21:56,659 INFO L290 TraceCheckUtils]: 59: Hoare triple {28468#false} assume !(1 == ~E_3~0); {28468#false} is VALID [2022-02-21 04:21:56,659 INFO L290 TraceCheckUtils]: 60: Hoare triple {28468#false} assume !(1 == ~E_4~0); {28468#false} is VALID [2022-02-21 04:21:56,659 INFO L290 TraceCheckUtils]: 61: Hoare triple {28468#false} assume { :end_inline_reset_delta_events } true; {28468#false} is VALID [2022-02-21 04:21:56,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,659 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,660 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170291340] [2022-02-21 04:21:56,660 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170291340] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,660 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,660 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,660 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594306359] [2022-02-21 04:21:56,660 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,661 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:56,661 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,661 INFO L85 PathProgramCache]: Analyzing trace with hash 2017175470, now seen corresponding path program 1 times [2022-02-21 04:21:56,661 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,661 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776644830] [2022-02-21 04:21:56,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,683 INFO L290 TraceCheckUtils]: 0: Hoare triple {28471#true} assume !false; {28471#true} is VALID [2022-02-21 04:21:56,683 INFO L290 TraceCheckUtils]: 1: Hoare triple {28471#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {28471#true} is VALID [2022-02-21 04:21:56,683 INFO L290 TraceCheckUtils]: 2: Hoare triple {28471#true} assume !false; {28471#true} is VALID [2022-02-21 04:21:56,683 INFO L290 TraceCheckUtils]: 3: Hoare triple {28471#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {28471#true} is VALID [2022-02-21 04:21:56,683 INFO L290 TraceCheckUtils]: 4: Hoare triple {28471#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 5: Hoare triple {28471#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 6: Hoare triple {28471#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 7: Hoare triple {28471#true} assume !(0 != eval_~tmp~0#1); {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 8: Hoare triple {28471#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 9: Hoare triple {28471#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 10: Hoare triple {28471#true} assume 0 == ~M_E~0;~M_E~0 := 1; {28471#true} is VALID [2022-02-21 04:21:56,684 INFO L290 TraceCheckUtils]: 11: Hoare triple {28471#true} assume !(0 == ~T1_E~0); {28471#true} is VALID [2022-02-21 04:21:56,685 INFO L290 TraceCheckUtils]: 12: Hoare triple {28471#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {28471#true} is VALID [2022-02-21 04:21:56,685 INFO L290 TraceCheckUtils]: 13: Hoare triple {28471#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {28471#true} is VALID [2022-02-21 04:21:56,685 INFO L290 TraceCheckUtils]: 14: Hoare triple {28471#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {28471#true} is VALID [2022-02-21 04:21:56,685 INFO L290 TraceCheckUtils]: 15: Hoare triple {28471#true} assume 0 == ~E_M~0;~E_M~0 := 1; {28471#true} is VALID [2022-02-21 04:21:56,685 INFO L290 TraceCheckUtils]: 16: Hoare triple {28471#true} assume 0 == ~E_1~0;~E_1~0 := 1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,686 INFO L290 TraceCheckUtils]: 17: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,687 INFO L290 TraceCheckUtils]: 18: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,687 INFO L290 TraceCheckUtils]: 19: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,688 INFO L290 TraceCheckUtils]: 20: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,688 INFO L290 TraceCheckUtils]: 21: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,688 INFO L290 TraceCheckUtils]: 22: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,689 INFO L290 TraceCheckUtils]: 23: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,689 INFO L290 TraceCheckUtils]: 24: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,690 INFO L290 TraceCheckUtils]: 25: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,690 INFO L290 TraceCheckUtils]: 26: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,690 INFO L290 TraceCheckUtils]: 27: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t1_pc~0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,691 INFO L290 TraceCheckUtils]: 28: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,691 INFO L290 TraceCheckUtils]: 29: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,691 INFO L290 TraceCheckUtils]: 30: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,692 INFO L290 TraceCheckUtils]: 31: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,692 INFO L290 TraceCheckUtils]: 32: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,693 INFO L290 TraceCheckUtils]: 33: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,693 INFO L290 TraceCheckUtils]: 34: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,693 INFO L290 TraceCheckUtils]: 35: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,694 INFO L290 TraceCheckUtils]: 36: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,694 INFO L290 TraceCheckUtils]: 37: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,694 INFO L290 TraceCheckUtils]: 38: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,695 INFO L290 TraceCheckUtils]: 39: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,695 INFO L290 TraceCheckUtils]: 40: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,696 INFO L290 TraceCheckUtils]: 41: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,696 INFO L290 TraceCheckUtils]: 42: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,696 INFO L290 TraceCheckUtils]: 43: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,697 INFO L290 TraceCheckUtils]: 44: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,697 INFO L290 TraceCheckUtils]: 45: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,697 INFO L290 TraceCheckUtils]: 46: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,698 INFO L290 TraceCheckUtils]: 47: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,698 INFO L290 TraceCheckUtils]: 48: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,699 INFO L290 TraceCheckUtils]: 49: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,699 INFO L290 TraceCheckUtils]: 50: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,699 INFO L290 TraceCheckUtils]: 51: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,700 INFO L290 TraceCheckUtils]: 52: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,700 INFO L290 TraceCheckUtils]: 53: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,701 INFO L290 TraceCheckUtils]: 54: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,701 INFO L290 TraceCheckUtils]: 55: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,701 INFO L290 TraceCheckUtils]: 56: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {28473#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 57: Hoare triple {28473#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {28472#false} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 58: Hoare triple {28472#false} assume 1 == ~E_2~0;~E_2~0 := 2; {28472#false} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 59: Hoare triple {28472#false} assume 1 == ~E_3~0;~E_3~0 := 2; {28472#false} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 60: Hoare triple {28472#false} assume 1 == ~E_4~0;~E_4~0 := 2; {28472#false} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 61: Hoare triple {28472#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {28472#false} is VALID [2022-02-21 04:21:56,702 INFO L290 TraceCheckUtils]: 62: Hoare triple {28472#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 63: Hoare triple {28472#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 64: Hoare triple {28472#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 65: Hoare triple {28472#false} assume !(0 == start_simulation_~tmp~3#1); {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 66: Hoare triple {28472#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 67: Hoare triple {28472#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 68: Hoare triple {28472#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {28472#false} is VALID [2022-02-21 04:21:56,703 INFO L290 TraceCheckUtils]: 69: Hoare triple {28472#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {28472#false} is VALID [2022-02-21 04:21:56,704 INFO L290 TraceCheckUtils]: 70: Hoare triple {28472#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {28472#false} is VALID [2022-02-21 04:21:56,704 INFO L290 TraceCheckUtils]: 71: Hoare triple {28472#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {28472#false} is VALID [2022-02-21 04:21:56,704 INFO L290 TraceCheckUtils]: 72: Hoare triple {28472#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {28472#false} is VALID [2022-02-21 04:21:56,704 INFO L290 TraceCheckUtils]: 73: Hoare triple {28472#false} assume !(0 != start_simulation_~tmp___0~1#1); {28472#false} is VALID [2022-02-21 04:21:56,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,705 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,705 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776644830] [2022-02-21 04:21:56,705 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776644830] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,705 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,705 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,705 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540157743] [2022-02-21 04:21:56,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,706 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:56,706 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:56,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:56,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:56,707 INFO L87 Difference]: Start difference. First operand 1323 states and 1903 transitions. cyclomatic complexity: 584 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,949 INFO L93 Difference]: Finished difference Result 3026 states and 4300 transitions. [2022-02-21 04:21:57,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:57,950 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,990 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:57,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,201 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2856 [2022-02-21 04:21:58,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3026 states to 3026 states and 4300 transitions. [2022-02-21 04:21:58,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3026 [2022-02-21 04:21:58,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3026 [2022-02-21 04:21:58,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:58,430 INFO L681 BuchiCegarLoop]: Abstraction has 3026 states and 4300 transitions. [2022-02-21 04:21:58,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3026 to 2378. [2022-02-21 04:21:58,464 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:58,467 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3026 states and 4300 transitions. Second operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,469 INFO L74 IsIncluded]: Start isIncluded. First operand 3026 states and 4300 transitions. Second operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,471 INFO L87 Difference]: Start difference. First operand 3026 states and 4300 transitions. Second operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,678 INFO L93 Difference]: Finished difference Result 3026 states and 4300 transitions. [2022-02-21 04:21:58,679 INFO L276 IsEmpty]: Start isEmpty. Operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,681 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,681 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,684 INFO L74 IsIncluded]: Start isIncluded. First operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,686 INFO L87 Difference]: Start difference. First operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,920 INFO L93 Difference]: Finished difference Result 3026 states and 4300 transitions. [2022-02-21 04:21:58,920 INFO L276 IsEmpty]: Start isEmpty. Operand 3026 states and 4300 transitions. [2022-02-21 04:21:58,923 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,923 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,923 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:58,923 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:58,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2378 states, 2378 states have (on average 1.430613961312027) internal successors, (3402), 2377 states have internal predecessors, (3402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2378 states to 2378 states and 3402 transitions. [2022-02-21 04:21:59,115 INFO L704 BuchiCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-02-21 04:21:59,115 INFO L587 BuchiCegarLoop]: Abstraction has 2378 states and 3402 transitions. [2022-02-21 04:21:59,115 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:21:59,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2378 states and 3402 transitions. [2022-02-21 04:21:59,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2296 [2022-02-21 04:21:59,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:59,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:59,123 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,123 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,124 INFO L791 eck$LassoCheckResult]: Stem: 31992#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 31961#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 31850#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31591#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31592#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 31646#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31917#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31597#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31598#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31723#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31627#L514 assume !(0 == ~M_E~0); 31628#L514-2 assume !(0 == ~T1_E~0); 31938#L519-1 assume !(0 == ~T2_E~0); 31583#L524-1 assume !(0 == ~T3_E~0); 31584#L529-1 assume !(0 == ~T4_E~0); 31700#L534-1 assume !(0 == ~E_M~0); 31891#L539-1 assume !(0 == ~E_1~0); 31892#L544-1 assume !(0 == ~E_2~0); 31914#L549-1 assume !(0 == ~E_3~0); 31915#L554-1 assume !(0 == ~E_4~0); 31578#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31579#L250 assume !(1 == ~m_pc~0); 31799#L250-2 is_master_triggered_~__retres1~0#1 := 0; 31921#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31760#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 31761#L637 assume !(0 != activate_threads_~tmp~1#1); 31585#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31586#L269 assume !(1 == ~t1_pc~0); 31522#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31695#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31995#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31939#L645 assume !(0 != activate_threads_~tmp___0~0#1); 31757#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31758#L288 assume !(1 == ~t2_pc~0); 31749#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 31750#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31772#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31773#L653 assume !(0 != activate_threads_~tmp___1~0#1); 31886#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31787#L307 assume !(1 == ~t3_pc~0); 31713#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31714#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31842#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31926#L661 assume !(0 != activate_threads_~tmp___2~0#1); 31730#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31731#L326 assume 1 == ~t4_pc~0; 31952#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31536#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31785#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31890#L669 assume !(0 != activate_threads_~tmp___3~0#1); 31887#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31888#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 31922#L572-2 assume !(1 == ~T1_E~0); 31593#L577-1 assume !(1 == ~T2_E~0); 31594#L582-1 assume !(1 == ~T3_E~0); 31881#L587-1 assume !(1 == ~T4_E~0); 31882#L592-1 assume !(1 == ~E_M~0); 31533#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 31534#L602-1 assume !(1 == ~E_2~0); 31746#L607-1 assume !(1 == ~E_3~0); 31747#L612-1 assume !(1 == ~E_4~0); 31698#L617-1 assume { :end_inline_reset_delta_events } true; 31699#L803-2 [2022-02-21 04:21:59,124 INFO L793 eck$LassoCheckResult]: Loop: 31699#L803-2 assume !false; 31852#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31619#L489 assume !false; 31986#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31790#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31635#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31693#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31984#L428 assume !(0 != eval_~tmp~0#1); 31985#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33877#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33789#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33790#L514-5 assume !(0 == ~T1_E~0); 33859#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33858#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33857#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33856#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 33855#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33854#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33853#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33852#L554-3 assume !(0 == ~E_4~0); 33851#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33850#L250-18 assume !(1 == ~m_pc~0); 33849#L250-20 is_master_triggered_~__retres1~0#1 := 0; 33848#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33847#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 33846#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33845#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33844#L269-18 assume !(1 == ~t1_pc~0); 33841#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 33840#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33839#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 33838#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 33836#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33835#L288-18 assume !(1 == ~t2_pc~0); 33315#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 33834#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33833#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 33832#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33831#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33830#L307-18 assume !(1 == ~t3_pc~0); 33828#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 33827#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33826#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33825#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33824#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33823#L326-18 assume 1 == ~t4_pc~0; 33821#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33820#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33819#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33818#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33817#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33816#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31987#L572-5 assume !(1 == ~T1_E~0); 33815#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33814#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33813#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33812#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33811#L597-3 assume !(1 == ~E_1~0); 33810#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33809#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33808#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31691#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 33806#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31727#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31728#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 31782#L822 assume !(0 == start_simulation_~tmp~3#1); 31784#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 31896#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 31829#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31786#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 31548#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31549#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31827#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 31843#L835 assume !(0 != start_simulation_~tmp___0~1#1); 31699#L803-2 [2022-02-21 04:21:59,125 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2022-02-21 04:21:59,125 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,125 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472823906] [2022-02-21 04:21:59,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,157 INFO L290 TraceCheckUtils]: 0: Hoare triple {39935#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,157 INFO L290 TraceCheckUtils]: 1: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,157 INFO L290 TraceCheckUtils]: 2: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,158 INFO L290 TraceCheckUtils]: 3: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,158 INFO L290 TraceCheckUtils]: 4: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,158 INFO L290 TraceCheckUtils]: 5: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,159 INFO L290 TraceCheckUtils]: 6: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,159 INFO L290 TraceCheckUtils]: 7: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,159 INFO L290 TraceCheckUtils]: 8: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,160 INFO L290 TraceCheckUtils]: 9: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~M_E~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,161 INFO L290 TraceCheckUtils]: 11: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~T1_E~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,161 INFO L290 TraceCheckUtils]: 12: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~T2_E~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,161 INFO L290 TraceCheckUtils]: 13: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~T3_E~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,162 INFO L290 TraceCheckUtils]: 14: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~T4_E~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,162 INFO L290 TraceCheckUtils]: 15: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~E_M~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,162 INFO L290 TraceCheckUtils]: 16: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~E_1~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,163 INFO L290 TraceCheckUtils]: 17: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~E_2~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,163 INFO L290 TraceCheckUtils]: 18: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~E_3~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,163 INFO L290 TraceCheckUtils]: 19: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 == ~E_4~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,164 INFO L290 TraceCheckUtils]: 20: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,164 INFO L290 TraceCheckUtils]: 21: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(1 == ~m_pc~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,164 INFO L290 TraceCheckUtils]: 22: Hoare triple {39937#(<= ~t4_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,165 INFO L290 TraceCheckUtils]: 23: Hoare triple {39937#(<= ~t4_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,165 INFO L290 TraceCheckUtils]: 24: Hoare triple {39937#(<= ~t4_pc~0 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,165 INFO L290 TraceCheckUtils]: 25: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,166 INFO L290 TraceCheckUtils]: 26: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,166 INFO L290 TraceCheckUtils]: 27: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(1 == ~t1_pc~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,166 INFO L290 TraceCheckUtils]: 28: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,167 INFO L290 TraceCheckUtils]: 30: Hoare triple {39937#(<= ~t4_pc~0 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,167 INFO L290 TraceCheckUtils]: 31: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,168 INFO L290 TraceCheckUtils]: 32: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,168 INFO L290 TraceCheckUtils]: 33: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(1 == ~t2_pc~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,168 INFO L290 TraceCheckUtils]: 34: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,169 INFO L290 TraceCheckUtils]: 35: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,169 INFO L290 TraceCheckUtils]: 36: Hoare triple {39937#(<= ~t4_pc~0 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,169 INFO L290 TraceCheckUtils]: 37: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,170 INFO L290 TraceCheckUtils]: 38: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,170 INFO L290 TraceCheckUtils]: 39: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(1 == ~t3_pc~0); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,170 INFO L290 TraceCheckUtils]: 40: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,171 INFO L290 TraceCheckUtils]: 41: Hoare triple {39937#(<= ~t4_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,171 INFO L290 TraceCheckUtils]: 42: Hoare triple {39937#(<= ~t4_pc~0 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,172 INFO L290 TraceCheckUtils]: 43: Hoare triple {39937#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,172 INFO L290 TraceCheckUtils]: 44: Hoare triple {39937#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39937#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:21:59,172 INFO L290 TraceCheckUtils]: 45: Hoare triple {39937#(<= ~t4_pc~0 0)} assume 1 == ~t4_pc~0; {39936#false} is VALID [2022-02-21 04:21:59,172 INFO L290 TraceCheckUtils]: 46: Hoare triple {39936#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 47: Hoare triple {39936#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 48: Hoare triple {39936#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 49: Hoare triple {39936#false} assume !(0 != activate_threads_~tmp___3~0#1); {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 50: Hoare triple {39936#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 51: Hoare triple {39936#false} assume 1 == ~M_E~0;~M_E~0 := 2; {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 52: Hoare triple {39936#false} assume !(1 == ~T1_E~0); {39936#false} is VALID [2022-02-21 04:21:59,173 INFO L290 TraceCheckUtils]: 53: Hoare triple {39936#false} assume !(1 == ~T2_E~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 54: Hoare triple {39936#false} assume !(1 == ~T3_E~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 55: Hoare triple {39936#false} assume !(1 == ~T4_E~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 56: Hoare triple {39936#false} assume !(1 == ~E_M~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 57: Hoare triple {39936#false} assume 1 == ~E_1~0;~E_1~0 := 2; {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 58: Hoare triple {39936#false} assume !(1 == ~E_2~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 59: Hoare triple {39936#false} assume !(1 == ~E_3~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 60: Hoare triple {39936#false} assume !(1 == ~E_4~0); {39936#false} is VALID [2022-02-21 04:21:59,174 INFO L290 TraceCheckUtils]: 61: Hoare triple {39936#false} assume { :end_inline_reset_delta_events } true; {39936#false} is VALID [2022-02-21 04:21:59,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,175 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,175 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472823906] [2022-02-21 04:21:59,175 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472823906] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,175 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,176 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:59,176 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812502347] [2022-02-21 04:21:59,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,176 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:59,177 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,177 INFO L85 PathProgramCache]: Analyzing trace with hash -773659983, now seen corresponding path program 1 times [2022-02-21 04:21:59,177 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,177 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986218731] [2022-02-21 04:21:59,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,205 INFO L290 TraceCheckUtils]: 0: Hoare triple {39938#true} assume !false; {39938#true} is VALID [2022-02-21 04:21:59,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {39938#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {39938#true} is VALID [2022-02-21 04:21:59,205 INFO L290 TraceCheckUtils]: 2: Hoare triple {39938#true} assume !false; {39938#true} is VALID [2022-02-21 04:21:59,205 INFO L290 TraceCheckUtils]: 3: Hoare triple {39938#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {39938#true} is VALID [2022-02-21 04:21:59,205 INFO L290 TraceCheckUtils]: 4: Hoare triple {39938#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 5: Hoare triple {39938#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 6: Hoare triple {39938#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 7: Hoare triple {39938#true} assume !(0 != eval_~tmp~0#1); {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 8: Hoare triple {39938#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 9: Hoare triple {39938#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {39938#true} is VALID [2022-02-21 04:21:59,206 INFO L290 TraceCheckUtils]: 10: Hoare triple {39938#true} assume 0 == ~M_E~0;~M_E~0 := 1; {39938#true} is VALID [2022-02-21 04:21:59,207 INFO L290 TraceCheckUtils]: 11: Hoare triple {39938#true} assume !(0 == ~T1_E~0); {39938#true} is VALID [2022-02-21 04:21:59,207 INFO L290 TraceCheckUtils]: 12: Hoare triple {39938#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {39938#true} is VALID [2022-02-21 04:21:59,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {39938#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {39938#true} is VALID [2022-02-21 04:21:59,207 INFO L290 TraceCheckUtils]: 14: Hoare triple {39938#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {39938#true} is VALID [2022-02-21 04:21:59,207 INFO L290 TraceCheckUtils]: 15: Hoare triple {39938#true} assume 0 == ~E_M~0;~E_M~0 := 1; {39938#true} is VALID [2022-02-21 04:21:59,208 INFO L290 TraceCheckUtils]: 16: Hoare triple {39938#true} assume 0 == ~E_1~0;~E_1~0 := 1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,208 INFO L290 TraceCheckUtils]: 17: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,208 INFO L290 TraceCheckUtils]: 18: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,209 INFO L290 TraceCheckUtils]: 19: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,209 INFO L290 TraceCheckUtils]: 20: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,210 INFO L290 TraceCheckUtils]: 21: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,210 INFO L290 TraceCheckUtils]: 22: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,210 INFO L290 TraceCheckUtils]: 23: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,211 INFO L290 TraceCheckUtils]: 24: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,211 INFO L290 TraceCheckUtils]: 25: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,211 INFO L290 TraceCheckUtils]: 26: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,212 INFO L290 TraceCheckUtils]: 27: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,212 INFO L290 TraceCheckUtils]: 28: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,213 INFO L290 TraceCheckUtils]: 29: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,213 INFO L290 TraceCheckUtils]: 30: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,213 INFO L290 TraceCheckUtils]: 31: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,214 INFO L290 TraceCheckUtils]: 32: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,214 INFO L290 TraceCheckUtils]: 33: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,215 INFO L290 TraceCheckUtils]: 34: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,215 INFO L290 TraceCheckUtils]: 35: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,215 INFO L290 TraceCheckUtils]: 36: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,216 INFO L290 TraceCheckUtils]: 37: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,216 INFO L290 TraceCheckUtils]: 38: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,217 INFO L290 TraceCheckUtils]: 39: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,217 INFO L290 TraceCheckUtils]: 40: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,217 INFO L290 TraceCheckUtils]: 41: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,218 INFO L290 TraceCheckUtils]: 42: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,218 INFO L290 TraceCheckUtils]: 43: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,218 INFO L290 TraceCheckUtils]: 44: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,219 INFO L290 TraceCheckUtils]: 45: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~t4_pc~0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,219 INFO L290 TraceCheckUtils]: 46: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,220 INFO L290 TraceCheckUtils]: 47: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,220 INFO L290 TraceCheckUtils]: 48: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,220 INFO L290 TraceCheckUtils]: 49: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,221 INFO L290 TraceCheckUtils]: 50: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,221 INFO L290 TraceCheckUtils]: 51: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,222 INFO L290 TraceCheckUtils]: 52: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,222 INFO L290 TraceCheckUtils]: 53: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,222 INFO L290 TraceCheckUtils]: 54: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,223 INFO L290 TraceCheckUtils]: 55: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,223 INFO L290 TraceCheckUtils]: 56: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {39940#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 57: Hoare triple {39940#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 58: Hoare triple {39939#false} assume 1 == ~E_2~0;~E_2~0 := 2; {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 59: Hoare triple {39939#false} assume 1 == ~E_3~0;~E_3~0 := 2; {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 60: Hoare triple {39939#false} assume 1 == ~E_4~0;~E_4~0 := 2; {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 61: Hoare triple {39939#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 62: Hoare triple {39939#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {39939#false} is VALID [2022-02-21 04:21:59,224 INFO L290 TraceCheckUtils]: 63: Hoare triple {39939#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 64: Hoare triple {39939#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 65: Hoare triple {39939#false} assume !(0 == start_simulation_~tmp~3#1); {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 66: Hoare triple {39939#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 67: Hoare triple {39939#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 68: Hoare triple {39939#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 69: Hoare triple {39939#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 70: Hoare triple {39939#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {39939#false} is VALID [2022-02-21 04:21:59,225 INFO L290 TraceCheckUtils]: 71: Hoare triple {39939#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {39939#false} is VALID [2022-02-21 04:21:59,226 INFO L290 TraceCheckUtils]: 72: Hoare triple {39939#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {39939#false} is VALID [2022-02-21 04:21:59,226 INFO L290 TraceCheckUtils]: 73: Hoare triple {39939#false} assume !(0 != start_simulation_~tmp___0~1#1); {39939#false} is VALID [2022-02-21 04:21:59,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,226 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,227 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986218731] [2022-02-21 04:21:59,227 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986218731] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,227 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,227 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,227 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [300408819] [2022-02-21 04:21:59,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,228 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:59,228 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:59,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:59,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:59,229 INFO L87 Difference]: Start difference. First operand 2378 states and 3402 transitions. cyclomatic complexity: 1028 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,228 INFO L93 Difference]: Finished difference Result 4325 states and 6159 transitions. [2022-02-21 04:22:00,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:00,228 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,274 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:00,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4325 states and 6159 transitions. [2022-02-21 04:22:00,713 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4224 [2022-02-21 04:22:01,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4325 states to 4325 states and 6159 transitions. [2022-02-21 04:22:01,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4325 [2022-02-21 04:22:01,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4325 [2022-02-21 04:22:01,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4325 states and 6159 transitions. [2022-02-21 04:22:01,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:01,143 INFO L681 BuchiCegarLoop]: Abstraction has 4325 states and 6159 transitions. [2022-02-21 04:22:01,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4325 states and 6159 transitions. [2022-02-21 04:22:01,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4325 to 4309. [2022-02-21 04:22:01,194 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:01,200 INFO L82 GeneralOperation]: Start isEquivalent. First operand 4325 states and 6159 transitions. Second operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,204 INFO L74 IsIncluded]: Start isIncluded. First operand 4325 states and 6159 transitions. Second operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,208 INFO L87 Difference]: Start difference. First operand 4325 states and 6159 transitions. Second operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,663 INFO L93 Difference]: Finished difference Result 4325 states and 6159 transitions. [2022-02-21 04:22:01,663 INFO L276 IsEmpty]: Start isEmpty. Operand 4325 states and 6159 transitions. [2022-02-21 04:22:01,667 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:01,667 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:01,671 INFO L74 IsIncluded]: Start isIncluded. First operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4325 states and 6159 transitions. [2022-02-21 04:22:01,676 INFO L87 Difference]: Start difference. First operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 4325 states and 6159 transitions. [2022-02-21 04:22:02,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,132 INFO L93 Difference]: Finished difference Result 4325 states and 6159 transitions. [2022-02-21 04:22:02,133 INFO L276 IsEmpty]: Start isEmpty. Operand 4325 states and 6159 transitions. [2022-02-21 04:22:02,136 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:02,136 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:02,136 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:02,136 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:02,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4309 states, 4309 states have (on average 1.4256207936876306) internal successors, (6143), 4308 states have internal predecessors, (6143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4309 states to 4309 states and 6143 transitions. [2022-02-21 04:22:02,558 INFO L704 BuchiCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-02-21 04:22:02,558 INFO L587 BuchiCegarLoop]: Abstraction has 4309 states and 6143 transitions. [2022-02-21 04:22:02,558 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:02,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4309 states and 6143 transitions. [2022-02-21 04:22:02,567 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4208 [2022-02-21 04:22:02,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:02,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:02,569 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,569 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,569 INFO L791 eck$LassoCheckResult]: Stem: 44770#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 44735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 44629#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44357#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44358#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 44413#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44699#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44363#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44364#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44493#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44393#L514 assume !(0 == ~M_E~0); 44394#L514-2 assume !(0 == ~T1_E~0); 44716#L519-1 assume !(0 == ~T2_E~0); 44347#L524-1 assume !(0 == ~T3_E~0); 44348#L529-1 assume !(0 == ~T4_E~0); 44467#L534-1 assume !(0 == ~E_M~0); 44673#L539-1 assume !(0 == ~E_1~0); 44674#L544-1 assume !(0 == ~E_2~0); 44696#L549-1 assume !(0 == ~E_3~0); 44697#L554-1 assume !(0 == ~E_4~0); 44342#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44343#L250 assume !(1 == ~m_pc~0); 44568#L250-2 is_master_triggered_~__retres1~0#1 := 0; 44702#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44530#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 44531#L637 assume !(0 != activate_threads_~tmp~1#1); 44351#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44352#L269 assume !(1 == ~t1_pc~0); 44286#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 44462#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44773#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44717#L645 assume !(0 != activate_threads_~tmp___0~0#1); 44527#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44528#L288 assume !(1 == ~t2_pc~0); 44520#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 44521#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44541#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44542#L653 assume !(0 != activate_threads_~tmp___1~0#1); 44667#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44556#L307 assume !(1 == ~t3_pc~0); 44480#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 44481#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44619#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44707#L661 assume !(0 != activate_threads_~tmp___2~0#1); 44499#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44500#L326 assume !(1 == ~t4_pc~0); 44299#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 44300#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44554#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44672#L669 assume !(0 != activate_threads_~tmp___3~0#1); 44669#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44670#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 44703#L572-2 assume !(1 == ~T1_E~0); 44359#L577-1 assume !(1 == ~T2_E~0); 44360#L582-1 assume !(1 == ~T3_E~0); 44661#L587-1 assume !(1 == ~T4_E~0); 44662#L592-1 assume !(1 == ~E_M~0); 44296#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 44297#L602-1 assume !(1 == ~E_2~0); 44517#L607-1 assume !(1 == ~E_3~0); 44518#L612-1 assume !(1 == ~E_4~0); 44465#L617-1 assume { :end_inline_reset_delta_events } true; 44466#L803-2 [2022-02-21 04:22:02,569 INFO L793 eck$LassoCheckResult]: Loop: 44466#L803-2 assume !false; 44631#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44385#L489 assume !false; 44600#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 44557#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44403#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44461#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44765#L428 assume !(0 != eval_~tmp~0#1); 44766#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48317#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48316#L514-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48315#L514-5 assume !(0 == ~T1_E~0); 48314#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48312#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48310#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48309#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48308#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48306#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48302#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 48300#L554-3 assume !(0 == ~E_4~0); 44591#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44592#L250-18 assume !(1 == ~m_pc~0); 44680#L250-20 is_master_triggered_~__retres1~0#1 := 0; 48280#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48279#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 48278#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48277#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48276#L269-18 assume !(1 == ~t1_pc~0); 48274#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 48272#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48270#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 48269#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 48267#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48266#L288-18 assume !(1 == ~t2_pc~0); 46145#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 48265#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48264#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48263#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48262#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48261#L307-18 assume !(1 == ~t3_pc~0); 48259#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 48258#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48257#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48256#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48255#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48254#L326-18 assume !(1 == ~t4_pc~0); 48253#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 48252#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48250#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48248#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48246#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48244#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46123#L572-5 assume !(1 == ~T1_E~0); 48241#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48238#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48236#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48234#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 48232#L597-3 assume !(1 == ~E_1~0); 48230#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48228#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 48225#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46100#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48217#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 48213#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 48212#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 44551#L822 assume !(0 == start_simulation_~tmp~3#1); 44553#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 48287#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 44752#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 44555#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 44312#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44313#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44602#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 44620#L835 assume !(0 != start_simulation_~tmp___0~1#1); 44466#L803-2 [2022-02-21 04:22:02,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:02,570 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2022-02-21 04:22:02,570 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:02,570 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [736944632] [2022-02-21 04:22:02,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:02,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:02,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:02,593 INFO L290 TraceCheckUtils]: 0: Hoare triple {57228#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,593 INFO L290 TraceCheckUtils]: 1: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,593 INFO L290 TraceCheckUtils]: 2: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,594 INFO L290 TraceCheckUtils]: 3: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,594 INFO L290 TraceCheckUtils]: 4: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~m_i~0;~m_st~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,594 INFO L290 TraceCheckUtils]: 5: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,595 INFO L290 TraceCheckUtils]: 6: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,595 INFO L290 TraceCheckUtils]: 7: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,596 INFO L290 TraceCheckUtils]: 8: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,596 INFO L290 TraceCheckUtils]: 9: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,596 INFO L290 TraceCheckUtils]: 10: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~M_E~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,597 INFO L290 TraceCheckUtils]: 11: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~T1_E~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,597 INFO L290 TraceCheckUtils]: 12: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~T2_E~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,598 INFO L290 TraceCheckUtils]: 13: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~T3_E~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,598 INFO L290 TraceCheckUtils]: 14: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~T4_E~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,598 INFO L290 TraceCheckUtils]: 15: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~E_M~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,599 INFO L290 TraceCheckUtils]: 16: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~E_1~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,599 INFO L290 TraceCheckUtils]: 17: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~E_2~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,599 INFO L290 TraceCheckUtils]: 18: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~E_3~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,600 INFO L290 TraceCheckUtils]: 19: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 == ~E_4~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,600 INFO L290 TraceCheckUtils]: 20: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,601 INFO L290 TraceCheckUtils]: 21: Hoare triple {57230#(= ~M_E~0 2)} assume !(1 == ~m_pc~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,601 INFO L290 TraceCheckUtils]: 22: Hoare triple {57230#(= ~M_E~0 2)} is_master_triggered_~__retres1~0#1 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,601 INFO L290 TraceCheckUtils]: 23: Hoare triple {57230#(= ~M_E~0 2)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,602 INFO L290 TraceCheckUtils]: 24: Hoare triple {57230#(= ~M_E~0 2)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,602 INFO L290 TraceCheckUtils]: 25: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp~1#1); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,602 INFO L290 TraceCheckUtils]: 26: Hoare triple {57230#(= ~M_E~0 2)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,603 INFO L290 TraceCheckUtils]: 27: Hoare triple {57230#(= ~M_E~0 2)} assume !(1 == ~t1_pc~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,603 INFO L290 TraceCheckUtils]: 28: Hoare triple {57230#(= ~M_E~0 2)} is_transmit1_triggered_~__retres1~1#1 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,603 INFO L290 TraceCheckUtils]: 29: Hoare triple {57230#(= ~M_E~0 2)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,604 INFO L290 TraceCheckUtils]: 30: Hoare triple {57230#(= ~M_E~0 2)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,604 INFO L290 TraceCheckUtils]: 31: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___0~0#1); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,605 INFO L290 TraceCheckUtils]: 32: Hoare triple {57230#(= ~M_E~0 2)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,605 INFO L290 TraceCheckUtils]: 33: Hoare triple {57230#(= ~M_E~0 2)} assume !(1 == ~t2_pc~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,605 INFO L290 TraceCheckUtils]: 34: Hoare triple {57230#(= ~M_E~0 2)} is_transmit2_triggered_~__retres1~2#1 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,606 INFO L290 TraceCheckUtils]: 35: Hoare triple {57230#(= ~M_E~0 2)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,606 INFO L290 TraceCheckUtils]: 36: Hoare triple {57230#(= ~M_E~0 2)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,606 INFO L290 TraceCheckUtils]: 37: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___1~0#1); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,607 INFO L290 TraceCheckUtils]: 38: Hoare triple {57230#(= ~M_E~0 2)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,607 INFO L290 TraceCheckUtils]: 39: Hoare triple {57230#(= ~M_E~0 2)} assume !(1 == ~t3_pc~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,608 INFO L290 TraceCheckUtils]: 40: Hoare triple {57230#(= ~M_E~0 2)} is_transmit3_triggered_~__retres1~3#1 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,608 INFO L290 TraceCheckUtils]: 41: Hoare triple {57230#(= ~M_E~0 2)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,608 INFO L290 TraceCheckUtils]: 42: Hoare triple {57230#(= ~M_E~0 2)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,609 INFO L290 TraceCheckUtils]: 43: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___2~0#1); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,609 INFO L290 TraceCheckUtils]: 44: Hoare triple {57230#(= ~M_E~0 2)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,609 INFO L290 TraceCheckUtils]: 45: Hoare triple {57230#(= ~M_E~0 2)} assume !(1 == ~t4_pc~0); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,610 INFO L290 TraceCheckUtils]: 46: Hoare triple {57230#(= ~M_E~0 2)} is_transmit4_triggered_~__retres1~4#1 := 0; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,610 INFO L290 TraceCheckUtils]: 47: Hoare triple {57230#(= ~M_E~0 2)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,610 INFO L290 TraceCheckUtils]: 48: Hoare triple {57230#(= ~M_E~0 2)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,611 INFO L290 TraceCheckUtils]: 49: Hoare triple {57230#(= ~M_E~0 2)} assume !(0 != activate_threads_~tmp___3~0#1); {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,611 INFO L290 TraceCheckUtils]: 50: Hoare triple {57230#(= ~M_E~0 2)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57230#(= ~M_E~0 2)} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 51: Hoare triple {57230#(= ~M_E~0 2)} assume 1 == ~M_E~0;~M_E~0 := 2; {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 52: Hoare triple {57229#false} assume !(1 == ~T1_E~0); {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 53: Hoare triple {57229#false} assume !(1 == ~T2_E~0); {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 54: Hoare triple {57229#false} assume !(1 == ~T3_E~0); {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 55: Hoare triple {57229#false} assume !(1 == ~T4_E~0); {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 56: Hoare triple {57229#false} assume !(1 == ~E_M~0); {57229#false} is VALID [2022-02-21 04:22:02,612 INFO L290 TraceCheckUtils]: 57: Hoare triple {57229#false} assume 1 == ~E_1~0;~E_1~0 := 2; {57229#false} is VALID [2022-02-21 04:22:02,613 INFO L290 TraceCheckUtils]: 58: Hoare triple {57229#false} assume !(1 == ~E_2~0); {57229#false} is VALID [2022-02-21 04:22:02,613 INFO L290 TraceCheckUtils]: 59: Hoare triple {57229#false} assume !(1 == ~E_3~0); {57229#false} is VALID [2022-02-21 04:22:02,613 INFO L290 TraceCheckUtils]: 60: Hoare triple {57229#false} assume !(1 == ~E_4~0); {57229#false} is VALID [2022-02-21 04:22:02,613 INFO L290 TraceCheckUtils]: 61: Hoare triple {57229#false} assume { :end_inline_reset_delta_events } true; {57229#false} is VALID [2022-02-21 04:22:02,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:02,613 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:02,614 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [736944632] [2022-02-21 04:22:02,614 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [736944632] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:02,614 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:02,614 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:02,614 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770106140] [2022-02-21 04:22:02,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:02,615 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:02,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:02,615 INFO L85 PathProgramCache]: Analyzing trace with hash -1745334670, now seen corresponding path program 1 times [2022-02-21 04:22:02,615 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:02,615 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518087860] [2022-02-21 04:22:02,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:02,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:02,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:02,633 INFO L290 TraceCheckUtils]: 0: Hoare triple {57231#true} assume !false; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 1: Hoare triple {57231#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 2: Hoare triple {57231#true} assume !false; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 3: Hoare triple {57231#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 4: Hoare triple {57231#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 5: Hoare triple {57231#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 6: Hoare triple {57231#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {57231#true} is VALID [2022-02-21 04:22:02,634 INFO L290 TraceCheckUtils]: 7: Hoare triple {57231#true} assume !(0 != eval_~tmp~0#1); {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 8: Hoare triple {57231#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 9: Hoare triple {57231#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 10: Hoare triple {57231#true} assume 0 == ~M_E~0;~M_E~0 := 1; {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 11: Hoare triple {57231#true} assume !(0 == ~T1_E~0); {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 12: Hoare triple {57231#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 13: Hoare triple {57231#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {57231#true} is VALID [2022-02-21 04:22:02,635 INFO L290 TraceCheckUtils]: 14: Hoare triple {57231#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {57231#true} is VALID [2022-02-21 04:22:02,636 INFO L290 TraceCheckUtils]: 15: Hoare triple {57231#true} assume 0 == ~E_M~0;~E_M~0 := 1; {57231#true} is VALID [2022-02-21 04:22:02,636 INFO L290 TraceCheckUtils]: 16: Hoare triple {57231#true} assume 0 == ~E_1~0;~E_1~0 := 1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,636 INFO L290 TraceCheckUtils]: 17: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,637 INFO L290 TraceCheckUtils]: 18: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,637 INFO L290 TraceCheckUtils]: 19: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,638 INFO L290 TraceCheckUtils]: 20: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,638 INFO L290 TraceCheckUtils]: 21: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,638 INFO L290 TraceCheckUtils]: 22: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,639 INFO L290 TraceCheckUtils]: 23: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,639 INFO L290 TraceCheckUtils]: 24: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,639 INFO L290 TraceCheckUtils]: 25: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,640 INFO L290 TraceCheckUtils]: 26: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,640 INFO L290 TraceCheckUtils]: 27: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,641 INFO L290 TraceCheckUtils]: 28: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,641 INFO L290 TraceCheckUtils]: 29: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,641 INFO L290 TraceCheckUtils]: 30: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,642 INFO L290 TraceCheckUtils]: 31: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,642 INFO L290 TraceCheckUtils]: 32: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,642 INFO L290 TraceCheckUtils]: 33: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,643 INFO L290 TraceCheckUtils]: 34: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,643 INFO L290 TraceCheckUtils]: 35: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,644 INFO L290 TraceCheckUtils]: 36: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,644 INFO L290 TraceCheckUtils]: 37: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,644 INFO L290 TraceCheckUtils]: 38: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,645 INFO L290 TraceCheckUtils]: 39: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,645 INFO L290 TraceCheckUtils]: 40: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,645 INFO L290 TraceCheckUtils]: 41: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,646 INFO L290 TraceCheckUtils]: 42: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,646 INFO L290 TraceCheckUtils]: 43: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,647 INFO L290 TraceCheckUtils]: 44: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,647 INFO L290 TraceCheckUtils]: 45: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t4_pc~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,647 INFO L290 TraceCheckUtils]: 46: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,648 INFO L290 TraceCheckUtils]: 47: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,648 INFO L290 TraceCheckUtils]: 48: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,649 INFO L290 TraceCheckUtils]: 49: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,649 INFO L290 TraceCheckUtils]: 50: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,649 INFO L290 TraceCheckUtils]: 51: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,650 INFO L290 TraceCheckUtils]: 52: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,650 INFO L290 TraceCheckUtils]: 53: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,651 INFO L290 TraceCheckUtils]: 54: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,651 INFO L290 TraceCheckUtils]: 55: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,651 INFO L290 TraceCheckUtils]: 56: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {57233#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 57: Hoare triple {57233#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {57232#false} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 58: Hoare triple {57232#false} assume 1 == ~E_2~0;~E_2~0 := 2; {57232#false} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 59: Hoare triple {57232#false} assume 1 == ~E_3~0;~E_3~0 := 2; {57232#false} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 60: Hoare triple {57232#false} assume 1 == ~E_4~0;~E_4~0 := 2; {57232#false} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 61: Hoare triple {57232#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {57232#false} is VALID [2022-02-21 04:22:02,652 INFO L290 TraceCheckUtils]: 62: Hoare triple {57232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 63: Hoare triple {57232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 64: Hoare triple {57232#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 65: Hoare triple {57232#false} assume !(0 == start_simulation_~tmp~3#1); {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 66: Hoare triple {57232#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 67: Hoare triple {57232#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 68: Hoare triple {57232#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {57232#false} is VALID [2022-02-21 04:22:02,653 INFO L290 TraceCheckUtils]: 69: Hoare triple {57232#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {57232#false} is VALID [2022-02-21 04:22:02,654 INFO L290 TraceCheckUtils]: 70: Hoare triple {57232#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {57232#false} is VALID [2022-02-21 04:22:02,654 INFO L290 TraceCheckUtils]: 71: Hoare triple {57232#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {57232#false} is VALID [2022-02-21 04:22:02,654 INFO L290 TraceCheckUtils]: 72: Hoare triple {57232#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {57232#false} is VALID [2022-02-21 04:22:02,654 INFO L290 TraceCheckUtils]: 73: Hoare triple {57232#false} assume !(0 != start_simulation_~tmp___0~1#1); {57232#false} is VALID [2022-02-21 04:22:02,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:02,654 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:02,655 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518087860] [2022-02-21 04:22:02,655 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518087860] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:02,655 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:02,655 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:02,655 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906998621] [2022-02-21 04:22:02,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:02,656 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:02,656 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:02,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:02,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:02,657 INFO L87 Difference]: Start difference. First operand 4309 states and 6143 transitions. cyclomatic complexity: 1842 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,030 INFO L93 Difference]: Finished difference Result 6456 states and 9189 transitions. [2022-02-21 04:22:04,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:04,030 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,069 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:04,069 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6456 states and 9189 transitions. [2022-02-21 04:22:04,900 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6352 [2022-02-21 04:22:05,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6456 states to 6456 states and 9189 transitions. [2022-02-21 04:22:05,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6456 [2022-02-21 04:22:05,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6456 [2022-02-21 04:22:05,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6456 states and 9189 transitions. [2022-02-21 04:22:05,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:05,768 INFO L681 BuchiCegarLoop]: Abstraction has 6456 states and 9189 transitions. [2022-02-21 04:22:05,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6456 states and 9189 transitions. [2022-02-21 04:22:05,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6456 to 4687. [2022-02-21 04:22:05,827 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:05,832 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6456 states and 9189 transitions. Second operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,836 INFO L74 IsIncluded]: Start isIncluded. First operand 6456 states and 9189 transitions. Second operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,840 INFO L87 Difference]: Start difference. First operand 6456 states and 9189 transitions. Second operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:06,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:06,813 INFO L93 Difference]: Finished difference Result 6456 states and 9189 transitions. [2022-02-21 04:22:06,813 INFO L276 IsEmpty]: Start isEmpty. Operand 6456 states and 9189 transitions. [2022-02-21 04:22:06,858 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:06,859 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:06,864 INFO L74 IsIncluded]: Start isIncluded. First operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6456 states and 9189 transitions. [2022-02-21 04:22:06,867 INFO L87 Difference]: Start difference. First operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6456 states and 9189 transitions. [2022-02-21 04:22:07,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,716 INFO L93 Difference]: Finished difference Result 6456 states and 9189 transitions. [2022-02-21 04:22:07,716 INFO L276 IsEmpty]: Start isEmpty. Operand 6456 states and 9189 transitions. [2022-02-21 04:22:07,723 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:07,723 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:07,723 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:07,723 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:07,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4687 states, 4687 states have (on average 1.421804992532537) internal successors, (6664), 4686 states have internal predecessors, (6664), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4687 states to 4687 states and 6664 transitions. [2022-02-21 04:22:08,206 INFO L704 BuchiCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-02-21 04:22:08,206 INFO L587 BuchiCegarLoop]: Abstraction has 4687 states and 6664 transitions. [2022-02-21 04:22:08,206 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:22:08,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4687 states and 6664 transitions. [2022-02-21 04:22:08,216 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4596 [2022-02-21 04:22:08,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:08,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:08,217 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,217 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:08,218 INFO L791 eck$LassoCheckResult]: Stem: 64182#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 64151#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 64043#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63781#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63782#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 63836#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64114#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63787#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63788#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63909#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63817#L514 assume !(0 == ~M_E~0); 63818#L514-2 assume !(0 == ~T1_E~0); 64133#L519-1 assume !(0 == ~T2_E~0); 63771#L524-1 assume !(0 == ~T3_E~0); 63772#L529-1 assume !(0 == ~T4_E~0); 63887#L534-1 assume !(0 == ~E_M~0); 64088#L539-1 assume !(0 == ~E_1~0); 64089#L544-1 assume !(0 == ~E_2~0); 64112#L549-1 assume !(0 == ~E_3~0); 64113#L554-1 assume !(0 == ~E_4~0); 63766#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 63767#L250 assume !(1 == ~m_pc~0); 63983#L250-2 is_master_triggered_~__retres1~0#1 := 0; 64118#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63947#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 63948#L637 assume !(0 != activate_threads_~tmp~1#1); 63773#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63774#L269 assume !(1 == ~t1_pc~0); 63710#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63882#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64185#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 64134#L645 assume !(0 != activate_threads_~tmp___0~0#1); 63944#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63945#L288 assume !(1 == ~t2_pc~0); 63938#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 63939#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63958#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 63959#L653 assume !(0 != activate_threads_~tmp___1~0#1); 64082#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63972#L307 assume !(1 == ~t3_pc~0); 63900#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63901#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64028#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 64123#L661 assume !(0 != activate_threads_~tmp___2~0#1); 63918#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63919#L326 assume !(1 == ~t4_pc~0); 63723#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63724#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63968#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64087#L669 assume !(0 != activate_threads_~tmp___3~0#1); 64084#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64085#L572 assume !(1 == ~M_E~0); 64119#L572-2 assume !(1 == ~T1_E~0); 63783#L577-1 assume !(1 == ~T2_E~0); 63784#L582-1 assume !(1 == ~T3_E~0); 64071#L587-1 assume !(1 == ~T4_E~0); 64078#L592-1 assume !(1 == ~E_M~0); 63715#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 63716#L602-1 assume !(1 == ~E_2~0); 63935#L607-1 assume !(1 == ~E_3~0); 63936#L612-1 assume !(1 == ~E_4~0); 63885#L617-1 assume { :end_inline_reset_delta_events } true; 63886#L803-2 [2022-02-21 04:22:08,218 INFO L793 eck$LassoCheckResult]: Loop: 63886#L803-2 assume !false; 66915#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66913#L489 assume !false; 66911#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66908#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66902#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66900#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 66897#L428 assume !(0 != eval_~tmp~0#1); 66895#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66893#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66892#L514-3 assume !(0 == ~M_E~0); 66890#L514-5 assume !(0 == ~T1_E~0); 66888#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66886#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66884#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66882#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 66880#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 66878#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66876#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 66873#L554-3 assume !(0 == ~E_4~0); 66869#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66864#L250-18 assume !(1 == ~m_pc~0); 66859#L250-20 is_master_triggered_~__retres1~0#1 := 0; 66855#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66851#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 66847#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66843#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66838#L269-18 assume !(1 == ~t1_pc~0); 66833#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 66827#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66821#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66816#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 66810#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66806#L288-18 assume !(1 == ~t2_pc~0); 66745#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 66797#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66792#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66786#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66781#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66780#L307-18 assume !(1 == ~t3_pc~0); 66771#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 66765#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66759#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66753#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66747#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66740#L326-18 assume !(1 == ~t4_pc~0); 66732#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 66726#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66721#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66715#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66709#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66704#L572-3 assume !(1 == ~M_E~0); 66056#L572-5 assume !(1 == ~T1_E~0); 66696#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66691#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66686#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66680#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 66675#L597-3 assume !(1 == ~E_1~0); 66670#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66665#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66660#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66648#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 64322#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 64313#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 64303#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 64296#L822 assume !(0 == start_simulation_~tmp~3#1); 64297#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 67523#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 67519#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66950#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 66948#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66947#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66946#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 66945#L835 assume !(0 != start_simulation_~tmp___0~1#1); 63886#L803-2 [2022-02-21 04:22:08,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2022-02-21 04:22:08,219 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,219 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1868596230] [2022-02-21 04:22:08,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,245 INFO L290 TraceCheckUtils]: 0: Hoare triple {81292#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,246 INFO L290 TraceCheckUtils]: 1: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,246 INFO L290 TraceCheckUtils]: 2: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,246 INFO L290 TraceCheckUtils]: 3: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,247 INFO L290 TraceCheckUtils]: 4: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,247 INFO L290 TraceCheckUtils]: 5: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,247 INFO L290 TraceCheckUtils]: 6: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,248 INFO L290 TraceCheckUtils]: 7: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,248 INFO L290 TraceCheckUtils]: 8: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,248 INFO L290 TraceCheckUtils]: 9: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,249 INFO L290 TraceCheckUtils]: 10: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~M_E~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,249 INFO L290 TraceCheckUtils]: 11: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~T1_E~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,249 INFO L290 TraceCheckUtils]: 12: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~T2_E~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,250 INFO L290 TraceCheckUtils]: 13: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~T3_E~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,250 INFO L290 TraceCheckUtils]: 14: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~T4_E~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,250 INFO L290 TraceCheckUtils]: 15: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~E_M~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,251 INFO L290 TraceCheckUtils]: 16: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~E_1~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,251 INFO L290 TraceCheckUtils]: 17: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~E_2~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,251 INFO L290 TraceCheckUtils]: 18: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~E_3~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,252 INFO L290 TraceCheckUtils]: 19: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 == ~E_4~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,252 INFO L290 TraceCheckUtils]: 20: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,252 INFO L290 TraceCheckUtils]: 21: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~m_pc~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,253 INFO L290 TraceCheckUtils]: 22: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_master_triggered_~__retres1~0#1 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,253 INFO L290 TraceCheckUtils]: 23: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,253 INFO L290 TraceCheckUtils]: 24: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,254 INFO L290 TraceCheckUtils]: 25: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 != activate_threads_~tmp~1#1); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,254 INFO L290 TraceCheckUtils]: 26: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,254 INFO L290 TraceCheckUtils]: 27: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~t1_pc~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,255 INFO L290 TraceCheckUtils]: 28: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit1_triggered_~__retres1~1#1 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,255 INFO L290 TraceCheckUtils]: 29: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,255 INFO L290 TraceCheckUtils]: 30: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,256 INFO L290 TraceCheckUtils]: 31: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___0~0#1); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,256 INFO L290 TraceCheckUtils]: 32: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,256 INFO L290 TraceCheckUtils]: 33: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~t2_pc~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,257 INFO L290 TraceCheckUtils]: 34: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit2_triggered_~__retres1~2#1 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,257 INFO L290 TraceCheckUtils]: 35: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,257 INFO L290 TraceCheckUtils]: 36: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,258 INFO L290 TraceCheckUtils]: 37: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___1~0#1); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,258 INFO L290 TraceCheckUtils]: 38: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,258 INFO L290 TraceCheckUtils]: 39: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~t3_pc~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,259 INFO L290 TraceCheckUtils]: 40: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit3_triggered_~__retres1~3#1 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,259 INFO L290 TraceCheckUtils]: 41: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,259 INFO L290 TraceCheckUtils]: 42: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,260 INFO L290 TraceCheckUtils]: 43: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___2~0#1); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,260 INFO L290 TraceCheckUtils]: 44: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,260 INFO L290 TraceCheckUtils]: 45: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~t4_pc~0); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,261 INFO L290 TraceCheckUtils]: 46: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit4_triggered_~__retres1~4#1 := 0; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,261 INFO L290 TraceCheckUtils]: 47: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,261 INFO L290 TraceCheckUtils]: 48: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,262 INFO L290 TraceCheckUtils]: 49: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(0 != activate_threads_~tmp___3~0#1); {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,262 INFO L290 TraceCheckUtils]: 50: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {81294#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:08,262 INFO L290 TraceCheckUtils]: 51: Hoare triple {81294#(= ~E_1~0 ~M_E~0)} assume !(1 == ~M_E~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,263 INFO L290 TraceCheckUtils]: 52: Hoare triple {81295#(not (= ~E_1~0 1))} assume !(1 == ~T1_E~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,263 INFO L290 TraceCheckUtils]: 53: Hoare triple {81295#(not (= ~E_1~0 1))} assume !(1 == ~T2_E~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,263 INFO L290 TraceCheckUtils]: 54: Hoare triple {81295#(not (= ~E_1~0 1))} assume !(1 == ~T3_E~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,264 INFO L290 TraceCheckUtils]: 55: Hoare triple {81295#(not (= ~E_1~0 1))} assume !(1 == ~T4_E~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,264 INFO L290 TraceCheckUtils]: 56: Hoare triple {81295#(not (= ~E_1~0 1))} assume !(1 == ~E_M~0); {81295#(not (= ~E_1~0 1))} is VALID [2022-02-21 04:22:08,264 INFO L290 TraceCheckUtils]: 57: Hoare triple {81295#(not (= ~E_1~0 1))} assume 1 == ~E_1~0;~E_1~0 := 2; {81293#false} is VALID [2022-02-21 04:22:08,265 INFO L290 TraceCheckUtils]: 58: Hoare triple {81293#false} assume !(1 == ~E_2~0); {81293#false} is VALID [2022-02-21 04:22:08,265 INFO L290 TraceCheckUtils]: 59: Hoare triple {81293#false} assume !(1 == ~E_3~0); {81293#false} is VALID [2022-02-21 04:22:08,265 INFO L290 TraceCheckUtils]: 60: Hoare triple {81293#false} assume !(1 == ~E_4~0); {81293#false} is VALID [2022-02-21 04:22:08,265 INFO L290 TraceCheckUtils]: 61: Hoare triple {81293#false} assume { :end_inline_reset_delta_events } true; {81293#false} is VALID [2022-02-21 04:22:08,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,266 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,266 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1868596230] [2022-02-21 04:22:08,266 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1868596230] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,267 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,268 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,269 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577228292] [2022-02-21 04:22:08,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,270 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:08,270 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:08,270 INFO L85 PathProgramCache]: Analyzing trace with hash 689801394, now seen corresponding path program 1 times [2022-02-21 04:22:08,270 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:08,270 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652261315] [2022-02-21 04:22:08,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:08,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:08,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:08,292 INFO L290 TraceCheckUtils]: 0: Hoare triple {81296#true} assume !false; {81296#true} is VALID [2022-02-21 04:22:08,292 INFO L290 TraceCheckUtils]: 1: Hoare triple {81296#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {81296#true} is VALID [2022-02-21 04:22:08,292 INFO L290 TraceCheckUtils]: 2: Hoare triple {81296#true} assume !false; {81296#true} is VALID [2022-02-21 04:22:08,292 INFO L290 TraceCheckUtils]: 3: Hoare triple {81296#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {81296#true} is VALID [2022-02-21 04:22:08,292 INFO L290 TraceCheckUtils]: 4: Hoare triple {81296#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 5: Hoare triple {81296#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 6: Hoare triple {81296#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 7: Hoare triple {81296#true} assume !(0 != eval_~tmp~0#1); {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 8: Hoare triple {81296#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 9: Hoare triple {81296#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 10: Hoare triple {81296#true} assume !(0 == ~M_E~0); {81296#true} is VALID [2022-02-21 04:22:08,293 INFO L290 TraceCheckUtils]: 11: Hoare triple {81296#true} assume !(0 == ~T1_E~0); {81296#true} is VALID [2022-02-21 04:22:08,294 INFO L290 TraceCheckUtils]: 12: Hoare triple {81296#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {81296#true} is VALID [2022-02-21 04:22:08,294 INFO L290 TraceCheckUtils]: 13: Hoare triple {81296#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {81296#true} is VALID [2022-02-21 04:22:08,294 INFO L290 TraceCheckUtils]: 14: Hoare triple {81296#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {81296#true} is VALID [2022-02-21 04:22:08,294 INFO L290 TraceCheckUtils]: 15: Hoare triple {81296#true} assume 0 == ~E_M~0;~E_M~0 := 1; {81296#true} is VALID [2022-02-21 04:22:08,294 INFO L290 TraceCheckUtils]: 16: Hoare triple {81296#true} assume 0 == ~E_1~0;~E_1~0 := 1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,295 INFO L290 TraceCheckUtils]: 17: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,295 INFO L290 TraceCheckUtils]: 18: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,296 INFO L290 TraceCheckUtils]: 19: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,296 INFO L290 TraceCheckUtils]: 20: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,296 INFO L290 TraceCheckUtils]: 21: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,297 INFO L290 TraceCheckUtils]: 22: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,297 INFO L290 TraceCheckUtils]: 23: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,298 INFO L290 TraceCheckUtils]: 24: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,298 INFO L290 TraceCheckUtils]: 25: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,298 INFO L290 TraceCheckUtils]: 26: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,299 INFO L290 TraceCheckUtils]: 27: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,299 INFO L290 TraceCheckUtils]: 28: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,299 INFO L290 TraceCheckUtils]: 29: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,300 INFO L290 TraceCheckUtils]: 30: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,300 INFO L290 TraceCheckUtils]: 31: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,301 INFO L290 TraceCheckUtils]: 32: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,301 INFO L290 TraceCheckUtils]: 33: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,301 INFO L290 TraceCheckUtils]: 34: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,302 INFO L290 TraceCheckUtils]: 35: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,302 INFO L290 TraceCheckUtils]: 36: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,302 INFO L290 TraceCheckUtils]: 37: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,303 INFO L290 TraceCheckUtils]: 38: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,303 INFO L290 TraceCheckUtils]: 39: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,304 INFO L290 TraceCheckUtils]: 40: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,304 INFO L290 TraceCheckUtils]: 41: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,304 INFO L290 TraceCheckUtils]: 42: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,305 INFO L290 TraceCheckUtils]: 43: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,305 INFO L290 TraceCheckUtils]: 44: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,305 INFO L290 TraceCheckUtils]: 45: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t4_pc~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,306 INFO L290 TraceCheckUtils]: 46: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,306 INFO L290 TraceCheckUtils]: 47: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,307 INFO L290 TraceCheckUtils]: 48: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,307 INFO L290 TraceCheckUtils]: 49: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,307 INFO L290 TraceCheckUtils]: 50: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,308 INFO L290 TraceCheckUtils]: 51: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~M_E~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,308 INFO L290 TraceCheckUtils]: 52: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,308 INFO L290 TraceCheckUtils]: 53: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,309 INFO L290 TraceCheckUtils]: 54: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,309 INFO L290 TraceCheckUtils]: 55: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,310 INFO L290 TraceCheckUtils]: 56: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {81298#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:08,310 INFO L290 TraceCheckUtils]: 57: Hoare triple {81298#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {81297#false} is VALID [2022-02-21 04:22:08,310 INFO L290 TraceCheckUtils]: 58: Hoare triple {81297#false} assume 1 == ~E_2~0;~E_2~0 := 2; {81297#false} is VALID [2022-02-21 04:22:08,310 INFO L290 TraceCheckUtils]: 59: Hoare triple {81297#false} assume 1 == ~E_3~0;~E_3~0 := 2; {81297#false} is VALID [2022-02-21 04:22:08,310 INFO L290 TraceCheckUtils]: 60: Hoare triple {81297#false} assume 1 == ~E_4~0;~E_4~0 := 2; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 61: Hoare triple {81297#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 62: Hoare triple {81297#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 63: Hoare triple {81297#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 64: Hoare triple {81297#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 65: Hoare triple {81297#false} assume !(0 == start_simulation_~tmp~3#1); {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 66: Hoare triple {81297#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {81297#false} is VALID [2022-02-21 04:22:08,311 INFO L290 TraceCheckUtils]: 67: Hoare triple {81297#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 68: Hoare triple {81297#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 69: Hoare triple {81297#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 70: Hoare triple {81297#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 71: Hoare triple {81297#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 72: Hoare triple {81297#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {81297#false} is VALID [2022-02-21 04:22:08,312 INFO L290 TraceCheckUtils]: 73: Hoare triple {81297#false} assume !(0 != start_simulation_~tmp___0~1#1); {81297#false} is VALID [2022-02-21 04:22:08,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:08,313 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:08,313 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652261315] [2022-02-21 04:22:08,313 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652261315] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:08,313 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:08,313 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:08,314 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307684259] [2022-02-21 04:22:08,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:08,314 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:08,314 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:08,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:08,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:08,315 INFO L87 Difference]: Start difference. First operand 4687 states and 6664 transitions. cyclomatic complexity: 1981 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,152 INFO L93 Difference]: Finished difference Result 6415 states and 8953 transitions. [2022-02-21 04:22:10,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:10,153 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,191 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:10,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6415 states and 8953 transitions. [2022-02-21 04:22:11,160 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6230 [2022-02-21 04:22:11,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6415 states to 6415 states and 8953 transitions. [2022-02-21 04:22:11,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6415 [2022-02-21 04:22:11,978 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6415 [2022-02-21 04:22:11,978 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6415 states and 8953 transitions. [2022-02-21 04:22:11,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:11,984 INFO L681 BuchiCegarLoop]: Abstraction has 6415 states and 8953 transitions. [2022-02-21 04:22:11,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6415 states and 8953 transitions. [2022-02-21 04:22:12,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6415 to 5274. [2022-02-21 04:22:12,037 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:12,044 INFO L82 GeneralOperation]: Start isEquivalent. First operand 6415 states and 8953 transitions. Second operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,048 INFO L74 IsIncluded]: Start isIncluded. First operand 6415 states and 8953 transitions. Second operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,053 INFO L87 Difference]: Start difference. First operand 6415 states and 8953 transitions. Second operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,932 INFO L93 Difference]: Finished difference Result 6415 states and 8953 transitions. [2022-02-21 04:22:12,932 INFO L276 IsEmpty]: Start isEmpty. Operand 6415 states and 8953 transitions. [2022-02-21 04:22:12,938 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,938 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,943 INFO L74 IsIncluded]: Start isIncluded. First operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6415 states and 8953 transitions. [2022-02-21 04:22:12,945 INFO L87 Difference]: Start difference. First operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 6415 states and 8953 transitions. [2022-02-21 04:22:13,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,787 INFO L93 Difference]: Finished difference Result 6415 states and 8953 transitions. [2022-02-21 04:22:13,787 INFO L276 IsEmpty]: Start isEmpty. Operand 6415 states and 8953 transitions. [2022-02-21 04:22:13,794 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,794 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,794 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:13,794 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:13,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5274 states, 5274 states have (on average 1.403109594235874) internal successors, (7400), 5273 states have internal predecessors, (7400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5274 states to 5274 states and 7400 transitions. [2022-02-21 04:22:14,362 INFO L704 BuchiCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-02-21 04:22:14,362 INFO L587 BuchiCegarLoop]: Abstraction has 5274 states and 7400 transitions. [2022-02-21 04:22:14,362 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2022-02-21 04:22:14,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5274 states and 7400 transitions. [2022-02-21 04:22:14,370 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5140 [2022-02-21 04:22:14,370 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:14,370 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:14,371 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,372 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,372 INFO L791 eck$LassoCheckResult]: Stem: 88216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 88191#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 88072#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 87805#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87806#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 87862#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88143#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 87811#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 87812#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 87937#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 87843#L514 assume !(0 == ~M_E~0); 87844#L514-2 assume !(0 == ~T1_E~0); 88167#L519-1 assume !(0 == ~T2_E~0); 87797#L524-1 assume !(0 == ~T3_E~0); 87798#L529-1 assume !(0 == ~T4_E~0); 87914#L534-1 assume !(0 == ~E_M~0); 88113#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 88114#L544-1 assume !(0 == ~E_2~0); 88258#L549-1 assume !(0 == ~E_3~0); 88257#L554-1 assume !(0 == ~E_4~0); 88256#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88255#L250 assume !(1 == ~m_pc~0); 88254#L250-2 is_master_triggered_~__retres1~0#1 := 0; 88253#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88252#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 88251#L637 assume !(0 != activate_threads_~tmp~1#1); 87799#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 87800#L269 assume !(1 == ~t1_pc~0); 87829#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88260#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88259#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88246#L645 assume !(0 != activate_threads_~tmp___0~0#1); 88245#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88244#L288 assume !(1 == ~t2_pc~0); 88243#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88242#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88241#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88240#L653 assume !(0 != activate_threads_~tmp___1~0#1); 88239#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88238#L307 assume !(1 == ~t3_pc~0); 88236#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 88235#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88234#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88233#L661 assume !(0 != activate_threads_~tmp___2~0#1); 88232#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88231#L326 assume !(1 == ~t4_pc~0); 88230#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88229#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88228#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88227#L669 assume !(0 != activate_threads_~tmp___3~0#1); 88226#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88225#L572 assume !(1 == ~M_E~0); 88224#L572-2 assume !(1 == ~T1_E~0); 88223#L577-1 assume !(1 == ~T2_E~0); 88222#L582-1 assume !(1 == ~T3_E~0); 88221#L587-1 assume !(1 == ~T4_E~0); 88220#L592-1 assume !(1 == ~E_M~0); 88219#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 87750#L602-1 assume !(1 == ~E_2~0); 87963#L607-1 assume !(1 == ~E_3~0); 87964#L612-1 assume !(1 == ~E_4~0); 87912#L617-1 assume { :end_inline_reset_delta_events } true; 87913#L803-2 [2022-02-21 04:22:14,372 INFO L793 eck$LassoCheckResult]: Loop: 87913#L803-2 assume !false; 88074#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 87835#L489 assume !false; 88045#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 88005#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87853#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87908#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 88210#L428 assume !(0 != eval_~tmp~0#1); 88211#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 92770#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 92768#L514-3 assume !(0 == ~M_E~0); 92766#L514-5 assume !(0 == ~T1_E~0); 92764#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 92763#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 92760#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 92758#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 87730#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87731#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 92913#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 92912#L554-3 assume !(0 == ~E_4~0); 92911#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92910#L250-18 assume !(1 == ~m_pc~0); 92909#L250-20 is_master_triggered_~__retres1~0#1 := 0; 92908#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92907#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 92906#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 92905#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92904#L269-18 assume !(1 == ~t1_pc~0); 92903#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 92901#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92899#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 92897#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 92895#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92894#L288-18 assume !(1 == ~t2_pc~0); 92518#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 92893#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92892#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92891#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 92890#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92889#L307-18 assume !(1 == ~t3_pc~0); 92887#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 92886#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92885#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92884#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 92883#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92882#L326-18 assume !(1 == ~t4_pc~0); 92881#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 92880#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92879#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92878#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 92877#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92876#L572-3 assume !(1 == ~M_E~0); 91939#L572-5 assume !(1 == ~T1_E~0); 92875#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 92874#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92873#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92872#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 92871#L597-3 assume !(1 == ~E_1~0); 92869#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 92868#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 92867#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 92866#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 92864#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 87941#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 87942#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 87997#L822 assume !(0 == start_simulation_~tmp~3#1); 87999#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 88119#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 88049#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 88001#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 87763#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 87764#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88047#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 88063#L835 assume !(0 != start_simulation_~tmp___0~1#1); 87913#L803-2 [2022-02-21 04:22:14,374 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,374 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2022-02-21 04:22:14,375 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,375 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254416638] [2022-02-21 04:22:14,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,399 INFO L290 TraceCheckUtils]: 0: Hoare triple {105823#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,399 INFO L290 TraceCheckUtils]: 1: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,400 INFO L290 TraceCheckUtils]: 2: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,400 INFO L290 TraceCheckUtils]: 3: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,400 INFO L290 TraceCheckUtils]: 4: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,401 INFO L290 TraceCheckUtils]: 5: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,401 INFO L290 TraceCheckUtils]: 6: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,401 INFO L290 TraceCheckUtils]: 7: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,402 INFO L290 TraceCheckUtils]: 8: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,402 INFO L290 TraceCheckUtils]: 9: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {105825#(= ~E_1~0 ~M_E~0)} is VALID [2022-02-21 04:22:14,402 INFO L290 TraceCheckUtils]: 10: Hoare triple {105825#(= ~E_1~0 ~M_E~0)} assume !(0 == ~M_E~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,403 INFO L290 TraceCheckUtils]: 11: Hoare triple {105826#(not (= ~E_1~0 0))} assume !(0 == ~T1_E~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,403 INFO L290 TraceCheckUtils]: 12: Hoare triple {105826#(not (= ~E_1~0 0))} assume !(0 == ~T2_E~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,403 INFO L290 TraceCheckUtils]: 13: Hoare triple {105826#(not (= ~E_1~0 0))} assume !(0 == ~T3_E~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,404 INFO L290 TraceCheckUtils]: 14: Hoare triple {105826#(not (= ~E_1~0 0))} assume !(0 == ~T4_E~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,404 INFO L290 TraceCheckUtils]: 15: Hoare triple {105826#(not (= ~E_1~0 0))} assume !(0 == ~E_M~0); {105826#(not (= ~E_1~0 0))} is VALID [2022-02-21 04:22:14,404 INFO L290 TraceCheckUtils]: 16: Hoare triple {105826#(not (= ~E_1~0 0))} assume 0 == ~E_1~0;~E_1~0 := 1; {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 17: Hoare triple {105824#false} assume !(0 == ~E_2~0); {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 18: Hoare triple {105824#false} assume !(0 == ~E_3~0); {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 19: Hoare triple {105824#false} assume !(0 == ~E_4~0); {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 20: Hoare triple {105824#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 21: Hoare triple {105824#false} assume !(1 == ~m_pc~0); {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 22: Hoare triple {105824#false} is_master_triggered_~__retres1~0#1 := 0; {105824#false} is VALID [2022-02-21 04:22:14,405 INFO L290 TraceCheckUtils]: 23: Hoare triple {105824#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 24: Hoare triple {105824#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 25: Hoare triple {105824#false} assume !(0 != activate_threads_~tmp~1#1); {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 26: Hoare triple {105824#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 27: Hoare triple {105824#false} assume !(1 == ~t1_pc~0); {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 28: Hoare triple {105824#false} is_transmit1_triggered_~__retres1~1#1 := 0; {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 29: Hoare triple {105824#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {105824#false} is VALID [2022-02-21 04:22:14,406 INFO L290 TraceCheckUtils]: 30: Hoare triple {105824#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 31: Hoare triple {105824#false} assume !(0 != activate_threads_~tmp___0~0#1); {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 32: Hoare triple {105824#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 33: Hoare triple {105824#false} assume !(1 == ~t2_pc~0); {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 34: Hoare triple {105824#false} is_transmit2_triggered_~__retres1~2#1 := 0; {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 35: Hoare triple {105824#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 36: Hoare triple {105824#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {105824#false} is VALID [2022-02-21 04:22:14,407 INFO L290 TraceCheckUtils]: 37: Hoare triple {105824#false} assume !(0 != activate_threads_~tmp___1~0#1); {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 38: Hoare triple {105824#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 39: Hoare triple {105824#false} assume !(1 == ~t3_pc~0); {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 40: Hoare triple {105824#false} is_transmit3_triggered_~__retres1~3#1 := 0; {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 41: Hoare triple {105824#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 42: Hoare triple {105824#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {105824#false} is VALID [2022-02-21 04:22:14,408 INFO L290 TraceCheckUtils]: 43: Hoare triple {105824#false} assume !(0 != activate_threads_~tmp___2~0#1); {105824#false} is VALID [2022-02-21 04:22:14,409 INFO L290 TraceCheckUtils]: 44: Hoare triple {105824#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {105824#false} is VALID [2022-02-21 04:22:14,409 INFO L290 TraceCheckUtils]: 45: Hoare triple {105824#false} assume !(1 == ~t4_pc~0); {105824#false} is VALID [2022-02-21 04:22:14,409 INFO L290 TraceCheckUtils]: 46: Hoare triple {105824#false} is_transmit4_triggered_~__retres1~4#1 := 0; {105824#false} is VALID [2022-02-21 04:22:14,409 INFO L290 TraceCheckUtils]: 47: Hoare triple {105824#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {105824#false} is VALID [2022-02-21 04:22:14,409 INFO L290 TraceCheckUtils]: 48: Hoare triple {105824#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 49: Hoare triple {105824#false} assume !(0 != activate_threads_~tmp___3~0#1); {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 50: Hoare triple {105824#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 51: Hoare triple {105824#false} assume !(1 == ~M_E~0); {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 52: Hoare triple {105824#false} assume !(1 == ~T1_E~0); {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 53: Hoare triple {105824#false} assume !(1 == ~T2_E~0); {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 54: Hoare triple {105824#false} assume !(1 == ~T3_E~0); {105824#false} is VALID [2022-02-21 04:22:14,410 INFO L290 TraceCheckUtils]: 55: Hoare triple {105824#false} assume !(1 == ~T4_E~0); {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 56: Hoare triple {105824#false} assume !(1 == ~E_M~0); {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 57: Hoare triple {105824#false} assume 1 == ~E_1~0;~E_1~0 := 2; {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 58: Hoare triple {105824#false} assume !(1 == ~E_2~0); {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 59: Hoare triple {105824#false} assume !(1 == ~E_3~0); {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 60: Hoare triple {105824#false} assume !(1 == ~E_4~0); {105824#false} is VALID [2022-02-21 04:22:14,411 INFO L290 TraceCheckUtils]: 61: Hoare triple {105824#false} assume { :end_inline_reset_delta_events } true; {105824#false} is VALID [2022-02-21 04:22:14,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,412 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,412 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254416638] [2022-02-21 04:22:14,412 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254416638] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,412 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,412 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,412 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292282078] [2022-02-21 04:22:14,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,413 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:14,414 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,414 INFO L85 PathProgramCache]: Analyzing trace with hash 689801394, now seen corresponding path program 2 times [2022-02-21 04:22:14,414 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,414 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11302679] [2022-02-21 04:22:14,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,436 INFO L290 TraceCheckUtils]: 0: Hoare triple {105827#true} assume !false; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 1: Hoare triple {105827#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 2: Hoare triple {105827#true} assume !false; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 3: Hoare triple {105827#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 4: Hoare triple {105827#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 5: Hoare triple {105827#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {105827#true} is VALID [2022-02-21 04:22:14,437 INFO L290 TraceCheckUtils]: 6: Hoare triple {105827#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 7: Hoare triple {105827#true} assume !(0 != eval_~tmp~0#1); {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 8: Hoare triple {105827#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 9: Hoare triple {105827#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 10: Hoare triple {105827#true} assume !(0 == ~M_E~0); {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 11: Hoare triple {105827#true} assume !(0 == ~T1_E~0); {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 12: Hoare triple {105827#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {105827#true} is VALID [2022-02-21 04:22:14,438 INFO L290 TraceCheckUtils]: 13: Hoare triple {105827#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {105827#true} is VALID [2022-02-21 04:22:14,439 INFO L290 TraceCheckUtils]: 14: Hoare triple {105827#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {105827#true} is VALID [2022-02-21 04:22:14,439 INFO L290 TraceCheckUtils]: 15: Hoare triple {105827#true} assume 0 == ~E_M~0;~E_M~0 := 1; {105827#true} is VALID [2022-02-21 04:22:14,439 INFO L290 TraceCheckUtils]: 16: Hoare triple {105827#true} assume 0 == ~E_1~0;~E_1~0 := 1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,440 INFO L290 TraceCheckUtils]: 17: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,440 INFO L290 TraceCheckUtils]: 18: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,440 INFO L290 TraceCheckUtils]: 19: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(0 == ~E_4~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,441 INFO L290 TraceCheckUtils]: 20: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,441 INFO L290 TraceCheckUtils]: 21: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~m_pc~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,441 INFO L290 TraceCheckUtils]: 22: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,442 INFO L290 TraceCheckUtils]: 23: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,442 INFO L290 TraceCheckUtils]: 24: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,443 INFO L290 TraceCheckUtils]: 25: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,443 INFO L290 TraceCheckUtils]: 26: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,443 INFO L290 TraceCheckUtils]: 27: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t1_pc~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,444 INFO L290 TraceCheckUtils]: 28: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,444 INFO L290 TraceCheckUtils]: 29: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,444 INFO L290 TraceCheckUtils]: 30: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,445 INFO L290 TraceCheckUtils]: 31: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(0 != activate_threads_~tmp___0~0#1); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,445 INFO L290 TraceCheckUtils]: 32: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,446 INFO L290 TraceCheckUtils]: 33: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t2_pc~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,446 INFO L290 TraceCheckUtils]: 34: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,446 INFO L290 TraceCheckUtils]: 35: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,447 INFO L290 TraceCheckUtils]: 36: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,447 INFO L290 TraceCheckUtils]: 37: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,447 INFO L290 TraceCheckUtils]: 38: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,448 INFO L290 TraceCheckUtils]: 39: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t3_pc~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,448 INFO L290 TraceCheckUtils]: 40: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,449 INFO L290 TraceCheckUtils]: 41: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,449 INFO L290 TraceCheckUtils]: 42: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,449 INFO L290 TraceCheckUtils]: 43: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,450 INFO L290 TraceCheckUtils]: 44: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,450 INFO L290 TraceCheckUtils]: 45: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~t4_pc~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,450 INFO L290 TraceCheckUtils]: 46: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,451 INFO L290 TraceCheckUtils]: 47: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,451 INFO L290 TraceCheckUtils]: 48: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,452 INFO L290 TraceCheckUtils]: 49: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,452 INFO L290 TraceCheckUtils]: 50: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,452 INFO L290 TraceCheckUtils]: 51: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~M_E~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,453 INFO L290 TraceCheckUtils]: 52: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~T1_E~0); {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,453 INFO L290 TraceCheckUtils]: 53: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,453 INFO L290 TraceCheckUtils]: 54: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,454 INFO L290 TraceCheckUtils]: 55: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,454 INFO L290 TraceCheckUtils]: 56: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume 1 == ~E_M~0;~E_M~0 := 2; {105829#(= (+ (- 1) ~E_1~0) 0)} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 57: Hoare triple {105829#(= (+ (- 1) ~E_1~0) 0)} assume !(1 == ~E_1~0); {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 58: Hoare triple {105828#false} assume 1 == ~E_2~0;~E_2~0 := 2; {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 59: Hoare triple {105828#false} assume 1 == ~E_3~0;~E_3~0 := 2; {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 60: Hoare triple {105828#false} assume 1 == ~E_4~0;~E_4~0 := 2; {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 61: Hoare triple {105828#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 62: Hoare triple {105828#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {105828#false} is VALID [2022-02-21 04:22:14,455 INFO L290 TraceCheckUtils]: 63: Hoare triple {105828#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 64: Hoare triple {105828#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 65: Hoare triple {105828#false} assume !(0 == start_simulation_~tmp~3#1); {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 66: Hoare triple {105828#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 67: Hoare triple {105828#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 68: Hoare triple {105828#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 69: Hoare triple {105828#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {105828#false} is VALID [2022-02-21 04:22:14,456 INFO L290 TraceCheckUtils]: 70: Hoare triple {105828#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {105828#false} is VALID [2022-02-21 04:22:14,457 INFO L290 TraceCheckUtils]: 71: Hoare triple {105828#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {105828#false} is VALID [2022-02-21 04:22:14,457 INFO L290 TraceCheckUtils]: 72: Hoare triple {105828#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {105828#false} is VALID [2022-02-21 04:22:14,457 INFO L290 TraceCheckUtils]: 73: Hoare triple {105828#false} assume !(0 != start_simulation_~tmp___0~1#1); {105828#false} is VALID [2022-02-21 04:22:14,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,457 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,458 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11302679] [2022-02-21 04:22:14,458 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11302679] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,458 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,458 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,458 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348967920] [2022-02-21 04:22:14,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,459 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:14,459 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:14,459 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:14,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:14,460 INFO L87 Difference]: Start difference. First operand 5274 states and 7400 transitions. cyclomatic complexity: 2130 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:15,636 INFO L93 Difference]: Finished difference Result 5366 states and 7487 transitions. [2022-02-21 04:22:15,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:15,636 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:15,675 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:15,676 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5366 states and 7487 transitions. [2022-02-21 04:22:16,221 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5262 [2022-02-21 04:22:16,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5366 states to 5366 states and 7487 transitions. [2022-02-21 04:22:16,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5366 [2022-02-21 04:22:16,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5366 [2022-02-21 04:22:16,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5366 states and 7487 transitions. [2022-02-21 04:22:16,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:16,811 INFO L681 BuchiCegarLoop]: Abstraction has 5366 states and 7487 transitions. [2022-02-21 04:22:16,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5366 states and 7487 transitions. [2022-02-21 04:22:16,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5366 to 4468. [2022-02-21 04:22:16,859 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:16,864 INFO L82 GeneralOperation]: Start isEquivalent. First operand 5366 states and 7487 transitions. Second operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,870 INFO L74 IsIncluded]: Start isIncluded. First operand 5366 states and 7487 transitions. Second operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,874 INFO L87 Difference]: Start difference. First operand 5366 states and 7487 transitions. Second operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:17,479 INFO L93 Difference]: Finished difference Result 5366 states and 7487 transitions. [2022-02-21 04:22:17,479 INFO L276 IsEmpty]: Start isEmpty. Operand 5366 states and 7487 transitions. [2022-02-21 04:22:17,488 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:17,488 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:17,492 INFO L74 IsIncluded]: Start isIncluded. First operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5366 states and 7487 transitions. [2022-02-21 04:22:17,495 INFO L87 Difference]: Start difference. First operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 5366 states and 7487 transitions. [2022-02-21 04:22:18,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,089 INFO L93 Difference]: Finished difference Result 5366 states and 7487 transitions. [2022-02-21 04:22:18,089 INFO L276 IsEmpty]: Start isEmpty. Operand 5366 states and 7487 transitions. [2022-02-21 04:22:18,092 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,093 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,093 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:18,093 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:18,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4468 states, 4468 states have (on average 1.3986123545210385) internal successors, (6249), 4467 states have internal predecessors, (6249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:18,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4468 states to 4468 states and 6249 transitions. [2022-02-21 04:22:18,510 INFO L704 BuchiCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-02-21 04:22:18,510 INFO L587 BuchiCegarLoop]: Abstraction has 4468 states and 6249 transitions. [2022-02-21 04:22:18,511 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2022-02-21 04:22:18,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4468 states and 6249 transitions. [2022-02-21 04:22:18,519 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4380 [2022-02-21 04:22:18,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:18,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:18,520 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:18,520 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:18,520 INFO L791 eck$LassoCheckResult]: Stem: 111692#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 111669#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 111556#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 111286#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 111287#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 111342#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 111626#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 111292#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 111293#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 111419#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 111323#L514 assume !(0 == ~M_E~0); 111324#L514-2 assume !(0 == ~T1_E~0); 111647#L519-1 assume !(0 == ~T2_E~0); 111276#L524-1 assume !(0 == ~T3_E~0); 111277#L529-1 assume !(0 == ~T4_E~0); 111395#L534-1 assume !(0 == ~E_M~0); 111602#L539-1 assume !(0 == ~E_1~0); 111603#L544-1 assume !(0 == ~E_2~0); 111623#L549-1 assume !(0 == ~E_3~0); 111624#L554-1 assume !(0 == ~E_4~0); 111271#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 111272#L250 assume !(1 == ~m_pc~0); 111499#L250-2 is_master_triggered_~__retres1~0#1 := 0; 111629#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 111460#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 111461#L637 assume !(0 != activate_threads_~tmp~1#1); 111280#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111281#L269 assume !(1 == ~t1_pc~0); 111217#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 111390#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 111415#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 111416#L645 assume !(0 != activate_threads_~tmp___0~0#1); 111457#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111458#L288 assume !(1 == ~t2_pc~0); 111449#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 111450#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111471#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 111472#L653 assume !(0 != activate_threads_~tmp___1~0#1); 111595#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111486#L307 assume !(1 == ~t3_pc~0); 111408#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 111409#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111546#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111633#L661 assume !(0 != activate_threads_~tmp___2~0#1); 111427#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111428#L326 assume !(1 == ~t4_pc~0); 111230#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 111231#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111484#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111601#L669 assume !(0 != activate_threads_~tmp___3~0#1); 111598#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111599#L572 assume !(1 == ~M_E~0); 111630#L572-2 assume !(1 == ~T1_E~0); 111288#L577-1 assume !(1 == ~T2_E~0); 111289#L582-1 assume !(1 == ~T3_E~0); 111584#L587-1 assume !(1 == ~T4_E~0); 111590#L592-1 assume !(1 == ~E_M~0); 111228#L597-1 assume !(1 == ~E_1~0); 111229#L602-1 assume !(1 == ~E_2~0); 111446#L607-1 assume !(1 == ~E_3~0); 111447#L612-1 assume !(1 == ~E_4~0); 111393#L617-1 assume { :end_inline_reset_delta_events } true; 111394#L803-2 [2022-02-21 04:22:18,521 INFO L793 eck$LassoCheckResult]: Loop: 111394#L803-2 assume !false; 111558#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111315#L489 assume !false; 111528#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 111487#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 111333#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 111389#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 111687#L428 assume !(0 != eval_~tmp~0#1); 111688#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 115475#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 115472#L514-3 assume !(0 == ~M_E~0); 115470#L514-5 assume !(0 == ~T1_E~0); 115468#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 115466#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 115464#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 115462#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 115460#L539-3 assume !(0 == ~E_1~0); 115459#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 115457#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 115455#L554-3 assume !(0 == ~E_4~0); 115453#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115451#L250-18 assume !(1 == ~m_pc~0); 115449#L250-20 is_master_triggered_~__retres1~0#1 := 0; 115446#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115444#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 115442#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 115440#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115438#L269-18 assume !(1 == ~t1_pc~0); 115435#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 115433#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 115431#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 115429#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 115427#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 111399#L288-18 assume !(1 == ~t2_pc~0); 111400#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 111220#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111221#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 111318#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 111378#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 111379#L307-18 assume !(1 == ~t3_pc~0); 111348#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 111349#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 111417#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 111359#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 111360#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111608#L326-18 assume !(1 == ~t4_pc~0); 111609#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 111616#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 111581#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 111208#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 111209#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111673#L572-3 assume !(1 == ~M_E~0); 111376#L572-5 assume !(1 == ~T1_E~0); 111377#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 111269#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 111270#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111519#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 111520#L597-3 assume !(1 == ~E_1~0); 111434#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 111435#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 111386#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 111387#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 111440#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 111404#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 111423#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 111675#L822 assume !(0 == start_simulation_~tmp~3#1); 111597#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 111605#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 111532#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 111485#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 111242#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 111243#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 111530#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 111547#L835 assume !(0 != start_simulation_~tmp___0~1#1); 111394#L803-2 [2022-02-21 04:22:18,521 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:18,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2022-02-21 04:22:18,521 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:18,522 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722370305] [2022-02-21 04:22:18,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:18,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:18,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:18,540 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:18,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:18,582 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:18,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:18,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1123530480, now seen corresponding path program 1 times [2022-02-21 04:22:18,584 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:18,584 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480611083] [2022-02-21 04:22:18,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:18,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:18,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:18,622 INFO L290 TraceCheckUtils]: 0: Hoare triple {126403#true} assume !false; {126403#true} is VALID [2022-02-21 04:22:18,622 INFO L290 TraceCheckUtils]: 1: Hoare triple {126403#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {126403#true} is VALID [2022-02-21 04:22:18,622 INFO L290 TraceCheckUtils]: 2: Hoare triple {126403#true} assume !false; {126403#true} is VALID [2022-02-21 04:22:18,622 INFO L290 TraceCheckUtils]: 3: Hoare triple {126403#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {126403#true} is VALID [2022-02-21 04:22:18,623 INFO L290 TraceCheckUtils]: 4: Hoare triple {126403#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {126405#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} is VALID [2022-02-21 04:22:18,623 INFO L290 TraceCheckUtils]: 5: Hoare triple {126405#(<= 1 |ULTIMATE.start_exists_runnable_thread_~__retres1~5#1|)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {126406#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} is VALID [2022-02-21 04:22:18,624 INFO L290 TraceCheckUtils]: 6: Hoare triple {126406#(<= 1 |ULTIMATE.start_exists_runnable_thread_#res#1|)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {126407#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} is VALID [2022-02-21 04:22:18,624 INFO L290 TraceCheckUtils]: 7: Hoare triple {126407#(<= 1 |ULTIMATE.start_eval_~tmp~0#1|)} assume !(0 != eval_~tmp~0#1); {126404#false} is VALID [2022-02-21 04:22:18,624 INFO L290 TraceCheckUtils]: 8: Hoare triple {126404#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {126404#false} is VALID [2022-02-21 04:22:18,624 INFO L290 TraceCheckUtils]: 9: Hoare triple {126404#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {126404#false} is VALID [2022-02-21 04:22:18,624 INFO L290 TraceCheckUtils]: 10: Hoare triple {126404#false} assume !(0 == ~M_E~0); {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 11: Hoare triple {126404#false} assume !(0 == ~T1_E~0); {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 12: Hoare triple {126404#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 13: Hoare triple {126404#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 14: Hoare triple {126404#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 15: Hoare triple {126404#false} assume 0 == ~E_M~0;~E_M~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 16: Hoare triple {126404#false} assume !(0 == ~E_1~0); {126404#false} is VALID [2022-02-21 04:22:18,625 INFO L290 TraceCheckUtils]: 17: Hoare triple {126404#false} assume 0 == ~E_2~0;~E_2~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 18: Hoare triple {126404#false} assume 0 == ~E_3~0;~E_3~0 := 1; {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 19: Hoare triple {126404#false} assume !(0 == ~E_4~0); {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 20: Hoare triple {126404#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 21: Hoare triple {126404#false} assume !(1 == ~m_pc~0); {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 22: Hoare triple {126404#false} is_master_triggered_~__retres1~0#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 23: Hoare triple {126404#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {126404#false} is VALID [2022-02-21 04:22:18,626 INFO L290 TraceCheckUtils]: 24: Hoare triple {126404#false} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 25: Hoare triple {126404#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 26: Hoare triple {126404#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 27: Hoare triple {126404#false} assume !(1 == ~t1_pc~0); {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 28: Hoare triple {126404#false} is_transmit1_triggered_~__retres1~1#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 29: Hoare triple {126404#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 30: Hoare triple {126404#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {126404#false} is VALID [2022-02-21 04:22:18,627 INFO L290 TraceCheckUtils]: 31: Hoare triple {126404#false} assume !(0 != activate_threads_~tmp___0~0#1); {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 32: Hoare triple {126404#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 33: Hoare triple {126404#false} assume !(1 == ~t2_pc~0); {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 34: Hoare triple {126404#false} is_transmit2_triggered_~__retres1~2#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 35: Hoare triple {126404#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 36: Hoare triple {126404#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 37: Hoare triple {126404#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {126404#false} is VALID [2022-02-21 04:22:18,628 INFO L290 TraceCheckUtils]: 38: Hoare triple {126404#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 39: Hoare triple {126404#false} assume !(1 == ~t3_pc~0); {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 40: Hoare triple {126404#false} is_transmit3_triggered_~__retres1~3#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 41: Hoare triple {126404#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 42: Hoare triple {126404#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 43: Hoare triple {126404#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 44: Hoare triple {126404#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {126404#false} is VALID [2022-02-21 04:22:18,629 INFO L290 TraceCheckUtils]: 45: Hoare triple {126404#false} assume !(1 == ~t4_pc~0); {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 46: Hoare triple {126404#false} is_transmit4_triggered_~__retres1~4#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 47: Hoare triple {126404#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 48: Hoare triple {126404#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 49: Hoare triple {126404#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 50: Hoare triple {126404#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 51: Hoare triple {126404#false} assume !(1 == ~M_E~0); {126404#false} is VALID [2022-02-21 04:22:18,630 INFO L290 TraceCheckUtils]: 52: Hoare triple {126404#false} assume !(1 == ~T1_E~0); {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 53: Hoare triple {126404#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 54: Hoare triple {126404#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 55: Hoare triple {126404#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 56: Hoare triple {126404#false} assume 1 == ~E_M~0;~E_M~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 57: Hoare triple {126404#false} assume !(1 == ~E_1~0); {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 58: Hoare triple {126404#false} assume 1 == ~E_2~0;~E_2~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,631 INFO L290 TraceCheckUtils]: 59: Hoare triple {126404#false} assume 1 == ~E_3~0;~E_3~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 60: Hoare triple {126404#false} assume 1 == ~E_4~0;~E_4~0 := 2; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 61: Hoare triple {126404#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 62: Hoare triple {126404#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 63: Hoare triple {126404#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 64: Hoare triple {126404#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 65: Hoare triple {126404#false} assume !(0 == start_simulation_~tmp~3#1); {126404#false} is VALID [2022-02-21 04:22:18,632 INFO L290 TraceCheckUtils]: 66: Hoare triple {126404#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 67: Hoare triple {126404#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 68: Hoare triple {126404#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 69: Hoare triple {126404#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 70: Hoare triple {126404#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 71: Hoare triple {126404#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 72: Hoare triple {126404#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {126404#false} is VALID [2022-02-21 04:22:18,633 INFO L290 TraceCheckUtils]: 73: Hoare triple {126404#false} assume !(0 != start_simulation_~tmp___0~1#1); {126404#false} is VALID [2022-02-21 04:22:18,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:18,634 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:18,634 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480611083] [2022-02-21 04:22:18,634 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480611083] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:18,634 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:18,634 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:22:18,635 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89358626] [2022-02-21 04:22:18,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:18,635 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:18,635 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:18,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:22:18,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:22:18,636 INFO L87 Difference]: Start difference. First operand 4468 states and 6249 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:20,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:20,965 INFO L93 Difference]: Finished difference Result 7888 states and 10869 transitions. [2022-02-21 04:22:20,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-02-21 04:22:20,965 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:21,022 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:21,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7888 states and 10869 transitions. [2022-02-21 04:22:22,417 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7776 [2022-02-21 04:22:23,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7888 states to 7888 states and 10869 transitions. [2022-02-21 04:22:23,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7888 [2022-02-21 04:22:23,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7888 [2022-02-21 04:22:23,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7888 states and 10869 transitions. [2022-02-21 04:22:23,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:23,753 INFO L681 BuchiCegarLoop]: Abstraction has 7888 states and 10869 transitions. [2022-02-21 04:22:23,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7888 states and 10869 transitions. [2022-02-21 04:22:23,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7888 to 4516. [2022-02-21 04:22:23,806 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:23,810 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7888 states and 10869 transitions. Second operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:23,813 INFO L74 IsIncluded]: Start isIncluded. First operand 7888 states and 10869 transitions. Second operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:23,816 INFO L87 Difference]: Start difference. First operand 7888 states and 10869 transitions. Second operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:25,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:25,055 INFO L93 Difference]: Finished difference Result 7888 states and 10869 transitions. [2022-02-21 04:22:25,055 INFO L276 IsEmpty]: Start isEmpty. Operand 7888 states and 10869 transitions. [2022-02-21 04:22:25,061 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:25,061 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:25,066 INFO L74 IsIncluded]: Start isIncluded. First operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7888 states and 10869 transitions. [2022-02-21 04:22:25,068 INFO L87 Difference]: Start difference. First operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7888 states and 10869 transitions. [2022-02-21 04:22:26,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:26,310 INFO L93 Difference]: Finished difference Result 7888 states and 10869 transitions. [2022-02-21 04:22:26,310 INFO L276 IsEmpty]: Start isEmpty. Operand 7888 states and 10869 transitions. [2022-02-21 04:22:26,315 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:26,315 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:26,315 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:26,315 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:26,318 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4516 states, 4516 states have (on average 1.3943755535872453) internal successors, (6297), 4515 states have internal predecessors, (6297), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:26,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4516 states to 4516 states and 6297 transitions. [2022-02-21 04:22:26,745 INFO L704 BuchiCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-02-21 04:22:26,745 INFO L587 BuchiCegarLoop]: Abstraction has 4516 states and 6297 transitions. [2022-02-21 04:22:26,745 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2022-02-21 04:22:26,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4516 states and 6297 transitions. [2022-02-21 04:22:26,751 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4428 [2022-02-21 04:22:26,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:26,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:26,753 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:26,753 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:26,754 INFO L791 eck$LassoCheckResult]: Stem: 134813#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 134778#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 134663#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134392#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 134393#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 134446#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 134737#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 134398#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 134399#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 134526#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 134428#L514 assume !(0 == ~M_E~0); 134429#L514-2 assume !(0 == ~T1_E~0); 134757#L519-1 assume !(0 == ~T2_E~0); 134382#L524-1 assume !(0 == ~T3_E~0); 134383#L529-1 assume !(0 == ~T4_E~0); 134501#L534-1 assume !(0 == ~E_M~0); 134707#L539-1 assume !(0 == ~E_1~0); 134708#L544-1 assume !(0 == ~E_2~0); 134734#L549-1 assume !(0 == ~E_3~0); 134735#L554-1 assume !(0 == ~E_4~0); 134377#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134378#L250 assume !(1 == ~m_pc~0); 134601#L250-2 is_master_triggered_~__retres1~0#1 := 0; 134740#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134562#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 134563#L637 assume !(0 != activate_threads_~tmp~1#1); 134386#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134387#L269 assume !(1 == ~t1_pc~0); 134323#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 134496#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134521#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 134522#L645 assume !(0 != activate_threads_~tmp___0~0#1); 134559#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134560#L288 assume !(1 == ~t2_pc~0); 134554#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 134555#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134573#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 134574#L653 assume !(0 != activate_threads_~tmp___1~0#1); 134701#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134588#L307 assume !(1 == ~t3_pc~0); 134514#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134515#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134652#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134745#L661 assume !(0 != activate_threads_~tmp___2~0#1); 134534#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134535#L326 assume !(1 == ~t4_pc~0); 134336#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 134337#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134586#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134706#L669 assume !(0 != activate_threads_~tmp___3~0#1); 134703#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134704#L572 assume !(1 == ~M_E~0); 134741#L572-2 assume !(1 == ~T1_E~0); 134394#L577-1 assume !(1 == ~T2_E~0); 134395#L582-1 assume !(1 == ~T3_E~0); 134691#L587-1 assume !(1 == ~T4_E~0); 134697#L592-1 assume !(1 == ~E_M~0); 134334#L597-1 assume !(1 == ~E_1~0); 134335#L602-1 assume !(1 == ~E_2~0); 134551#L607-1 assume !(1 == ~E_3~0); 134552#L612-1 assume !(1 == ~E_4~0); 134499#L617-1 assume { :end_inline_reset_delta_events } true; 134500#L803-2 [2022-02-21 04:22:26,754 INFO L793 eck$LassoCheckResult]: Loop: 134500#L803-2 assume !false; 138425#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 138170#L489 assume !false; 138422#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138421#L386 assume !(0 == ~m_st~0); 138418#L390 assume !(0 == ~t1_st~0); 138419#L394 assume !(0 == ~t2_st~0); 138420#L398 assume !(0 == ~t3_st~0); 138416#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 138417#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 134814#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 134815#L428 assume !(0 != eval_~tmp~0#1); 138604#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138603#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138602#L514-3 assume !(0 == ~M_E~0); 138601#L514-5 assume !(0 == ~T1_E~0); 138600#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138599#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138598#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134597#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 134598#L539-3 assume !(0 == ~E_1~0); 138597#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134798#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134519#L554-3 assume !(0 == ~E_4~0); 134520#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134715#L250-18 assume !(1 == ~m_pc~0); 134716#L250-20 is_master_triggered_~__retres1~0#1 := 0; 138594#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138592#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 138590#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138588#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138586#L269-18 assume !(1 == ~t1_pc~0); 138582#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 138580#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138578#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 138576#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 138574#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138572#L288-18 assume !(1 == ~t2_pc~0); 138070#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 138570#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138568#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138566#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138564#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138562#L307-18 assume 1 == ~t3_pc~0; 138560#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 138556#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138554#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138552#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138550#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138548#L326-18 assume !(1 == ~t4_pc~0); 138546#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 138544#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138542#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138540#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138538#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138536#L572-3 assume !(1 == ~M_E~0); 138533#L572-5 assume !(1 == ~T1_E~0); 138532#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 138531#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138530#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138529#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 138528#L597-3 assume !(1 == ~E_1~0); 138527#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 138526#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 138525#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 138524#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138522#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 138517#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 138515#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 138513#L822 assume !(0 == start_simulation_~tmp~3#1); 138507#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138443#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 138442#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 138436#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 138434#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138432#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138430#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 138428#L835 assume !(0 != start_simulation_~tmp___0~1#1); 134500#L803-2 [2022-02-21 04:22:26,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:26,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2022-02-21 04:22:26,755 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:26,755 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556909956] [2022-02-21 04:22:26,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:26,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:26,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:26,765 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:26,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:26,779 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:26,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:26,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1039754269, now seen corresponding path program 1 times [2022-02-21 04:22:26,780 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:26,780 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568682772] [2022-02-21 04:22:26,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:26,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:26,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:26,856 INFO L290 TraceCheckUtils]: 0: Hoare triple {154601#true} assume !false; {154601#true} is VALID [2022-02-21 04:22:26,857 INFO L290 TraceCheckUtils]: 1: Hoare triple {154601#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {154601#true} is VALID [2022-02-21 04:22:26,857 INFO L290 TraceCheckUtils]: 2: Hoare triple {154601#true} assume !false; {154601#true} is VALID [2022-02-21 04:22:26,857 INFO L290 TraceCheckUtils]: 3: Hoare triple {154601#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {154601#true} is VALID [2022-02-21 04:22:26,857 INFO L290 TraceCheckUtils]: 4: Hoare triple {154601#true} assume !(0 == ~m_st~0); {154601#true} is VALID [2022-02-21 04:22:26,857 INFO L290 TraceCheckUtils]: 5: Hoare triple {154601#true} assume !(0 == ~t1_st~0); {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 6: Hoare triple {154601#true} assume !(0 == ~t2_st~0); {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 7: Hoare triple {154601#true} assume !(0 == ~t3_st~0); {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 8: Hoare triple {154601#true} assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 9: Hoare triple {154601#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 10: Hoare triple {154601#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 11: Hoare triple {154601#true} assume !(0 != eval_~tmp~0#1); {154601#true} is VALID [2022-02-21 04:22:26,858 INFO L290 TraceCheckUtils]: 12: Hoare triple {154601#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 13: Hoare triple {154601#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 14: Hoare triple {154601#true} assume !(0 == ~M_E~0); {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 15: Hoare triple {154601#true} assume !(0 == ~T1_E~0); {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 16: Hoare triple {154601#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 17: Hoare triple {154601#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 18: Hoare triple {154601#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,859 INFO L290 TraceCheckUtils]: 19: Hoare triple {154601#true} assume 0 == ~E_M~0;~E_M~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 20: Hoare triple {154601#true} assume !(0 == ~E_1~0); {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 21: Hoare triple {154601#true} assume 0 == ~E_2~0;~E_2~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 22: Hoare triple {154601#true} assume 0 == ~E_3~0;~E_3~0 := 1; {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 23: Hoare triple {154601#true} assume !(0 == ~E_4~0); {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 24: Hoare triple {154601#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {154601#true} is VALID [2022-02-21 04:22:26,860 INFO L290 TraceCheckUtils]: 25: Hoare triple {154601#true} assume !(1 == ~m_pc~0); {154601#true} is VALID [2022-02-21 04:22:26,861 INFO L290 TraceCheckUtils]: 26: Hoare triple {154601#true} is_master_triggered_~__retres1~0#1 := 0; {154603#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is VALID [2022-02-21 04:22:26,861 INFO L290 TraceCheckUtils]: 27: Hoare triple {154603#(and (<= |ULTIMATE.start_is_master_triggered_~__retres1~0#1| 0) (<= 0 |ULTIMATE.start_is_master_triggered_~__retres1~0#1|))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {154604#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} is VALID [2022-02-21 04:22:26,862 INFO L290 TraceCheckUtils]: 28: Hoare triple {154604#(and (<= 0 |ULTIMATE.start_is_master_triggered_#res#1|) (<= |ULTIMATE.start_is_master_triggered_#res#1| 0))} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {154605#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} is VALID [2022-02-21 04:22:26,862 INFO L290 TraceCheckUtils]: 29: Hoare triple {154605#(and (<= |ULTIMATE.start_activate_threads_~tmp~1#1| 0) (< 0 (+ |ULTIMATE.start_activate_threads_~tmp~1#1| 1)))} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 30: Hoare triple {154602#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 31: Hoare triple {154602#false} assume !(1 == ~t1_pc~0); {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 32: Hoare triple {154602#false} is_transmit1_triggered_~__retres1~1#1 := 0; {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 33: Hoare triple {154602#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 34: Hoare triple {154602#false} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 35: Hoare triple {154602#false} assume !(0 != activate_threads_~tmp___0~0#1); {154602#false} is VALID [2022-02-21 04:22:26,863 INFO L290 TraceCheckUtils]: 36: Hoare triple {154602#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 37: Hoare triple {154602#false} assume !(1 == ~t2_pc~0); {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 38: Hoare triple {154602#false} is_transmit2_triggered_~__retres1~2#1 := 0; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 39: Hoare triple {154602#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 40: Hoare triple {154602#false} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 41: Hoare triple {154602#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 42: Hoare triple {154602#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {154602#false} is VALID [2022-02-21 04:22:26,864 INFO L290 TraceCheckUtils]: 43: Hoare triple {154602#false} assume 1 == ~t3_pc~0; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 44: Hoare triple {154602#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 45: Hoare triple {154602#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 46: Hoare triple {154602#false} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 47: Hoare triple {154602#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 48: Hoare triple {154602#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 49: Hoare triple {154602#false} assume !(1 == ~t4_pc~0); {154602#false} is VALID [2022-02-21 04:22:26,865 INFO L290 TraceCheckUtils]: 50: Hoare triple {154602#false} is_transmit4_triggered_~__retres1~4#1 := 0; {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 51: Hoare triple {154602#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 52: Hoare triple {154602#false} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 53: Hoare triple {154602#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 54: Hoare triple {154602#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 55: Hoare triple {154602#false} assume !(1 == ~M_E~0); {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 56: Hoare triple {154602#false} assume !(1 == ~T1_E~0); {154602#false} is VALID [2022-02-21 04:22:26,866 INFO L290 TraceCheckUtils]: 57: Hoare triple {154602#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 58: Hoare triple {154602#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 59: Hoare triple {154602#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 60: Hoare triple {154602#false} assume 1 == ~E_M~0;~E_M~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 61: Hoare triple {154602#false} assume !(1 == ~E_1~0); {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 62: Hoare triple {154602#false} assume 1 == ~E_2~0;~E_2~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 63: Hoare triple {154602#false} assume 1 == ~E_3~0;~E_3~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,867 INFO L290 TraceCheckUtils]: 64: Hoare triple {154602#false} assume 1 == ~E_4~0;~E_4~0 := 2; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 65: Hoare triple {154602#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 66: Hoare triple {154602#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 67: Hoare triple {154602#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 68: Hoare triple {154602#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 69: Hoare triple {154602#false} assume !(0 == start_simulation_~tmp~3#1); {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 70: Hoare triple {154602#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {154602#false} is VALID [2022-02-21 04:22:26,868 INFO L290 TraceCheckUtils]: 71: Hoare triple {154602#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 72: Hoare triple {154602#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 73: Hoare triple {154602#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 74: Hoare triple {154602#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 75: Hoare triple {154602#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 76: Hoare triple {154602#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {154602#false} is VALID [2022-02-21 04:22:26,869 INFO L290 TraceCheckUtils]: 77: Hoare triple {154602#false} assume !(0 != start_simulation_~tmp___0~1#1); {154602#false} is VALID [2022-02-21 04:22:26,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:26,870 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:26,870 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568682772] [2022-02-21 04:22:26,870 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568682772] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:26,870 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:26,870 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:22:26,871 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577001297] [2022-02-21 04:22:26,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:26,871 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:26,871 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:26,872 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:22:26,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:22:26,872 INFO L87 Difference]: Start difference. First operand 4516 states and 6297 transitions. cyclomatic complexity: 1785 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:30,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:30,250 INFO L93 Difference]: Finished difference Result 8960 states and 12392 transitions. [2022-02-21 04:22:30,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-02-21 04:22:30,250 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:30,293 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:30,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8960 states and 12392 transitions. [2022-02-21 04:22:31,972 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8856 [2022-02-21 04:22:33,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8960 states to 8960 states and 12392 transitions. [2022-02-21 04:22:33,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8960 [2022-02-21 04:22:33,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8960 [2022-02-21 04:22:33,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8960 states and 12392 transitions. [2022-02-21 04:22:33,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:33,611 INFO L681 BuchiCegarLoop]: Abstraction has 8960 states and 12392 transitions. [2022-02-21 04:22:33,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8960 states and 12392 transitions. [2022-02-21 04:22:33,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8960 to 4648. [2022-02-21 04:22:33,654 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:33,659 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8960 states and 12392 transitions. Second operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:33,662 INFO L74 IsIncluded]: Start isIncluded. First operand 8960 states and 12392 transitions. Second operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:33,666 INFO L87 Difference]: Start difference. First operand 8960 states and 12392 transitions. Second operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:35,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:35,368 INFO L93 Difference]: Finished difference Result 8960 states and 12392 transitions. [2022-02-21 04:22:35,368 INFO L276 IsEmpty]: Start isEmpty. Operand 8960 states and 12392 transitions. [2022-02-21 04:22:35,374 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:35,374 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:35,378 INFO L74 IsIncluded]: Start isIncluded. First operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8960 states and 12392 transitions. [2022-02-21 04:22:35,381 INFO L87 Difference]: Start difference. First operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8960 states and 12392 transitions. [2022-02-21 04:22:37,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:37,020 INFO L93 Difference]: Finished difference Result 8960 states and 12392 transitions. [2022-02-21 04:22:37,021 INFO L276 IsEmpty]: Start isEmpty. Operand 8960 states and 12392 transitions. [2022-02-21 04:22:37,025 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:37,026 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:37,026 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:37,026 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:37,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4648 states, 4648 states have (on average 1.3752151462994837) internal successors, (6392), 4647 states have internal predecessors, (6392), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:37,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4648 states to 4648 states and 6392 transitions. [2022-02-21 04:22:37,491 INFO L704 BuchiCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-02-21 04:22:37,491 INFO L587 BuchiCegarLoop]: Abstraction has 4648 states and 6392 transitions. [2022-02-21 04:22:37,491 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2022-02-21 04:22:37,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4648 states and 6392 transitions. [2022-02-21 04:22:37,498 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4560 [2022-02-21 04:22:37,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:37,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:37,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:37,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:37,500 INFO L791 eck$LassoCheckResult]: Stem: 164087#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 164051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 163930#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 163658#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163659#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 163714#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164002#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163664#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163665#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163790#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 163695#L514 assume !(0 == ~M_E~0); 163696#L514-2 assume !(0 == ~T1_E~0); 164030#L519-1 assume !(0 == ~T2_E~0); 163648#L524-1 assume !(0 == ~T3_E~0); 163649#L529-1 assume !(0 == ~T4_E~0); 163767#L534-1 assume !(0 == ~E_M~0); 163972#L539-1 assume !(0 == ~E_1~0); 163973#L544-1 assume !(0 == ~E_2~0); 164000#L549-1 assume !(0 == ~E_3~0); 164001#L554-1 assume !(0 == ~E_4~0); 163643#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 163644#L250 assume !(1 == ~m_pc~0); 163868#L250-2 is_master_triggered_~__retres1~0#1 := 0; 164007#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163830#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 163831#L637 assume !(0 != activate_threads_~tmp~1#1); 163650#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163651#L269 assume !(1 == ~t1_pc~0); 163590#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163762#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163787#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 163788#L645 assume !(0 != activate_threads_~tmp___0~0#1); 163826#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163827#L288 assume !(1 == ~t2_pc~0); 163820#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163821#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163841#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163842#L653 assume !(0 != activate_threads_~tmp___1~0#1); 163966#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163855#L307 assume !(1 == ~t3_pc~0); 163780#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 163781#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163916#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 164011#L661 assume !(0 != activate_threads_~tmp___2~0#1); 163799#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163800#L326 assume !(1 == ~t4_pc~0); 163603#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 163604#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 163851#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 163971#L669 assume !(0 != activate_threads_~tmp___3~0#1); 163968#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163969#L572 assume !(1 == ~M_E~0); 164008#L572-2 assume !(1 == ~T1_E~0); 163660#L577-1 assume !(1 == ~T2_E~0); 163661#L582-1 assume !(1 == ~T3_E~0); 163955#L587-1 assume !(1 == ~T4_E~0); 163962#L592-1 assume !(1 == ~E_M~0); 163595#L597-1 assume !(1 == ~E_1~0); 163596#L602-1 assume !(1 == ~E_2~0); 163817#L607-1 assume !(1 == ~E_3~0); 163818#L612-1 assume !(1 == ~E_4~0); 163765#L617-1 assume { :end_inline_reset_delta_events } true; 163766#L803-2 [2022-02-21 04:22:37,500 INFO L793 eck$LassoCheckResult]: Loop: 163766#L803-2 assume !false; 165228#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 165227#L489 assume !false; 165226#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 165225#L386 assume !(0 == ~m_st~0); 165222#L390 assume !(0 == ~t1_st~0); 165223#L394 assume !(0 == ~t2_st~0); 165224#L398 assume !(0 == ~t3_st~0); 165221#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 165220#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 164979#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 164980#L428 assume !(0 != eval_~tmp~0#1); 165219#L504 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 165218#L346-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 165217#L514-3 assume !(0 == ~M_E~0); 165216#L514-5 assume !(0 == ~T1_E~0); 165215#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 165214#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 165213#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 165212#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 165211#L539-3 assume !(0 == ~E_1~0); 165210#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 165209#L549-3 assume 0 == ~E_3~0;~E_3~0 := 1; 165208#L554-3 assume !(0 == ~E_4~0); 165207#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165206#L250-18 assume !(1 == ~m_pc~0); 165205#L250-20 is_master_triggered_~__retres1~0#1 := 0; 165204#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165203#L262-6 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 165202#L637-18 assume !(0 != activate_threads_~tmp~1#1); 165201#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165200#L269-18 assume !(1 == ~t1_pc~0); 165198#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 165197#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 165196#L281-6 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 165195#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 165194#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 165193#L288-18 assume !(1 == ~t2_pc~0); 164697#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 165192#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 165191#L300-6 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 165190#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 165189#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165188#L307-18 assume !(1 == ~t3_pc~0); 165186#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 165185#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165184#L319-6 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 165183#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 165182#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165181#L326-18 assume !(1 == ~t4_pc~0); 165180#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 165179#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165178#L338-6 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 165177#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 165175#L669-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165173#L572-3 assume !(1 == ~M_E~0); 165073#L572-5 assume !(1 == ~T1_E~0); 165170#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 165168#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 165166#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 165164#L592-3 assume 1 == ~E_M~0;~E_M~0 := 2; 165162#L597-3 assume !(1 == ~E_1~0); 165160#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 165158#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 165156#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 165154#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 165151#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 165146#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165144#L414-1 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 165141#L822 assume !(0 == start_simulation_~tmp~3#1); 165142#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 165249#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 165247#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 165245#L414-2 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 165243#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 165239#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 165237#L785 start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 165235#L835 assume !(0 != start_simulation_~tmp___0~1#1); 163766#L803-2 [2022-02-21 04:22:37,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:37,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2022-02-21 04:22:37,501 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:37,501 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1579545212] [2022-02-21 04:22:37,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:37,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:37,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:37,509 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:37,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:37,523 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:37,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:37,524 INFO L85 PathProgramCache]: Analyzing trace with hash -3823898, now seen corresponding path program 1 times [2022-02-21 04:22:37,524 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:37,524 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [352972871] [2022-02-21 04:22:37,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:37,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:37,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:37,545 INFO L290 TraceCheckUtils]: 0: Hoare triple {186144#true} assume !false; {186144#true} is VALID [2022-02-21 04:22:37,545 INFO L290 TraceCheckUtils]: 1: Hoare triple {186144#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {186144#true} is VALID [2022-02-21 04:22:37,545 INFO L290 TraceCheckUtils]: 2: Hoare triple {186144#true} assume !false; {186144#true} is VALID [2022-02-21 04:22:37,545 INFO L290 TraceCheckUtils]: 3: Hoare triple {186144#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {186144#true} is VALID [2022-02-21 04:22:37,546 INFO L290 TraceCheckUtils]: 4: Hoare triple {186144#true} assume !(0 == ~m_st~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,546 INFO L290 TraceCheckUtils]: 5: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~t1_st~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,546 INFO L290 TraceCheckUtils]: 6: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~t2_st~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,547 INFO L290 TraceCheckUtils]: 7: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~t3_st~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,547 INFO L290 TraceCheckUtils]: 8: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,547 INFO L290 TraceCheckUtils]: 9: Hoare triple {186146#(not (= ~m_st~0 0))} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,548 INFO L290 TraceCheckUtils]: 10: Hoare triple {186146#(not (= ~m_st~0 0))} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,548 INFO L290 TraceCheckUtils]: 11: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 != eval_~tmp~0#1); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,548 INFO L290 TraceCheckUtils]: 12: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,549 INFO L290 TraceCheckUtils]: 13: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,549 INFO L290 TraceCheckUtils]: 14: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~M_E~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,549 INFO L290 TraceCheckUtils]: 15: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~T1_E~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,550 INFO L290 TraceCheckUtils]: 16: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~T2_E~0;~T2_E~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,550 INFO L290 TraceCheckUtils]: 17: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~T3_E~0;~T3_E~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,550 INFO L290 TraceCheckUtils]: 18: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~T4_E~0;~T4_E~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,551 INFO L290 TraceCheckUtils]: 19: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,551 INFO L290 TraceCheckUtils]: 20: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~E_1~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,551 INFO L290 TraceCheckUtils]: 21: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~E_2~0;~E_2~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,552 INFO L290 TraceCheckUtils]: 22: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~E_3~0;~E_3~0 := 1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,552 INFO L290 TraceCheckUtils]: 23: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 == ~E_4~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,552 INFO L290 TraceCheckUtils]: 24: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,552 INFO L290 TraceCheckUtils]: 25: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~m_pc~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,553 INFO L290 TraceCheckUtils]: 26: Hoare triple {186146#(not (= ~m_st~0 0))} is_master_triggered_~__retres1~0#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,553 INFO L290 TraceCheckUtils]: 27: Hoare triple {186146#(not (= ~m_st~0 0))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,553 INFO L290 TraceCheckUtils]: 28: Hoare triple {186146#(not (= ~m_st~0 0))} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,554 INFO L290 TraceCheckUtils]: 29: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp~1#1); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,554 INFO L290 TraceCheckUtils]: 30: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,554 INFO L290 TraceCheckUtils]: 31: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~t1_pc~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,555 INFO L290 TraceCheckUtils]: 32: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit1_triggered_~__retres1~1#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,555 INFO L290 TraceCheckUtils]: 33: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,555 INFO L290 TraceCheckUtils]: 34: Hoare triple {186146#(not (= ~m_st~0 0))} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,556 INFO L290 TraceCheckUtils]: 35: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(0 != activate_threads_~tmp___0~0#1); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,556 INFO L290 TraceCheckUtils]: 36: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,556 INFO L290 TraceCheckUtils]: 37: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~t2_pc~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,557 INFO L290 TraceCheckUtils]: 38: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit2_triggered_~__retres1~2#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,557 INFO L290 TraceCheckUtils]: 39: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,557 INFO L290 TraceCheckUtils]: 40: Hoare triple {186146#(not (= ~m_st~0 0))} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,558 INFO L290 TraceCheckUtils]: 41: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,558 INFO L290 TraceCheckUtils]: 42: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,558 INFO L290 TraceCheckUtils]: 43: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~t3_pc~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,559 INFO L290 TraceCheckUtils]: 44: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit3_triggered_~__retres1~3#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,559 INFO L290 TraceCheckUtils]: 45: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,559 INFO L290 TraceCheckUtils]: 46: Hoare triple {186146#(not (= ~m_st~0 0))} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,559 INFO L290 TraceCheckUtils]: 47: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,560 INFO L290 TraceCheckUtils]: 48: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,560 INFO L290 TraceCheckUtils]: 49: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~t4_pc~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,560 INFO L290 TraceCheckUtils]: 50: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit4_triggered_~__retres1~4#1 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,560 INFO L290 TraceCheckUtils]: 51: Hoare triple {186146#(not (= ~m_st~0 0))} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,561 INFO L290 TraceCheckUtils]: 52: Hoare triple {186146#(not (= ~m_st~0 0))} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,561 INFO L290 TraceCheckUtils]: 53: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,561 INFO L290 TraceCheckUtils]: 54: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,561 INFO L290 TraceCheckUtils]: 55: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~M_E~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,562 INFO L290 TraceCheckUtils]: 56: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~T1_E~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,562 INFO L290 TraceCheckUtils]: 57: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~T2_E~0;~T2_E~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,562 INFO L290 TraceCheckUtils]: 58: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~T3_E~0;~T3_E~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,562 INFO L290 TraceCheckUtils]: 59: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~T4_E~0;~T4_E~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,563 INFO L290 TraceCheckUtils]: 60: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~E_M~0;~E_M~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,563 INFO L290 TraceCheckUtils]: 61: Hoare triple {186146#(not (= ~m_st~0 0))} assume !(1 == ~E_1~0); {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,563 INFO L290 TraceCheckUtils]: 62: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~E_2~0;~E_2~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,564 INFO L290 TraceCheckUtils]: 63: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~E_3~0;~E_3~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,564 INFO L290 TraceCheckUtils]: 64: Hoare triple {186146#(not (= ~m_st~0 0))} assume 1 == ~E_4~0;~E_4~0 := 2; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,564 INFO L290 TraceCheckUtils]: 65: Hoare triple {186146#(not (= ~m_st~0 0))} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {186146#(not (= ~m_st~0 0))} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 66: Hoare triple {186146#(not (= ~m_st~0 0))} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 67: Hoare triple {186145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 68: Hoare triple {186145#false} start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 69: Hoare triple {186145#false} assume !(0 == start_simulation_~tmp~3#1); {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 70: Hoare triple {186145#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 71: Hoare triple {186145#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 72: Hoare triple {186145#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {186145#false} is VALID [2022-02-21 04:22:37,565 INFO L290 TraceCheckUtils]: 73: Hoare triple {186145#false} stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; {186145#false} is VALID [2022-02-21 04:22:37,566 INFO L290 TraceCheckUtils]: 74: Hoare triple {186145#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {186145#false} is VALID [2022-02-21 04:22:37,566 INFO L290 TraceCheckUtils]: 75: Hoare triple {186145#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {186145#false} is VALID [2022-02-21 04:22:37,566 INFO L290 TraceCheckUtils]: 76: Hoare triple {186145#false} start_simulation_#t~ret18#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; {186145#false} is VALID [2022-02-21 04:22:37,566 INFO L290 TraceCheckUtils]: 77: Hoare triple {186145#false} assume !(0 != start_simulation_~tmp___0~1#1); {186145#false} is VALID [2022-02-21 04:22:37,567 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:37,567 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:37,567 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [352972871] [2022-02-21 04:22:37,567 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [352972871] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:37,567 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:37,567 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:37,567 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [513992865] [2022-02-21 04:22:37,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:37,568 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:37,568 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:37,568 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:37,568 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:37,568 INFO L87 Difference]: Start difference. First operand 4648 states and 6392 transitions. cyclomatic complexity: 1748 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:39,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:39,017 INFO L93 Difference]: Finished difference Result 7304 states and 9896 transitions. [2022-02-21 04:22:39,017 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:39,017 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:39,064 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:39,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7304 states and 9896 transitions. [2022-02-21 04:22:40,151 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7206 [2022-02-21 04:22:41,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7304 states to 7304 states and 9896 transitions. [2022-02-21 04:22:41,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7304 [2022-02-21 04:22:41,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7304 [2022-02-21 04:22:41,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7304 states and 9896 transitions. [2022-02-21 04:22:41,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:41,300 INFO L681 BuchiCegarLoop]: Abstraction has 7304 states and 9896 transitions. [2022-02-21 04:22:41,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7304 states and 9896 transitions. [2022-02-21 04:22:41,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7304 to 7048. [2022-02-21 04:22:41,363 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:41,370 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7304 states and 9896 transitions. Second operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:41,378 INFO L74 IsIncluded]: Start isIncluded. First operand 7304 states and 9896 transitions. Second operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:41,387 INFO L87 Difference]: Start difference. First operand 7304 states and 9896 transitions. Second operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:42,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:42,493 INFO L93 Difference]: Finished difference Result 7304 states and 9896 transitions. [2022-02-21 04:22:42,493 INFO L276 IsEmpty]: Start isEmpty. Operand 7304 states and 9896 transitions. [2022-02-21 04:22:42,498 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:42,498 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:42,505 INFO L74 IsIncluded]: Start isIncluded. First operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7304 states and 9896 transitions. [2022-02-21 04:22:42,510 INFO L87 Difference]: Start difference. First operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7304 states and 9896 transitions. [2022-02-21 04:22:43,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:43,599 INFO L93 Difference]: Finished difference Result 7304 states and 9896 transitions. [2022-02-21 04:22:43,599 INFO L276 IsEmpty]: Start isEmpty. Operand 7304 states and 9896 transitions. [2022-02-21 04:22:43,605 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:43,605 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:43,605 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:43,605 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:43,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7048 states, 7048 states have (on average 1.3564131668558457) internal successors, (9560), 7047 states have internal predecessors, (9560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:44,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7048 states to 7048 states and 9560 transitions. [2022-02-21 04:22:44,654 INFO L704 BuchiCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-02-21 04:22:44,654 INFO L587 BuchiCegarLoop]: Abstraction has 7048 states and 9560 transitions. [2022-02-21 04:22:44,654 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2022-02-21 04:22:44,654 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7048 states and 9560 transitions. [2022-02-21 04:22:44,663 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6950 [2022-02-21 04:22:44,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:44,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:44,664 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:44,664 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:44,664 INFO L791 eck$LassoCheckResult]: Stem: 193942#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 193912#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 193801#L766 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 193537#L346 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 193538#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 193593#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 193867#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 193543#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 193544#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193667#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 193573#L514 assume !(0 == ~M_E~0); 193574#L514-2 assume !(0 == ~T1_E~0); 193889#L519-1 assume !(0 == ~T2_E~0); 193529#L524-1 assume !(0 == ~T3_E~0); 193530#L529-1 assume !(0 == ~T4_E~0); 193645#L534-1 assume !(0 == ~E_M~0); 193845#L539-1 assume !(0 == ~E_1~0); 193846#L544-1 assume !(0 == ~E_2~0); 193865#L549-1 assume !(0 == ~E_3~0); 193866#L554-1 assume !(0 == ~E_4~0); 193524#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 193525#L250 assume !(1 == ~m_pc~0); 193741#L250-2 is_master_triggered_~__retres1~0#1 := 0; 193872#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 193705#L262 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 193706#L637 assume !(0 != activate_threads_~tmp~1#1); 193531#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 193532#L269 assume !(1 == ~t1_pc~0); 193470#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 193640#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 193664#L281 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 193665#L645 assume !(0 != activate_threads_~tmp___0~0#1); 193701#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 193702#L288 assume !(1 == ~t2_pc~0); 193696#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 193697#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 193717#L300 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 193718#L653 assume !(0 != activate_threads_~tmp___1~0#1); 193839#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 193730#L307 assume !(1 == ~t3_pc~0); 193658#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 193659#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 193784#L319 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 193877#L661 assume !(0 != activate_threads_~tmp___2~0#1); 193676#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 193677#L326 assume !(1 == ~t4_pc~0); 193483#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 193484#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 193726#L338 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 193844#L669 assume !(0 != activate_threads_~tmp___3~0#1); 193841#L669-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 193842#L572 assume !(1 == ~M_E~0); 193873#L572-2 assume !(1 == ~T1_E~0); 193539#L577-1 assume !(1 == ~T2_E~0); 193540#L582-1 assume !(1 == ~T3_E~0); 193827#L587-1 assume !(1 == ~T4_E~0); 193834#L592-1 assume !(1 == ~E_M~0); 193475#L597-1 assume !(1 == ~E_1~0); 193476#L602-1 assume !(1 == ~E_2~0); 193693#L607-1 assume !(1 == ~E_3~0); 193694#L612-1 assume !(1 == ~E_4~0); 193643#L617-1 assume { :end_inline_reset_delta_events } true; 193644#L803-2 assume !false; 194788#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 194752#L489 [2022-02-21 04:22:44,665 INFO L793 eck$LassoCheckResult]: Loop: 194752#L489 assume !false; 194753#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 194941#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 194939#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 194937#L414 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 194919#L428 assume 0 != eval_~tmp~0#1; 194912#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 194905#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 194829#L433 assume !(0 == ~t1_st~0); 194797#L447 assume !(0 == ~t2_st~0); 194787#L461 assume !(0 == ~t3_st~0); 194791#L475 assume !(0 == ~t4_st~0); 194752#L489 [2022-02-21 04:22:44,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,665 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2022-02-21 04:22:44,665 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,665 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380135392] [2022-02-21 04:22:44,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,675 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:44,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,689 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:44,690 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,690 INFO L85 PathProgramCache]: Analyzing trace with hash 1577382650, now seen corresponding path program 1 times [2022-02-21 04:22:44,690 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,690 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557173340] [2022-02-21 04:22:44,690 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,693 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-02-21 04:22:44,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-02-21 04:22:44,697 INFO L138 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-02-21 04:22:44,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:44,697 INFO L85 PathProgramCache]: Analyzing trace with hash 189250340, now seen corresponding path program 1 times [2022-02-21 04:22:44,697 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:44,698 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133672846] [2022-02-21 04:22:44,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:44,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:44,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:44,730 INFO L290 TraceCheckUtils]: 0: Hoare triple {215114#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; {215114#true} is VALID [2022-02-21 04:22:44,730 INFO L290 TraceCheckUtils]: 1: Hoare triple {215114#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; {215114#true} is VALID [2022-02-21 04:22:44,730 INFO L290 TraceCheckUtils]: 2: Hoare triple {215114#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {215114#true} is VALID [2022-02-21 04:22:44,730 INFO L290 TraceCheckUtils]: 3: Hoare triple {215114#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {215114#true} is VALID [2022-02-21 04:22:44,731 INFO L290 TraceCheckUtils]: 4: Hoare triple {215114#true} assume 1 == ~m_i~0;~m_st~0 := 0; {215114#true} is VALID [2022-02-21 04:22:44,731 INFO L290 TraceCheckUtils]: 5: Hoare triple {215114#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,731 INFO L290 TraceCheckUtils]: 6: Hoare triple {215116#(= ~t1_st~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,732 INFO L290 TraceCheckUtils]: 7: Hoare triple {215116#(= ~t1_st~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,732 INFO L290 TraceCheckUtils]: 8: Hoare triple {215116#(= ~t1_st~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,732 INFO L290 TraceCheckUtils]: 9: Hoare triple {215116#(= ~t1_st~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,733 INFO L290 TraceCheckUtils]: 10: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~M_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,733 INFO L290 TraceCheckUtils]: 11: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~T1_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,733 INFO L290 TraceCheckUtils]: 12: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~T2_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,733 INFO L290 TraceCheckUtils]: 13: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~T3_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,734 INFO L290 TraceCheckUtils]: 14: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~T4_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,734 INFO L290 TraceCheckUtils]: 15: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~E_M~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,734 INFO L290 TraceCheckUtils]: 16: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~E_1~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,735 INFO L290 TraceCheckUtils]: 17: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~E_2~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,735 INFO L290 TraceCheckUtils]: 18: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~E_3~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,735 INFO L290 TraceCheckUtils]: 19: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~E_4~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,736 INFO L290 TraceCheckUtils]: 20: Hoare triple {215116#(= ~t1_st~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,736 INFO L290 TraceCheckUtils]: 21: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~m_pc~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,736 INFO L290 TraceCheckUtils]: 22: Hoare triple {215116#(= ~t1_st~0 0)} is_master_triggered_~__retres1~0#1 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,737 INFO L290 TraceCheckUtils]: 23: Hoare triple {215116#(= ~t1_st~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,737 INFO L290 TraceCheckUtils]: 24: Hoare triple {215116#(= ~t1_st~0 0)} activate_threads_#t~ret11#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,737 INFO L290 TraceCheckUtils]: 25: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp~1#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,738 INFO L290 TraceCheckUtils]: 26: Hoare triple {215116#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,738 INFO L290 TraceCheckUtils]: 27: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~t1_pc~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,738 INFO L290 TraceCheckUtils]: 28: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,739 INFO L290 TraceCheckUtils]: 29: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,739 INFO L290 TraceCheckUtils]: 30: Hoare triple {215116#(= ~t1_st~0 0)} activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,739 INFO L290 TraceCheckUtils]: 31: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,740 INFO L290 TraceCheckUtils]: 32: Hoare triple {215116#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,740 INFO L290 TraceCheckUtils]: 33: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~t2_pc~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,740 INFO L290 TraceCheckUtils]: 34: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,741 INFO L290 TraceCheckUtils]: 35: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,741 INFO L290 TraceCheckUtils]: 36: Hoare triple {215116#(= ~t1_st~0 0)} activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,741 INFO L290 TraceCheckUtils]: 37: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,742 INFO L290 TraceCheckUtils]: 38: Hoare triple {215116#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,742 INFO L290 TraceCheckUtils]: 39: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~t3_pc~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,742 INFO L290 TraceCheckUtils]: 40: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,743 INFO L290 TraceCheckUtils]: 41: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,743 INFO L290 TraceCheckUtils]: 42: Hoare triple {215116#(= ~t1_st~0 0)} activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,743 INFO L290 TraceCheckUtils]: 43: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,744 INFO L290 TraceCheckUtils]: 44: Hoare triple {215116#(= ~t1_st~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,744 INFO L290 TraceCheckUtils]: 45: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~t4_pc~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,744 INFO L290 TraceCheckUtils]: 46: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,745 INFO L290 TraceCheckUtils]: 47: Hoare triple {215116#(= ~t1_st~0 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,745 INFO L290 TraceCheckUtils]: 48: Hoare triple {215116#(= ~t1_st~0 0)} activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,745 INFO L290 TraceCheckUtils]: 49: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != activate_threads_~tmp___3~0#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,746 INFO L290 TraceCheckUtils]: 50: Hoare triple {215116#(= ~t1_st~0 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,746 INFO L290 TraceCheckUtils]: 51: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~M_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,746 INFO L290 TraceCheckUtils]: 52: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~T1_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,747 INFO L290 TraceCheckUtils]: 53: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~T2_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,747 INFO L290 TraceCheckUtils]: 54: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~T3_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,747 INFO L290 TraceCheckUtils]: 55: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~T4_E~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,747 INFO L290 TraceCheckUtils]: 56: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~E_M~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,748 INFO L290 TraceCheckUtils]: 57: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~E_1~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,748 INFO L290 TraceCheckUtils]: 58: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~E_2~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,748 INFO L290 TraceCheckUtils]: 59: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~E_3~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,749 INFO L290 TraceCheckUtils]: 60: Hoare triple {215116#(= ~t1_st~0 0)} assume !(1 == ~E_4~0); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,749 INFO L290 TraceCheckUtils]: 61: Hoare triple {215116#(= ~t1_st~0 0)} assume { :end_inline_reset_delta_events } true; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,749 INFO L290 TraceCheckUtils]: 62: Hoare triple {215116#(= ~t1_st~0 0)} assume !false; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,750 INFO L290 TraceCheckUtils]: 63: Hoare triple {215116#(= ~t1_st~0 0)} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,750 INFO L290 TraceCheckUtils]: 64: Hoare triple {215116#(= ~t1_st~0 0)} assume !false; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,750 INFO L290 TraceCheckUtils]: 65: Hoare triple {215116#(= ~t1_st~0 0)} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,751 INFO L290 TraceCheckUtils]: 66: Hoare triple {215116#(= ~t1_st~0 0)} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,751 INFO L290 TraceCheckUtils]: 67: Hoare triple {215116#(= ~t1_st~0 0)} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,751 INFO L290 TraceCheckUtils]: 68: Hoare triple {215116#(= ~t1_st~0 0)} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,752 INFO L290 TraceCheckUtils]: 69: Hoare triple {215116#(= ~t1_st~0 0)} assume 0 != eval_~tmp~0#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,752 INFO L290 TraceCheckUtils]: 70: Hoare triple {215116#(= ~t1_st~0 0)} assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,752 INFO L290 TraceCheckUtils]: 71: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 != eval_~tmp_ndt_1~0#1); {215116#(= ~t1_st~0 0)} is VALID [2022-02-21 04:22:44,753 INFO L290 TraceCheckUtils]: 72: Hoare triple {215116#(= ~t1_st~0 0)} assume !(0 == ~t1_st~0); {215115#false} is VALID [2022-02-21 04:22:44,753 INFO L290 TraceCheckUtils]: 73: Hoare triple {215115#false} assume !(0 == ~t2_st~0); {215115#false} is VALID [2022-02-21 04:22:44,753 INFO L290 TraceCheckUtils]: 74: Hoare triple {215115#false} assume !(0 == ~t3_st~0); {215115#false} is VALID [2022-02-21 04:22:44,753 INFO L290 TraceCheckUtils]: 75: Hoare triple {215115#false} assume !(0 == ~t4_st~0); {215115#false} is VALID [2022-02-21 04:22:44,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:44,754 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:44,754 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133672846] [2022-02-21 04:22:44,754 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133672846] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:44,754 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:44,754 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:44,754 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963057505] [2022-02-21 04:22:44,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:44,832 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:44,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:44,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:44,833 INFO L87 Difference]: Start difference. First operand 7048 states and 9560 transitions. cyclomatic complexity: 2518 Second operand has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:48,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:48,233 INFO L93 Difference]: Finished difference Result 11326 states and 15229 transitions. [2022-02-21 04:22:48,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:48,233 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 25.333333333333332) internal successors, (76), 3 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:48,290 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:48,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11326 states and 15229 transitions.