./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:48,252 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:48,254 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:48,274 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:48,275 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:48,278 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:48,279 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:48,281 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:48,284 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:48,285 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:48,286 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:48,287 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:48,288 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:48,290 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:48,291 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:48,292 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:48,294 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:48,298 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:48,299 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:48,302 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:48,303 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:48,307 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:48,307 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:48,308 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:48,309 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:48,312 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:48,313 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:48,313 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:48,313 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:48,314 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:48,314 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:48,315 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:48,316 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:48,316 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:48,317 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:48,318 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:48,319 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:48,319 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:48,319 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:48,319 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:48,320 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:48,321 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:48,340 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:48,340 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:48,340 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:48,341 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:48,341 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:48,342 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:48,342 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:48,342 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:48,342 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:48,342 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:48,343 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:48,343 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:48,343 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:48,343 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:48,343 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:48,344 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:48,345 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:48,345 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:48,345 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:48,345 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:48,345 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:48,345 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:48,346 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:48,346 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:48,347 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:48,347 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2022-02-21 04:21:48,561 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:48,577 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:48,579 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:48,580 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:48,581 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:48,581 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-02-21 04:21:48,641 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0a5c6008c/a35f7408743e4e80949b866e9ad014a5/FLAG6c544119f [2022-02-21 04:21:49,041 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:49,042 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2022-02-21 04:21:49,049 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0a5c6008c/a35f7408743e4e80949b866e9ad014a5/FLAG6c544119f [2022-02-21 04:21:49,430 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0a5c6008c/a35f7408743e4e80949b866e9ad014a5 [2022-02-21 04:21:49,432 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:49,433 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:49,434 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:49,434 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:49,446 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:49,447 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,448 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74564081 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49, skipping insertion in model container [2022-02-21 04:21:49,448 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,457 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:49,479 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:49,602 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-02-21 04:21:49,708 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:49,723 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:49,733 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.06.cil-1.c[671,684] [2022-02-21 04:21:49,783 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:49,795 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:49,796 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49 WrapperNode [2022-02-21 04:21:49,796 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:49,797 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:49,797 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:49,798 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:49,802 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,826 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,873 INFO L137 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1662 [2022-02-21 04:21:49,874 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:49,875 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:49,875 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:49,875 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:49,881 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,881 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,884 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,885 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,913 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,940 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,959 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,964 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:49,965 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:49,965 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:49,965 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:49,967 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (1/1) ... [2022-02-21 04:21:49,972 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:49,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:50,020 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:50,071 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:50,087 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:50,087 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:50,087 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:50,087 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:50,203 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:50,205 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:51,181 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:51,191 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:51,192 INFO L299 CfgBuilder]: Removed 9 assume(true) statements. [2022-02-21 04:21:51,193 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:51 BoogieIcfgContainer [2022-02-21 04:21:51,194 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:51,194 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:51,194 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:51,197 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:51,197 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:51,197 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:49" (1/3) ... [2022-02-21 04:21:51,198 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f4ee0e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:51, skipping insertion in model container [2022-02-21 04:21:51,198 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:51,199 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:49" (2/3) ... [2022-02-21 04:21:51,199 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f4ee0e1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:51, skipping insertion in model container [2022-02-21 04:21:51,199 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:51,199 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:51" (3/3) ... [2022-02-21 04:21:51,200 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2022-02-21 04:21:51,236 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:51,237 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:51,237 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:51,237 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:51,237 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:51,237 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:51,237 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:51,238 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:51,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-02-21 04:21:51,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:51,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:51,425 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:51,425 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:51,425 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:51,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:51,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 599 [2022-02-21 04:21:51,484 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:51,484 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:51,489 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:51,489 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:51,500 INFO L791 eck$LassoCheckResult]: Stem: 670#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 558#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 487#L1028true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 400#L480true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 514#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 125#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 261#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 47#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 143#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 33#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 113#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 532#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 217#L696true assume !(0 == ~M_E~0); 526#L696-2true assume !(0 == ~T1_E~0); 529#L701-1true assume !(0 == ~T2_E~0); 557#L706-1true assume !(0 == ~T3_E~0); 299#L711-1true assume !(0 == ~T4_E~0); 145#L716-1true assume !(0 == ~T5_E~0); 577#L721-1true assume !(0 == ~T6_E~0); 266#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 463#L731-1true assume !(0 == ~E_1~0); 242#L736-1true assume !(0 == ~E_2~0); 309#L741-1true assume !(0 == ~E_3~0); 618#L746-1true assume !(0 == ~E_4~0); 166#L751-1true assume !(0 == ~E_5~0); 227#L756-1true assume !(0 == ~E_6~0); 142#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L346true assume !(1 == ~m_pc~0); 174#L346-2true is_master_triggered_~__retres1~0#1 := 0; 413#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12#L358true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 546#L861true assume !(0 != activate_threads_~tmp~1#1); 461#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70#L365true assume 1 == ~t1_pc~0; 132#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 508#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 488#L377true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66#L869true assume !(0 != activate_threads_~tmp___0~0#1); 361#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 492#L384true assume !(1 == ~t2_pc~0); 356#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 620#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 111#L396true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 231#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228#L403true assume 1 == ~t3_pc~0; 146#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 673#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137#L415true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 410#L885true assume !(0 != activate_threads_~tmp___2~0#1); 221#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 427#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 359#L434true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 438#L893true assume !(0 != activate_threads_~tmp___3~0#1); 286#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34#L441true assume !(1 == ~t5_pc~0); 453#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 608#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560#L453true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 691#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 293#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 417#L460true assume 1 == ~t6_pc~0; 5#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 549#L472true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414#L909true assume !(0 != activate_threads_~tmp___5~0#1); 542#L909-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274#L774true assume !(1 == ~M_E~0); 582#L774-2true assume !(1 == ~T1_E~0); 431#L779-1true assume !(1 == ~T2_E~0); 204#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 578#L789-1true assume !(1 == ~T4_E~0); 62#L794-1true assume !(1 == ~T5_E~0); 657#L799-1true assume !(1 == ~T6_E~0); 593#L804-1true assume !(1 == ~E_M~0); 650#L809-1true assume !(1 == ~E_1~0); 263#L814-1true assume !(1 == ~E_2~0); 13#L819-1true assume !(1 == ~E_3~0); 319#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 639#L829-1true assume !(1 == ~E_5~0); 420#L834-1true assume !(1 == ~E_6~0); 133#L839-1true assume { :end_inline_reset_delta_events } true; 127#L1065-2true [2022-02-21 04:21:51,502 INFO L793 eck$LassoCheckResult]: Loop: 127#L1065-2true assume !false; 336#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 475#L671true assume false; 597#L686true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 326#L480-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 572#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 192#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 665#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 541#L711-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 527#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 315#L721-3true assume !(0 == ~T6_E~0); 178#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 303#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 501#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 304#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 140#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 223#L751-3true assume 0 == ~E_5~0;~E_5~0 := 1; 421#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 76#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92#L346-24true assume !(1 == ~m_pc~0); 136#L346-26true is_master_triggered_~__retres1~0#1 := 0; 305#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 534#L358-8true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 489#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 428#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109#L365-24true assume !(1 == ~t1_pc~0); 687#L365-26true is_transmit1_triggered_~__retres1~1#1 := 0; 646#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 216#L377-8true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 385#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 576#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84#L384-24true assume 1 == ~t2_pc~0; 694#L385-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 631#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 491#L396-8true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 295#L877-24true assume !(0 != activate_threads_~tmp___1~0#1); 97#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168#L403-24true assume !(1 == ~t3_pc~0); 587#L403-26true is_transmit3_triggered_~__retres1~3#1 := 0; 193#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 626#L415-8true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 566#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126#L422-24true assume !(1 == ~t4_pc~0); 289#L422-26true is_transmit4_triggered_~__retres1~4#1 := 0; 102#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 609#L434-8true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 531#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 436#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134#L441-24true assume !(1 == ~t5_pc~0); 288#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 280#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373#L453-8true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67#L901-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 367#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364#L460-24true assume !(1 == ~t6_pc~0); 432#L460-26true is_transmit6_triggered_~__retres1~6#1 := 0; 679#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 395#L472-8true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 452#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 357#L909-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 628#L774-3true assume 1 == ~M_E~0;~M_E~0 := 2; 294#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 177#L779-3true assume !(1 == ~T2_E~0); 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 678#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 14#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 71#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 278#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 510#L809-3true assume 1 == ~E_1~0;~E_1~0 := 2; 69#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 215#L819-3true assume !(1 == ~E_3~0); 151#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 139#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 342#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 61#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 440#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 107#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 267#L568-1true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 32#L1084true assume !(0 == start_simulation_~tmp~3#1); 478#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 164#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 82#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 383#L568-2true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 167#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 79#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75#L1047true start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 171#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 127#L1065-2true [2022-02-21 04:21:51,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:51,508 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2022-02-21 04:21:51,514 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:51,515 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734798230] [2022-02-21 04:21:51,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:51,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:51,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:51,718 INFO L290 TraceCheckUtils]: 0: Hoare triple {698#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {698#true} is VALID [2022-02-21 04:21:51,732 INFO L290 TraceCheckUtils]: 1: Hoare triple {698#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {700#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:51,732 INFO L290 TraceCheckUtils]: 2: Hoare triple {700#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {700#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:51,733 INFO L290 TraceCheckUtils]: 3: Hoare triple {700#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {700#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:51,733 INFO L290 TraceCheckUtils]: 4: Hoare triple {700#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,733 INFO L290 TraceCheckUtils]: 5: Hoare triple {699#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 6: Hoare triple {699#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 7: Hoare triple {699#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 8: Hoare triple {699#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 9: Hoare triple {699#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 10: Hoare triple {699#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 11: Hoare triple {699#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 12: Hoare triple {699#false} assume !(0 == ~M_E~0); {699#false} is VALID [2022-02-21 04:21:51,734 INFO L290 TraceCheckUtils]: 13: Hoare triple {699#false} assume !(0 == ~T1_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 14: Hoare triple {699#false} assume !(0 == ~T2_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 15: Hoare triple {699#false} assume !(0 == ~T3_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 16: Hoare triple {699#false} assume !(0 == ~T4_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 17: Hoare triple {699#false} assume !(0 == ~T5_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 18: Hoare triple {699#false} assume !(0 == ~T6_E~0); {699#false} is VALID [2022-02-21 04:21:51,735 INFO L290 TraceCheckUtils]: 19: Hoare triple {699#false} assume 0 == ~E_M~0;~E_M~0 := 1; {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 20: Hoare triple {699#false} assume !(0 == ~E_1~0); {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 21: Hoare triple {699#false} assume !(0 == ~E_2~0); {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 22: Hoare triple {699#false} assume !(0 == ~E_3~0); {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 23: Hoare triple {699#false} assume !(0 == ~E_4~0); {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 24: Hoare triple {699#false} assume !(0 == ~E_5~0); {699#false} is VALID [2022-02-21 04:21:51,736 INFO L290 TraceCheckUtils]: 25: Hoare triple {699#false} assume !(0 == ~E_6~0); {699#false} is VALID [2022-02-21 04:21:51,737 INFO L290 TraceCheckUtils]: 26: Hoare triple {699#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {699#false} is VALID [2022-02-21 04:21:51,737 INFO L290 TraceCheckUtils]: 27: Hoare triple {699#false} assume !(1 == ~m_pc~0); {699#false} is VALID [2022-02-21 04:21:51,737 INFO L290 TraceCheckUtils]: 28: Hoare triple {699#false} is_master_triggered_~__retres1~0#1 := 0; {699#false} is VALID [2022-02-21 04:21:51,738 INFO L290 TraceCheckUtils]: 29: Hoare triple {699#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {699#false} is VALID [2022-02-21 04:21:51,738 INFO L290 TraceCheckUtils]: 30: Hoare triple {699#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {699#false} is VALID [2022-02-21 04:21:51,738 INFO L290 TraceCheckUtils]: 31: Hoare triple {699#false} assume !(0 != activate_threads_~tmp~1#1); {699#false} is VALID [2022-02-21 04:21:51,738 INFO L290 TraceCheckUtils]: 32: Hoare triple {699#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {699#false} is VALID [2022-02-21 04:21:51,738 INFO L290 TraceCheckUtils]: 33: Hoare triple {699#false} assume 1 == ~t1_pc~0; {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 34: Hoare triple {699#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 35: Hoare triple {699#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 36: Hoare triple {699#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 37: Hoare triple {699#false} assume !(0 != activate_threads_~tmp___0~0#1); {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 38: Hoare triple {699#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {699#false} is VALID [2022-02-21 04:21:51,739 INFO L290 TraceCheckUtils]: 39: Hoare triple {699#false} assume !(1 == ~t2_pc~0); {699#false} is VALID [2022-02-21 04:21:51,740 INFO L290 TraceCheckUtils]: 40: Hoare triple {699#false} is_transmit2_triggered_~__retres1~2#1 := 0; {699#false} is VALID [2022-02-21 04:21:51,740 INFO L290 TraceCheckUtils]: 41: Hoare triple {699#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {699#false} is VALID [2022-02-21 04:21:51,740 INFO L290 TraceCheckUtils]: 42: Hoare triple {699#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {699#false} is VALID [2022-02-21 04:21:51,740 INFO L290 TraceCheckUtils]: 43: Hoare triple {699#false} assume !(0 != activate_threads_~tmp___1~0#1); {699#false} is VALID [2022-02-21 04:21:51,740 INFO L290 TraceCheckUtils]: 44: Hoare triple {699#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {699#false} is VALID [2022-02-21 04:21:51,741 INFO L290 TraceCheckUtils]: 45: Hoare triple {699#false} assume 1 == ~t3_pc~0; {699#false} is VALID [2022-02-21 04:21:51,741 INFO L290 TraceCheckUtils]: 46: Hoare triple {699#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {699#false} is VALID [2022-02-21 04:21:51,741 INFO L290 TraceCheckUtils]: 47: Hoare triple {699#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {699#false} is VALID [2022-02-21 04:21:51,741 INFO L290 TraceCheckUtils]: 48: Hoare triple {699#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {699#false} is VALID [2022-02-21 04:21:51,741 INFO L290 TraceCheckUtils]: 49: Hoare triple {699#false} assume !(0 != activate_threads_~tmp___2~0#1); {699#false} is VALID [2022-02-21 04:21:51,742 INFO L290 TraceCheckUtils]: 50: Hoare triple {699#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {699#false} is VALID [2022-02-21 04:21:51,742 INFO L290 TraceCheckUtils]: 51: Hoare triple {699#false} assume 1 == ~t4_pc~0; {699#false} is VALID [2022-02-21 04:21:51,742 INFO L290 TraceCheckUtils]: 52: Hoare triple {699#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {699#false} is VALID [2022-02-21 04:21:51,742 INFO L290 TraceCheckUtils]: 53: Hoare triple {699#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {699#false} is VALID [2022-02-21 04:21:51,742 INFO L290 TraceCheckUtils]: 54: Hoare triple {699#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {699#false} is VALID [2022-02-21 04:21:51,743 INFO L290 TraceCheckUtils]: 55: Hoare triple {699#false} assume !(0 != activate_threads_~tmp___3~0#1); {699#false} is VALID [2022-02-21 04:21:51,743 INFO L290 TraceCheckUtils]: 56: Hoare triple {699#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {699#false} is VALID [2022-02-21 04:21:51,743 INFO L290 TraceCheckUtils]: 57: Hoare triple {699#false} assume !(1 == ~t5_pc~0); {699#false} is VALID [2022-02-21 04:21:51,743 INFO L290 TraceCheckUtils]: 58: Hoare triple {699#false} is_transmit5_triggered_~__retres1~5#1 := 0; {699#false} is VALID [2022-02-21 04:21:51,743 INFO L290 TraceCheckUtils]: 59: Hoare triple {699#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 60: Hoare triple {699#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 61: Hoare triple {699#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 62: Hoare triple {699#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 63: Hoare triple {699#false} assume 1 == ~t6_pc~0; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 64: Hoare triple {699#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {699#false} is VALID [2022-02-21 04:21:51,744 INFO L290 TraceCheckUtils]: 65: Hoare triple {699#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {699#false} is VALID [2022-02-21 04:21:51,745 INFO L290 TraceCheckUtils]: 66: Hoare triple {699#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {699#false} is VALID [2022-02-21 04:21:51,745 INFO L290 TraceCheckUtils]: 67: Hoare triple {699#false} assume !(0 != activate_threads_~tmp___5~0#1); {699#false} is VALID [2022-02-21 04:21:51,745 INFO L290 TraceCheckUtils]: 68: Hoare triple {699#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {699#false} is VALID [2022-02-21 04:21:51,745 INFO L290 TraceCheckUtils]: 69: Hoare triple {699#false} assume !(1 == ~M_E~0); {699#false} is VALID [2022-02-21 04:21:51,745 INFO L290 TraceCheckUtils]: 70: Hoare triple {699#false} assume !(1 == ~T1_E~0); {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 71: Hoare triple {699#false} assume !(1 == ~T2_E~0); {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 72: Hoare triple {699#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 73: Hoare triple {699#false} assume !(1 == ~T4_E~0); {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 74: Hoare triple {699#false} assume !(1 == ~T5_E~0); {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 75: Hoare triple {699#false} assume !(1 == ~T6_E~0); {699#false} is VALID [2022-02-21 04:21:51,746 INFO L290 TraceCheckUtils]: 76: Hoare triple {699#false} assume !(1 == ~E_M~0); {699#false} is VALID [2022-02-21 04:21:51,763 INFO L290 TraceCheckUtils]: 77: Hoare triple {699#false} assume !(1 == ~E_1~0); {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 78: Hoare triple {699#false} assume !(1 == ~E_2~0); {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 79: Hoare triple {699#false} assume !(1 == ~E_3~0); {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 80: Hoare triple {699#false} assume 1 == ~E_4~0;~E_4~0 := 2; {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 81: Hoare triple {699#false} assume !(1 == ~E_5~0); {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 82: Hoare triple {699#false} assume !(1 == ~E_6~0); {699#false} is VALID [2022-02-21 04:21:51,764 INFO L290 TraceCheckUtils]: 83: Hoare triple {699#false} assume { :end_inline_reset_delta_events } true; {699#false} is VALID [2022-02-21 04:21:51,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:51,766 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:51,766 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734798230] [2022-02-21 04:21:51,767 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734798230] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:51,767 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:51,768 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:51,769 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1993694446] [2022-02-21 04:21:51,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:51,774 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:51,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:51,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1299006910, now seen corresponding path program 1 times [2022-02-21 04:21:51,777 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:51,777 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749874616] [2022-02-21 04:21:51,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:51,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:51,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:51,838 INFO L290 TraceCheckUtils]: 0: Hoare triple {701#true} assume !false; {701#true} is VALID [2022-02-21 04:21:51,838 INFO L290 TraceCheckUtils]: 1: Hoare triple {701#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {701#true} is VALID [2022-02-21 04:21:51,839 INFO L290 TraceCheckUtils]: 2: Hoare triple {701#true} assume false; {702#false} is VALID [2022-02-21 04:21:51,841 INFO L290 TraceCheckUtils]: 3: Hoare triple {702#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {702#false} is VALID [2022-02-21 04:21:51,841 INFO L290 TraceCheckUtils]: 4: Hoare triple {702#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {702#false} is VALID [2022-02-21 04:21:51,841 INFO L290 TraceCheckUtils]: 5: Hoare triple {702#false} assume 0 == ~M_E~0;~M_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,842 INFO L290 TraceCheckUtils]: 6: Hoare triple {702#false} assume 0 == ~T1_E~0;~T1_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,842 INFO L290 TraceCheckUtils]: 7: Hoare triple {702#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,842 INFO L290 TraceCheckUtils]: 8: Hoare triple {702#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,842 INFO L290 TraceCheckUtils]: 9: Hoare triple {702#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,842 INFO L290 TraceCheckUtils]: 10: Hoare triple {702#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,843 INFO L290 TraceCheckUtils]: 11: Hoare triple {702#false} assume !(0 == ~T6_E~0); {702#false} is VALID [2022-02-21 04:21:51,843 INFO L290 TraceCheckUtils]: 12: Hoare triple {702#false} assume 0 == ~E_M~0;~E_M~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,843 INFO L290 TraceCheckUtils]: 13: Hoare triple {702#false} assume 0 == ~E_1~0;~E_1~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,843 INFO L290 TraceCheckUtils]: 14: Hoare triple {702#false} assume 0 == ~E_2~0;~E_2~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {702#false} assume 0 == ~E_3~0;~E_3~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,844 INFO L290 TraceCheckUtils]: 16: Hoare triple {702#false} assume 0 == ~E_4~0;~E_4~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,848 INFO L290 TraceCheckUtils]: 17: Hoare triple {702#false} assume 0 == ~E_5~0;~E_5~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,848 INFO L290 TraceCheckUtils]: 18: Hoare triple {702#false} assume 0 == ~E_6~0;~E_6~0 := 1; {702#false} is VALID [2022-02-21 04:21:51,848 INFO L290 TraceCheckUtils]: 19: Hoare triple {702#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {702#false} is VALID [2022-02-21 04:21:51,849 INFO L290 TraceCheckUtils]: 20: Hoare triple {702#false} assume !(1 == ~m_pc~0); {702#false} is VALID [2022-02-21 04:21:51,851 INFO L290 TraceCheckUtils]: 21: Hoare triple {702#false} is_master_triggered_~__retres1~0#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,852 INFO L290 TraceCheckUtils]: 22: Hoare triple {702#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {702#false} is VALID [2022-02-21 04:21:51,852 INFO L290 TraceCheckUtils]: 23: Hoare triple {702#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {702#false} is VALID [2022-02-21 04:21:51,852 INFO L290 TraceCheckUtils]: 24: Hoare triple {702#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,852 INFO L290 TraceCheckUtils]: 25: Hoare triple {702#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {702#false} is VALID [2022-02-21 04:21:51,852 INFO L290 TraceCheckUtils]: 26: Hoare triple {702#false} assume !(1 == ~t1_pc~0); {702#false} is VALID [2022-02-21 04:21:51,853 INFO L290 TraceCheckUtils]: 27: Hoare triple {702#false} is_transmit1_triggered_~__retres1~1#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,853 INFO L290 TraceCheckUtils]: 28: Hoare triple {702#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {702#false} is VALID [2022-02-21 04:21:51,853 INFO L290 TraceCheckUtils]: 29: Hoare triple {702#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {702#false} is VALID [2022-02-21 04:21:51,854 INFO L290 TraceCheckUtils]: 30: Hoare triple {702#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,854 INFO L290 TraceCheckUtils]: 31: Hoare triple {702#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:51,855 INFO L290 TraceCheckUtils]: 32: Hoare triple {702#false} assume 1 == ~t2_pc~0; {702#false} is VALID [2022-02-21 04:21:51,856 INFO L290 TraceCheckUtils]: 33: Hoare triple {702#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {702#false} is VALID [2022-02-21 04:21:51,857 INFO L290 TraceCheckUtils]: 34: Hoare triple {702#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {702#false} is VALID [2022-02-21 04:21:51,868 INFO L290 TraceCheckUtils]: 35: Hoare triple {702#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {702#false} is VALID [2022-02-21 04:21:51,868 INFO L290 TraceCheckUtils]: 36: Hoare triple {702#false} assume !(0 != activate_threads_~tmp___1~0#1); {702#false} is VALID [2022-02-21 04:21:51,868 INFO L290 TraceCheckUtils]: 37: Hoare triple {702#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {702#false} is VALID [2022-02-21 04:21:51,869 INFO L290 TraceCheckUtils]: 38: Hoare triple {702#false} assume !(1 == ~t3_pc~0); {702#false} is VALID [2022-02-21 04:21:51,883 INFO L290 TraceCheckUtils]: 39: Hoare triple {702#false} is_transmit3_triggered_~__retres1~3#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 40: Hoare triple {702#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 41: Hoare triple {702#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 42: Hoare triple {702#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 43: Hoare triple {702#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 44: Hoare triple {702#false} assume !(1 == ~t4_pc~0); {702#false} is VALID [2022-02-21 04:21:51,884 INFO L290 TraceCheckUtils]: 45: Hoare triple {702#false} is_transmit4_triggered_~__retres1~4#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 46: Hoare triple {702#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 47: Hoare triple {702#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 48: Hoare triple {702#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 49: Hoare triple {702#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 50: Hoare triple {702#false} assume !(1 == ~t5_pc~0); {702#false} is VALID [2022-02-21 04:21:51,885 INFO L290 TraceCheckUtils]: 51: Hoare triple {702#false} is_transmit5_triggered_~__retres1~5#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 52: Hoare triple {702#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 53: Hoare triple {702#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 54: Hoare triple {702#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 55: Hoare triple {702#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 56: Hoare triple {702#false} assume !(1 == ~t6_pc~0); {702#false} is VALID [2022-02-21 04:21:51,886 INFO L290 TraceCheckUtils]: 57: Hoare triple {702#false} is_transmit6_triggered_~__retres1~6#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 58: Hoare triple {702#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 59: Hoare triple {702#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 60: Hoare triple {702#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 61: Hoare triple {702#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 62: Hoare triple {702#false} assume 1 == ~M_E~0;~M_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 63: Hoare triple {702#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,887 INFO L290 TraceCheckUtils]: 64: Hoare triple {702#false} assume !(1 == ~T2_E~0); {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 65: Hoare triple {702#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 66: Hoare triple {702#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 67: Hoare triple {702#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 68: Hoare triple {702#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 69: Hoare triple {702#false} assume 1 == ~E_M~0;~E_M~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,888 INFO L290 TraceCheckUtils]: 70: Hoare triple {702#false} assume 1 == ~E_1~0;~E_1~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 71: Hoare triple {702#false} assume 1 == ~E_2~0;~E_2~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 72: Hoare triple {702#false} assume !(1 == ~E_3~0); {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 73: Hoare triple {702#false} assume 1 == ~E_4~0;~E_4~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 74: Hoare triple {702#false} assume 1 == ~E_5~0;~E_5~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 75: Hoare triple {702#false} assume 1 == ~E_6~0;~E_6~0 := 2; {702#false} is VALID [2022-02-21 04:21:51,889 INFO L290 TraceCheckUtils]: 76: Hoare triple {702#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 77: Hoare triple {702#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 78: Hoare triple {702#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 79: Hoare triple {702#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 80: Hoare triple {702#false} assume !(0 == start_simulation_~tmp~3#1); {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 81: Hoare triple {702#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 82: Hoare triple {702#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {702#false} is VALID [2022-02-21 04:21:51,890 INFO L290 TraceCheckUtils]: 83: Hoare triple {702#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {702#false} is VALID [2022-02-21 04:21:51,891 INFO L290 TraceCheckUtils]: 84: Hoare triple {702#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {702#false} is VALID [2022-02-21 04:21:51,891 INFO L290 TraceCheckUtils]: 85: Hoare triple {702#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {702#false} is VALID [2022-02-21 04:21:51,891 INFO L290 TraceCheckUtils]: 86: Hoare triple {702#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {702#false} is VALID [2022-02-21 04:21:51,891 INFO L290 TraceCheckUtils]: 87: Hoare triple {702#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {702#false} is VALID [2022-02-21 04:21:51,891 INFO L290 TraceCheckUtils]: 88: Hoare triple {702#false} assume !(0 != start_simulation_~tmp___0~1#1); {702#false} is VALID [2022-02-21 04:21:51,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:51,892 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:51,892 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749874616] [2022-02-21 04:21:51,892 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749874616] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:51,893 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:51,893 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:51,893 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [545553076] [2022-02-21 04:21:51,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:51,894 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:51,895 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:51,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:51,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:51,932 INFO L87 Difference]: Start difference. First operand has 694 states, 693 states have (on average 1.5252525252525253) internal successors, (1057), 693 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,564 INFO L93 Difference]: Finished difference Result 692 states and 1034 transitions. [2022-02-21 04:21:52,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:52,566 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,623 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:52,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 692 states and 1034 transitions. [2022-02-21 04:21:52,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:52,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 692 states to 686 states and 1028 transitions. [2022-02-21 04:21:52,674 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:52,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:52,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1028 transitions. [2022-02-21 04:21:52,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:52,680 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-02-21 04:21:52,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1028 transitions. [2022-02-21 04:21:52,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:52,715 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:52,717 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1028 transitions. Second operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,719 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1028 transitions. Second operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,722 INFO L87 Difference]: Start difference. First operand 686 states and 1028 transitions. Second operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,742 INFO L93 Difference]: Finished difference Result 686 states and 1028 transitions. [2022-02-21 04:21:52,742 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1028 transitions. [2022-02-21 04:21:52,747 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,748 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,749 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1028 transitions. [2022-02-21 04:21:52,750 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1028 transitions. [2022-02-21 04:21:52,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:52,777 INFO L93 Difference]: Finished difference Result 686 states and 1028 transitions. [2022-02-21 04:21:52,777 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1028 transitions. [2022-02-21 04:21:52,778 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:52,778 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:52,778 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:52,778 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:52,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.498542274052478) internal successors, (1028), 685 states have internal predecessors, (1028), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:52,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1028 transitions. [2022-02-21 04:21:52,795 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-02-21 04:21:52,795 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1028 transitions. [2022-02-21 04:21:52,795 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:52,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1028 transitions. [2022-02-21 04:21:52,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:52,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:52,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:52,799 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,799 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:52,800 INFO L791 eck$LassoCheckResult]: Stem: 2080#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 2058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2033#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1979#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1980#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1644#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1645#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1494#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1495#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1461#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1462#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1622#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1782#L696 assume !(0 == ~M_E~0); 1783#L696-2 assume !(0 == ~T1_E~0); 2048#L701-1 assume !(0 == ~T2_E~0); 2050#L706-1 assume !(0 == ~T3_E~0); 1893#L711-1 assume !(0 == ~T4_E~0); 1678#L716-1 assume !(0 == ~T5_E~0); 1679#L721-1 assume !(0 == ~T6_E~0); 1849#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1850#L731-1 assume !(0 == ~E_1~0); 1821#L736-1 assume !(0 == ~E_2~0); 1822#L741-1 assume !(0 == ~E_3~0); 1900#L746-1 assume !(0 == ~E_4~0); 1712#L751-1 assume !(0 == ~E_5~0); 1713#L756-1 assume !(0 == ~E_6~0); 1675#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1509#L346 assume !(1 == ~m_pc~0); 1510#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1723#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1419#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1420#L861 assume !(0 != activate_threads_~tmp~1#1); 2020#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1541#L365 assume 1 == ~t1_pc~0; 1542#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1662#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2036#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1531#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1532#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1947#L384 assume !(1 == ~t2_pc~0); 1939#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1940#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1618#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1443#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1444#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1800#L403 assume 1 == ~t3_pc~0; 1680#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1681#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1671#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1672#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1793#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1794#L422 assume 1 == ~t4_pc~0; 1440#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1441#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1943#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1944#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1877#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1463#L441 assume !(1 == ~t5_pc~0); 1464#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2017#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2060#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2061#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1886#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1887#L460 assume 1 == ~t6_pc~0; 1403#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1404#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1471#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1988#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1989#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1859#L774 assume !(1 == ~M_E~0); 1860#L774-2 assume !(1 == ~T1_E~0); 2003#L779-1 assume !(1 == ~T2_E~0); 1764#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1765#L789-1 assume !(1 == ~T4_E~0); 1525#L794-1 assume !(1 == ~T5_E~0); 1526#L799-1 assume !(1 == ~T6_E~0); 2071#L804-1 assume !(1 == ~E_M~0); 2072#L809-1 assume !(1 == ~E_1~0); 1847#L814-1 assume !(1 == ~E_2~0); 1421#L819-1 assume !(1 == ~E_3~0); 1422#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1907#L829-1 assume !(1 == ~E_5~0); 1995#L834-1 assume !(1 == ~E_6~0); 1663#L839-1 assume { :end_inline_reset_delta_events } true; 1649#L1065-2 [2022-02-21 04:21:52,801 INFO L793 eck$LassoCheckResult]: Loop: 1649#L1065-2 assume !false; 1650#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1702#L671 assume !false; 2029#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1975#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1502#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1512#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1923#L582 assume !(0 != eval_~tmp~0#1); 2073#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1910#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1698#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1699#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1744#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1745#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2054#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2049#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1903#L721-3 assume !(0 == ~T6_E~0); 1727#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1728#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1897#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1898#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1673#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1674#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1795#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1551#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1552#L346-24 assume 1 == ~m_pc~0; 1585#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1666#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1899#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2037#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2001#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1613#L365-24 assume 1 == ~t1_pc~0; 1614#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1902#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1780#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1781#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1966#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1567#L384-24 assume !(1 == ~t2_pc~0); 1568#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1587#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2038#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1888#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 1592#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1593#L403-24 assume 1 == ~t3_pc~0; 1715#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1746#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1747#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1845#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1846#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1646#L422-24 assume 1 == ~t4_pc~0; 1648#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1599#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2051#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2009#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1659#L441-24 assume 1 == ~t5_pc~0; 1660#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1865#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1866#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1533#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1534#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1948#L460-24 assume !(1 == ~t6_pc~0); 1949#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 2004#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1977#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1978#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1937#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1938#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1885#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1726#L779-3 assume !(1 == ~T2_E~0); 1438#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1439#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1417#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1418#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1540#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1864#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1538#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1539#L819-3 assume !(1 == ~E_3~0); 1688#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1669#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1670#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1523#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1524#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1521#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1609#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1456#L1084 assume !(0 == start_simulation_~tmp~3#1); 1458#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1708#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1424#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1563#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1714#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1556#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1549#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1550#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1649#L1065-2 [2022-02-21 04:21:52,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,801 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2022-02-21 04:21:52,802 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,802 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196109079] [2022-02-21 04:21:52,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,874 INFO L290 TraceCheckUtils]: 0: Hoare triple {3456#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {3456#true} is VALID [2022-02-21 04:21:52,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {3456#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {3458#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:52,875 INFO L290 TraceCheckUtils]: 2: Hoare triple {3458#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {3458#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:52,875 INFO L290 TraceCheckUtils]: 3: Hoare triple {3458#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {3458#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:52,876 INFO L290 TraceCheckUtils]: 4: Hoare triple {3458#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {3458#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:52,876 INFO L290 TraceCheckUtils]: 5: Hoare triple {3458#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {3458#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:52,876 INFO L290 TraceCheckUtils]: 6: Hoare triple {3458#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,876 INFO L290 TraceCheckUtils]: 7: Hoare triple {3457#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,877 INFO L290 TraceCheckUtils]: 8: Hoare triple {3457#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,877 INFO L290 TraceCheckUtils]: 9: Hoare triple {3457#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,877 INFO L290 TraceCheckUtils]: 10: Hoare triple {3457#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,879 INFO L290 TraceCheckUtils]: 11: Hoare triple {3457#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {3457#false} is VALID [2022-02-21 04:21:52,879 INFO L290 TraceCheckUtils]: 12: Hoare triple {3457#false} assume !(0 == ~M_E~0); {3457#false} is VALID [2022-02-21 04:21:52,879 INFO L290 TraceCheckUtils]: 13: Hoare triple {3457#false} assume !(0 == ~T1_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 14: Hoare triple {3457#false} assume !(0 == ~T2_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 15: Hoare triple {3457#false} assume !(0 == ~T3_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 16: Hoare triple {3457#false} assume !(0 == ~T4_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 17: Hoare triple {3457#false} assume !(0 == ~T5_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 18: Hoare triple {3457#false} assume !(0 == ~T6_E~0); {3457#false} is VALID [2022-02-21 04:21:52,880 INFO L290 TraceCheckUtils]: 19: Hoare triple {3457#false} assume 0 == ~E_M~0;~E_M~0 := 1; {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 20: Hoare triple {3457#false} assume !(0 == ~E_1~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 21: Hoare triple {3457#false} assume !(0 == ~E_2~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 22: Hoare triple {3457#false} assume !(0 == ~E_3~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 23: Hoare triple {3457#false} assume !(0 == ~E_4~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 24: Hoare triple {3457#false} assume !(0 == ~E_5~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 25: Hoare triple {3457#false} assume !(0 == ~E_6~0); {3457#false} is VALID [2022-02-21 04:21:52,881 INFO L290 TraceCheckUtils]: 26: Hoare triple {3457#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3457#false} is VALID [2022-02-21 04:21:52,882 INFO L290 TraceCheckUtils]: 27: Hoare triple {3457#false} assume !(1 == ~m_pc~0); {3457#false} is VALID [2022-02-21 04:21:52,882 INFO L290 TraceCheckUtils]: 28: Hoare triple {3457#false} is_master_triggered_~__retres1~0#1 := 0; {3457#false} is VALID [2022-02-21 04:21:52,882 INFO L290 TraceCheckUtils]: 29: Hoare triple {3457#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3457#false} is VALID [2022-02-21 04:21:52,884 INFO L290 TraceCheckUtils]: 30: Hoare triple {3457#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3457#false} is VALID [2022-02-21 04:21:52,884 INFO L290 TraceCheckUtils]: 31: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp~1#1); {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 32: Hoare triple {3457#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 33: Hoare triple {3457#false} assume 1 == ~t1_pc~0; {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 34: Hoare triple {3457#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 35: Hoare triple {3457#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 36: Hoare triple {3457#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 37: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp___0~0#1); {3457#false} is VALID [2022-02-21 04:21:52,885 INFO L290 TraceCheckUtils]: 38: Hoare triple {3457#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 39: Hoare triple {3457#false} assume !(1 == ~t2_pc~0); {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 40: Hoare triple {3457#false} is_transmit2_triggered_~__retres1~2#1 := 0; {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 41: Hoare triple {3457#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 42: Hoare triple {3457#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 43: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp___1~0#1); {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 44: Hoare triple {3457#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3457#false} is VALID [2022-02-21 04:21:52,886 INFO L290 TraceCheckUtils]: 45: Hoare triple {3457#false} assume 1 == ~t3_pc~0; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 46: Hoare triple {3457#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 47: Hoare triple {3457#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 48: Hoare triple {3457#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 49: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp___2~0#1); {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 50: Hoare triple {3457#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 51: Hoare triple {3457#false} assume 1 == ~t4_pc~0; {3457#false} is VALID [2022-02-21 04:21:52,887 INFO L290 TraceCheckUtils]: 52: Hoare triple {3457#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3457#false} is VALID [2022-02-21 04:21:52,888 INFO L290 TraceCheckUtils]: 53: Hoare triple {3457#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3457#false} is VALID [2022-02-21 04:21:52,888 INFO L290 TraceCheckUtils]: 54: Hoare triple {3457#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3457#false} is VALID [2022-02-21 04:21:52,889 INFO L290 TraceCheckUtils]: 55: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp___3~0#1); {3457#false} is VALID [2022-02-21 04:21:52,889 INFO L290 TraceCheckUtils]: 56: Hoare triple {3457#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 57: Hoare triple {3457#false} assume !(1 == ~t5_pc~0); {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 58: Hoare triple {3457#false} is_transmit5_triggered_~__retres1~5#1 := 0; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 59: Hoare triple {3457#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 60: Hoare triple {3457#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 61: Hoare triple {3457#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 62: Hoare triple {3457#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3457#false} is VALID [2022-02-21 04:21:52,890 INFO L290 TraceCheckUtils]: 63: Hoare triple {3457#false} assume 1 == ~t6_pc~0; {3457#false} is VALID [2022-02-21 04:21:52,891 INFO L290 TraceCheckUtils]: 64: Hoare triple {3457#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {3457#false} is VALID [2022-02-21 04:21:52,891 INFO L290 TraceCheckUtils]: 65: Hoare triple {3457#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3457#false} is VALID [2022-02-21 04:21:52,892 INFO L290 TraceCheckUtils]: 66: Hoare triple {3457#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {3457#false} is VALID [2022-02-21 04:21:52,892 INFO L290 TraceCheckUtils]: 67: Hoare triple {3457#false} assume !(0 != activate_threads_~tmp___5~0#1); {3457#false} is VALID [2022-02-21 04:21:52,892 INFO L290 TraceCheckUtils]: 68: Hoare triple {3457#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3457#false} is VALID [2022-02-21 04:21:52,892 INFO L290 TraceCheckUtils]: 69: Hoare triple {3457#false} assume !(1 == ~M_E~0); {3457#false} is VALID [2022-02-21 04:21:52,892 INFO L290 TraceCheckUtils]: 70: Hoare triple {3457#false} assume !(1 == ~T1_E~0); {3457#false} is VALID [2022-02-21 04:21:52,893 INFO L290 TraceCheckUtils]: 71: Hoare triple {3457#false} assume !(1 == ~T2_E~0); {3457#false} is VALID [2022-02-21 04:21:52,893 INFO L290 TraceCheckUtils]: 72: Hoare triple {3457#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,895 INFO L290 TraceCheckUtils]: 73: Hoare triple {3457#false} assume !(1 == ~T4_E~0); {3457#false} is VALID [2022-02-21 04:21:52,896 INFO L290 TraceCheckUtils]: 74: Hoare triple {3457#false} assume !(1 == ~T5_E~0); {3457#false} is VALID [2022-02-21 04:21:52,898 INFO L290 TraceCheckUtils]: 75: Hoare triple {3457#false} assume !(1 == ~T6_E~0); {3457#false} is VALID [2022-02-21 04:21:52,899 INFO L290 TraceCheckUtils]: 76: Hoare triple {3457#false} assume !(1 == ~E_M~0); {3457#false} is VALID [2022-02-21 04:21:52,899 INFO L290 TraceCheckUtils]: 77: Hoare triple {3457#false} assume !(1 == ~E_1~0); {3457#false} is VALID [2022-02-21 04:21:52,899 INFO L290 TraceCheckUtils]: 78: Hoare triple {3457#false} assume !(1 == ~E_2~0); {3457#false} is VALID [2022-02-21 04:21:52,900 INFO L290 TraceCheckUtils]: 79: Hoare triple {3457#false} assume !(1 == ~E_3~0); {3457#false} is VALID [2022-02-21 04:21:52,900 INFO L290 TraceCheckUtils]: 80: Hoare triple {3457#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3457#false} is VALID [2022-02-21 04:21:52,900 INFO L290 TraceCheckUtils]: 81: Hoare triple {3457#false} assume !(1 == ~E_5~0); {3457#false} is VALID [2022-02-21 04:21:52,900 INFO L290 TraceCheckUtils]: 82: Hoare triple {3457#false} assume !(1 == ~E_6~0); {3457#false} is VALID [2022-02-21 04:21:52,902 INFO L290 TraceCheckUtils]: 83: Hoare triple {3457#false} assume { :end_inline_reset_delta_events } true; {3457#false} is VALID [2022-02-21 04:21:52,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:52,903 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:52,903 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196109079] [2022-02-21 04:21:52,903 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196109079] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:52,903 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:52,903 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:52,904 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415586678] [2022-02-21 04:21:52,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:52,904 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:52,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:52,906 INFO L85 PathProgramCache]: Analyzing trace with hash 1167110331, now seen corresponding path program 1 times [2022-02-21 04:21:52,906 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:52,906 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631527263] [2022-02-21 04:21:52,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:52,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:52,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 0: Hoare triple {3459#true} assume !false; {3459#true} is VALID [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 1: Hoare triple {3459#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {3459#true} is VALID [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 2: Hoare triple {3459#true} assume !false; {3459#true} is VALID [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 3: Hoare triple {3459#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3459#true} is VALID [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 4: Hoare triple {3459#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3459#true} is VALID [2022-02-21 04:21:52,998 INFO L290 TraceCheckUtils]: 5: Hoare triple {3459#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 6: Hoare triple {3459#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 7: Hoare triple {3459#true} assume !(0 != eval_~tmp~0#1); {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 8: Hoare triple {3459#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 9: Hoare triple {3459#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 10: Hoare triple {3459#true} assume 0 == ~M_E~0;~M_E~0 := 1; {3459#true} is VALID [2022-02-21 04:21:52,999 INFO L290 TraceCheckUtils]: 11: Hoare triple {3459#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {3459#true} is VALID [2022-02-21 04:21:53,000 INFO L290 TraceCheckUtils]: 12: Hoare triple {3459#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,000 INFO L290 TraceCheckUtils]: 13: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,000 INFO L290 TraceCheckUtils]: 14: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,001 INFO L290 TraceCheckUtils]: 15: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,001 INFO L290 TraceCheckUtils]: 16: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,001 INFO L290 TraceCheckUtils]: 17: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,001 INFO L290 TraceCheckUtils]: 18: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,002 INFO L290 TraceCheckUtils]: 19: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,002 INFO L290 TraceCheckUtils]: 20: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,002 INFO L290 TraceCheckUtils]: 21: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,003 INFO L290 TraceCheckUtils]: 22: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,003 INFO L290 TraceCheckUtils]: 23: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,003 INFO L290 TraceCheckUtils]: 24: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,004 INFO L290 TraceCheckUtils]: 25: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,004 INFO L290 TraceCheckUtils]: 26: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,004 INFO L290 TraceCheckUtils]: 27: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,005 INFO L290 TraceCheckUtils]: 28: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,005 INFO L290 TraceCheckUtils]: 29: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,005 INFO L290 TraceCheckUtils]: 30: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,005 INFO L290 TraceCheckUtils]: 31: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,006 INFO L290 TraceCheckUtils]: 32: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,006 INFO L290 TraceCheckUtils]: 33: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,006 INFO L290 TraceCheckUtils]: 34: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,007 INFO L290 TraceCheckUtils]: 35: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,007 INFO L290 TraceCheckUtils]: 36: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,007 INFO L290 TraceCheckUtils]: 37: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,008 INFO L290 TraceCheckUtils]: 38: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,008 INFO L290 TraceCheckUtils]: 39: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,008 INFO L290 TraceCheckUtils]: 40: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,009 INFO L290 TraceCheckUtils]: 41: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,009 INFO L290 TraceCheckUtils]: 42: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,009 INFO L290 TraceCheckUtils]: 43: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,009 INFO L290 TraceCheckUtils]: 44: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,010 INFO L290 TraceCheckUtils]: 45: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,010 INFO L290 TraceCheckUtils]: 46: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,010 INFO L290 TraceCheckUtils]: 47: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,011 INFO L290 TraceCheckUtils]: 48: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,011 INFO L290 TraceCheckUtils]: 49: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,011 INFO L290 TraceCheckUtils]: 50: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,012 INFO L290 TraceCheckUtils]: 51: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,012 INFO L290 TraceCheckUtils]: 52: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,012 INFO L290 TraceCheckUtils]: 53: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,012 INFO L290 TraceCheckUtils]: 54: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,013 INFO L290 TraceCheckUtils]: 55: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,013 INFO L290 TraceCheckUtils]: 56: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,013 INFO L290 TraceCheckUtils]: 57: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,014 INFO L290 TraceCheckUtils]: 58: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,014 INFO L290 TraceCheckUtils]: 59: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,014 INFO L290 TraceCheckUtils]: 60: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,015 INFO L290 TraceCheckUtils]: 61: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,015 INFO L290 TraceCheckUtils]: 62: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,015 INFO L290 TraceCheckUtils]: 63: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,015 INFO L290 TraceCheckUtils]: 64: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,016 INFO L290 TraceCheckUtils]: 65: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,016 INFO L290 TraceCheckUtils]: 66: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,016 INFO L290 TraceCheckUtils]: 67: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,017 INFO L290 TraceCheckUtils]: 68: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {3461#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,017 INFO L290 TraceCheckUtils]: 69: Hoare triple {3461#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {3460#false} is VALID [2022-02-21 04:21:53,017 INFO L290 TraceCheckUtils]: 70: Hoare triple {3460#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,017 INFO L290 TraceCheckUtils]: 71: Hoare triple {3460#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,017 INFO L290 TraceCheckUtils]: 72: Hoare triple {3460#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 73: Hoare triple {3460#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 74: Hoare triple {3460#false} assume 1 == ~E_M~0;~E_M~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 75: Hoare triple {3460#false} assume 1 == ~E_1~0;~E_1~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 76: Hoare triple {3460#false} assume 1 == ~E_2~0;~E_2~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 77: Hoare triple {3460#false} assume !(1 == ~E_3~0); {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 78: Hoare triple {3460#false} assume 1 == ~E_4~0;~E_4~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 79: Hoare triple {3460#false} assume 1 == ~E_5~0;~E_5~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,018 INFO L290 TraceCheckUtils]: 80: Hoare triple {3460#false} assume 1 == ~E_6~0;~E_6~0 := 2; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 81: Hoare triple {3460#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 82: Hoare triple {3460#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 83: Hoare triple {3460#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 84: Hoare triple {3460#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 85: Hoare triple {3460#false} assume !(0 == start_simulation_~tmp~3#1); {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 86: Hoare triple {3460#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 87: Hoare triple {3460#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {3460#false} is VALID [2022-02-21 04:21:53,019 INFO L290 TraceCheckUtils]: 88: Hoare triple {3460#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {3460#false} is VALID [2022-02-21 04:21:53,020 INFO L290 TraceCheckUtils]: 89: Hoare triple {3460#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {3460#false} is VALID [2022-02-21 04:21:53,020 INFO L290 TraceCheckUtils]: 90: Hoare triple {3460#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {3460#false} is VALID [2022-02-21 04:21:53,020 INFO L290 TraceCheckUtils]: 91: Hoare triple {3460#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {3460#false} is VALID [2022-02-21 04:21:53,020 INFO L290 TraceCheckUtils]: 92: Hoare triple {3460#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {3460#false} is VALID [2022-02-21 04:21:53,021 INFO L290 TraceCheckUtils]: 93: Hoare triple {3460#false} assume !(0 != start_simulation_~tmp___0~1#1); {3460#false} is VALID [2022-02-21 04:21:53,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,023 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,024 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [631527263] [2022-02-21 04:21:53,024 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [631527263] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,024 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,025 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:53,025 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284589065] [2022-02-21 04:21:53,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,025 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:53,026 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:53,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:53,027 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:53,027 INFO L87 Difference]: Start difference. First operand 686 states and 1028 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,518 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2022-02-21 04:21:53,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:53,518 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,566 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:53,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:53,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1027 transitions. [2022-02-21 04:21:53,596 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:53,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:53,597 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,597 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:53,597 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-02-21 04:21:53,598 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:53,616 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:53,618 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1027 transitions. Second operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,619 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1027 transitions. Second operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,620 INFO L87 Difference]: Start difference. First operand 686 states and 1027 transitions. Second operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,659 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2022-02-21 04:21:53,659 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,660 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,660 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,662 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1027 transitions. [2022-02-21 04:21:53,663 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1027 transitions. [2022-02-21 04:21:53,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:53,684 INFO L93 Difference]: Finished difference Result 686 states and 1027 transitions. [2022-02-21 04:21:53,684 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,685 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:53,685 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:53,685 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:53,685 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:53,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4970845481049562) internal successors, (1027), 685 states have internal predecessors, (1027), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:53,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1027 transitions. [2022-02-21 04:21:53,716 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-02-21 04:21:53,716 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1027 transitions. [2022-02-21 04:21:53,716 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:53,717 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1027 transitions. [2022-02-21 04:21:53,719 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:53,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:53,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:53,736 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,736 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:53,737 INFO L791 eck$LassoCheckResult]: Stem: 4833#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4811#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4786#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4732#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4733#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4397#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4398#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4245#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4246#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4214#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4215#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4375#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4535#L696 assume !(0 == ~M_E~0); 4536#L696-2 assume !(0 == ~T1_E~0); 4801#L701-1 assume !(0 == ~T2_E~0); 4803#L706-1 assume !(0 == ~T3_E~0); 4646#L711-1 assume !(0 == ~T4_E~0); 4431#L716-1 assume !(0 == ~T5_E~0); 4432#L721-1 assume !(0 == ~T6_E~0); 4602#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4603#L731-1 assume !(0 == ~E_1~0); 4574#L736-1 assume !(0 == ~E_2~0); 4575#L741-1 assume !(0 == ~E_3~0); 4653#L746-1 assume !(0 == ~E_4~0); 4465#L751-1 assume !(0 == ~E_5~0); 4466#L756-1 assume !(0 == ~E_6~0); 4428#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4262#L346 assume !(1 == ~m_pc~0); 4263#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4476#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4170#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4171#L861 assume !(0 != activate_threads_~tmp~1#1); 4773#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4293#L365 assume 1 == ~t1_pc~0; 4294#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4412#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4787#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4284#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4285#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4700#L384 assume !(1 == ~t2_pc~0); 4690#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4691#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4371#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4196#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4197#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4552#L403 assume 1 == ~t3_pc~0; 4433#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4434#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4420#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4421#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4543#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4544#L422 assume 1 == ~t4_pc~0; 4191#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4192#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4696#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4697#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4630#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4216#L441 assume !(1 == ~t5_pc~0); 4217#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4770#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4813#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4814#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4638#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4639#L460 assume 1 == ~t6_pc~0; 4153#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4154#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4224#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4741#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4742#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4612#L774 assume !(1 == ~M_E~0); 4613#L774-2 assume !(1 == ~T1_E~0); 4756#L779-1 assume !(1 == ~T2_E~0); 4517#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4518#L789-1 assume !(1 == ~T4_E~0); 4278#L794-1 assume !(1 == ~T5_E~0); 4279#L799-1 assume !(1 == ~T6_E~0); 4824#L804-1 assume !(1 == ~E_M~0); 4825#L809-1 assume !(1 == ~E_1~0); 4600#L814-1 assume !(1 == ~E_2~0); 4172#L819-1 assume !(1 == ~E_3~0); 4173#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4660#L829-1 assume !(1 == ~E_5~0); 4748#L834-1 assume !(1 == ~E_6~0); 4413#L839-1 assume { :end_inline_reset_delta_events } true; 4402#L1065-2 [2022-02-21 04:21:53,737 INFO L793 eck$LassoCheckResult]: Loop: 4402#L1065-2 assume !false; 4403#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4455#L671 assume !false; 4782#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4728#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4255#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4265#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4675#L582 assume !(0 != eval_~tmp~0#1); 4826#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4663#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4451#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4452#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4497#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4498#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4807#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4802#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4655#L721-3 assume !(0 == ~T6_E~0); 4480#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4481#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4650#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4651#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4426#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4427#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4548#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4304#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4305#L346-24 assume !(1 == ~m_pc~0); 4336#L346-26 is_master_triggered_~__retres1~0#1 := 0; 4419#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4652#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4788#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4754#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4366#L365-24 assume !(1 == ~t1_pc~0); 4368#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 4656#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4533#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4534#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4720#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4322#L384-24 assume !(1 == ~t2_pc~0); 4323#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4340#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4791#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4641#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 4346#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4347#L403-24 assume 1 == ~t3_pc~0; 4468#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4499#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4500#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4598#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4599#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4399#L422-24 assume !(1 == ~t4_pc~0); 4400#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 4353#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4354#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4804#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4762#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4414#L441-24 assume !(1 == ~t5_pc~0); 4416#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4619#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4620#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4286#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4287#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4701#L460-24 assume !(1 == ~t6_pc~0); 4702#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 4757#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4730#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4731#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4692#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4693#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4640#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4479#L779-3 assume !(1 == ~T2_E~0); 4194#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4195#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4174#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4175#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4296#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4617#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4291#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4292#L819-3 assume !(1 == ~E_3~0); 4441#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4424#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4425#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4276#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4277#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4274#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4362#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4211#L1084 assume !(0 == start_simulation_~tmp~3#1); 4213#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4461#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4177#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4316#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4467#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4310#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4302#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4303#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4402#L1065-2 [2022-02-21 04:21:53,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,738 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2022-02-21 04:21:53,738 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,738 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163296578] [2022-02-21 04:21:53,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,775 INFO L290 TraceCheckUtils]: 0: Hoare triple {6209#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {6209#true} is VALID [2022-02-21 04:21:53,776 INFO L290 TraceCheckUtils]: 1: Hoare triple {6209#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,776 INFO L290 TraceCheckUtils]: 2: Hoare triple {6211#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,777 INFO L290 TraceCheckUtils]: 3: Hoare triple {6211#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,777 INFO L290 TraceCheckUtils]: 4: Hoare triple {6211#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,777 INFO L290 TraceCheckUtils]: 5: Hoare triple {6211#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 6: Hoare triple {6211#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {6211#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {6211#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 8: Hoare triple {6210#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 9: Hoare triple {6210#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 10: Hoare triple {6210#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 11: Hoare triple {6210#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {6210#false} is VALID [2022-02-21 04:21:53,778 INFO L290 TraceCheckUtils]: 12: Hoare triple {6210#false} assume !(0 == ~M_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 13: Hoare triple {6210#false} assume !(0 == ~T1_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 14: Hoare triple {6210#false} assume !(0 == ~T2_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 15: Hoare triple {6210#false} assume !(0 == ~T3_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 16: Hoare triple {6210#false} assume !(0 == ~T4_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 17: Hoare triple {6210#false} assume !(0 == ~T5_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 18: Hoare triple {6210#false} assume !(0 == ~T6_E~0); {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 19: Hoare triple {6210#false} assume 0 == ~E_M~0;~E_M~0 := 1; {6210#false} is VALID [2022-02-21 04:21:53,779 INFO L290 TraceCheckUtils]: 20: Hoare triple {6210#false} assume !(0 == ~E_1~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 21: Hoare triple {6210#false} assume !(0 == ~E_2~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 22: Hoare triple {6210#false} assume !(0 == ~E_3~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 23: Hoare triple {6210#false} assume !(0 == ~E_4~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 24: Hoare triple {6210#false} assume !(0 == ~E_5~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 25: Hoare triple {6210#false} assume !(0 == ~E_6~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 26: Hoare triple {6210#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 27: Hoare triple {6210#false} assume !(1 == ~m_pc~0); {6210#false} is VALID [2022-02-21 04:21:53,780 INFO L290 TraceCheckUtils]: 28: Hoare triple {6210#false} is_master_triggered_~__retres1~0#1 := 0; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 29: Hoare triple {6210#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 30: Hoare triple {6210#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 31: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp~1#1); {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 32: Hoare triple {6210#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 33: Hoare triple {6210#false} assume 1 == ~t1_pc~0; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 34: Hoare triple {6210#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 35: Hoare triple {6210#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6210#false} is VALID [2022-02-21 04:21:53,781 INFO L290 TraceCheckUtils]: 36: Hoare triple {6210#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 37: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp___0~0#1); {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 38: Hoare triple {6210#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 39: Hoare triple {6210#false} assume !(1 == ~t2_pc~0); {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 40: Hoare triple {6210#false} is_transmit2_triggered_~__retres1~2#1 := 0; {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 41: Hoare triple {6210#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 42: Hoare triple {6210#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 43: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp___1~0#1); {6210#false} is VALID [2022-02-21 04:21:53,782 INFO L290 TraceCheckUtils]: 44: Hoare triple {6210#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 45: Hoare triple {6210#false} assume 1 == ~t3_pc~0; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 46: Hoare triple {6210#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 47: Hoare triple {6210#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 48: Hoare triple {6210#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 49: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp___2~0#1); {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 50: Hoare triple {6210#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 51: Hoare triple {6210#false} assume 1 == ~t4_pc~0; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 52: Hoare triple {6210#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {6210#false} is VALID [2022-02-21 04:21:53,783 INFO L290 TraceCheckUtils]: 53: Hoare triple {6210#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 54: Hoare triple {6210#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 55: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp___3~0#1); {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 56: Hoare triple {6210#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 57: Hoare triple {6210#false} assume !(1 == ~t5_pc~0); {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 58: Hoare triple {6210#false} is_transmit5_triggered_~__retres1~5#1 := 0; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 59: Hoare triple {6210#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 60: Hoare triple {6210#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6210#false} is VALID [2022-02-21 04:21:53,784 INFO L290 TraceCheckUtils]: 61: Hoare triple {6210#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 62: Hoare triple {6210#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 63: Hoare triple {6210#false} assume 1 == ~t6_pc~0; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 64: Hoare triple {6210#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 65: Hoare triple {6210#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 66: Hoare triple {6210#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 67: Hoare triple {6210#false} assume !(0 != activate_threads_~tmp___5~0#1); {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 68: Hoare triple {6210#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6210#false} is VALID [2022-02-21 04:21:53,785 INFO L290 TraceCheckUtils]: 69: Hoare triple {6210#false} assume !(1 == ~M_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 70: Hoare triple {6210#false} assume !(1 == ~T1_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 71: Hoare triple {6210#false} assume !(1 == ~T2_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 72: Hoare triple {6210#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 73: Hoare triple {6210#false} assume !(1 == ~T4_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 74: Hoare triple {6210#false} assume !(1 == ~T5_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 75: Hoare triple {6210#false} assume !(1 == ~T6_E~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 76: Hoare triple {6210#false} assume !(1 == ~E_M~0); {6210#false} is VALID [2022-02-21 04:21:53,786 INFO L290 TraceCheckUtils]: 77: Hoare triple {6210#false} assume !(1 == ~E_1~0); {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 78: Hoare triple {6210#false} assume !(1 == ~E_2~0); {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 79: Hoare triple {6210#false} assume !(1 == ~E_3~0); {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 80: Hoare triple {6210#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 81: Hoare triple {6210#false} assume !(1 == ~E_5~0); {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 82: Hoare triple {6210#false} assume !(1 == ~E_6~0); {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L290 TraceCheckUtils]: 83: Hoare triple {6210#false} assume { :end_inline_reset_delta_events } true; {6210#false} is VALID [2022-02-21 04:21:53,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,788 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,788 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163296578] [2022-02-21 04:21:53,788 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163296578] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,788 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,788 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:53,788 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144983661] [2022-02-21 04:21:53,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,789 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:53,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:53,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1051261759, now seen corresponding path program 1 times [2022-02-21 04:21:53,789 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:53,789 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345298929] [2022-02-21 04:21:53,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:53,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:53,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:53,820 INFO L290 TraceCheckUtils]: 0: Hoare triple {6212#true} assume !false; {6212#true} is VALID [2022-02-21 04:21:53,820 INFO L290 TraceCheckUtils]: 1: Hoare triple {6212#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {6212#true} is VALID [2022-02-21 04:21:53,820 INFO L290 TraceCheckUtils]: 2: Hoare triple {6212#true} assume !false; {6212#true} is VALID [2022-02-21 04:21:53,820 INFO L290 TraceCheckUtils]: 3: Hoare triple {6212#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 4: Hoare triple {6212#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 5: Hoare triple {6212#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 6: Hoare triple {6212#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 7: Hoare triple {6212#true} assume !(0 != eval_~tmp~0#1); {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 8: Hoare triple {6212#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 9: Hoare triple {6212#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 10: Hoare triple {6212#true} assume 0 == ~M_E~0;~M_E~0 := 1; {6212#true} is VALID [2022-02-21 04:21:53,821 INFO L290 TraceCheckUtils]: 11: Hoare triple {6212#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {6212#true} is VALID [2022-02-21 04:21:53,822 INFO L290 TraceCheckUtils]: 12: Hoare triple {6212#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,822 INFO L290 TraceCheckUtils]: 13: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,822 INFO L290 TraceCheckUtils]: 14: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,823 INFO L290 TraceCheckUtils]: 15: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,823 INFO L290 TraceCheckUtils]: 16: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,823 INFO L290 TraceCheckUtils]: 17: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,824 INFO L290 TraceCheckUtils]: 18: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,824 INFO L290 TraceCheckUtils]: 19: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,824 INFO L290 TraceCheckUtils]: 20: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,824 INFO L290 TraceCheckUtils]: 21: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,825 INFO L290 TraceCheckUtils]: 22: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,825 INFO L290 TraceCheckUtils]: 23: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,825 INFO L290 TraceCheckUtils]: 24: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,826 INFO L290 TraceCheckUtils]: 25: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,826 INFO L290 TraceCheckUtils]: 26: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,826 INFO L290 TraceCheckUtils]: 27: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,827 INFO L290 TraceCheckUtils]: 28: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,827 INFO L290 TraceCheckUtils]: 29: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,827 INFO L290 TraceCheckUtils]: 30: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,827 INFO L290 TraceCheckUtils]: 31: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,828 INFO L290 TraceCheckUtils]: 32: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,828 INFO L290 TraceCheckUtils]: 33: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,828 INFO L290 TraceCheckUtils]: 34: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,829 INFO L290 TraceCheckUtils]: 35: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,829 INFO L290 TraceCheckUtils]: 36: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,829 INFO L290 TraceCheckUtils]: 37: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,829 INFO L290 TraceCheckUtils]: 38: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,830 INFO L290 TraceCheckUtils]: 39: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,830 INFO L290 TraceCheckUtils]: 40: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,830 INFO L290 TraceCheckUtils]: 41: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,831 INFO L290 TraceCheckUtils]: 42: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,831 INFO L290 TraceCheckUtils]: 43: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,831 INFO L290 TraceCheckUtils]: 44: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,832 INFO L290 TraceCheckUtils]: 45: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,832 INFO L290 TraceCheckUtils]: 46: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,832 INFO L290 TraceCheckUtils]: 47: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,832 INFO L290 TraceCheckUtils]: 48: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,833 INFO L290 TraceCheckUtils]: 49: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,833 INFO L290 TraceCheckUtils]: 50: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,833 INFO L290 TraceCheckUtils]: 51: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,834 INFO L290 TraceCheckUtils]: 52: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,834 INFO L290 TraceCheckUtils]: 53: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,834 INFO L290 TraceCheckUtils]: 54: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,834 INFO L290 TraceCheckUtils]: 55: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,835 INFO L290 TraceCheckUtils]: 56: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,835 INFO L290 TraceCheckUtils]: 57: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,835 INFO L290 TraceCheckUtils]: 58: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,836 INFO L290 TraceCheckUtils]: 59: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,836 INFO L290 TraceCheckUtils]: 60: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,836 INFO L290 TraceCheckUtils]: 61: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,837 INFO L290 TraceCheckUtils]: 62: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,837 INFO L290 TraceCheckUtils]: 63: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,837 INFO L290 TraceCheckUtils]: 64: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,837 INFO L290 TraceCheckUtils]: 65: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,838 INFO L290 TraceCheckUtils]: 66: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,838 INFO L290 TraceCheckUtils]: 67: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,838 INFO L290 TraceCheckUtils]: 68: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {6214#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 69: Hoare triple {6214#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 70: Hoare triple {6213#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 71: Hoare triple {6213#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 72: Hoare triple {6213#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 73: Hoare triple {6213#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 74: Hoare triple {6213#false} assume 1 == ~E_M~0;~E_M~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,839 INFO L290 TraceCheckUtils]: 75: Hoare triple {6213#false} assume 1 == ~E_1~0;~E_1~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 76: Hoare triple {6213#false} assume 1 == ~E_2~0;~E_2~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 77: Hoare triple {6213#false} assume !(1 == ~E_3~0); {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 78: Hoare triple {6213#false} assume 1 == ~E_4~0;~E_4~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 79: Hoare triple {6213#false} assume 1 == ~E_5~0;~E_5~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 80: Hoare triple {6213#false} assume 1 == ~E_6~0;~E_6~0 := 2; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 81: Hoare triple {6213#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 82: Hoare triple {6213#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {6213#false} is VALID [2022-02-21 04:21:53,840 INFO L290 TraceCheckUtils]: 83: Hoare triple {6213#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 84: Hoare triple {6213#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 85: Hoare triple {6213#false} assume !(0 == start_simulation_~tmp~3#1); {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 86: Hoare triple {6213#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 87: Hoare triple {6213#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 88: Hoare triple {6213#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 89: Hoare triple {6213#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 90: Hoare triple {6213#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {6213#false} is VALID [2022-02-21 04:21:53,841 INFO L290 TraceCheckUtils]: 91: Hoare triple {6213#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {6213#false} is VALID [2022-02-21 04:21:53,842 INFO L290 TraceCheckUtils]: 92: Hoare triple {6213#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {6213#false} is VALID [2022-02-21 04:21:53,842 INFO L290 TraceCheckUtils]: 93: Hoare triple {6213#false} assume !(0 != start_simulation_~tmp___0~1#1); {6213#false} is VALID [2022-02-21 04:21:53,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:53,842 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:53,842 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345298929] [2022-02-21 04:21:53,842 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345298929] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:53,843 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:53,843 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:53,843 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810169679] [2022-02-21 04:21:53,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:53,843 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:53,843 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:53,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:53,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:53,844 INFO L87 Difference]: Start difference. First operand 686 states and 1027 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,298 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2022-02-21 04:21:54,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:54,298 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,351 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:54,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:54,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1026 transitions. [2022-02-21 04:21:54,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:54,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:54,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,382 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:54,382 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-02-21 04:21:54,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:54,387 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:54,388 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1026 transitions. Second operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,389 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1026 transitions. Second operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,390 INFO L87 Difference]: Start difference. First operand 686 states and 1026 transitions. Second operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,403 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2022-02-21 04:21:54,403 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,404 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:54,404 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:54,405 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1026 transitions. [2022-02-21 04:21:54,406 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1026 transitions. [2022-02-21 04:21:54,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,419 INFO L93 Difference]: Finished difference Result 686 states and 1026 transitions. [2022-02-21 04:21:54,419 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,420 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:54,420 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:54,420 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:54,420 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:54,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4956268221574345) internal successors, (1026), 685 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1026 transitions. [2022-02-21 04:21:54,452 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-02-21 04:21:54,453 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1026 transitions. [2022-02-21 04:21:54,453 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:54,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1026 transitions. [2022-02-21 04:21:54,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:54,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:54,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:54,457 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,457 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,457 INFO L791 eck$LassoCheckResult]: Stem: 7586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7564#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7539#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7485#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7486#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7150#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7151#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6998#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6999#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6967#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6968#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7128#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7288#L696 assume !(0 == ~M_E~0); 7289#L696-2 assume !(0 == ~T1_E~0); 7554#L701-1 assume !(0 == ~T2_E~0); 7556#L706-1 assume !(0 == ~T3_E~0); 7399#L711-1 assume !(0 == ~T4_E~0); 7184#L716-1 assume !(0 == ~T5_E~0); 7185#L721-1 assume !(0 == ~T6_E~0); 7355#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7356#L731-1 assume !(0 == ~E_1~0); 7327#L736-1 assume !(0 == ~E_2~0); 7328#L741-1 assume !(0 == ~E_3~0); 7406#L746-1 assume !(0 == ~E_4~0); 7218#L751-1 assume !(0 == ~E_5~0); 7219#L756-1 assume !(0 == ~E_6~0); 7181#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7015#L346 assume !(1 == ~m_pc~0); 7016#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7229#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6923#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6924#L861 assume !(0 != activate_threads_~tmp~1#1); 7526#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7046#L365 assume 1 == ~t1_pc~0; 7047#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7165#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7540#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7037#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7038#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7453#L384 assume !(1 == ~t2_pc~0); 7443#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7444#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7124#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6949#L877 assume !(0 != activate_threads_~tmp___1~0#1); 6950#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7305#L403 assume 1 == ~t3_pc~0; 7186#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7187#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7173#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7174#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7296#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7297#L422 assume 1 == ~t4_pc~0; 6944#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6945#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7449#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7450#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7383#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6969#L441 assume !(1 == ~t5_pc~0); 6970#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7523#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7566#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7567#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7391#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7392#L460 assume 1 == ~t6_pc~0; 6906#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6907#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6977#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7494#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7495#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7365#L774 assume !(1 == ~M_E~0); 7366#L774-2 assume !(1 == ~T1_E~0); 7509#L779-1 assume !(1 == ~T2_E~0); 7270#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7271#L789-1 assume !(1 == ~T4_E~0); 7031#L794-1 assume !(1 == ~T5_E~0); 7032#L799-1 assume !(1 == ~T6_E~0); 7577#L804-1 assume !(1 == ~E_M~0); 7578#L809-1 assume !(1 == ~E_1~0); 7353#L814-1 assume !(1 == ~E_2~0); 6925#L819-1 assume !(1 == ~E_3~0); 6926#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7413#L829-1 assume !(1 == ~E_5~0); 7501#L834-1 assume !(1 == ~E_6~0); 7166#L839-1 assume { :end_inline_reset_delta_events } true; 7155#L1065-2 [2022-02-21 04:21:54,457 INFO L793 eck$LassoCheckResult]: Loop: 7155#L1065-2 assume !false; 7156#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7208#L671 assume !false; 7535#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7481#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7008#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7018#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7428#L582 assume !(0 != eval_~tmp~0#1); 7579#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7416#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7204#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7205#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7250#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7251#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7560#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7555#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7408#L721-3 assume !(0 == ~T6_E~0); 7233#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7234#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7403#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7404#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7179#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7180#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7301#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7057#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7058#L346-24 assume 1 == ~m_pc~0; 7088#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7172#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7405#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7541#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7507#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7119#L365-24 assume 1 == ~t1_pc~0; 7120#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7409#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7286#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7287#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7473#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7073#L384-24 assume !(1 == ~t2_pc~0); 7074#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7093#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7544#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7394#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 7099#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7100#L403-24 assume 1 == ~t3_pc~0; 7221#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7252#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7253#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7351#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7352#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7152#L422-24 assume !(1 == ~t4_pc~0); 7153#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 7106#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7107#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7557#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7515#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7167#L441-24 assume 1 == ~t5_pc~0; 7168#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7372#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7373#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7039#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7040#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7454#L460-24 assume 1 == ~t6_pc~0; 7456#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7510#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7483#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7484#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7445#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7446#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7393#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7232#L779-3 assume !(1 == ~T2_E~0); 6947#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6948#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6927#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6928#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7049#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7370#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7044#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7045#L819-3 assume !(1 == ~E_3~0); 7194#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7177#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7178#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7029#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7030#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7027#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7115#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6964#L1084 assume !(0 == start_simulation_~tmp~3#1); 6966#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7214#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6930#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7069#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7220#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7063#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7055#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7056#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7155#L1065-2 [2022-02-21 04:21:54,458 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:54,458 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2022-02-21 04:21:54,458 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:54,458 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1909553120] [2022-02-21 04:21:54,458 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:54,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:54,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:54,479 INFO L290 TraceCheckUtils]: 0: Hoare triple {8962#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {8962#true} is VALID [2022-02-21 04:21:54,479 INFO L290 TraceCheckUtils]: 1: Hoare triple {8962#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,479 INFO L290 TraceCheckUtils]: 2: Hoare triple {8964#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,480 INFO L290 TraceCheckUtils]: 3: Hoare triple {8964#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,480 INFO L290 TraceCheckUtils]: 4: Hoare triple {8964#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,480 INFO L290 TraceCheckUtils]: 5: Hoare triple {8964#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,480 INFO L290 TraceCheckUtils]: 6: Hoare triple {8964#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 7: Hoare triple {8964#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {8964#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 8: Hoare triple {8964#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {8963#false} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 9: Hoare triple {8963#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {8963#false} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 10: Hoare triple {8963#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {8963#false} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 11: Hoare triple {8963#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {8963#false} is VALID [2022-02-21 04:21:54,481 INFO L290 TraceCheckUtils]: 12: Hoare triple {8963#false} assume !(0 == ~M_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 13: Hoare triple {8963#false} assume !(0 == ~T1_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 14: Hoare triple {8963#false} assume !(0 == ~T2_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 15: Hoare triple {8963#false} assume !(0 == ~T3_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 16: Hoare triple {8963#false} assume !(0 == ~T4_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 17: Hoare triple {8963#false} assume !(0 == ~T5_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 18: Hoare triple {8963#false} assume !(0 == ~T6_E~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 19: Hoare triple {8963#false} assume 0 == ~E_M~0;~E_M~0 := 1; {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 20: Hoare triple {8963#false} assume !(0 == ~E_1~0); {8963#false} is VALID [2022-02-21 04:21:54,482 INFO L290 TraceCheckUtils]: 21: Hoare triple {8963#false} assume !(0 == ~E_2~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 22: Hoare triple {8963#false} assume !(0 == ~E_3~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 23: Hoare triple {8963#false} assume !(0 == ~E_4~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 24: Hoare triple {8963#false} assume !(0 == ~E_5~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 25: Hoare triple {8963#false} assume !(0 == ~E_6~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 26: Hoare triple {8963#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 27: Hoare triple {8963#false} assume !(1 == ~m_pc~0); {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 28: Hoare triple {8963#false} is_master_triggered_~__retres1~0#1 := 0; {8963#false} is VALID [2022-02-21 04:21:54,483 INFO L290 TraceCheckUtils]: 29: Hoare triple {8963#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 30: Hoare triple {8963#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 31: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp~1#1); {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 32: Hoare triple {8963#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 33: Hoare triple {8963#false} assume 1 == ~t1_pc~0; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 34: Hoare triple {8963#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 35: Hoare triple {8963#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 36: Hoare triple {8963#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 37: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp___0~0#1); {8963#false} is VALID [2022-02-21 04:21:54,484 INFO L290 TraceCheckUtils]: 38: Hoare triple {8963#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 39: Hoare triple {8963#false} assume !(1 == ~t2_pc~0); {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 40: Hoare triple {8963#false} is_transmit2_triggered_~__retres1~2#1 := 0; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 41: Hoare triple {8963#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 42: Hoare triple {8963#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 43: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp___1~0#1); {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 44: Hoare triple {8963#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 45: Hoare triple {8963#false} assume 1 == ~t3_pc~0; {8963#false} is VALID [2022-02-21 04:21:54,485 INFO L290 TraceCheckUtils]: 46: Hoare triple {8963#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 47: Hoare triple {8963#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 48: Hoare triple {8963#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 49: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp___2~0#1); {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 50: Hoare triple {8963#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 51: Hoare triple {8963#false} assume 1 == ~t4_pc~0; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 52: Hoare triple {8963#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 53: Hoare triple {8963#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 54: Hoare triple {8963#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8963#false} is VALID [2022-02-21 04:21:54,486 INFO L290 TraceCheckUtils]: 55: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp___3~0#1); {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 56: Hoare triple {8963#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 57: Hoare triple {8963#false} assume !(1 == ~t5_pc~0); {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 58: Hoare triple {8963#false} is_transmit5_triggered_~__retres1~5#1 := 0; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 59: Hoare triple {8963#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 60: Hoare triple {8963#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 61: Hoare triple {8963#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 62: Hoare triple {8963#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 63: Hoare triple {8963#false} assume 1 == ~t6_pc~0; {8963#false} is VALID [2022-02-21 04:21:54,487 INFO L290 TraceCheckUtils]: 64: Hoare triple {8963#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 65: Hoare triple {8963#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 66: Hoare triple {8963#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 67: Hoare triple {8963#false} assume !(0 != activate_threads_~tmp___5~0#1); {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 68: Hoare triple {8963#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 69: Hoare triple {8963#false} assume !(1 == ~M_E~0); {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 70: Hoare triple {8963#false} assume !(1 == ~T1_E~0); {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 71: Hoare triple {8963#false} assume !(1 == ~T2_E~0); {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 72: Hoare triple {8963#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8963#false} is VALID [2022-02-21 04:21:54,488 INFO L290 TraceCheckUtils]: 73: Hoare triple {8963#false} assume !(1 == ~T4_E~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 74: Hoare triple {8963#false} assume !(1 == ~T5_E~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 75: Hoare triple {8963#false} assume !(1 == ~T6_E~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 76: Hoare triple {8963#false} assume !(1 == ~E_M~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 77: Hoare triple {8963#false} assume !(1 == ~E_1~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 78: Hoare triple {8963#false} assume !(1 == ~E_2~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 79: Hoare triple {8963#false} assume !(1 == ~E_3~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 80: Hoare triple {8963#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 81: Hoare triple {8963#false} assume !(1 == ~E_5~0); {8963#false} is VALID [2022-02-21 04:21:54,489 INFO L290 TraceCheckUtils]: 82: Hoare triple {8963#false} assume !(1 == ~E_6~0); {8963#false} is VALID [2022-02-21 04:21:54,490 INFO L290 TraceCheckUtils]: 83: Hoare triple {8963#false} assume { :end_inline_reset_delta_events } true; {8963#false} is VALID [2022-02-21 04:21:54,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:54,490 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:54,490 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1909553120] [2022-02-21 04:21:54,490 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1909553120] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:54,490 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:54,491 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:54,491 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862683750] [2022-02-21 04:21:54,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:54,491 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:54,491 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:54,492 INFO L85 PathProgramCache]: Analyzing trace with hash 1870190395, now seen corresponding path program 1 times [2022-02-21 04:21:54,492 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:54,492 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118867090] [2022-02-21 04:21:54,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:54,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:54,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:54,517 INFO L290 TraceCheckUtils]: 0: Hoare triple {8965#true} assume !false; {8965#true} is VALID [2022-02-21 04:21:54,517 INFO L290 TraceCheckUtils]: 1: Hoare triple {8965#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {8965#true} is VALID [2022-02-21 04:21:54,517 INFO L290 TraceCheckUtils]: 2: Hoare triple {8965#true} assume !false; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 3: Hoare triple {8965#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 4: Hoare triple {8965#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 5: Hoare triple {8965#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 6: Hoare triple {8965#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 7: Hoare triple {8965#true} assume !(0 != eval_~tmp~0#1); {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 8: Hoare triple {8965#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 9: Hoare triple {8965#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 10: Hoare triple {8965#true} assume 0 == ~M_E~0;~M_E~0 := 1; {8965#true} is VALID [2022-02-21 04:21:54,518 INFO L290 TraceCheckUtils]: 11: Hoare triple {8965#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {8965#true} is VALID [2022-02-21 04:21:54,519 INFO L290 TraceCheckUtils]: 12: Hoare triple {8965#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,519 INFO L290 TraceCheckUtils]: 13: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,519 INFO L290 TraceCheckUtils]: 14: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,520 INFO L290 TraceCheckUtils]: 15: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,520 INFO L290 TraceCheckUtils]: 16: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,520 INFO L290 TraceCheckUtils]: 17: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,520 INFO L290 TraceCheckUtils]: 18: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,521 INFO L290 TraceCheckUtils]: 19: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,521 INFO L290 TraceCheckUtils]: 20: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,521 INFO L290 TraceCheckUtils]: 21: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,522 INFO L290 TraceCheckUtils]: 22: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,522 INFO L290 TraceCheckUtils]: 23: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,522 INFO L290 TraceCheckUtils]: 24: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,522 INFO L290 TraceCheckUtils]: 25: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,523 INFO L290 TraceCheckUtils]: 26: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,523 INFO L290 TraceCheckUtils]: 27: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,523 INFO L290 TraceCheckUtils]: 28: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,524 INFO L290 TraceCheckUtils]: 29: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,524 INFO L290 TraceCheckUtils]: 30: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,524 INFO L290 TraceCheckUtils]: 31: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,524 INFO L290 TraceCheckUtils]: 32: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,525 INFO L290 TraceCheckUtils]: 33: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,525 INFO L290 TraceCheckUtils]: 34: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,525 INFO L290 TraceCheckUtils]: 35: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,525 INFO L290 TraceCheckUtils]: 36: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,526 INFO L290 TraceCheckUtils]: 37: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,526 INFO L290 TraceCheckUtils]: 38: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,526 INFO L290 TraceCheckUtils]: 39: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,527 INFO L290 TraceCheckUtils]: 40: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,527 INFO L290 TraceCheckUtils]: 41: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,527 INFO L290 TraceCheckUtils]: 42: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,527 INFO L290 TraceCheckUtils]: 43: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,528 INFO L290 TraceCheckUtils]: 44: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,528 INFO L290 TraceCheckUtils]: 45: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,528 INFO L290 TraceCheckUtils]: 46: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,528 INFO L290 TraceCheckUtils]: 47: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,529 INFO L290 TraceCheckUtils]: 48: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,529 INFO L290 TraceCheckUtils]: 49: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,529 INFO L290 TraceCheckUtils]: 50: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,530 INFO L290 TraceCheckUtils]: 51: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,530 INFO L290 TraceCheckUtils]: 52: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,530 INFO L290 TraceCheckUtils]: 53: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,530 INFO L290 TraceCheckUtils]: 54: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,531 INFO L290 TraceCheckUtils]: 55: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,531 INFO L290 TraceCheckUtils]: 56: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,531 INFO L290 TraceCheckUtils]: 57: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,531 INFO L290 TraceCheckUtils]: 58: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,532 INFO L290 TraceCheckUtils]: 59: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,532 INFO L290 TraceCheckUtils]: 60: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,532 INFO L290 TraceCheckUtils]: 61: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,533 INFO L290 TraceCheckUtils]: 62: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,533 INFO L290 TraceCheckUtils]: 63: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,533 INFO L290 TraceCheckUtils]: 64: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,533 INFO L290 TraceCheckUtils]: 65: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,534 INFO L290 TraceCheckUtils]: 66: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,534 INFO L290 TraceCheckUtils]: 67: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,534 INFO L290 TraceCheckUtils]: 68: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {8967#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 69: Hoare triple {8967#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 70: Hoare triple {8966#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 71: Hoare triple {8966#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 72: Hoare triple {8966#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 73: Hoare triple {8966#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 74: Hoare triple {8966#false} assume 1 == ~E_M~0;~E_M~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 75: Hoare triple {8966#false} assume 1 == ~E_1~0;~E_1~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 76: Hoare triple {8966#false} assume 1 == ~E_2~0;~E_2~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,535 INFO L290 TraceCheckUtils]: 77: Hoare triple {8966#false} assume !(1 == ~E_3~0); {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 78: Hoare triple {8966#false} assume 1 == ~E_4~0;~E_4~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 79: Hoare triple {8966#false} assume 1 == ~E_5~0;~E_5~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 80: Hoare triple {8966#false} assume 1 == ~E_6~0;~E_6~0 := 2; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 81: Hoare triple {8966#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 82: Hoare triple {8966#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 83: Hoare triple {8966#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 84: Hoare triple {8966#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 85: Hoare triple {8966#false} assume !(0 == start_simulation_~tmp~3#1); {8966#false} is VALID [2022-02-21 04:21:54,536 INFO L290 TraceCheckUtils]: 86: Hoare triple {8966#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 87: Hoare triple {8966#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 88: Hoare triple {8966#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 89: Hoare triple {8966#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 90: Hoare triple {8966#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 91: Hoare triple {8966#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 92: Hoare triple {8966#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {8966#false} is VALID [2022-02-21 04:21:54,537 INFO L290 TraceCheckUtils]: 93: Hoare triple {8966#false} assume !(0 != start_simulation_~tmp___0~1#1); {8966#false} is VALID [2022-02-21 04:21:54,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:54,538 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:54,538 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118867090] [2022-02-21 04:21:54,538 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118867090] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:54,538 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:54,538 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:54,538 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [788410569] [2022-02-21 04:21:54,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:54,539 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:54,539 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:54,539 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:54,539 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:54,540 INFO L87 Difference]: Start difference. First operand 686 states and 1026 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,981 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:54,981 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2022-02-21 04:21:54,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:54,982 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,029 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:55,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:55,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1025 transitions. [2022-02-21 04:21:55,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:55,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:55,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:55,059 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-02-21 04:21:55,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:55,065 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:55,066 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1025 transitions. Second operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,067 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1025 transitions. Second operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,068 INFO L87 Difference]: Start difference. First operand 686 states and 1025 transitions. Second operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,081 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2022-02-21 04:21:55,081 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,081 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,082 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,083 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1025 transitions. [2022-02-21 04:21:55,084 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1025 transitions. [2022-02-21 04:21:55,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,097 INFO L93 Difference]: Finished difference Result 686 states and 1025 transitions. [2022-02-21 04:21:55,097 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,098 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,098 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,098 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:55,098 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:55,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4941690962099126) internal successors, (1025), 685 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,112 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1025 transitions. [2022-02-21 04:21:55,112 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-02-21 04:21:55,113 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1025 transitions. [2022-02-21 04:21:55,113 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:55,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1025 transitions. [2022-02-21 04:21:55,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:55,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:55,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:55,116 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,116 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,116 INFO L791 eck$LassoCheckResult]: Stem: 10339#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10317#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10292#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10238#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10239#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 9903#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9904#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9753#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9754#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9720#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9721#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9881#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10041#L696 assume !(0 == ~M_E~0); 10042#L696-2 assume !(0 == ~T1_E~0); 10307#L701-1 assume !(0 == ~T2_E~0); 10309#L706-1 assume !(0 == ~T3_E~0); 10152#L711-1 assume !(0 == ~T4_E~0); 9937#L716-1 assume !(0 == ~T5_E~0); 9938#L721-1 assume !(0 == ~T6_E~0); 10108#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 10109#L731-1 assume !(0 == ~E_1~0); 10080#L736-1 assume !(0 == ~E_2~0); 10081#L741-1 assume !(0 == ~E_3~0); 10159#L746-1 assume !(0 == ~E_4~0); 9971#L751-1 assume !(0 == ~E_5~0); 9972#L756-1 assume !(0 == ~E_6~0); 9934#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9768#L346 assume !(1 == ~m_pc~0); 9769#L346-2 is_master_triggered_~__retres1~0#1 := 0; 9982#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9678#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9679#L861 assume !(0 != activate_threads_~tmp~1#1); 10279#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9800#L365 assume 1 == ~t1_pc~0; 9801#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9921#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10296#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9790#L869 assume !(0 != activate_threads_~tmp___0~0#1); 9791#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10206#L384 assume !(1 == ~t2_pc~0); 10198#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10199#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9880#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9704#L877 assume !(0 != activate_threads_~tmp___1~0#1); 9705#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10059#L403 assume 1 == ~t3_pc~0; 9939#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9940#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9930#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9931#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10052#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10053#L422 assume 1 == ~t4_pc~0; 9699#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9700#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10202#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10203#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10136#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9722#L441 assume !(1 == ~t5_pc~0); 9723#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10276#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10319#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10320#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10145#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10146#L460 assume 1 == ~t6_pc~0; 9662#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9663#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9730#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10247#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10248#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10118#L774 assume !(1 == ~M_E~0); 10119#L774-2 assume !(1 == ~T1_E~0); 10262#L779-1 assume !(1 == ~T2_E~0); 10023#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10024#L789-1 assume !(1 == ~T4_E~0); 9784#L794-1 assume !(1 == ~T5_E~0); 9785#L799-1 assume !(1 == ~T6_E~0); 10330#L804-1 assume !(1 == ~E_M~0); 10331#L809-1 assume !(1 == ~E_1~0); 10106#L814-1 assume !(1 == ~E_2~0); 9680#L819-1 assume !(1 == ~E_3~0); 9681#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10166#L829-1 assume !(1 == ~E_5~0); 10254#L834-1 assume !(1 == ~E_6~0); 9922#L839-1 assume { :end_inline_reset_delta_events } true; 9912#L1065-2 [2022-02-21 04:21:55,117 INFO L793 eck$LassoCheckResult]: Loop: 9912#L1065-2 assume !false; 9913#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9961#L671 assume !false; 10288#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10234#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9761#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9771#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10182#L582 assume !(0 != eval_~tmp~0#1); 10332#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10169#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9957#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9958#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10003#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10004#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10313#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10308#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10162#L721-3 assume !(0 == ~T6_E~0); 9986#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9987#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10156#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10157#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9932#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9933#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10054#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9810#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9811#L346-24 assume 1 == ~m_pc~0; 9841#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9923#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10158#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10293#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10260#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9872#L365-24 assume 1 == ~t1_pc~0; 9873#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10161#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10039#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10040#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10226#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9826#L384-24 assume !(1 == ~t2_pc~0); 9827#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9846#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10297#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10147#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 9851#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9852#L403-24 assume 1 == ~t3_pc~0; 9974#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10005#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10006#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10104#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10105#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9905#L422-24 assume !(1 == ~t4_pc~0); 9906#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 9858#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9859#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10310#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10268#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9918#L441-24 assume !(1 == ~t5_pc~0); 9920#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 10124#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10125#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9792#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9793#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10207#L460-24 assume !(1 == ~t6_pc~0); 10208#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 10263#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10236#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10237#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10196#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10197#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10144#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9985#L779-3 assume !(1 == ~T2_E~0); 9697#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9698#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9676#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9677#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9799#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10123#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9797#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9798#L819-3 assume !(1 == ~E_3~0); 9947#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9928#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9929#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9782#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9783#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9780#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9868#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9717#L1084 assume !(0 == start_simulation_~tmp~3#1); 9719#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9967#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9683#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9822#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9973#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9815#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9808#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9809#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 9912#L1065-2 [2022-02-21 04:21:55,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2022-02-21 04:21:55,117 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,118 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253662064] [2022-02-21 04:21:55,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,134 INFO L290 TraceCheckUtils]: 0: Hoare triple {11715#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {11715#true} is VALID [2022-02-21 04:21:55,134 INFO L290 TraceCheckUtils]: 1: Hoare triple {11715#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,135 INFO L290 TraceCheckUtils]: 2: Hoare triple {11717#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,135 INFO L290 TraceCheckUtils]: 3: Hoare triple {11717#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,135 INFO L290 TraceCheckUtils]: 4: Hoare triple {11717#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,136 INFO L290 TraceCheckUtils]: 5: Hoare triple {11717#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,136 INFO L290 TraceCheckUtils]: 6: Hoare triple {11717#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,136 INFO L290 TraceCheckUtils]: 7: Hoare triple {11717#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,136 INFO L290 TraceCheckUtils]: 8: Hoare triple {11717#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {11717#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 9: Hoare triple {11717#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 10: Hoare triple {11716#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 11: Hoare triple {11716#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 12: Hoare triple {11716#false} assume !(0 == ~M_E~0); {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 13: Hoare triple {11716#false} assume !(0 == ~T1_E~0); {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 14: Hoare triple {11716#false} assume !(0 == ~T2_E~0); {11716#false} is VALID [2022-02-21 04:21:55,137 INFO L290 TraceCheckUtils]: 15: Hoare triple {11716#false} assume !(0 == ~T3_E~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 16: Hoare triple {11716#false} assume !(0 == ~T4_E~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 17: Hoare triple {11716#false} assume !(0 == ~T5_E~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 18: Hoare triple {11716#false} assume !(0 == ~T6_E~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 19: Hoare triple {11716#false} assume 0 == ~E_M~0;~E_M~0 := 1; {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 20: Hoare triple {11716#false} assume !(0 == ~E_1~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 21: Hoare triple {11716#false} assume !(0 == ~E_2~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 22: Hoare triple {11716#false} assume !(0 == ~E_3~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 23: Hoare triple {11716#false} assume !(0 == ~E_4~0); {11716#false} is VALID [2022-02-21 04:21:55,138 INFO L290 TraceCheckUtils]: 24: Hoare triple {11716#false} assume !(0 == ~E_5~0); {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 25: Hoare triple {11716#false} assume !(0 == ~E_6~0); {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 26: Hoare triple {11716#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 27: Hoare triple {11716#false} assume !(1 == ~m_pc~0); {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 28: Hoare triple {11716#false} is_master_triggered_~__retres1~0#1 := 0; {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 29: Hoare triple {11716#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {11716#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 31: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp~1#1); {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 32: Hoare triple {11716#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11716#false} is VALID [2022-02-21 04:21:55,139 INFO L290 TraceCheckUtils]: 33: Hoare triple {11716#false} assume 1 == ~t1_pc~0; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 34: Hoare triple {11716#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 35: Hoare triple {11716#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 36: Hoare triple {11716#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 37: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp___0~0#1); {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 38: Hoare triple {11716#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 39: Hoare triple {11716#false} assume !(1 == ~t2_pc~0); {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 40: Hoare triple {11716#false} is_transmit2_triggered_~__retres1~2#1 := 0; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 41: Hoare triple {11716#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11716#false} is VALID [2022-02-21 04:21:55,140 INFO L290 TraceCheckUtils]: 42: Hoare triple {11716#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 43: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp___1~0#1); {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 44: Hoare triple {11716#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 45: Hoare triple {11716#false} assume 1 == ~t3_pc~0; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 46: Hoare triple {11716#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 47: Hoare triple {11716#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 48: Hoare triple {11716#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 49: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp___2~0#1); {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 50: Hoare triple {11716#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11716#false} is VALID [2022-02-21 04:21:55,141 INFO L290 TraceCheckUtils]: 51: Hoare triple {11716#false} assume 1 == ~t4_pc~0; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 52: Hoare triple {11716#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 53: Hoare triple {11716#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 54: Hoare triple {11716#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 55: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp___3~0#1); {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 56: Hoare triple {11716#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 57: Hoare triple {11716#false} assume !(1 == ~t5_pc~0); {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 58: Hoare triple {11716#false} is_transmit5_triggered_~__retres1~5#1 := 0; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 59: Hoare triple {11716#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {11716#false} is VALID [2022-02-21 04:21:55,142 INFO L290 TraceCheckUtils]: 60: Hoare triple {11716#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 61: Hoare triple {11716#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 62: Hoare triple {11716#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 63: Hoare triple {11716#false} assume 1 == ~t6_pc~0; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 64: Hoare triple {11716#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 65: Hoare triple {11716#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 66: Hoare triple {11716#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 67: Hoare triple {11716#false} assume !(0 != activate_threads_~tmp___5~0#1); {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 68: Hoare triple {11716#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11716#false} is VALID [2022-02-21 04:21:55,143 INFO L290 TraceCheckUtils]: 69: Hoare triple {11716#false} assume !(1 == ~M_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 70: Hoare triple {11716#false} assume !(1 == ~T1_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 71: Hoare triple {11716#false} assume !(1 == ~T2_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 72: Hoare triple {11716#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 73: Hoare triple {11716#false} assume !(1 == ~T4_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 74: Hoare triple {11716#false} assume !(1 == ~T5_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 75: Hoare triple {11716#false} assume !(1 == ~T6_E~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 76: Hoare triple {11716#false} assume !(1 == ~E_M~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 77: Hoare triple {11716#false} assume !(1 == ~E_1~0); {11716#false} is VALID [2022-02-21 04:21:55,144 INFO L290 TraceCheckUtils]: 78: Hoare triple {11716#false} assume !(1 == ~E_2~0); {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L290 TraceCheckUtils]: 79: Hoare triple {11716#false} assume !(1 == ~E_3~0); {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L290 TraceCheckUtils]: 80: Hoare triple {11716#false} assume 1 == ~E_4~0;~E_4~0 := 2; {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L290 TraceCheckUtils]: 81: Hoare triple {11716#false} assume !(1 == ~E_5~0); {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L290 TraceCheckUtils]: 82: Hoare triple {11716#false} assume !(1 == ~E_6~0); {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L290 TraceCheckUtils]: 83: Hoare triple {11716#false} assume { :end_inline_reset_delta_events } true; {11716#false} is VALID [2022-02-21 04:21:55,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,145 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,146 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253662064] [2022-02-21 04:21:55,146 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253662064] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,146 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,146 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:55,146 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675260387] [2022-02-21 04:21:55,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,146 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:55,147 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,147 INFO L85 PathProgramCache]: Analyzing trace with hash -663295747, now seen corresponding path program 1 times [2022-02-21 04:21:55,147 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,147 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215104598] [2022-02-21 04:21:55,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 0: Hoare triple {11718#true} assume !false; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 1: Hoare triple {11718#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 2: Hoare triple {11718#true} assume !false; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 3: Hoare triple {11718#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 4: Hoare triple {11718#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 5: Hoare triple {11718#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {11718#true} is VALID [2022-02-21 04:21:55,176 INFO L290 TraceCheckUtils]: 6: Hoare triple {11718#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 7: Hoare triple {11718#true} assume !(0 != eval_~tmp~0#1); {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 8: Hoare triple {11718#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 9: Hoare triple {11718#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 10: Hoare triple {11718#true} assume 0 == ~M_E~0;~M_E~0 := 1; {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 11: Hoare triple {11718#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {11718#true} is VALID [2022-02-21 04:21:55,177 INFO L290 TraceCheckUtils]: 12: Hoare triple {11718#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,178 INFO L290 TraceCheckUtils]: 13: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,178 INFO L290 TraceCheckUtils]: 14: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,178 INFO L290 TraceCheckUtils]: 15: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,179 INFO L290 TraceCheckUtils]: 16: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,179 INFO L290 TraceCheckUtils]: 17: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,179 INFO L290 TraceCheckUtils]: 18: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,180 INFO L290 TraceCheckUtils]: 19: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,180 INFO L290 TraceCheckUtils]: 20: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,180 INFO L290 TraceCheckUtils]: 21: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,180 INFO L290 TraceCheckUtils]: 22: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,181 INFO L290 TraceCheckUtils]: 23: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,181 INFO L290 TraceCheckUtils]: 24: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,181 INFO L290 TraceCheckUtils]: 25: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,182 INFO L290 TraceCheckUtils]: 26: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,182 INFO L290 TraceCheckUtils]: 27: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,182 INFO L290 TraceCheckUtils]: 28: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,182 INFO L290 TraceCheckUtils]: 29: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,183 INFO L290 TraceCheckUtils]: 30: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,183 INFO L290 TraceCheckUtils]: 31: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,183 INFO L290 TraceCheckUtils]: 32: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,184 INFO L290 TraceCheckUtils]: 33: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,184 INFO L290 TraceCheckUtils]: 34: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,184 INFO L290 TraceCheckUtils]: 35: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,185 INFO L290 TraceCheckUtils]: 36: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,185 INFO L290 TraceCheckUtils]: 37: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,185 INFO L290 TraceCheckUtils]: 38: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,185 INFO L290 TraceCheckUtils]: 39: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,186 INFO L290 TraceCheckUtils]: 40: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,186 INFO L290 TraceCheckUtils]: 41: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,186 INFO L290 TraceCheckUtils]: 42: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,187 INFO L290 TraceCheckUtils]: 43: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,187 INFO L290 TraceCheckUtils]: 44: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,187 INFO L290 TraceCheckUtils]: 45: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,187 INFO L290 TraceCheckUtils]: 46: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,188 INFO L290 TraceCheckUtils]: 47: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,188 INFO L290 TraceCheckUtils]: 48: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,188 INFO L290 TraceCheckUtils]: 49: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,189 INFO L290 TraceCheckUtils]: 50: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,189 INFO L290 TraceCheckUtils]: 51: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,189 INFO L290 TraceCheckUtils]: 52: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,189 INFO L290 TraceCheckUtils]: 53: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,190 INFO L290 TraceCheckUtils]: 54: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,190 INFO L290 TraceCheckUtils]: 55: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,190 INFO L290 TraceCheckUtils]: 56: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,191 INFO L290 TraceCheckUtils]: 57: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,191 INFO L290 TraceCheckUtils]: 58: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,191 INFO L290 TraceCheckUtils]: 59: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,191 INFO L290 TraceCheckUtils]: 60: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,192 INFO L290 TraceCheckUtils]: 61: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,192 INFO L290 TraceCheckUtils]: 62: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,192 INFO L290 TraceCheckUtils]: 63: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,192 INFO L290 TraceCheckUtils]: 64: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,193 INFO L290 TraceCheckUtils]: 65: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,193 INFO L290 TraceCheckUtils]: 66: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,193 INFO L290 TraceCheckUtils]: 67: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 68: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {11720#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 69: Hoare triple {11720#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {11719#false} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 70: Hoare triple {11719#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 71: Hoare triple {11719#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 72: Hoare triple {11719#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 73: Hoare triple {11719#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,194 INFO L290 TraceCheckUtils]: 74: Hoare triple {11719#false} assume 1 == ~E_M~0;~E_M~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 75: Hoare triple {11719#false} assume 1 == ~E_1~0;~E_1~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 76: Hoare triple {11719#false} assume 1 == ~E_2~0;~E_2~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 77: Hoare triple {11719#false} assume !(1 == ~E_3~0); {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 78: Hoare triple {11719#false} assume 1 == ~E_4~0;~E_4~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 79: Hoare triple {11719#false} assume 1 == ~E_5~0;~E_5~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 80: Hoare triple {11719#false} assume 1 == ~E_6~0;~E_6~0 := 2; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 81: Hoare triple {11719#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 82: Hoare triple {11719#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {11719#false} is VALID [2022-02-21 04:21:55,195 INFO L290 TraceCheckUtils]: 83: Hoare triple {11719#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 84: Hoare triple {11719#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 85: Hoare triple {11719#false} assume !(0 == start_simulation_~tmp~3#1); {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 86: Hoare triple {11719#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 87: Hoare triple {11719#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 88: Hoare triple {11719#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 89: Hoare triple {11719#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 90: Hoare triple {11719#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 91: Hoare triple {11719#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {11719#false} is VALID [2022-02-21 04:21:55,196 INFO L290 TraceCheckUtils]: 92: Hoare triple {11719#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {11719#false} is VALID [2022-02-21 04:21:55,197 INFO L290 TraceCheckUtils]: 93: Hoare triple {11719#false} assume !(0 != start_simulation_~tmp___0~1#1); {11719#false} is VALID [2022-02-21 04:21:55,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,197 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,197 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215104598] [2022-02-21 04:21:55,197 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215104598] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,197 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,198 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:55,198 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974647887] [2022-02-21 04:21:55,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,198 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:55,198 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:55,199 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:55,199 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:55,199 INFO L87 Difference]: Start difference. First operand 686 states and 1025 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,686 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-02-21 04:21:55,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:55,686 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,736 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:55,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:55,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1024 transitions. [2022-02-21 04:21:55,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:55,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:55,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:55,767 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-02-21 04:21:55,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:55,772 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:55,773 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1024 transitions. Second operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,774 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1024 transitions. Second operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,775 INFO L87 Difference]: Start difference. First operand 686 states and 1024 transitions. Second operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,789 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-02-21 04:21:55,789 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,790 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,790 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,791 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1024 transitions. [2022-02-21 04:21:55,792 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1024 transitions. [2022-02-21 04:21:55,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,806 INFO L93 Difference]: Finished difference Result 686 states and 1024 transitions. [2022-02-21 04:21:55,806 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,807 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:55,807 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:55,807 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:55,807 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:55,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4927113702623906) internal successors, (1024), 685 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1024 transitions. [2022-02-21 04:21:55,821 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-02-21 04:21:55,821 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1024 transitions. [2022-02-21 04:21:55,821 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:55,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1024 transitions. [2022-02-21 04:21:55,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:55,824 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:55,824 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:55,825 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,825 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:55,825 INFO L791 eck$LassoCheckResult]: Stem: 13092#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 13070#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 13045#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12991#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12992#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 12656#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12657#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12504#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12505#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12473#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12474#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12634#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12794#L696 assume !(0 == ~M_E~0); 12795#L696-2 assume !(0 == ~T1_E~0); 13060#L701-1 assume !(0 == ~T2_E~0); 13062#L706-1 assume !(0 == ~T3_E~0); 12905#L711-1 assume !(0 == ~T4_E~0); 12690#L716-1 assume !(0 == ~T5_E~0); 12691#L721-1 assume !(0 == ~T6_E~0); 12861#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 12862#L731-1 assume !(0 == ~E_1~0); 12833#L736-1 assume !(0 == ~E_2~0); 12834#L741-1 assume !(0 == ~E_3~0); 12912#L746-1 assume !(0 == ~E_4~0); 12724#L751-1 assume !(0 == ~E_5~0); 12725#L756-1 assume !(0 == ~E_6~0); 12687#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12521#L346 assume !(1 == ~m_pc~0); 12522#L346-2 is_master_triggered_~__retres1~0#1 := 0; 12735#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12431#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12432#L861 assume !(0 != activate_threads_~tmp~1#1); 13032#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12553#L365 assume 1 == ~t1_pc~0; 12554#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12671#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13046#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12543#L869 assume !(0 != activate_threads_~tmp___0~0#1); 12544#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12959#L384 assume !(1 == ~t2_pc~0); 12951#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12952#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12630#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12455#L877 assume !(0 != activate_threads_~tmp___1~0#1); 12456#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12811#L403 assume 1 == ~t3_pc~0; 12692#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12693#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12681#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12682#L885 assume !(0 != activate_threads_~tmp___2~0#1); 12802#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12803#L422 assume 1 == ~t4_pc~0; 12452#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12453#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12955#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12956#L893 assume !(0 != activate_threads_~tmp___3~0#1); 12889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12475#L441 assume !(1 == ~t5_pc~0); 12476#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13029#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13072#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13073#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12898#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12899#L460 assume 1 == ~t6_pc~0; 12412#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12413#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12483#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13000#L909 assume !(0 != activate_threads_~tmp___5~0#1); 13001#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12871#L774 assume !(1 == ~M_E~0); 12872#L774-2 assume !(1 == ~T1_E~0); 13015#L779-1 assume !(1 == ~T2_E~0); 12776#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12777#L789-1 assume !(1 == ~T4_E~0); 12537#L794-1 assume !(1 == ~T5_E~0); 12538#L799-1 assume !(1 == ~T6_E~0); 13083#L804-1 assume !(1 == ~E_M~0); 13084#L809-1 assume !(1 == ~E_1~0); 12859#L814-1 assume !(1 == ~E_2~0); 12433#L819-1 assume !(1 == ~E_3~0); 12434#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12919#L829-1 assume !(1 == ~E_5~0); 13007#L834-1 assume !(1 == ~E_6~0); 12672#L839-1 assume { :end_inline_reset_delta_events } true; 12661#L1065-2 [2022-02-21 04:21:55,825 INFO L793 eck$LassoCheckResult]: Loop: 12661#L1065-2 assume !false; 12662#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12714#L671 assume !false; 13041#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12987#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12514#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12524#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12934#L582 assume !(0 != eval_~tmp~0#1); 13085#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12922#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12710#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12711#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12756#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12757#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13066#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13061#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12914#L721-3 assume !(0 == ~T6_E~0); 12739#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12740#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12909#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12910#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12685#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12686#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12807#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12563#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12564#L346-24 assume 1 == ~m_pc~0; 12594#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12678#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12911#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13047#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13013#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12627#L365-24 assume 1 == ~t1_pc~0; 12628#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12915#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12792#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12793#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12979#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12581#L384-24 assume !(1 == ~t2_pc~0); 12582#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 12599#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13050#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12900#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 12605#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12606#L403-24 assume 1 == ~t3_pc~0; 12727#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12758#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12759#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12857#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12858#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12658#L422-24 assume !(1 == ~t4_pc~0); 12659#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 12612#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12613#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13063#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13021#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12673#L441-24 assume 1 == ~t5_pc~0; 12674#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12878#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12879#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12545#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12546#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12960#L460-24 assume !(1 == ~t6_pc~0); 12961#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13016#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12989#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12990#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12949#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12950#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12897#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12738#L779-3 assume !(1 == ~T2_E~0); 12450#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12451#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12429#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12430#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12552#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12876#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12547#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12548#L819-3 assume !(1 == ~E_3~0); 12698#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12679#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12680#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12535#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12536#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12533#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12621#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 12468#L1084 assume !(0 == start_simulation_~tmp~3#1); 12470#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12720#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12436#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12575#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 12726#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12565#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12561#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12562#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 12661#L1065-2 [2022-02-21 04:21:55,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,826 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2022-02-21 04:21:55,826 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,826 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1689005255] [2022-02-21 04:21:55,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,843 INFO L290 TraceCheckUtils]: 0: Hoare triple {14468#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {14468#true} is VALID [2022-02-21 04:21:55,843 INFO L290 TraceCheckUtils]: 1: Hoare triple {14468#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,843 INFO L290 TraceCheckUtils]: 2: Hoare triple {14470#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,844 INFO L290 TraceCheckUtils]: 3: Hoare triple {14470#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,844 INFO L290 TraceCheckUtils]: 4: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,844 INFO L290 TraceCheckUtils]: 5: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,845 INFO L290 TraceCheckUtils]: 6: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,845 INFO L290 TraceCheckUtils]: 7: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,845 INFO L290 TraceCheckUtils]: 8: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,845 INFO L290 TraceCheckUtils]: 9: Hoare triple {14470#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {14470#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 10: Hoare triple {14470#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 11: Hoare triple {14469#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 12: Hoare triple {14469#false} assume !(0 == ~M_E~0); {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 13: Hoare triple {14469#false} assume !(0 == ~T1_E~0); {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 14: Hoare triple {14469#false} assume !(0 == ~T2_E~0); {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 15: Hoare triple {14469#false} assume !(0 == ~T3_E~0); {14469#false} is VALID [2022-02-21 04:21:55,846 INFO L290 TraceCheckUtils]: 16: Hoare triple {14469#false} assume !(0 == ~T4_E~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 17: Hoare triple {14469#false} assume !(0 == ~T5_E~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 18: Hoare triple {14469#false} assume !(0 == ~T6_E~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 19: Hoare triple {14469#false} assume 0 == ~E_M~0;~E_M~0 := 1; {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 20: Hoare triple {14469#false} assume !(0 == ~E_1~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 21: Hoare triple {14469#false} assume !(0 == ~E_2~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 22: Hoare triple {14469#false} assume !(0 == ~E_3~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 23: Hoare triple {14469#false} assume !(0 == ~E_4~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 24: Hoare triple {14469#false} assume !(0 == ~E_5~0); {14469#false} is VALID [2022-02-21 04:21:55,847 INFO L290 TraceCheckUtils]: 25: Hoare triple {14469#false} assume !(0 == ~E_6~0); {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 26: Hoare triple {14469#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 27: Hoare triple {14469#false} assume !(1 == ~m_pc~0); {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 28: Hoare triple {14469#false} is_master_triggered_~__retres1~0#1 := 0; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 29: Hoare triple {14469#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 30: Hoare triple {14469#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 31: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp~1#1); {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 32: Hoare triple {14469#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 33: Hoare triple {14469#false} assume 1 == ~t1_pc~0; {14469#false} is VALID [2022-02-21 04:21:55,848 INFO L290 TraceCheckUtils]: 34: Hoare triple {14469#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 35: Hoare triple {14469#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 36: Hoare triple {14469#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 37: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp___0~0#1); {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 38: Hoare triple {14469#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 39: Hoare triple {14469#false} assume !(1 == ~t2_pc~0); {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 40: Hoare triple {14469#false} is_transmit2_triggered_~__retres1~2#1 := 0; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 41: Hoare triple {14469#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 42: Hoare triple {14469#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 43: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp___1~0#1); {14469#false} is VALID [2022-02-21 04:21:55,849 INFO L290 TraceCheckUtils]: 44: Hoare triple {14469#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 45: Hoare triple {14469#false} assume 1 == ~t3_pc~0; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 46: Hoare triple {14469#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 47: Hoare triple {14469#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 48: Hoare triple {14469#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 49: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp___2~0#1); {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 50: Hoare triple {14469#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 51: Hoare triple {14469#false} assume 1 == ~t4_pc~0; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 52: Hoare triple {14469#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {14469#false} is VALID [2022-02-21 04:21:55,850 INFO L290 TraceCheckUtils]: 53: Hoare triple {14469#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 54: Hoare triple {14469#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 55: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp___3~0#1); {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 56: Hoare triple {14469#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 57: Hoare triple {14469#false} assume !(1 == ~t5_pc~0); {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 58: Hoare triple {14469#false} is_transmit5_triggered_~__retres1~5#1 := 0; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 59: Hoare triple {14469#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 60: Hoare triple {14469#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 61: Hoare triple {14469#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 62: Hoare triple {14469#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14469#false} is VALID [2022-02-21 04:21:55,851 INFO L290 TraceCheckUtils]: 63: Hoare triple {14469#false} assume 1 == ~t6_pc~0; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 64: Hoare triple {14469#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 65: Hoare triple {14469#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 66: Hoare triple {14469#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 67: Hoare triple {14469#false} assume !(0 != activate_threads_~tmp___5~0#1); {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 68: Hoare triple {14469#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 69: Hoare triple {14469#false} assume !(1 == ~M_E~0); {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 70: Hoare triple {14469#false} assume !(1 == ~T1_E~0); {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 71: Hoare triple {14469#false} assume !(1 == ~T2_E~0); {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 72: Hoare triple {14469#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14469#false} is VALID [2022-02-21 04:21:55,852 INFO L290 TraceCheckUtils]: 73: Hoare triple {14469#false} assume !(1 == ~T4_E~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 74: Hoare triple {14469#false} assume !(1 == ~T5_E~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 75: Hoare triple {14469#false} assume !(1 == ~T6_E~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 76: Hoare triple {14469#false} assume !(1 == ~E_M~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 77: Hoare triple {14469#false} assume !(1 == ~E_1~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 78: Hoare triple {14469#false} assume !(1 == ~E_2~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 79: Hoare triple {14469#false} assume !(1 == ~E_3~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 80: Hoare triple {14469#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 81: Hoare triple {14469#false} assume !(1 == ~E_5~0); {14469#false} is VALID [2022-02-21 04:21:55,853 INFO L290 TraceCheckUtils]: 82: Hoare triple {14469#false} assume !(1 == ~E_6~0); {14469#false} is VALID [2022-02-21 04:21:55,854 INFO L290 TraceCheckUtils]: 83: Hoare triple {14469#false} assume { :end_inline_reset_delta_events } true; {14469#false} is VALID [2022-02-21 04:21:55,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,854 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,854 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1689005255] [2022-02-21 04:21:55,854 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1689005255] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,854 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,854 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:55,855 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461009107] [2022-02-21 04:21:55,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,855 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:55,855 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,855 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 1 times [2022-02-21 04:21:55,856 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,856 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944809221] [2022-02-21 04:21:55,856 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 0: Hoare triple {14471#true} assume !false; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 1: Hoare triple {14471#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 2: Hoare triple {14471#true} assume !false; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 3: Hoare triple {14471#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 4: Hoare triple {14471#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 5: Hoare triple {14471#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 6: Hoare triple {14471#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {14471#true} is VALID [2022-02-21 04:21:55,878 INFO L290 TraceCheckUtils]: 7: Hoare triple {14471#true} assume !(0 != eval_~tmp~0#1); {14471#true} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 8: Hoare triple {14471#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14471#true} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 9: Hoare triple {14471#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14471#true} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 10: Hoare triple {14471#true} assume 0 == ~M_E~0;~M_E~0 := 1; {14471#true} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 11: Hoare triple {14471#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {14471#true} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 12: Hoare triple {14471#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,879 INFO L290 TraceCheckUtils]: 13: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,880 INFO L290 TraceCheckUtils]: 14: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,880 INFO L290 TraceCheckUtils]: 15: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,880 INFO L290 TraceCheckUtils]: 16: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,880 INFO L290 TraceCheckUtils]: 17: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,881 INFO L290 TraceCheckUtils]: 18: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,881 INFO L290 TraceCheckUtils]: 19: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,881 INFO L290 TraceCheckUtils]: 20: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,882 INFO L290 TraceCheckUtils]: 21: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,882 INFO L290 TraceCheckUtils]: 22: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,882 INFO L290 TraceCheckUtils]: 23: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,882 INFO L290 TraceCheckUtils]: 24: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,883 INFO L290 TraceCheckUtils]: 25: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,883 INFO L290 TraceCheckUtils]: 26: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,883 INFO L290 TraceCheckUtils]: 27: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,883 INFO L290 TraceCheckUtils]: 28: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,884 INFO L290 TraceCheckUtils]: 29: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,884 INFO L290 TraceCheckUtils]: 30: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,884 INFO L290 TraceCheckUtils]: 31: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,884 INFO L290 TraceCheckUtils]: 32: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,885 INFO L290 TraceCheckUtils]: 33: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,885 INFO L290 TraceCheckUtils]: 34: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,885 INFO L290 TraceCheckUtils]: 35: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,885 INFO L290 TraceCheckUtils]: 36: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,886 INFO L290 TraceCheckUtils]: 37: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,886 INFO L290 TraceCheckUtils]: 38: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,886 INFO L290 TraceCheckUtils]: 39: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,886 INFO L290 TraceCheckUtils]: 40: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,887 INFO L290 TraceCheckUtils]: 41: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,887 INFO L290 TraceCheckUtils]: 42: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,887 INFO L290 TraceCheckUtils]: 43: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,888 INFO L290 TraceCheckUtils]: 44: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,888 INFO L290 TraceCheckUtils]: 45: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,888 INFO L290 TraceCheckUtils]: 46: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,888 INFO L290 TraceCheckUtils]: 47: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,889 INFO L290 TraceCheckUtils]: 48: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,889 INFO L290 TraceCheckUtils]: 49: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,889 INFO L290 TraceCheckUtils]: 50: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,889 INFO L290 TraceCheckUtils]: 51: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,890 INFO L290 TraceCheckUtils]: 52: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,890 INFO L290 TraceCheckUtils]: 53: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,890 INFO L290 TraceCheckUtils]: 54: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,890 INFO L290 TraceCheckUtils]: 55: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,891 INFO L290 TraceCheckUtils]: 56: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,891 INFO L290 TraceCheckUtils]: 57: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,891 INFO L290 TraceCheckUtils]: 58: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,891 INFO L290 TraceCheckUtils]: 59: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,892 INFO L290 TraceCheckUtils]: 60: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,892 INFO L290 TraceCheckUtils]: 61: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,892 INFO L290 TraceCheckUtils]: 62: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,892 INFO L290 TraceCheckUtils]: 63: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,893 INFO L290 TraceCheckUtils]: 64: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,893 INFO L290 TraceCheckUtils]: 65: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,893 INFO L290 TraceCheckUtils]: 66: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 67: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 68: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {14473#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 69: Hoare triple {14473#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {14472#false} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 70: Hoare triple {14472#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 71: Hoare triple {14472#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,894 INFO L290 TraceCheckUtils]: 72: Hoare triple {14472#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 73: Hoare triple {14472#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 74: Hoare triple {14472#false} assume 1 == ~E_M~0;~E_M~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 75: Hoare triple {14472#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 76: Hoare triple {14472#false} assume 1 == ~E_2~0;~E_2~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 77: Hoare triple {14472#false} assume !(1 == ~E_3~0); {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 78: Hoare triple {14472#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 79: Hoare triple {14472#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 80: Hoare triple {14472#false} assume 1 == ~E_6~0;~E_6~0 := 2; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 81: Hoare triple {14472#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {14472#false} is VALID [2022-02-21 04:21:55,895 INFO L290 TraceCheckUtils]: 82: Hoare triple {14472#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 83: Hoare triple {14472#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 84: Hoare triple {14472#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 85: Hoare triple {14472#false} assume !(0 == start_simulation_~tmp~3#1); {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 86: Hoare triple {14472#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 87: Hoare triple {14472#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 88: Hoare triple {14472#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 89: Hoare triple {14472#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 90: Hoare triple {14472#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14472#false} is VALID [2022-02-21 04:21:55,896 INFO L290 TraceCheckUtils]: 91: Hoare triple {14472#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14472#false} is VALID [2022-02-21 04:21:55,897 INFO L290 TraceCheckUtils]: 92: Hoare triple {14472#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {14472#false} is VALID [2022-02-21 04:21:55,897 INFO L290 TraceCheckUtils]: 93: Hoare triple {14472#false} assume !(0 != start_simulation_~tmp___0~1#1); {14472#false} is VALID [2022-02-21 04:21:55,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,897 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,897 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944809221] [2022-02-21 04:21:55,898 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944809221] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,898 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,898 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:55,898 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671150905] [2022-02-21 04:21:55,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,898 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:55,899 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:55,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:55,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:55,899 INFO L87 Difference]: Start difference. First operand 686 states and 1024 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,358 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2022-02-21 04:21:56,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:56,359 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,402 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:56,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:56,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 686 states to 686 states and 1023 transitions. [2022-02-21 04:21:56,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 686 [2022-02-21 04:21:56,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 686 [2022-02-21 04:21:56,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:56,435 INFO L681 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-02-21 04:21:56,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 686 to 686. [2022-02-21 04:21:56,441 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:56,442 INFO L82 GeneralOperation]: Start isEquivalent. First operand 686 states and 1023 transitions. Second operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,443 INFO L74 IsIncluded]: Start isIncluded. First operand 686 states and 1023 transitions. Second operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,444 INFO L87 Difference]: Start difference. First operand 686 states and 1023 transitions. Second operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,457 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2022-02-21 04:21:56,457 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,458 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,458 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,460 INFO L74 IsIncluded]: Start isIncluded. First operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1023 transitions. [2022-02-21 04:21:56,461 INFO L87 Difference]: Start difference. First operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 686 states and 1023 transitions. [2022-02-21 04:21:56,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,475 INFO L93 Difference]: Finished difference Result 686 states and 1023 transitions. [2022-02-21 04:21:56,475 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,475 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,475 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,475 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:56,476 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:56,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 686 states, 686 states have (on average 1.4912536443148687) internal successors, (1023), 685 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 1023 transitions. [2022-02-21 04:21:56,490 INFO L704 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-02-21 04:21:56,490 INFO L587 BuchiCegarLoop]: Abstraction has 686 states and 1023 transitions. [2022-02-21 04:21:56,490 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:21:56,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 686 states and 1023 transitions. [2022-02-21 04:21:56,493 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 595 [2022-02-21 04:21:56,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,494 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,494 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,494 INFO L791 eck$LassoCheckResult]: Stem: 15845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15823#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15798#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15744#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15745#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 15409#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15410#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15257#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15258#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15226#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15227#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15387#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15547#L696 assume !(0 == ~M_E~0); 15548#L696-2 assume !(0 == ~T1_E~0); 15813#L701-1 assume !(0 == ~T2_E~0); 15815#L706-1 assume !(0 == ~T3_E~0); 15658#L711-1 assume !(0 == ~T4_E~0); 15443#L716-1 assume !(0 == ~T5_E~0); 15444#L721-1 assume !(0 == ~T6_E~0); 15614#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 15615#L731-1 assume !(0 == ~E_1~0); 15586#L736-1 assume !(0 == ~E_2~0); 15587#L741-1 assume !(0 == ~E_3~0); 15665#L746-1 assume !(0 == ~E_4~0); 15477#L751-1 assume !(0 == ~E_5~0); 15478#L756-1 assume !(0 == ~E_6~0); 15440#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15274#L346 assume !(1 == ~m_pc~0); 15275#L346-2 is_master_triggered_~__retres1~0#1 := 0; 15488#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15182#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15183#L861 assume !(0 != activate_threads_~tmp~1#1); 15785#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15305#L365 assume 1 == ~t1_pc~0; 15306#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15424#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15799#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15296#L869 assume !(0 != activate_threads_~tmp___0~0#1); 15297#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15712#L384 assume !(1 == ~t2_pc~0); 15702#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15703#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15383#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15208#L877 assume !(0 != activate_threads_~tmp___1~0#1); 15209#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15564#L403 assume 1 == ~t3_pc~0; 15445#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15446#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15432#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15433#L885 assume !(0 != activate_threads_~tmp___2~0#1); 15555#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15556#L422 assume 1 == ~t4_pc~0; 15203#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15204#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15708#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15709#L893 assume !(0 != activate_threads_~tmp___3~0#1); 15642#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15228#L441 assume !(1 == ~t5_pc~0); 15229#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15782#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15825#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15826#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15650#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15651#L460 assume 1 == ~t6_pc~0; 15165#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15166#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15236#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15753#L909 assume !(0 != activate_threads_~tmp___5~0#1); 15754#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15624#L774 assume !(1 == ~M_E~0); 15625#L774-2 assume !(1 == ~T1_E~0); 15768#L779-1 assume !(1 == ~T2_E~0); 15529#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15530#L789-1 assume !(1 == ~T4_E~0); 15290#L794-1 assume !(1 == ~T5_E~0); 15291#L799-1 assume !(1 == ~T6_E~0); 15836#L804-1 assume !(1 == ~E_M~0); 15837#L809-1 assume !(1 == ~E_1~0); 15612#L814-1 assume !(1 == ~E_2~0); 15184#L819-1 assume !(1 == ~E_3~0); 15185#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15672#L829-1 assume !(1 == ~E_5~0); 15760#L834-1 assume !(1 == ~E_6~0); 15425#L839-1 assume { :end_inline_reset_delta_events } true; 15414#L1065-2 [2022-02-21 04:21:56,494 INFO L793 eck$LassoCheckResult]: Loop: 15414#L1065-2 assume !false; 15415#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15467#L671 assume !false; 15794#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15740#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15267#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15277#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15687#L582 assume !(0 != eval_~tmp~0#1); 15838#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15675#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15463#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15464#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15509#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15510#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15819#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15814#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15667#L721-3 assume !(0 == ~T6_E~0); 15492#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15493#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15662#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15663#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15438#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15439#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15560#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15316#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15317#L346-24 assume 1 == ~m_pc~0; 15347#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15431#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15664#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15800#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15766#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15378#L365-24 assume 1 == ~t1_pc~0; 15379#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15668#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15545#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15546#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15732#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15332#L384-24 assume !(1 == ~t2_pc~0); 15333#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 15352#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15803#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15653#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 15358#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15359#L403-24 assume 1 == ~t3_pc~0; 15480#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15511#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15512#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15610#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15611#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15411#L422-24 assume !(1 == ~t4_pc~0); 15412#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 15365#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15366#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15816#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15774#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15426#L441-24 assume 1 == ~t5_pc~0; 15427#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15631#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15632#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15298#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15299#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15713#L460-24 assume !(1 == ~t6_pc~0); 15714#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 15769#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15742#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15743#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15704#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15705#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15652#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15491#L779-3 assume !(1 == ~T2_E~0); 15206#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15207#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15186#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15187#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15308#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15629#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15303#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15304#L819-3 assume !(1 == ~E_3~0); 15453#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15436#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15437#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15288#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15289#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15286#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15374#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15223#L1084 assume !(0 == start_simulation_~tmp~3#1); 15225#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15473#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15189#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15328#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 15479#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15322#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15314#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15315#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 15414#L1065-2 [2022-02-21 04:21:56,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,495 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2022-02-21 04:21:56,495 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,495 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545225425] [2022-02-21 04:21:56,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,535 INFO L290 TraceCheckUtils]: 0: Hoare triple {17221#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,535 INFO L290 TraceCheckUtils]: 1: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,536 INFO L290 TraceCheckUtils]: 2: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,536 INFO L290 TraceCheckUtils]: 3: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,536 INFO L290 TraceCheckUtils]: 4: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,536 INFO L290 TraceCheckUtils]: 5: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,537 INFO L290 TraceCheckUtils]: 6: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,537 INFO L290 TraceCheckUtils]: 7: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,537 INFO L290 TraceCheckUtils]: 8: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,537 INFO L290 TraceCheckUtils]: 9: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,538 INFO L290 TraceCheckUtils]: 10: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,538 INFO L290 TraceCheckUtils]: 11: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17223#(= ~E_M~0 ~M_E~0)} is VALID [2022-02-21 04:21:56,538 INFO L290 TraceCheckUtils]: 12: Hoare triple {17223#(= ~E_M~0 ~M_E~0)} assume !(0 == ~M_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,539 INFO L290 TraceCheckUtils]: 13: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T1_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,539 INFO L290 TraceCheckUtils]: 14: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T2_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,539 INFO L290 TraceCheckUtils]: 15: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T3_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,539 INFO L290 TraceCheckUtils]: 16: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T4_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 17: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T5_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 18: Hoare triple {17224#(not (= ~E_M~0 0))} assume !(0 == ~T6_E~0); {17224#(not (= ~E_M~0 0))} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 19: Hoare triple {17224#(not (= ~E_M~0 0))} assume 0 == ~E_M~0;~E_M~0 := 1; {17222#false} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 20: Hoare triple {17222#false} assume !(0 == ~E_1~0); {17222#false} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 21: Hoare triple {17222#false} assume !(0 == ~E_2~0); {17222#false} is VALID [2022-02-21 04:21:56,540 INFO L290 TraceCheckUtils]: 22: Hoare triple {17222#false} assume !(0 == ~E_3~0); {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 23: Hoare triple {17222#false} assume !(0 == ~E_4~0); {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 24: Hoare triple {17222#false} assume !(0 == ~E_5~0); {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 25: Hoare triple {17222#false} assume !(0 == ~E_6~0); {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 26: Hoare triple {17222#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 27: Hoare triple {17222#false} assume !(1 == ~m_pc~0); {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 28: Hoare triple {17222#false} is_master_triggered_~__retres1~0#1 := 0; {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 29: Hoare triple {17222#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 30: Hoare triple {17222#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17222#false} is VALID [2022-02-21 04:21:56,541 INFO L290 TraceCheckUtils]: 31: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp~1#1); {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 32: Hoare triple {17222#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 33: Hoare triple {17222#false} assume 1 == ~t1_pc~0; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 34: Hoare triple {17222#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 35: Hoare triple {17222#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 36: Hoare triple {17222#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 37: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp___0~0#1); {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 38: Hoare triple {17222#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 39: Hoare triple {17222#false} assume !(1 == ~t2_pc~0); {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 40: Hoare triple {17222#false} is_transmit2_triggered_~__retres1~2#1 := 0; {17222#false} is VALID [2022-02-21 04:21:56,542 INFO L290 TraceCheckUtils]: 41: Hoare triple {17222#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 42: Hoare triple {17222#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 43: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp___1~0#1); {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 44: Hoare triple {17222#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 45: Hoare triple {17222#false} assume 1 == ~t3_pc~0; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 46: Hoare triple {17222#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 47: Hoare triple {17222#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 48: Hoare triple {17222#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 49: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp___2~0#1); {17222#false} is VALID [2022-02-21 04:21:56,543 INFO L290 TraceCheckUtils]: 50: Hoare triple {17222#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 51: Hoare triple {17222#false} assume 1 == ~t4_pc~0; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 52: Hoare triple {17222#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 53: Hoare triple {17222#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 54: Hoare triple {17222#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 55: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp___3~0#1); {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 56: Hoare triple {17222#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 57: Hoare triple {17222#false} assume !(1 == ~t5_pc~0); {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 58: Hoare triple {17222#false} is_transmit5_triggered_~__retres1~5#1 := 0; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 59: Hoare triple {17222#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17222#false} is VALID [2022-02-21 04:21:56,544 INFO L290 TraceCheckUtils]: 60: Hoare triple {17222#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 61: Hoare triple {17222#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 62: Hoare triple {17222#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 63: Hoare triple {17222#false} assume 1 == ~t6_pc~0; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 64: Hoare triple {17222#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 65: Hoare triple {17222#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 66: Hoare triple {17222#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 67: Hoare triple {17222#false} assume !(0 != activate_threads_~tmp___5~0#1); {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 68: Hoare triple {17222#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17222#false} is VALID [2022-02-21 04:21:56,545 INFO L290 TraceCheckUtils]: 69: Hoare triple {17222#false} assume !(1 == ~M_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 70: Hoare triple {17222#false} assume !(1 == ~T1_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 71: Hoare triple {17222#false} assume !(1 == ~T2_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 72: Hoare triple {17222#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 73: Hoare triple {17222#false} assume !(1 == ~T4_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 74: Hoare triple {17222#false} assume !(1 == ~T5_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 75: Hoare triple {17222#false} assume !(1 == ~T6_E~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 76: Hoare triple {17222#false} assume !(1 == ~E_M~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 77: Hoare triple {17222#false} assume !(1 == ~E_1~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 78: Hoare triple {17222#false} assume !(1 == ~E_2~0); {17222#false} is VALID [2022-02-21 04:21:56,546 INFO L290 TraceCheckUtils]: 79: Hoare triple {17222#false} assume !(1 == ~E_3~0); {17222#false} is VALID [2022-02-21 04:21:56,547 INFO L290 TraceCheckUtils]: 80: Hoare triple {17222#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17222#false} is VALID [2022-02-21 04:21:56,547 INFO L290 TraceCheckUtils]: 81: Hoare triple {17222#false} assume !(1 == ~E_5~0); {17222#false} is VALID [2022-02-21 04:21:56,547 INFO L290 TraceCheckUtils]: 82: Hoare triple {17222#false} assume !(1 == ~E_6~0); {17222#false} is VALID [2022-02-21 04:21:56,547 INFO L290 TraceCheckUtils]: 83: Hoare triple {17222#false} assume { :end_inline_reset_delta_events } true; {17222#false} is VALID [2022-02-21 04:21:56,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,547 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,547 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545225425] [2022-02-21 04:21:56,548 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545225425] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,548 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,548 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,548 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046007163] [2022-02-21 04:21:56,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,548 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:56,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,549 INFO L85 PathProgramCache]: Analyzing trace with hash 293632636, now seen corresponding path program 2 times [2022-02-21 04:21:56,549 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,549 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776519225] [2022-02-21 04:21:56,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,569 INFO L290 TraceCheckUtils]: 0: Hoare triple {17225#true} assume !false; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 1: Hoare triple {17225#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 2: Hoare triple {17225#true} assume !false; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 3: Hoare triple {17225#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 4: Hoare triple {17225#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 5: Hoare triple {17225#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 6: Hoare triple {17225#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 7: Hoare triple {17225#true} assume !(0 != eval_~tmp~0#1); {17225#true} is VALID [2022-02-21 04:21:56,570 INFO L290 TraceCheckUtils]: 8: Hoare triple {17225#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17225#true} is VALID [2022-02-21 04:21:56,571 INFO L290 TraceCheckUtils]: 9: Hoare triple {17225#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17225#true} is VALID [2022-02-21 04:21:56,571 INFO L290 TraceCheckUtils]: 10: Hoare triple {17225#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17225#true} is VALID [2022-02-21 04:21:56,571 INFO L290 TraceCheckUtils]: 11: Hoare triple {17225#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {17225#true} is VALID [2022-02-21 04:21:56,571 INFO L290 TraceCheckUtils]: 12: Hoare triple {17225#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,571 INFO L290 TraceCheckUtils]: 13: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,572 INFO L290 TraceCheckUtils]: 14: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,572 INFO L290 TraceCheckUtils]: 15: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,572 INFO L290 TraceCheckUtils]: 17: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,573 INFO L290 TraceCheckUtils]: 18: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,573 INFO L290 TraceCheckUtils]: 19: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,573 INFO L290 TraceCheckUtils]: 20: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,573 INFO L290 TraceCheckUtils]: 21: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,574 INFO L290 TraceCheckUtils]: 22: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,574 INFO L290 TraceCheckUtils]: 23: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,574 INFO L290 TraceCheckUtils]: 24: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,575 INFO L290 TraceCheckUtils]: 25: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,575 INFO L290 TraceCheckUtils]: 26: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,575 INFO L290 TraceCheckUtils]: 27: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,575 INFO L290 TraceCheckUtils]: 28: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,576 INFO L290 TraceCheckUtils]: 29: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,576 INFO L290 TraceCheckUtils]: 30: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,576 INFO L290 TraceCheckUtils]: 31: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,576 INFO L290 TraceCheckUtils]: 32: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,577 INFO L290 TraceCheckUtils]: 33: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,577 INFO L290 TraceCheckUtils]: 34: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,577 INFO L290 TraceCheckUtils]: 35: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,577 INFO L290 TraceCheckUtils]: 36: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,578 INFO L290 TraceCheckUtils]: 37: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,578 INFO L290 TraceCheckUtils]: 38: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,578 INFO L290 TraceCheckUtils]: 39: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,579 INFO L290 TraceCheckUtils]: 40: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,579 INFO L290 TraceCheckUtils]: 41: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,579 INFO L290 TraceCheckUtils]: 42: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,579 INFO L290 TraceCheckUtils]: 43: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,580 INFO L290 TraceCheckUtils]: 44: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,580 INFO L290 TraceCheckUtils]: 45: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,580 INFO L290 TraceCheckUtils]: 46: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,580 INFO L290 TraceCheckUtils]: 47: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,581 INFO L290 TraceCheckUtils]: 48: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,581 INFO L290 TraceCheckUtils]: 49: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,581 INFO L290 TraceCheckUtils]: 50: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,581 INFO L290 TraceCheckUtils]: 51: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,582 INFO L290 TraceCheckUtils]: 52: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,582 INFO L290 TraceCheckUtils]: 53: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,582 INFO L290 TraceCheckUtils]: 54: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,583 INFO L290 TraceCheckUtils]: 55: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,583 INFO L290 TraceCheckUtils]: 56: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,583 INFO L290 TraceCheckUtils]: 57: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,583 INFO L290 TraceCheckUtils]: 58: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,584 INFO L290 TraceCheckUtils]: 59: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,584 INFO L290 TraceCheckUtils]: 60: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,584 INFO L290 TraceCheckUtils]: 61: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,584 INFO L290 TraceCheckUtils]: 62: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,585 INFO L290 TraceCheckUtils]: 63: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,585 INFO L290 TraceCheckUtils]: 64: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,585 INFO L290 TraceCheckUtils]: 65: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,585 INFO L290 TraceCheckUtils]: 66: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,586 INFO L290 TraceCheckUtils]: 67: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,586 INFO L290 TraceCheckUtils]: 68: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17227#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,586 INFO L290 TraceCheckUtils]: 69: Hoare triple {17227#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {17226#false} is VALID [2022-02-21 04:21:56,586 INFO L290 TraceCheckUtils]: 70: Hoare triple {17226#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 71: Hoare triple {17226#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 72: Hoare triple {17226#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 73: Hoare triple {17226#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 74: Hoare triple {17226#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 75: Hoare triple {17226#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 76: Hoare triple {17226#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 77: Hoare triple {17226#false} assume !(1 == ~E_3~0); {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 78: Hoare triple {17226#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,587 INFO L290 TraceCheckUtils]: 79: Hoare triple {17226#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 80: Hoare triple {17226#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 81: Hoare triple {17226#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 82: Hoare triple {17226#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 83: Hoare triple {17226#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 84: Hoare triple {17226#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 85: Hoare triple {17226#false} assume !(0 == start_simulation_~tmp~3#1); {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 86: Hoare triple {17226#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 87: Hoare triple {17226#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 88: Hoare triple {17226#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {17226#false} is VALID [2022-02-21 04:21:56,588 INFO L290 TraceCheckUtils]: 89: Hoare triple {17226#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {17226#false} is VALID [2022-02-21 04:21:56,589 INFO L290 TraceCheckUtils]: 90: Hoare triple {17226#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17226#false} is VALID [2022-02-21 04:21:56,589 INFO L290 TraceCheckUtils]: 91: Hoare triple {17226#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17226#false} is VALID [2022-02-21 04:21:56,589 INFO L290 TraceCheckUtils]: 92: Hoare triple {17226#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {17226#false} is VALID [2022-02-21 04:21:56,589 INFO L290 TraceCheckUtils]: 93: Hoare triple {17226#false} assume !(0 != start_simulation_~tmp___0~1#1); {17226#false} is VALID [2022-02-21 04:21:56,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,589 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,589 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776519225] [2022-02-21 04:21:56,590 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776519225] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,590 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,590 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,590 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690651773] [2022-02-21 04:21:56,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,590 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:56,590 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:56,591 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:56,591 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:56,592 INFO L87 Difference]: Start difference. First operand 686 states and 1023 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,794 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2022-02-21 04:21:57,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:57,795 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,837 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:57,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1180 states and 1756 transitions. [2022-02-21 04:21:57,874 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-02-21 04:21:57,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1180 states to 1180 states and 1756 transitions. [2022-02-21 04:21:57,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1180 [2022-02-21 04:21:57,909 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1180 [2022-02-21 04:21:57,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1180 states and 1756 transitions. [2022-02-21 04:21:57,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:57,911 INFO L681 BuchiCegarLoop]: Abstraction has 1180 states and 1756 transitions. [2022-02-21 04:21:57,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1180 states and 1756 transitions. [2022-02-21 04:21:57,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1180 to 1179. [2022-02-21 04:21:57,924 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:57,926 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1180 states and 1756 transitions. Second operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,927 INFO L74 IsIncluded]: Start isIncluded. First operand 1180 states and 1756 transitions. Second operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,928 INFO L87 Difference]: Start difference. First operand 1180 states and 1756 transitions. Second operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,963 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2022-02-21 04:21:57,963 INFO L276 IsEmpty]: Start isEmpty. Operand 1180 states and 1756 transitions. [2022-02-21 04:21:57,964 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:57,964 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:57,966 INFO L74 IsIncluded]: Start isIncluded. First operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1180 states and 1756 transitions. [2022-02-21 04:21:57,967 INFO L87 Difference]: Start difference. First operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1180 states and 1756 transitions. [2022-02-21 04:21:58,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,003 INFO L93 Difference]: Finished difference Result 1180 states and 1756 transitions. [2022-02-21 04:21:58,003 INFO L276 IsEmpty]: Start isEmpty. Operand 1180 states and 1756 transitions. [2022-02-21 04:21:58,004 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,005 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:58,005 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:58,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1179 states, 1179 states have (on average 1.4885496183206106) internal successors, (1755), 1178 states have internal predecessors, (1755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1179 states to 1179 states and 1755 transitions. [2022-02-21 04:21:58,039 INFO L704 BuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-02-21 04:21:58,039 INFO L587 BuchiCegarLoop]: Abstraction has 1179 states and 1755 transitions. [2022-02-21 04:21:58,039 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:21:58,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1179 states and 1755 transitions. [2022-02-21 04:21:58,043 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1074 [2022-02-21 04:21:58,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:58,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:58,044 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,044 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,045 INFO L791 eck$LassoCheckResult]: Stem: 19155#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 19117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 19088#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19022#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19023#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 18662#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18663#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18507#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18508#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18476#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18477#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18640#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18806#L696 assume !(0 == ~M_E~0); 18807#L696-2 assume !(0 == ~T1_E~0); 19106#L701-1 assume !(0 == ~T2_E~0); 19108#L706-1 assume !(0 == ~T3_E~0); 18921#L711-1 assume !(0 == ~T4_E~0); 18696#L716-1 assume !(0 == ~T5_E~0); 18697#L721-1 assume !(0 == ~T6_E~0); 18875#L726-1 assume !(0 == ~E_M~0); 18876#L731-1 assume !(0 == ~E_1~0); 18846#L736-1 assume !(0 == ~E_2~0); 18847#L741-1 assume !(0 == ~E_3~0); 18929#L746-1 assume !(0 == ~E_4~0); 18731#L751-1 assume !(0 == ~E_5~0); 18732#L756-1 assume !(0 == ~E_6~0); 18693#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18524#L346 assume !(1 == ~m_pc~0); 18525#L346-2 is_master_triggered_~__retres1~0#1 := 0; 18744#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18432#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18433#L861 assume !(0 != activate_threads_~tmp~1#1); 19069#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18556#L365 assume 1 == ~t1_pc~0; 18557#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18677#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19089#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18547#L869 assume !(0 != activate_threads_~tmp___0~0#1); 18548#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18984#L384 assume !(1 == ~t2_pc~0); 18973#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18974#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18636#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18458#L877 assume !(0 != activate_threads_~tmp___1~0#1); 18459#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18824#L403 assume 1 == ~t3_pc~0; 18698#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18699#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18685#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18686#L885 assume !(0 != activate_threads_~tmp___2~0#1); 18815#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18816#L422 assume 1 == ~t4_pc~0; 18453#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18454#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18980#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18981#L893 assume !(0 != activate_threads_~tmp___3~0#1); 18905#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18478#L441 assume !(1 == ~t5_pc~0); 18479#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19066#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19119#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19120#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18913#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18914#L460 assume 1 == ~t6_pc~0; 18415#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18416#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18486#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19031#L909 assume !(0 != activate_threads_~tmp___5~0#1); 19032#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18885#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 18886#L774-2 assume !(1 == ~T1_E~0); 19233#L779-1 assume !(1 == ~T2_E~0); 19232#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19225#L789-1 assume !(1 == ~T4_E~0); 18541#L794-1 assume !(1 == ~T5_E~0); 18542#L799-1 assume !(1 == ~T6_E~0); 19189#L804-1 assume !(1 == ~E_M~0); 19137#L809-1 assume !(1 == ~E_1~0); 19186#L814-1 assume !(1 == ~E_2~0); 19184#L819-1 assume !(1 == ~E_3~0); 19183#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 19182#L829-1 assume !(1 == ~E_5~0); 19038#L834-1 assume !(1 == ~E_6~0); 19039#L839-1 assume { :end_inline_reset_delta_events } true; 19175#L1065-2 [2022-02-21 04:21:58,045 INFO L793 eck$LassoCheckResult]: Loop: 19175#L1065-2 assume !false; 18954#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18721#L671 assume !false; 19121#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19122#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 18527#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 18528#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19157#L582 assume !(0 != eval_~tmp~0#1); 19159#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18940#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18941#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19160#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19318#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19317#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19316#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19315#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19314#L721-3 assume !(0 == ~T6_E~0); 19313#L726-3 assume !(0 == ~E_M~0); 19312#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19311#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19310#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19309#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19308#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19307#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19306#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19305#L346-24 assume 1 == ~m_pc~0; 19303#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19302#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19301#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19300#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19299#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19298#L365-24 assume !(1 == ~t1_pc~0); 19296#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 19295#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19294#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19293#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19292#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19291#L384-24 assume 1 == ~t2_pc~0; 19289#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19288#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19287#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19286#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 19285#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19284#L403-24 assume 1 == ~t3_pc~0; 19282#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19281#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19280#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19279#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19278#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19277#L422-24 assume 1 == ~t4_pc~0; 19275#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19274#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19273#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19272#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19271#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19270#L441-24 assume 1 == ~t5_pc~0; 19268#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19267#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19266#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19265#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19264#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19263#L460-24 assume !(1 == ~t6_pc~0); 19261#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 19260#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19259#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19258#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19257#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19256#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19146#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19255#L779-3 assume !(1 == ~T2_E~0); 19254#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19253#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19252#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19251#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19250#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18891#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19249#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19248#L819-3 assume !(1 == ~E_3~0); 19247#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19246#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19245#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19244#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19242#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19236#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19235#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 19234#L1084 assume !(0 == start_simulation_~tmp~3#1); 19061#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 18727#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 18439#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19006#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 19007#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18573#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18565#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 18566#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 19175#L1065-2 [2022-02-21 04:21:58,045 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2022-02-21 04:21:58,046 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,046 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059763649] [2022-02-21 04:21:58,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,090 INFO L290 TraceCheckUtils]: 0: Hoare triple {21952#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,090 INFO L290 TraceCheckUtils]: 1: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,091 INFO L290 TraceCheckUtils]: 2: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,091 INFO L290 TraceCheckUtils]: 3: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,091 INFO L290 TraceCheckUtils]: 4: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,091 INFO L290 TraceCheckUtils]: 5: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,092 INFO L290 TraceCheckUtils]: 6: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,092 INFO L290 TraceCheckUtils]: 7: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,092 INFO L290 TraceCheckUtils]: 8: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,093 INFO L290 TraceCheckUtils]: 9: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,093 INFO L290 TraceCheckUtils]: 10: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,093 INFO L290 TraceCheckUtils]: 11: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,094 INFO L290 TraceCheckUtils]: 12: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,094 INFO L290 TraceCheckUtils]: 13: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,094 INFO L290 TraceCheckUtils]: 14: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,094 INFO L290 TraceCheckUtils]: 15: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,095 INFO L290 TraceCheckUtils]: 16: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,095 INFO L290 TraceCheckUtils]: 17: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,095 INFO L290 TraceCheckUtils]: 18: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,096 INFO L290 TraceCheckUtils]: 19: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,096 INFO L290 TraceCheckUtils]: 20: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,096 INFO L290 TraceCheckUtils]: 21: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,096 INFO L290 TraceCheckUtils]: 22: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,097 INFO L290 TraceCheckUtils]: 23: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,097 INFO L290 TraceCheckUtils]: 24: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,097 INFO L290 TraceCheckUtils]: 25: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,098 INFO L290 TraceCheckUtils]: 26: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21954#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:21:58,098 INFO L290 TraceCheckUtils]: 27: Hoare triple {21954#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,098 INFO L290 TraceCheckUtils]: 28: Hoare triple {21955#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,098 INFO L290 TraceCheckUtils]: 29: Hoare triple {21955#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,099 INFO L290 TraceCheckUtils]: 30: Hoare triple {21955#(not (= ~t1_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,099 INFO L290 TraceCheckUtils]: 31: Hoare triple {21955#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,099 INFO L290 TraceCheckUtils]: 32: Hoare triple {21955#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21955#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:21:58,099 INFO L290 TraceCheckUtils]: 33: Hoare triple {21955#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 34: Hoare triple {21953#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 35: Hoare triple {21953#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 36: Hoare triple {21953#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 37: Hoare triple {21953#false} assume !(0 != activate_threads_~tmp___0~0#1); {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 38: Hoare triple {21953#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 39: Hoare triple {21953#false} assume !(1 == ~t2_pc~0); {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 40: Hoare triple {21953#false} is_transmit2_triggered_~__retres1~2#1 := 0; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 41: Hoare triple {21953#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21953#false} is VALID [2022-02-21 04:21:58,100 INFO L290 TraceCheckUtils]: 42: Hoare triple {21953#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 43: Hoare triple {21953#false} assume !(0 != activate_threads_~tmp___1~0#1); {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 44: Hoare triple {21953#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 45: Hoare triple {21953#false} assume 1 == ~t3_pc~0; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 46: Hoare triple {21953#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 47: Hoare triple {21953#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 48: Hoare triple {21953#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 49: Hoare triple {21953#false} assume !(0 != activate_threads_~tmp___2~0#1); {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 50: Hoare triple {21953#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 51: Hoare triple {21953#false} assume 1 == ~t4_pc~0; {21953#false} is VALID [2022-02-21 04:21:58,101 INFO L290 TraceCheckUtils]: 52: Hoare triple {21953#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 53: Hoare triple {21953#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 54: Hoare triple {21953#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 55: Hoare triple {21953#false} assume !(0 != activate_threads_~tmp___3~0#1); {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 56: Hoare triple {21953#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 57: Hoare triple {21953#false} assume !(1 == ~t5_pc~0); {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 58: Hoare triple {21953#false} is_transmit5_triggered_~__retres1~5#1 := 0; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 59: Hoare triple {21953#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 60: Hoare triple {21953#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 61: Hoare triple {21953#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {21953#false} is VALID [2022-02-21 04:21:58,102 INFO L290 TraceCheckUtils]: 62: Hoare triple {21953#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 63: Hoare triple {21953#false} assume 1 == ~t6_pc~0; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 64: Hoare triple {21953#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 65: Hoare triple {21953#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 66: Hoare triple {21953#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 67: Hoare triple {21953#false} assume !(0 != activate_threads_~tmp___5~0#1); {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 68: Hoare triple {21953#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 69: Hoare triple {21953#false} assume 1 == ~M_E~0;~M_E~0 := 2; {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 70: Hoare triple {21953#false} assume !(1 == ~T1_E~0); {21953#false} is VALID [2022-02-21 04:21:58,103 INFO L290 TraceCheckUtils]: 71: Hoare triple {21953#false} assume !(1 == ~T2_E~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 72: Hoare triple {21953#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 73: Hoare triple {21953#false} assume !(1 == ~T4_E~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 74: Hoare triple {21953#false} assume !(1 == ~T5_E~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 75: Hoare triple {21953#false} assume !(1 == ~T6_E~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 76: Hoare triple {21953#false} assume !(1 == ~E_M~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 77: Hoare triple {21953#false} assume !(1 == ~E_1~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 78: Hoare triple {21953#false} assume !(1 == ~E_2~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 79: Hoare triple {21953#false} assume !(1 == ~E_3~0); {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 80: Hoare triple {21953#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21953#false} is VALID [2022-02-21 04:21:58,104 INFO L290 TraceCheckUtils]: 81: Hoare triple {21953#false} assume !(1 == ~E_5~0); {21953#false} is VALID [2022-02-21 04:21:58,105 INFO L290 TraceCheckUtils]: 82: Hoare triple {21953#false} assume !(1 == ~E_6~0); {21953#false} is VALID [2022-02-21 04:21:58,105 INFO L290 TraceCheckUtils]: 83: Hoare triple {21953#false} assume { :end_inline_reset_delta_events } true; {21953#false} is VALID [2022-02-21 04:21:58,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,105 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,105 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059763649] [2022-02-21 04:21:58,105 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059763649] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,106 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,106 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,107 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923805855] [2022-02-21 04:21:58,107 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,107 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:58,107 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1530837245, now seen corresponding path program 1 times [2022-02-21 04:21:58,108 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,110 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892968112] [2022-02-21 04:21:58,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,132 INFO L290 TraceCheckUtils]: 0: Hoare triple {21956#true} assume !false; {21956#true} is VALID [2022-02-21 04:21:58,132 INFO L290 TraceCheckUtils]: 1: Hoare triple {21956#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {21956#true} is VALID [2022-02-21 04:21:58,132 INFO L290 TraceCheckUtils]: 2: Hoare triple {21956#true} assume !false; {21956#true} is VALID [2022-02-21 04:21:58,132 INFO L290 TraceCheckUtils]: 3: Hoare triple {21956#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 4: Hoare triple {21956#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 5: Hoare triple {21956#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 6: Hoare triple {21956#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 7: Hoare triple {21956#true} assume !(0 != eval_~tmp~0#1); {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 8: Hoare triple {21956#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 9: Hoare triple {21956#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 10: Hoare triple {21956#true} assume 0 == ~M_E~0;~M_E~0 := 1; {21956#true} is VALID [2022-02-21 04:21:58,133 INFO L290 TraceCheckUtils]: 11: Hoare triple {21956#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {21956#true} is VALID [2022-02-21 04:21:58,134 INFO L290 TraceCheckUtils]: 12: Hoare triple {21956#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,134 INFO L290 TraceCheckUtils]: 13: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,134 INFO L290 TraceCheckUtils]: 14: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,134 INFO L290 TraceCheckUtils]: 15: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,135 INFO L290 TraceCheckUtils]: 16: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,135 INFO L290 TraceCheckUtils]: 17: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_M~0); {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,135 INFO L290 TraceCheckUtils]: 18: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,135 INFO L290 TraceCheckUtils]: 19: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,136 INFO L290 TraceCheckUtils]: 20: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,136 INFO L290 TraceCheckUtils]: 21: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,136 INFO L290 TraceCheckUtils]: 22: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,137 INFO L290 TraceCheckUtils]: 23: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,137 INFO L290 TraceCheckUtils]: 24: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,137 INFO L290 TraceCheckUtils]: 25: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,137 INFO L290 TraceCheckUtils]: 26: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,138 INFO L290 TraceCheckUtils]: 27: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,138 INFO L290 TraceCheckUtils]: 28: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,138 INFO L290 TraceCheckUtils]: 29: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,138 INFO L290 TraceCheckUtils]: 30: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,139 INFO L290 TraceCheckUtils]: 31: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,139 INFO L290 TraceCheckUtils]: 32: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,139 INFO L290 TraceCheckUtils]: 33: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,139 INFO L290 TraceCheckUtils]: 34: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,140 INFO L290 TraceCheckUtils]: 35: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,140 INFO L290 TraceCheckUtils]: 36: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,140 INFO L290 TraceCheckUtils]: 37: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,141 INFO L290 TraceCheckUtils]: 38: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,141 INFO L290 TraceCheckUtils]: 39: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,141 INFO L290 TraceCheckUtils]: 40: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,141 INFO L290 TraceCheckUtils]: 41: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,142 INFO L290 TraceCheckUtils]: 42: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,142 INFO L290 TraceCheckUtils]: 43: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,142 INFO L290 TraceCheckUtils]: 44: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,142 INFO L290 TraceCheckUtils]: 45: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,143 INFO L290 TraceCheckUtils]: 46: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,143 INFO L290 TraceCheckUtils]: 47: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,143 INFO L290 TraceCheckUtils]: 48: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,143 INFO L290 TraceCheckUtils]: 49: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,144 INFO L290 TraceCheckUtils]: 50: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,144 INFO L290 TraceCheckUtils]: 51: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,144 INFO L290 TraceCheckUtils]: 52: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,145 INFO L290 TraceCheckUtils]: 53: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,145 INFO L290 TraceCheckUtils]: 54: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,145 INFO L290 TraceCheckUtils]: 55: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,145 INFO L290 TraceCheckUtils]: 56: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,146 INFO L290 TraceCheckUtils]: 57: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,146 INFO L290 TraceCheckUtils]: 58: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,146 INFO L290 TraceCheckUtils]: 59: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,146 INFO L290 TraceCheckUtils]: 60: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,147 INFO L290 TraceCheckUtils]: 61: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,147 INFO L290 TraceCheckUtils]: 62: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,147 INFO L290 TraceCheckUtils]: 63: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,147 INFO L290 TraceCheckUtils]: 64: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,148 INFO L290 TraceCheckUtils]: 65: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,148 INFO L290 TraceCheckUtils]: 66: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,148 INFO L290 TraceCheckUtils]: 67: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 68: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {21958#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 69: Hoare triple {21958#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 70: Hoare triple {21957#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 71: Hoare triple {21957#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 72: Hoare triple {21957#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 73: Hoare triple {21957#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 74: Hoare triple {21957#false} assume 1 == ~E_M~0;~E_M~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,149 INFO L290 TraceCheckUtils]: 75: Hoare triple {21957#false} assume 1 == ~E_1~0;~E_1~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 76: Hoare triple {21957#false} assume 1 == ~E_2~0;~E_2~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 77: Hoare triple {21957#false} assume !(1 == ~E_3~0); {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 78: Hoare triple {21957#false} assume 1 == ~E_4~0;~E_4~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 79: Hoare triple {21957#false} assume 1 == ~E_5~0;~E_5~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 80: Hoare triple {21957#false} assume 1 == ~E_6~0;~E_6~0 := 2; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 81: Hoare triple {21957#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 82: Hoare triple {21957#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 83: Hoare triple {21957#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 84: Hoare triple {21957#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {21957#false} is VALID [2022-02-21 04:21:58,150 INFO L290 TraceCheckUtils]: 85: Hoare triple {21957#false} assume !(0 == start_simulation_~tmp~3#1); {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 86: Hoare triple {21957#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 87: Hoare triple {21957#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 88: Hoare triple {21957#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 89: Hoare triple {21957#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 90: Hoare triple {21957#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 91: Hoare triple {21957#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 92: Hoare triple {21957#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {21957#false} is VALID [2022-02-21 04:21:58,151 INFO L290 TraceCheckUtils]: 93: Hoare triple {21957#false} assume !(0 != start_simulation_~tmp___0~1#1); {21957#false} is VALID [2022-02-21 04:21:58,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,152 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,153 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892968112] [2022-02-21 04:21:58,154 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892968112] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,155 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,155 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,155 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514186945] [2022-02-21 04:21:58,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,155 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:58,155 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:58,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:21:58,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:21:58,156 INFO L87 Difference]: Start difference. First operand 1179 states and 1755 transitions. cyclomatic complexity: 578 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,953 INFO L93 Difference]: Finished difference Result 3143 states and 4595 transitions. [2022-02-21 04:21:59,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:21:59,954 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,985 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:59,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,208 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2928 [2022-02-21 04:22:00,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3143 states to 3143 states and 4595 transitions. [2022-02-21 04:22:00,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3143 [2022-02-21 04:22:00,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3143 [2022-02-21 04:22:00,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:00,433 INFO L681 BuchiCegarLoop]: Abstraction has 3143 states and 4595 transitions. [2022-02-21 04:22:00,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3143 to 2955. [2022-02-21 04:22:00,461 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:00,464 INFO L82 GeneralOperation]: Start isEquivalent. First operand 3143 states and 4595 transitions. Second operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,468 INFO L74 IsIncluded]: Start isIncluded. First operand 3143 states and 4595 transitions. Second operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,471 INFO L87 Difference]: Start difference. First operand 3143 states and 4595 transitions. Second operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,693 INFO L93 Difference]: Finished difference Result 3143 states and 4595 transitions. [2022-02-21 04:22:00,693 INFO L276 IsEmpty]: Start isEmpty. Operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,697 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,697 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,700 INFO L74 IsIncluded]: Start isIncluded. First operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,702 INFO L87 Difference]: Start difference. First operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,923 INFO L93 Difference]: Finished difference Result 3143 states and 4595 transitions. [2022-02-21 04:22:00,923 INFO L276 IsEmpty]: Start isEmpty. Operand 3143 states and 4595 transitions. [2022-02-21 04:22:00,927 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,927 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,927 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:00,927 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:00,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2955 states, 2955 states have (on average 1.4683587140439933) internal successors, (4339), 2954 states have internal predecessors, (4339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2955 states to 2955 states and 4339 transitions. [2022-02-21 04:22:01,122 INFO L704 BuchiCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-02-21 04:22:01,122 INFO L587 BuchiCegarLoop]: Abstraction has 2955 states and 4339 transitions. [2022-02-21 04:22:01,122 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:22:01,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2955 states and 4339 transitions. [2022-02-21 04:22:01,129 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2842 [2022-02-21 04:22:01,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:01,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:01,130 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,130 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,131 INFO L791 eck$LassoCheckResult]: Stem: 25870#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 25817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 25777#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25709#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25710#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 25348#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25349#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25200#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25201#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25169#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25170#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25327#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25489#L696 assume !(0 == ~M_E~0); 25490#L696-2 assume !(0 == ~T1_E~0); 25799#L701-1 assume !(0 == ~T2_E~0); 25800#L706-1 assume !(0 == ~T3_E~0); 25609#L711-1 assume !(0 == ~T4_E~0); 25382#L716-1 assume !(0 == ~T5_E~0); 25383#L721-1 assume !(0 == ~T6_E~0); 25562#L726-1 assume !(0 == ~E_M~0); 25563#L731-1 assume !(0 == ~E_1~0); 25528#L736-1 assume !(0 == ~E_2~0); 25529#L741-1 assume !(0 == ~E_3~0); 25616#L746-1 assume !(0 == ~E_4~0); 25417#L751-1 assume !(0 == ~E_5~0); 25418#L756-1 assume !(0 == ~E_6~0); 25379#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25217#L346 assume !(1 == ~m_pc~0); 25218#L346-2 is_master_triggered_~__retres1~0#1 := 0; 25428#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25127#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25128#L861 assume !(0 != activate_threads_~tmp~1#1); 25759#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25249#L365 assume !(1 == ~t1_pc~0); 25250#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25776#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25779#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25239#L869 assume !(0 != activate_threads_~tmp___0~0#1); 25240#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25669#L384 assume !(1 == ~t2_pc~0); 25661#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25662#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25324#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25151#L877 assume !(0 != activate_threads_~tmp___1~0#1); 25152#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25506#L403 assume 1 == ~t3_pc~0; 25384#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25385#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25372#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25373#L885 assume !(0 != activate_threads_~tmp___2~0#1); 25497#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25498#L422 assume 1 == ~t4_pc~0; 25148#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25149#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25665#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25666#L893 assume !(0 != activate_threads_~tmp___3~0#1); 25592#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25171#L441 assume !(1 == ~t5_pc~0); 25172#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25755#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25819#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25820#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25601#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25602#L460 assume 1 == ~t6_pc~0; 25109#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25110#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25181#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25718#L909 assume !(0 != activate_threads_~tmp___5~0#1); 25719#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25572#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 25573#L774-2 assume !(1 == ~T1_E~0); 25734#L779-1 assume !(1 == ~T2_E~0); 25470#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25471#L789-1 assume !(1 == ~T4_E~0); 25232#L794-1 assume !(1 == ~T5_E~0); 25233#L799-1 assume !(1 == ~T6_E~0); 25867#L804-1 assume !(1 == ~E_M~0); 25840#L809-1 assume !(1 == ~E_1~0); 25560#L814-1 assume !(1 == ~E_2~0); 25129#L819-1 assume !(1 == ~E_3~0); 25130#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27026#L829-1 assume !(1 == ~E_5~0); 27009#L834-1 assume !(1 == ~E_6~0); 27000#L839-1 assume { :end_inline_reset_delta_events } true; 26993#L1065-2 [2022-02-21 04:22:01,131 INFO L793 eck$LassoCheckResult]: Loop: 26993#L1065-2 assume !false; 26986#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26983#L671 assume !false; 26982#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 26980#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 26974#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 26973#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26971#L582 assume !(0 != eval_~tmp~0#1); 26970#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26968#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26965#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26962#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26961#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26960#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26957#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26956#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26955#L721-3 assume !(0 == ~T6_E~0); 26954#L726-3 assume !(0 == ~E_M~0); 26953#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26952#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26951#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26950#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26949#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26947#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26945#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26943#L346-24 assume !(1 == ~m_pc~0); 26941#L346-26 is_master_triggered_~__retres1~0#1 := 0; 26939#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26936#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26934#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26932#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26930#L365-24 assume !(1 == ~t1_pc~0); 26928#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 26926#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26923#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26921#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26919#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26917#L384-24 assume 1 == ~t2_pc~0; 26914#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26912#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26909#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26907#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 26905#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26903#L403-24 assume 1 == ~t3_pc~0; 26885#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26883#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26880#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26878#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26876#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26864#L422-24 assume 1 == ~t4_pc~0; 26856#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26851#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26844#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26838#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26832#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26816#L441-24 assume 1 == ~t5_pc~0; 26809#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26804#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26802#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26799#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26797#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26793#L460-24 assume !(1 == ~t6_pc~0); 25735#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 25736#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25707#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25708#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25659#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25660#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25860#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27209#L779-3 assume !(1 == ~T2_E~0); 27206#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27204#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27202#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27200#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27198#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25578#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27194#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27192#L819-3 assume !(1 == ~E_3~0); 27190#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27188#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27186#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27184#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 27162#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 27155#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 27153#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 27151#L1084 assume !(0 == start_simulation_~tmp~3#1); 27148#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 27040#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 27036#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 27034#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 27031#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27029#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 27010#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 27001#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 26993#L1065-2 [2022-02-21 04:22:01,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2022-02-21 04:22:01,132 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,132 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535521234] [2022-02-21 04:22:01,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {34348#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,153 INFO L290 TraceCheckUtils]: 1: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,153 INFO L290 TraceCheckUtils]: 2: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,153 INFO L290 TraceCheckUtils]: 3: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,154 INFO L290 TraceCheckUtils]: 4: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,154 INFO L290 TraceCheckUtils]: 5: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,154 INFO L290 TraceCheckUtils]: 6: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,155 INFO L290 TraceCheckUtils]: 7: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,155 INFO L290 TraceCheckUtils]: 8: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,155 INFO L290 TraceCheckUtils]: 9: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,155 INFO L290 TraceCheckUtils]: 10: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,156 INFO L290 TraceCheckUtils]: 11: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,156 INFO L290 TraceCheckUtils]: 12: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,156 INFO L290 TraceCheckUtils]: 13: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,157 INFO L290 TraceCheckUtils]: 14: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,157 INFO L290 TraceCheckUtils]: 15: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,157 INFO L290 TraceCheckUtils]: 16: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,157 INFO L290 TraceCheckUtils]: 17: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,158 INFO L290 TraceCheckUtils]: 18: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,158 INFO L290 TraceCheckUtils]: 19: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,158 INFO L290 TraceCheckUtils]: 20: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,159 INFO L290 TraceCheckUtils]: 21: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,159 INFO L290 TraceCheckUtils]: 22: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,159 INFO L290 TraceCheckUtils]: 23: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,159 INFO L290 TraceCheckUtils]: 24: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,160 INFO L290 TraceCheckUtils]: 25: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,160 INFO L290 TraceCheckUtils]: 26: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34350#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:01,160 INFO L290 TraceCheckUtils]: 27: Hoare triple {34350#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,161 INFO L290 TraceCheckUtils]: 28: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,161 INFO L290 TraceCheckUtils]: 29: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,161 INFO L290 TraceCheckUtils]: 30: Hoare triple {34351#(not (= ~t3_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,161 INFO L290 TraceCheckUtils]: 31: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,162 INFO L290 TraceCheckUtils]: 32: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,162 INFO L290 TraceCheckUtils]: 33: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,162 INFO L290 TraceCheckUtils]: 34: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,162 INFO L290 TraceCheckUtils]: 35: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,163 INFO L290 TraceCheckUtils]: 36: Hoare triple {34351#(not (= ~t3_pc~0 1))} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,163 INFO L290 TraceCheckUtils]: 37: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,163 INFO L290 TraceCheckUtils]: 38: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,163 INFO L290 TraceCheckUtils]: 39: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,164 INFO L290 TraceCheckUtils]: 40: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,164 INFO L290 TraceCheckUtils]: 41: Hoare triple {34351#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,164 INFO L290 TraceCheckUtils]: 42: Hoare triple {34351#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,164 INFO L290 TraceCheckUtils]: 43: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 44: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34351#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 45: Hoare triple {34351#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 46: Hoare triple {34349#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 47: Hoare triple {34349#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 48: Hoare triple {34349#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 49: Hoare triple {34349#false} assume !(0 != activate_threads_~tmp___2~0#1); {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 50: Hoare triple {34349#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34349#false} is VALID [2022-02-21 04:22:01,165 INFO L290 TraceCheckUtils]: 51: Hoare triple {34349#false} assume 1 == ~t4_pc~0; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 52: Hoare triple {34349#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 53: Hoare triple {34349#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 54: Hoare triple {34349#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 55: Hoare triple {34349#false} assume !(0 != activate_threads_~tmp___3~0#1); {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 56: Hoare triple {34349#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 57: Hoare triple {34349#false} assume !(1 == ~t5_pc~0); {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 58: Hoare triple {34349#false} is_transmit5_triggered_~__retres1~5#1 := 0; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 59: Hoare triple {34349#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34349#false} is VALID [2022-02-21 04:22:01,166 INFO L290 TraceCheckUtils]: 60: Hoare triple {34349#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 61: Hoare triple {34349#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 62: Hoare triple {34349#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 63: Hoare triple {34349#false} assume 1 == ~t6_pc~0; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 64: Hoare triple {34349#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 65: Hoare triple {34349#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 66: Hoare triple {34349#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 67: Hoare triple {34349#false} assume !(0 != activate_threads_~tmp___5~0#1); {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 68: Hoare triple {34349#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 69: Hoare triple {34349#false} assume 1 == ~M_E~0;~M_E~0 := 2; {34349#false} is VALID [2022-02-21 04:22:01,167 INFO L290 TraceCheckUtils]: 70: Hoare triple {34349#false} assume !(1 == ~T1_E~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 71: Hoare triple {34349#false} assume !(1 == ~T2_E~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 72: Hoare triple {34349#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 73: Hoare triple {34349#false} assume !(1 == ~T4_E~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 74: Hoare triple {34349#false} assume !(1 == ~T5_E~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 75: Hoare triple {34349#false} assume !(1 == ~T6_E~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 76: Hoare triple {34349#false} assume !(1 == ~E_M~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 77: Hoare triple {34349#false} assume !(1 == ~E_1~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 78: Hoare triple {34349#false} assume !(1 == ~E_2~0); {34349#false} is VALID [2022-02-21 04:22:01,168 INFO L290 TraceCheckUtils]: 79: Hoare triple {34349#false} assume !(1 == ~E_3~0); {34349#false} is VALID [2022-02-21 04:22:01,169 INFO L290 TraceCheckUtils]: 80: Hoare triple {34349#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34349#false} is VALID [2022-02-21 04:22:01,169 INFO L290 TraceCheckUtils]: 81: Hoare triple {34349#false} assume !(1 == ~E_5~0); {34349#false} is VALID [2022-02-21 04:22:01,169 INFO L290 TraceCheckUtils]: 82: Hoare triple {34349#false} assume !(1 == ~E_6~0); {34349#false} is VALID [2022-02-21 04:22:01,169 INFO L290 TraceCheckUtils]: 83: Hoare triple {34349#false} assume { :end_inline_reset_delta_events } true; {34349#false} is VALID [2022-02-21 04:22:01,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,169 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,169 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535521234] [2022-02-21 04:22:01,169 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535521234] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,170 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,170 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,170 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618275223] [2022-02-21 04:22:01,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,170 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:01,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1626501186, now seen corresponding path program 1 times [2022-02-21 04:22:01,171 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,171 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853265461] [2022-02-21 04:22:01,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,190 INFO L290 TraceCheckUtils]: 0: Hoare triple {34352#true} assume !false; {34352#true} is VALID [2022-02-21 04:22:01,190 INFO L290 TraceCheckUtils]: 1: Hoare triple {34352#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 2: Hoare triple {34352#true} assume !false; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 3: Hoare triple {34352#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 4: Hoare triple {34352#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 5: Hoare triple {34352#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 6: Hoare triple {34352#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 7: Hoare triple {34352#true} assume !(0 != eval_~tmp~0#1); {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 8: Hoare triple {34352#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 9: Hoare triple {34352#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {34352#true} is VALID [2022-02-21 04:22:01,191 INFO L290 TraceCheckUtils]: 10: Hoare triple {34352#true} assume 0 == ~M_E~0;~M_E~0 := 1; {34352#true} is VALID [2022-02-21 04:22:01,192 INFO L290 TraceCheckUtils]: 11: Hoare triple {34352#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {34352#true} is VALID [2022-02-21 04:22:01,192 INFO L290 TraceCheckUtils]: 12: Hoare triple {34352#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,192 INFO L290 TraceCheckUtils]: 13: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,193 INFO L290 TraceCheckUtils]: 15: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,193 INFO L290 TraceCheckUtils]: 16: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,193 INFO L290 TraceCheckUtils]: 17: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_M~0); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,193 INFO L290 TraceCheckUtils]: 18: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,194 INFO L290 TraceCheckUtils]: 19: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,194 INFO L290 TraceCheckUtils]: 20: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,194 INFO L290 TraceCheckUtils]: 21: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,194 INFO L290 TraceCheckUtils]: 22: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,195 INFO L290 TraceCheckUtils]: 23: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,195 INFO L290 TraceCheckUtils]: 24: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,195 INFO L290 TraceCheckUtils]: 25: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,195 INFO L290 TraceCheckUtils]: 26: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,196 INFO L290 TraceCheckUtils]: 27: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,196 INFO L290 TraceCheckUtils]: 28: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,196 INFO L290 TraceCheckUtils]: 29: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,196 INFO L290 TraceCheckUtils]: 30: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,197 INFO L290 TraceCheckUtils]: 31: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,197 INFO L290 TraceCheckUtils]: 32: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,197 INFO L290 TraceCheckUtils]: 33: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,197 INFO L290 TraceCheckUtils]: 34: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,198 INFO L290 TraceCheckUtils]: 35: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,198 INFO L290 TraceCheckUtils]: 36: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,198 INFO L290 TraceCheckUtils]: 37: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,199 INFO L290 TraceCheckUtils]: 38: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,199 INFO L290 TraceCheckUtils]: 39: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,199 INFO L290 TraceCheckUtils]: 40: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,199 INFO L290 TraceCheckUtils]: 41: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,200 INFO L290 TraceCheckUtils]: 42: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,200 INFO L290 TraceCheckUtils]: 43: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,200 INFO L290 TraceCheckUtils]: 44: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,200 INFO L290 TraceCheckUtils]: 45: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,201 INFO L290 TraceCheckUtils]: 46: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,201 INFO L290 TraceCheckUtils]: 47: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,201 INFO L290 TraceCheckUtils]: 48: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,201 INFO L290 TraceCheckUtils]: 49: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,202 INFO L290 TraceCheckUtils]: 50: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,202 INFO L290 TraceCheckUtils]: 51: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,202 INFO L290 TraceCheckUtils]: 52: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,202 INFO L290 TraceCheckUtils]: 53: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,203 INFO L290 TraceCheckUtils]: 54: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,203 INFO L290 TraceCheckUtils]: 55: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,203 INFO L290 TraceCheckUtils]: 56: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,203 INFO L290 TraceCheckUtils]: 57: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,204 INFO L290 TraceCheckUtils]: 58: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,204 INFO L290 TraceCheckUtils]: 59: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,204 INFO L290 TraceCheckUtils]: 60: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,204 INFO L290 TraceCheckUtils]: 61: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,205 INFO L290 TraceCheckUtils]: 62: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,205 INFO L290 TraceCheckUtils]: 63: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,205 INFO L290 TraceCheckUtils]: 64: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,205 INFO L290 TraceCheckUtils]: 65: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,206 INFO L290 TraceCheckUtils]: 66: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,206 INFO L290 TraceCheckUtils]: 67: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,206 INFO L290 TraceCheckUtils]: 68: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {34354#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,206 INFO L290 TraceCheckUtils]: 69: Hoare triple {34354#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 70: Hoare triple {34353#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 71: Hoare triple {34353#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 72: Hoare triple {34353#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 73: Hoare triple {34353#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 74: Hoare triple {34353#false} assume 1 == ~E_M~0;~E_M~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 75: Hoare triple {34353#false} assume 1 == ~E_1~0;~E_1~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 76: Hoare triple {34353#false} assume 1 == ~E_2~0;~E_2~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 77: Hoare triple {34353#false} assume !(1 == ~E_3~0); {34353#false} is VALID [2022-02-21 04:22:01,207 INFO L290 TraceCheckUtils]: 78: Hoare triple {34353#false} assume 1 == ~E_4~0;~E_4~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 79: Hoare triple {34353#false} assume 1 == ~E_5~0;~E_5~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 80: Hoare triple {34353#false} assume 1 == ~E_6~0;~E_6~0 := 2; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 81: Hoare triple {34353#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 82: Hoare triple {34353#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 83: Hoare triple {34353#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 84: Hoare triple {34353#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 85: Hoare triple {34353#false} assume !(0 == start_simulation_~tmp~3#1); {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 86: Hoare triple {34353#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 87: Hoare triple {34353#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {34353#false} is VALID [2022-02-21 04:22:01,208 INFO L290 TraceCheckUtils]: 88: Hoare triple {34353#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L290 TraceCheckUtils]: 89: Hoare triple {34353#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L290 TraceCheckUtils]: 90: Hoare triple {34353#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L290 TraceCheckUtils]: 91: Hoare triple {34353#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L290 TraceCheckUtils]: 92: Hoare triple {34353#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L290 TraceCheckUtils]: 93: Hoare triple {34353#false} assume !(0 != start_simulation_~tmp___0~1#1); {34353#false} is VALID [2022-02-21 04:22:01,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,209 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,210 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1853265461] [2022-02-21 04:22:01,210 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1853265461] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,210 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,210 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,210 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130273034] [2022-02-21 04:22:01,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,210 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:01,210 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:01,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:01,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:01,212 INFO L87 Difference]: Start difference. First operand 2955 states and 4339 transitions. cyclomatic complexity: 1388 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,136 INFO L93 Difference]: Finished difference Result 8082 states and 11722 transitions. [2022-02-21 04:22:04,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:04,136 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,191 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:04,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8082 states and 11722 transitions. [2022-02-21 04:22:05,800 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7720 [2022-02-21 04:22:07,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8082 states to 8082 states and 11722 transitions. [2022-02-21 04:22:07,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8082 [2022-02-21 04:22:07,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8082 [2022-02-21 04:22:07,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8082 states and 11722 transitions. [2022-02-21 04:22:07,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:07,500 INFO L681 BuchiCegarLoop]: Abstraction has 8082 states and 11722 transitions. [2022-02-21 04:22:07,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8082 states and 11722 transitions. [2022-02-21 04:22:07,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8082 to 7678. [2022-02-21 04:22:07,626 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:07,634 INFO L82 GeneralOperation]: Start isEquivalent. First operand 8082 states and 11722 transitions. Second operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,642 INFO L74 IsIncluded]: Start isIncluded. First operand 8082 states and 11722 transitions. Second operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,649 INFO L87 Difference]: Start difference. First operand 8082 states and 11722 transitions. Second operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,057 INFO L93 Difference]: Finished difference Result 8082 states and 11722 transitions. [2022-02-21 04:22:09,057 INFO L276 IsEmpty]: Start isEmpty. Operand 8082 states and 11722 transitions. [2022-02-21 04:22:09,066 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:09,066 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:09,076 INFO L74 IsIncluded]: Start isIncluded. First operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8082 states and 11722 transitions. [2022-02-21 04:22:09,084 INFO L87 Difference]: Start difference. First operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 8082 states and 11722 transitions. [2022-02-21 04:22:10,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,542 INFO L93 Difference]: Finished difference Result 8082 states and 11722 transitions. [2022-02-21 04:22:10,543 INFO L276 IsEmpty]: Start isEmpty. Operand 8082 states and 11722 transitions. [2022-02-21 04:22:10,550 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,551 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,551 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:10,551 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:10,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7678 states, 7678 states have (on average 1.456629330554832) internal successors, (11184), 7677 states have internal predecessors, (11184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7678 states to 7678 states and 11184 transitions. [2022-02-21 04:22:12,019 INFO L704 BuchiCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-02-21 04:22:12,019 INFO L587 BuchiCegarLoop]: Abstraction has 7678 states and 11184 transitions. [2022-02-21 04:22:12,019 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:22:12,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7678 states and 11184 transitions. [2022-02-21 04:22:12,037 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7546 [2022-02-21 04:22:12,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:12,038 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:12,038 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,039 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:12,039 INFO L791 eck$LassoCheckResult]: Stem: 43327#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 43245#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 43184#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43093#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43094#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 42687#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42688#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42533#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42534#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42502#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42503#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42665#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42834#L696 assume !(0 == ~M_E~0); 42835#L696-2 assume !(0 == ~T1_E~0); 43211#L701-1 assume !(0 == ~T2_E~0); 43214#L706-1 assume !(0 == ~T3_E~0); 42966#L711-1 assume !(0 == ~T4_E~0); 42722#L716-1 assume !(0 == ~T5_E~0); 42723#L721-1 assume !(0 == ~T6_E~0); 42914#L726-1 assume !(0 == ~E_M~0); 42915#L731-1 assume !(0 == ~E_1~0); 42874#L736-1 assume !(0 == ~E_2~0); 42875#L741-1 assume !(0 == ~E_3~0); 42976#L746-1 assume !(0 == ~E_4~0); 42753#L751-1 assume !(0 == ~E_5~0); 42754#L756-1 assume !(0 == ~E_6~0); 42719#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42549#L346 assume !(1 == ~m_pc~0); 42550#L346-2 is_master_triggered_~__retres1~0#1 := 0; 42765#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42460#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42461#L861 assume !(0 != activate_threads_~tmp~1#1); 43164#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42581#L365 assume !(1 == ~t1_pc~0); 42582#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43183#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43185#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42572#L869 assume !(0 != activate_threads_~tmp___0~0#1); 42573#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43040#L384 assume !(1 == ~t2_pc~0); 43030#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43031#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42662#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42484#L877 assume !(0 != activate_threads_~tmp___1~0#1); 42485#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42852#L403 assume !(1 == ~t3_pc~0); 42853#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43086#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42709#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42710#L885 assume !(0 != activate_threads_~tmp___2~0#1); 42842#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42843#L422 assume 1 == ~t4_pc~0; 42479#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42480#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43036#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43037#L893 assume !(0 != activate_threads_~tmp___3~0#1); 42947#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42504#L441 assume !(1 == ~t5_pc~0); 42505#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 43154#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43247#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43248#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42956#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42957#L460 assume 1 == ~t6_pc~0; 42444#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42445#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42512#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43104#L909 assume !(0 != activate_threads_~tmp___5~0#1); 43105#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42927#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 42928#L774-2 assume !(1 == ~T1_E~0); 43130#L779-1 assume !(1 == ~T2_E~0); 42814#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42815#L789-1 assume !(1 == ~T4_E~0); 42564#L794-1 assume !(1 == ~T5_E~0); 42565#L799-1 assume !(1 == ~T6_E~0); 43273#L804-1 assume !(1 == ~E_M~0); 43274#L809-1 assume !(1 == ~E_1~0); 42907#L814-1 assume !(1 == ~E_2~0); 42908#L819-1 assume !(1 == ~E_3~0); 42989#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 42990#L829-1 assume !(1 == ~E_5~0); 43112#L834-1 assume !(1 == ~E_6~0); 43113#L839-1 assume { :end_inline_reset_delta_events } true; 49721#L1065-2 [2022-02-21 04:22:12,039 INFO L793 eck$LassoCheckResult]: Loop: 49721#L1065-2 assume !false; 49713#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49710#L671 assume !false; 49709#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49698#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49692#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49691#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43337#L582 assume !(0 != eval_~tmp~0#1); 43277#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42998#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42999#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49637#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42793#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42794#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43321#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43212#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43213#L721-3 assume !(0 == ~T6_E~0); 42770#L726-3 assume !(0 == ~E_M~0); 42771#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43196#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43197#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50004#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42847#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42848#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42592#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42593#L346-24 assume !(1 == ~m_pc~0); 42707#L346-26 is_master_triggered_~__retres1~0#1 := 0; 42708#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43219#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43220#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43124#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43125#L365-24 assume !(1 == ~t1_pc~0); 49992#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 49991#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49990#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 49989#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49988#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49987#L384-24 assume 1 == ~t2_pc~0; 49985#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49984#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49983#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49982#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 49981#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49980#L403-24 assume !(1 == ~t3_pc~0); 49979#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 49978#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49977#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49976#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49975#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49974#L422-24 assume 1 == ~t4_pc~0; 49891#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49890#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49889#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49888#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49887#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49886#L441-24 assume 1 == ~t5_pc~0; 49884#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42936#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42937#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42574#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42575#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43042#L460-24 assume !(1 == ~t6_pc~0); 43043#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 43330#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43089#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43090#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49880#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43298#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 43299#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49877#L779-3 assume !(1 == ~T2_E~0); 42482#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42483#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42464#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42465#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42583#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 42934#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42579#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42580#L819-3 assume !(1 == ~E_3~0); 42729#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42713#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42714#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43018#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 43142#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 42560#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 42654#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 42499#L1084 assume !(0 == start_simulation_~tmp~3#1); 42501#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 49736#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 49733#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 43071#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 42755#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42598#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42599#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 49725#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 49721#L1065-2 [2022-02-21 04:22:12,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,040 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2022-02-21 04:22:12,040 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,040 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723581325] [2022-02-21 04:22:12,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,040 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,064 INFO L290 TraceCheckUtils]: 0: Hoare triple {66284#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,065 INFO L290 TraceCheckUtils]: 1: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,065 INFO L290 TraceCheckUtils]: 2: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,065 INFO L290 TraceCheckUtils]: 3: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,065 INFO L290 TraceCheckUtils]: 4: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,066 INFO L290 TraceCheckUtils]: 5: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,066 INFO L290 TraceCheckUtils]: 6: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,066 INFO L290 TraceCheckUtils]: 7: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,067 INFO L290 TraceCheckUtils]: 8: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,067 INFO L290 TraceCheckUtils]: 9: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,067 INFO L290 TraceCheckUtils]: 10: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,067 INFO L290 TraceCheckUtils]: 11: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,068 INFO L290 TraceCheckUtils]: 12: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~M_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,068 INFO L290 TraceCheckUtils]: 13: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T1_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,068 INFO L290 TraceCheckUtils]: 14: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T2_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,068 INFO L290 TraceCheckUtils]: 15: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T3_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,069 INFO L290 TraceCheckUtils]: 16: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T4_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,069 INFO L290 TraceCheckUtils]: 17: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T5_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,069 INFO L290 TraceCheckUtils]: 18: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~T6_E~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,070 INFO L290 TraceCheckUtils]: 19: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_M~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,070 INFO L290 TraceCheckUtils]: 20: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_1~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,070 INFO L290 TraceCheckUtils]: 21: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_2~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,070 INFO L290 TraceCheckUtils]: 22: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_3~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,071 INFO L290 TraceCheckUtils]: 23: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_4~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,071 INFO L290 TraceCheckUtils]: 24: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_5~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,071 INFO L290 TraceCheckUtils]: 25: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 == ~E_6~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,071 INFO L290 TraceCheckUtils]: 26: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,072 INFO L290 TraceCheckUtils]: 27: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(1 == ~m_pc~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,072 INFO L290 TraceCheckUtils]: 28: Hoare triple {66286#(<= ~t4_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,072 INFO L290 TraceCheckUtils]: 29: Hoare triple {66286#(<= ~t4_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,073 INFO L290 TraceCheckUtils]: 30: Hoare triple {66286#(<= ~t4_pc~0 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,073 INFO L290 TraceCheckUtils]: 31: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,073 INFO L290 TraceCheckUtils]: 32: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,073 INFO L290 TraceCheckUtils]: 33: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(1 == ~t1_pc~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,074 INFO L290 TraceCheckUtils]: 34: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,074 INFO L290 TraceCheckUtils]: 35: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,074 INFO L290 TraceCheckUtils]: 36: Hoare triple {66286#(<= ~t4_pc~0 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,074 INFO L290 TraceCheckUtils]: 37: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,075 INFO L290 TraceCheckUtils]: 38: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,075 INFO L290 TraceCheckUtils]: 39: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(1 == ~t2_pc~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,075 INFO L290 TraceCheckUtils]: 40: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,076 INFO L290 TraceCheckUtils]: 41: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,076 INFO L290 TraceCheckUtils]: 42: Hoare triple {66286#(<= ~t4_pc~0 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,076 INFO L290 TraceCheckUtils]: 43: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,076 INFO L290 TraceCheckUtils]: 44: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,077 INFO L290 TraceCheckUtils]: 45: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(1 == ~t3_pc~0); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,077 INFO L290 TraceCheckUtils]: 46: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,077 INFO L290 TraceCheckUtils]: 47: Hoare triple {66286#(<= ~t4_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,077 INFO L290 TraceCheckUtils]: 48: Hoare triple {66286#(<= ~t4_pc~0 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,078 INFO L290 TraceCheckUtils]: 49: Hoare triple {66286#(<= ~t4_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,078 INFO L290 TraceCheckUtils]: 50: Hoare triple {66286#(<= ~t4_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66286#(<= ~t4_pc~0 0)} is VALID [2022-02-21 04:22:12,078 INFO L290 TraceCheckUtils]: 51: Hoare triple {66286#(<= ~t4_pc~0 0)} assume 1 == ~t4_pc~0; {66285#false} is VALID [2022-02-21 04:22:12,078 INFO L290 TraceCheckUtils]: 52: Hoare triple {66285#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66285#false} is VALID [2022-02-21 04:22:12,078 INFO L290 TraceCheckUtils]: 53: Hoare triple {66285#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 54: Hoare triple {66285#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 55: Hoare triple {66285#false} assume !(0 != activate_threads_~tmp___3~0#1); {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 56: Hoare triple {66285#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 57: Hoare triple {66285#false} assume !(1 == ~t5_pc~0); {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 58: Hoare triple {66285#false} is_transmit5_triggered_~__retres1~5#1 := 0; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 59: Hoare triple {66285#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 60: Hoare triple {66285#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 61: Hoare triple {66285#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66285#false} is VALID [2022-02-21 04:22:12,079 INFO L290 TraceCheckUtils]: 62: Hoare triple {66285#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 63: Hoare triple {66285#false} assume 1 == ~t6_pc~0; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 64: Hoare triple {66285#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 65: Hoare triple {66285#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 66: Hoare triple {66285#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 67: Hoare triple {66285#false} assume !(0 != activate_threads_~tmp___5~0#1); {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 68: Hoare triple {66285#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 69: Hoare triple {66285#false} assume 1 == ~M_E~0;~M_E~0 := 2; {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 70: Hoare triple {66285#false} assume !(1 == ~T1_E~0); {66285#false} is VALID [2022-02-21 04:22:12,080 INFO L290 TraceCheckUtils]: 71: Hoare triple {66285#false} assume !(1 == ~T2_E~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 72: Hoare triple {66285#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 73: Hoare triple {66285#false} assume !(1 == ~T4_E~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 74: Hoare triple {66285#false} assume !(1 == ~T5_E~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 75: Hoare triple {66285#false} assume !(1 == ~T6_E~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 76: Hoare triple {66285#false} assume !(1 == ~E_M~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 77: Hoare triple {66285#false} assume !(1 == ~E_1~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 78: Hoare triple {66285#false} assume !(1 == ~E_2~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 79: Hoare triple {66285#false} assume !(1 == ~E_3~0); {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 80: Hoare triple {66285#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66285#false} is VALID [2022-02-21 04:22:12,081 INFO L290 TraceCheckUtils]: 81: Hoare triple {66285#false} assume !(1 == ~E_5~0); {66285#false} is VALID [2022-02-21 04:22:12,082 INFO L290 TraceCheckUtils]: 82: Hoare triple {66285#false} assume !(1 == ~E_6~0); {66285#false} is VALID [2022-02-21 04:22:12,082 INFO L290 TraceCheckUtils]: 83: Hoare triple {66285#false} assume { :end_inline_reset_delta_events } true; {66285#false} is VALID [2022-02-21 04:22:12,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,082 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,082 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723581325] [2022-02-21 04:22:12,082 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723581325] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,082 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,083 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:22:12,083 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501208465] [2022-02-21 04:22:12,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,083 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:12,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:12,083 INFO L85 PathProgramCache]: Analyzing trace with hash 567624895, now seen corresponding path program 1 times [2022-02-21 04:22:12,084 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:12,084 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915199476] [2022-02-21 04:22:12,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:12,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:12,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:12,103 INFO L290 TraceCheckUtils]: 0: Hoare triple {66287#true} assume !false; {66287#true} is VALID [2022-02-21 04:22:12,103 INFO L290 TraceCheckUtils]: 1: Hoare triple {66287#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 2: Hoare triple {66287#true} assume !false; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 3: Hoare triple {66287#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 4: Hoare triple {66287#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 5: Hoare triple {66287#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 6: Hoare triple {66287#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 7: Hoare triple {66287#true} assume !(0 != eval_~tmp~0#1); {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 8: Hoare triple {66287#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 9: Hoare triple {66287#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 10: Hoare triple {66287#true} assume 0 == ~M_E~0;~M_E~0 := 1; {66287#true} is VALID [2022-02-21 04:22:12,104 INFO L290 TraceCheckUtils]: 11: Hoare triple {66287#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {66287#true} is VALID [2022-02-21 04:22:12,105 INFO L290 TraceCheckUtils]: 12: Hoare triple {66287#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,105 INFO L290 TraceCheckUtils]: 13: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,105 INFO L290 TraceCheckUtils]: 14: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,106 INFO L290 TraceCheckUtils]: 15: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,106 INFO L290 TraceCheckUtils]: 16: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,106 INFO L290 TraceCheckUtils]: 17: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_M~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,106 INFO L290 TraceCheckUtils]: 18: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,107 INFO L290 TraceCheckUtils]: 19: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,107 INFO L290 TraceCheckUtils]: 20: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,107 INFO L290 TraceCheckUtils]: 21: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,107 INFO L290 TraceCheckUtils]: 22: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,108 INFO L290 TraceCheckUtils]: 23: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,108 INFO L290 TraceCheckUtils]: 24: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,108 INFO L290 TraceCheckUtils]: 25: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,109 INFO L290 TraceCheckUtils]: 26: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,109 INFO L290 TraceCheckUtils]: 27: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,109 INFO L290 TraceCheckUtils]: 28: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,110 INFO L290 TraceCheckUtils]: 29: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,110 INFO L290 TraceCheckUtils]: 30: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,110 INFO L290 TraceCheckUtils]: 31: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,110 INFO L290 TraceCheckUtils]: 32: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,111 INFO L290 TraceCheckUtils]: 33: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,111 INFO L290 TraceCheckUtils]: 34: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,111 INFO L290 TraceCheckUtils]: 35: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,111 INFO L290 TraceCheckUtils]: 36: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,112 INFO L290 TraceCheckUtils]: 37: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,112 INFO L290 TraceCheckUtils]: 38: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,112 INFO L290 TraceCheckUtils]: 39: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,112 INFO L290 TraceCheckUtils]: 40: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,113 INFO L290 TraceCheckUtils]: 41: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,113 INFO L290 TraceCheckUtils]: 42: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,113 INFO L290 TraceCheckUtils]: 43: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,114 INFO L290 TraceCheckUtils]: 44: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,114 INFO L290 TraceCheckUtils]: 45: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,114 INFO L290 TraceCheckUtils]: 46: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,114 INFO L290 TraceCheckUtils]: 47: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,115 INFO L290 TraceCheckUtils]: 48: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,115 INFO L290 TraceCheckUtils]: 49: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,115 INFO L290 TraceCheckUtils]: 50: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,115 INFO L290 TraceCheckUtils]: 51: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,116 INFO L290 TraceCheckUtils]: 52: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,116 INFO L290 TraceCheckUtils]: 53: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,116 INFO L290 TraceCheckUtils]: 54: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,116 INFO L290 TraceCheckUtils]: 55: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,117 INFO L290 TraceCheckUtils]: 56: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,117 INFO L290 TraceCheckUtils]: 57: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,117 INFO L290 TraceCheckUtils]: 58: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,118 INFO L290 TraceCheckUtils]: 59: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,118 INFO L290 TraceCheckUtils]: 60: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,118 INFO L290 TraceCheckUtils]: 61: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,118 INFO L290 TraceCheckUtils]: 62: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,119 INFO L290 TraceCheckUtils]: 63: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,119 INFO L290 TraceCheckUtils]: 64: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,119 INFO L290 TraceCheckUtils]: 65: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,119 INFO L290 TraceCheckUtils]: 66: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,120 INFO L290 TraceCheckUtils]: 67: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,120 INFO L290 TraceCheckUtils]: 68: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {66289#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:12,120 INFO L290 TraceCheckUtils]: 69: Hoare triple {66289#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {66288#false} is VALID [2022-02-21 04:22:12,120 INFO L290 TraceCheckUtils]: 70: Hoare triple {66288#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,120 INFO L290 TraceCheckUtils]: 71: Hoare triple {66288#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 72: Hoare triple {66288#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 73: Hoare triple {66288#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 74: Hoare triple {66288#false} assume 1 == ~E_M~0;~E_M~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 75: Hoare triple {66288#false} assume 1 == ~E_1~0;~E_1~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 76: Hoare triple {66288#false} assume 1 == ~E_2~0;~E_2~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 77: Hoare triple {66288#false} assume !(1 == ~E_3~0); {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 78: Hoare triple {66288#false} assume 1 == ~E_4~0;~E_4~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 79: Hoare triple {66288#false} assume 1 == ~E_5~0;~E_5~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,121 INFO L290 TraceCheckUtils]: 80: Hoare triple {66288#false} assume 1 == ~E_6~0;~E_6~0 := 2; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 81: Hoare triple {66288#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 82: Hoare triple {66288#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 83: Hoare triple {66288#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 84: Hoare triple {66288#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 85: Hoare triple {66288#false} assume !(0 == start_simulation_~tmp~3#1); {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 86: Hoare triple {66288#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 87: Hoare triple {66288#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 88: Hoare triple {66288#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 89: Hoare triple {66288#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {66288#false} is VALID [2022-02-21 04:22:12,122 INFO L290 TraceCheckUtils]: 90: Hoare triple {66288#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {66288#false} is VALID [2022-02-21 04:22:12,123 INFO L290 TraceCheckUtils]: 91: Hoare triple {66288#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {66288#false} is VALID [2022-02-21 04:22:12,123 INFO L290 TraceCheckUtils]: 92: Hoare triple {66288#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {66288#false} is VALID [2022-02-21 04:22:12,123 INFO L290 TraceCheckUtils]: 93: Hoare triple {66288#false} assume !(0 != start_simulation_~tmp___0~1#1); {66288#false} is VALID [2022-02-21 04:22:12,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:12,123 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:12,123 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915199476] [2022-02-21 04:22:12,124 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915199476] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:12,124 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:12,124 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:12,124 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705558413] [2022-02-21 04:22:12,124 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:12,124 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:12,124 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:12,125 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:12,125 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:12,125 INFO L87 Difference]: Start difference. First operand 7678 states and 11184 transitions. cyclomatic complexity: 3514 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:17,489 INFO L93 Difference]: Finished difference Result 14259 states and 20702 transitions. [2022-02-21 04:22:17,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:17,489 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,523 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:17,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14259 states and 20702 transitions. [2022-02-21 04:22:22,548 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14062 [2022-02-21 04:22:27,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14259 states to 14259 states and 20702 transitions. [2022-02-21 04:22:27,520 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14259 [2022-02-21 04:22:27,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14259 [2022-02-21 04:22:27,527 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14259 states and 20702 transitions. [2022-02-21 04:22:27,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:27,541 INFO L681 BuchiCegarLoop]: Abstraction has 14259 states and 20702 transitions. [2022-02-21 04:22:27,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14259 states and 20702 transitions. [2022-02-21 04:22:27,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14259 to 14223. [2022-02-21 04:22:27,759 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:27,776 INFO L82 GeneralOperation]: Start isEquivalent. First operand 14259 states and 20702 transitions. Second operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:27,794 INFO L74 IsIncluded]: Start isIncluded. First operand 14259 states and 20702 transitions. Second operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:27,811 INFO L87 Difference]: Start difference. First operand 14259 states and 20702 transitions. Second operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:32,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:32,316 INFO L93 Difference]: Finished difference Result 14259 states and 20702 transitions. [2022-02-21 04:22:32,316 INFO L276 IsEmpty]: Start isEmpty. Operand 14259 states and 20702 transitions. [2022-02-21 04:22:32,332 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:32,332 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:32,348 INFO L74 IsIncluded]: Start isIncluded. First operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 14259 states and 20702 transitions. [2022-02-21 04:22:32,365 INFO L87 Difference]: Start difference. First operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 14259 states and 20702 transitions. [2022-02-21 04:22:36,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:36,645 INFO L93 Difference]: Finished difference Result 14259 states and 20702 transitions. [2022-02-21 04:22:36,646 INFO L276 IsEmpty]: Start isEmpty. Operand 14259 states and 20702 transitions. [2022-02-21 04:22:36,660 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:36,661 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:36,661 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:36,661 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:36,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14223 states, 14223 states have (on average 1.452998664135555) internal successors, (20666), 14222 states have internal predecessors, (20666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:41,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14223 states to 14223 states and 20666 transitions. [2022-02-21 04:22:41,841 INFO L704 BuchiCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-02-21 04:22:41,841 INFO L587 BuchiCegarLoop]: Abstraction has 14223 states and 20666 transitions. [2022-02-21 04:22:41,841 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:41,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14223 states and 20666 transitions. [2022-02-21 04:22:41,873 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14026 [2022-02-21 04:22:41,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:41,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:41,874 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:41,874 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:41,874 INFO L791 eck$LassoCheckResult]: Stem: 81315#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 81260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 81209#L1028 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81143#L480 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81144#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 80787#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 80788#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80640#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80641#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80609#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80610#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 80766#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80920#L696 assume !(0 == ~M_E~0); 80921#L696-2 assume !(0 == ~T1_E~0); 81232#L701-1 assume !(0 == ~T2_E~0); 81234#L706-1 assume !(0 == ~T3_E~0); 81044#L711-1 assume !(0 == ~T4_E~0); 80820#L716-1 assume !(0 == ~T5_E~0); 80821#L721-1 assume !(0 == ~T6_E~0); 80996#L726-1 assume !(0 == ~E_M~0); 80997#L731-1 assume !(0 == ~E_1~0); 80962#L736-1 assume !(0 == ~E_2~0); 80963#L741-1 assume !(0 == ~E_3~0); 81050#L746-1 assume !(0 == ~E_4~0); 80851#L751-1 assume !(0 == ~E_5~0); 80852#L756-1 assume !(0 == ~E_6~0); 80817#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80656#L346 assume !(1 == ~m_pc~0); 80657#L346-2 is_master_triggered_~__retres1~0#1 := 0; 80862#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 80570#L358 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80571#L861 assume !(0 != activate_threads_~tmp~1#1); 81190#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80686#L365 assume !(1 == ~t1_pc~0); 80687#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81208#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81210#L377 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80677#L869 assume !(0 != activate_threads_~tmp___0~0#1); 80678#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81105#L384 assume !(1 == ~t2_pc~0); 81095#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81096#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80763#L396 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80591#L877 assume !(0 != activate_threads_~tmp___1~0#1); 80592#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80938#L403 assume !(1 == ~t3_pc~0); 80939#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81138#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80809#L415 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80810#L885 assume !(0 != activate_threads_~tmp___2~0#1); 80929#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 80930#L422 assume !(1 == ~t4_pc~0); 81062#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81063#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81101#L434 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81102#L893 assume !(0 != activate_threads_~tmp___3~0#1); 81028#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 80611#L441 assume !(1 == ~t5_pc~0); 80612#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 81187#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81262#L453 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 81263#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 81036#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 81037#L460 assume 1 == ~t6_pc~0; 80554#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 80555#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80619#L472 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81151#L909 assume !(0 != activate_threads_~tmp___5~0#1); 81152#L909-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81008#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 81009#L774-2 assume !(1 == ~T1_E~0); 86324#L779-1 assume !(1 == ~T2_E~0); 86323#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86322#L789-1 assume !(1 == ~T4_E~0); 86321#L794-1 assume !(1 == ~T5_E~0); 86320#L799-1 assume !(1 == ~T6_E~0); 86319#L804-1 assume !(1 == ~E_M~0); 81284#L809-1 assume !(1 == ~E_1~0); 86318#L814-1 assume !(1 == ~E_2~0); 86317#L819-1 assume !(1 == ~E_3~0); 86316#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 86315#L829-1 assume !(1 == ~E_5~0); 86314#L834-1 assume !(1 == ~E_6~0); 85976#L839-1 assume { :end_inline_reset_delta_events } true; 85977#L1065-2 [2022-02-21 04:22:41,875 INFO L793 eck$LassoCheckResult]: Loop: 85977#L1065-2 assume !false; 85971#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85966#L671 assume !false; 85967#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 87752#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 87746#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 85952#L568 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85948#L582 assume !(0 != eval_~tmp~0#1); 85950#L686 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88754#L480-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88753#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 88752#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88751#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88750#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 88749#L711-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88748#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88747#L721-3 assume !(0 == ~T6_E~0); 88746#L726-3 assume !(0 == ~E_M~0); 88745#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 88744#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88743#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88742#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88741#L751-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88740#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 88739#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88738#L346-24 assume !(1 == ~m_pc~0); 88737#L346-26 is_master_triggered_~__retres1~0#1 := 0; 88736#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88735#L358-8 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88734#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 88733#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88732#L365-24 assume !(1 == ~t1_pc~0); 88731#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 88730#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88729#L377-8 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 88728#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88727#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88726#L384-24 assume !(1 == ~t2_pc~0); 88725#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 88723#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88722#L396-8 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88721#L877-24 assume !(0 != activate_threads_~tmp___1~0#1); 88720#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88719#L403-24 assume !(1 == ~t3_pc~0); 88718#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 88717#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 88716#L415-8 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88715#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 88714#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88713#L422-24 assume !(1 == ~t4_pc~0); 88712#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 88711#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88710#L434-8 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 88709#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 88708#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88707#L441-24 assume 1 == ~t5_pc~0; 88705#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 88704#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88703#L453-8 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 88702#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 88701#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 88700#L460-24 assume 1 == ~t6_pc~0; 88699#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 88697#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 88696#L472-8 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 88695#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 88694#L909-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88585#L774-3 assume 1 == ~M_E~0;~M_E~0 := 2; 88584#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88583#L779-3 assume !(1 == ~T2_E~0); 88582#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88581#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 88580#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 88579#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 88578#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 88575#L809-3 assume 1 == ~E_1~0;~E_1~0 := 2; 88574#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 88573#L819-3 assume !(1 == ~E_3~0); 88572#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88571#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88570#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 88569#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 88567#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 88561#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 88560#L568-1 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 88558#L1084 assume !(0 == start_simulation_~tmp~3#1); 88556#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 88551#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 88548#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 88547#L568-2 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 88546#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 88545#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 88544#L1047 start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 88543#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 85977#L1065-2 [2022-02-21 04:22:41,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:41,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2022-02-21 04:22:41,875 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:41,875 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607864911] [2022-02-21 04:22:41,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:41,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:41,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:41,902 INFO L290 TraceCheckUtils]: 0: Hoare triple {123293#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 1: Hoare triple {123293#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 2: Hoare triple {123293#true} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 3: Hoare triple {123293#true} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 4: Hoare triple {123293#true} assume 1 == ~m_i~0;~m_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 5: Hoare triple {123293#true} assume 1 == ~t1_i~0;~t1_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 6: Hoare triple {123293#true} assume 1 == ~t2_i~0;~t2_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,903 INFO L290 TraceCheckUtils]: 7: Hoare triple {123293#true} assume 1 == ~t3_i~0;~t3_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 8: Hoare triple {123293#true} assume 1 == ~t4_i~0;~t4_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 9: Hoare triple {123293#true} assume 1 == ~t5_i~0;~t5_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 10: Hoare triple {123293#true} assume 1 == ~t6_i~0;~t6_st~0 := 0; {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 11: Hoare triple {123293#true} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 12: Hoare triple {123293#true} assume !(0 == ~M_E~0); {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 13: Hoare triple {123293#true} assume !(0 == ~T1_E~0); {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 14: Hoare triple {123293#true} assume !(0 == ~T2_E~0); {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 15: Hoare triple {123293#true} assume !(0 == ~T3_E~0); {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 16: Hoare triple {123293#true} assume !(0 == ~T4_E~0); {123293#true} is VALID [2022-02-21 04:22:41,904 INFO L290 TraceCheckUtils]: 17: Hoare triple {123293#true} assume !(0 == ~T5_E~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 18: Hoare triple {123293#true} assume !(0 == ~T6_E~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 19: Hoare triple {123293#true} assume !(0 == ~E_M~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 20: Hoare triple {123293#true} assume !(0 == ~E_1~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 21: Hoare triple {123293#true} assume !(0 == ~E_2~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 22: Hoare triple {123293#true} assume !(0 == ~E_3~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 23: Hoare triple {123293#true} assume !(0 == ~E_4~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 24: Hoare triple {123293#true} assume !(0 == ~E_5~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 25: Hoare triple {123293#true} assume !(0 == ~E_6~0); {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 26: Hoare triple {123293#true} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {123293#true} is VALID [2022-02-21 04:22:41,905 INFO L290 TraceCheckUtils]: 27: Hoare triple {123293#true} assume !(1 == ~m_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 28: Hoare triple {123293#true} is_master_triggered_~__retres1~0#1 := 0; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 29: Hoare triple {123293#true} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 30: Hoare triple {123293#true} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 31: Hoare triple {123293#true} assume !(0 != activate_threads_~tmp~1#1); {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 32: Hoare triple {123293#true} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 33: Hoare triple {123293#true} assume !(1 == ~t1_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 34: Hoare triple {123293#true} is_transmit1_triggered_~__retres1~1#1 := 0; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 35: Hoare triple {123293#true} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {123293#true} is VALID [2022-02-21 04:22:41,906 INFO L290 TraceCheckUtils]: 36: Hoare triple {123293#true} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 37: Hoare triple {123293#true} assume !(0 != activate_threads_~tmp___0~0#1); {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 38: Hoare triple {123293#true} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 39: Hoare triple {123293#true} assume !(1 == ~t2_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 40: Hoare triple {123293#true} is_transmit2_triggered_~__retres1~2#1 := 0; {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 41: Hoare triple {123293#true} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 42: Hoare triple {123293#true} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 43: Hoare triple {123293#true} assume !(0 != activate_threads_~tmp___1~0#1); {123293#true} is VALID [2022-02-21 04:22:41,907 INFO L290 TraceCheckUtils]: 44: Hoare triple {123293#true} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 45: Hoare triple {123293#true} assume !(1 == ~t3_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 46: Hoare triple {123293#true} is_transmit3_triggered_~__retres1~3#1 := 0; {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 47: Hoare triple {123293#true} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 48: Hoare triple {123293#true} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 49: Hoare triple {123293#true} assume !(0 != activate_threads_~tmp___2~0#1); {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 50: Hoare triple {123293#true} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 51: Hoare triple {123293#true} assume !(1 == ~t4_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,908 INFO L290 TraceCheckUtils]: 52: Hoare triple {123293#true} is_transmit4_triggered_~__retres1~4#1 := 0; {123293#true} is VALID [2022-02-21 04:22:41,909 INFO L290 TraceCheckUtils]: 53: Hoare triple {123293#true} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {123293#true} is VALID [2022-02-21 04:22:41,909 INFO L290 TraceCheckUtils]: 54: Hoare triple {123293#true} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {123293#true} is VALID [2022-02-21 04:22:41,909 INFO L290 TraceCheckUtils]: 55: Hoare triple {123293#true} assume !(0 != activate_threads_~tmp___3~0#1); {123293#true} is VALID [2022-02-21 04:22:41,909 INFO L290 TraceCheckUtils]: 56: Hoare triple {123293#true} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {123293#true} is VALID [2022-02-21 04:22:41,909 INFO L290 TraceCheckUtils]: 57: Hoare triple {123293#true} assume !(1 == ~t5_pc~0); {123293#true} is VALID [2022-02-21 04:22:41,910 INFO L290 TraceCheckUtils]: 58: Hoare triple {123293#true} is_transmit5_triggered_~__retres1~5#1 := 0; {123295#(= |ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1| 0)} is VALID [2022-02-21 04:22:41,910 INFO L290 TraceCheckUtils]: 59: Hoare triple {123295#(= |ULTIMATE.start_is_transmit5_triggered_~__retres1~5#1| 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {123296#(= |ULTIMATE.start_is_transmit5_triggered_#res#1| 0)} is VALID [2022-02-21 04:22:41,910 INFO L290 TraceCheckUtils]: 60: Hoare triple {123296#(= |ULTIMATE.start_is_transmit5_triggered_#res#1| 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {123297#(= |ULTIMATE.start_activate_threads_~tmp___4~0#1| 0)} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 61: Hoare triple {123297#(= |ULTIMATE.start_activate_threads_~tmp___4~0#1| 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 62: Hoare triple {123294#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 63: Hoare triple {123294#false} assume 1 == ~t6_pc~0; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 64: Hoare triple {123294#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 65: Hoare triple {123294#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 66: Hoare triple {123294#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {123294#false} is VALID [2022-02-21 04:22:41,911 INFO L290 TraceCheckUtils]: 67: Hoare triple {123294#false} assume !(0 != activate_threads_~tmp___5~0#1); {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 68: Hoare triple {123294#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 69: Hoare triple {123294#false} assume 1 == ~M_E~0;~M_E~0 := 2; {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 70: Hoare triple {123294#false} assume !(1 == ~T1_E~0); {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 71: Hoare triple {123294#false} assume !(1 == ~T2_E~0); {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 72: Hoare triple {123294#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 73: Hoare triple {123294#false} assume !(1 == ~T4_E~0); {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 74: Hoare triple {123294#false} assume !(1 == ~T5_E~0); {123294#false} is VALID [2022-02-21 04:22:41,912 INFO L290 TraceCheckUtils]: 75: Hoare triple {123294#false} assume !(1 == ~T6_E~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 76: Hoare triple {123294#false} assume !(1 == ~E_M~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 77: Hoare triple {123294#false} assume !(1 == ~E_1~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 78: Hoare triple {123294#false} assume !(1 == ~E_2~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 79: Hoare triple {123294#false} assume !(1 == ~E_3~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 80: Hoare triple {123294#false} assume 1 == ~E_4~0;~E_4~0 := 2; {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 81: Hoare triple {123294#false} assume !(1 == ~E_5~0); {123294#false} is VALID [2022-02-21 04:22:41,913 INFO L290 TraceCheckUtils]: 82: Hoare triple {123294#false} assume !(1 == ~E_6~0); {123294#false} is VALID [2022-02-21 04:22:41,914 INFO L290 TraceCheckUtils]: 83: Hoare triple {123294#false} assume { :end_inline_reset_delta_events } true; {123294#false} is VALID [2022-02-21 04:22:41,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:41,914 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:41,914 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607864911] [2022-02-21 04:22:41,914 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607864911] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:41,914 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:41,915 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-02-21 04:22:41,915 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [59285630] [2022-02-21 04:22:41,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:41,915 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:41,915 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:41,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1510972288, now seen corresponding path program 1 times [2022-02-21 04:22:41,916 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:41,916 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482469780] [2022-02-21 04:22:41,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:41,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:41,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:41,939 INFO L290 TraceCheckUtils]: 0: Hoare triple {123298#true} assume !false; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 1: Hoare triple {123298#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 2: Hoare triple {123298#true} assume !false; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 3: Hoare triple {123298#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 4: Hoare triple {123298#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 5: Hoare triple {123298#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 6: Hoare triple {123298#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 7: Hoare triple {123298#true} assume !(0 != eval_~tmp~0#1); {123298#true} is VALID [2022-02-21 04:22:41,940 INFO L290 TraceCheckUtils]: 8: Hoare triple {123298#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {123298#true} is VALID [2022-02-21 04:22:41,941 INFO L290 TraceCheckUtils]: 9: Hoare triple {123298#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {123298#true} is VALID [2022-02-21 04:22:41,941 INFO L290 TraceCheckUtils]: 10: Hoare triple {123298#true} assume 0 == ~M_E~0;~M_E~0 := 1; {123298#true} is VALID [2022-02-21 04:22:41,941 INFO L290 TraceCheckUtils]: 11: Hoare triple {123298#true} assume 0 == ~T1_E~0;~T1_E~0 := 1; {123298#true} is VALID [2022-02-21 04:22:41,941 INFO L290 TraceCheckUtils]: 12: Hoare triple {123298#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,941 INFO L290 TraceCheckUtils]: 13: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,942 INFO L290 TraceCheckUtils]: 14: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,942 INFO L290 TraceCheckUtils]: 15: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,942 INFO L290 TraceCheckUtils]: 16: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,942 INFO L290 TraceCheckUtils]: 17: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_M~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,943 INFO L290 TraceCheckUtils]: 18: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_1~0;~E_1~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,943 INFO L290 TraceCheckUtils]: 19: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,943 INFO L290 TraceCheckUtils]: 20: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,943 INFO L290 TraceCheckUtils]: 21: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,944 INFO L290 TraceCheckUtils]: 22: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,944 INFO L290 TraceCheckUtils]: 23: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,944 INFO L290 TraceCheckUtils]: 24: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,944 INFO L290 TraceCheckUtils]: 25: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,945 INFO L290 TraceCheckUtils]: 26: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,945 INFO L290 TraceCheckUtils]: 27: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,945 INFO L290 TraceCheckUtils]: 28: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,946 INFO L290 TraceCheckUtils]: 29: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,946 INFO L290 TraceCheckUtils]: 30: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,946 INFO L290 TraceCheckUtils]: 31: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,946 INFO L290 TraceCheckUtils]: 32: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,947 INFO L290 TraceCheckUtils]: 33: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,947 INFO L290 TraceCheckUtils]: 34: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,947 INFO L290 TraceCheckUtils]: 35: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,947 INFO L290 TraceCheckUtils]: 36: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,948 INFO L290 TraceCheckUtils]: 37: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,948 INFO L290 TraceCheckUtils]: 38: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,948 INFO L290 TraceCheckUtils]: 39: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,948 INFO L290 TraceCheckUtils]: 40: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,949 INFO L290 TraceCheckUtils]: 41: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___1~0#1); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,949 INFO L290 TraceCheckUtils]: 42: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,949 INFO L290 TraceCheckUtils]: 43: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,949 INFO L290 TraceCheckUtils]: 44: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,950 INFO L290 TraceCheckUtils]: 45: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,950 INFO L290 TraceCheckUtils]: 46: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,950 INFO L290 TraceCheckUtils]: 47: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,950 INFO L290 TraceCheckUtils]: 48: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,951 INFO L290 TraceCheckUtils]: 49: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,951 INFO L290 TraceCheckUtils]: 50: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,951 INFO L290 TraceCheckUtils]: 51: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,952 INFO L290 TraceCheckUtils]: 52: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,952 INFO L290 TraceCheckUtils]: 53: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,952 INFO L290 TraceCheckUtils]: 54: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,952 INFO L290 TraceCheckUtils]: 55: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,953 INFO L290 TraceCheckUtils]: 56: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,953 INFO L290 TraceCheckUtils]: 57: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,953 INFO L290 TraceCheckUtils]: 58: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,953 INFO L290 TraceCheckUtils]: 59: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,954 INFO L290 TraceCheckUtils]: 60: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,954 INFO L290 TraceCheckUtils]: 61: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,954 INFO L290 TraceCheckUtils]: 62: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,954 INFO L290 TraceCheckUtils]: 63: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,955 INFO L290 TraceCheckUtils]: 64: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,955 INFO L290 TraceCheckUtils]: 65: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,955 INFO L290 TraceCheckUtils]: 66: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 67: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 68: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {123300#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 69: Hoare triple {123300#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {123299#false} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 70: Hoare triple {123299#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 71: Hoare triple {123299#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,956 INFO L290 TraceCheckUtils]: 72: Hoare triple {123299#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 73: Hoare triple {123299#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 74: Hoare triple {123299#false} assume 1 == ~E_M~0;~E_M~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 75: Hoare triple {123299#false} assume 1 == ~E_1~0;~E_1~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 76: Hoare triple {123299#false} assume 1 == ~E_2~0;~E_2~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 77: Hoare triple {123299#false} assume !(1 == ~E_3~0); {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 78: Hoare triple {123299#false} assume 1 == ~E_4~0;~E_4~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 79: Hoare triple {123299#false} assume 1 == ~E_5~0;~E_5~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 80: Hoare triple {123299#false} assume 1 == ~E_6~0;~E_6~0 := 2; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 81: Hoare triple {123299#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {123299#false} is VALID [2022-02-21 04:22:41,957 INFO L290 TraceCheckUtils]: 82: Hoare triple {123299#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 83: Hoare triple {123299#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 84: Hoare triple {123299#false} start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 85: Hoare triple {123299#false} assume !(0 == start_simulation_~tmp~3#1); {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 86: Hoare triple {123299#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 87: Hoare triple {123299#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 88: Hoare triple {123299#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 89: Hoare triple {123299#false} stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 90: Hoare triple {123299#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {123299#false} is VALID [2022-02-21 04:22:41,958 INFO L290 TraceCheckUtils]: 91: Hoare triple {123299#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {123299#false} is VALID [2022-02-21 04:22:41,959 INFO L290 TraceCheckUtils]: 92: Hoare triple {123299#false} start_simulation_#t~ret23#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {123299#false} is VALID [2022-02-21 04:22:41,959 INFO L290 TraceCheckUtils]: 93: Hoare triple {123299#false} assume !(0 != start_simulation_~tmp___0~1#1); {123299#false} is VALID [2022-02-21 04:22:41,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:41,959 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:41,959 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482469780] [2022-02-21 04:22:41,959 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482469780] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:41,959 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:41,959 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:41,960 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721809908] [2022-02-21 04:22:41,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:41,960 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:41,960 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:41,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-02-21 04:22:41,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-02-21 04:22:41,961 INFO L87 Difference]: Start difference. First operand 14223 states and 20666 transitions. cyclomatic complexity: 6459 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)