./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:52,055 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:52,058 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:52,095 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:52,096 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:52,099 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:52,101 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:52,103 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:52,104 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:52,109 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:52,109 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:52,110 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:52,110 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:52,112 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:52,113 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:52,114 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:52,117 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:52,118 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:52,119 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:52,120 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:52,123 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:52,123 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:52,124 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:52,125 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:52,129 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:52,129 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:52,129 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:52,130 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:52,131 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:52,131 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:52,131 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:52,132 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:52,133 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:52,134 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:52,135 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:52,135 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:52,135 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:52,136 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:52,136 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:52,136 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:52,137 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:52,137 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:52,165 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:52,165 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:52,166 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:52,166 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:52,167 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:52,167 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:52,167 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:52,167 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:52,167 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:52,168 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:52,168 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:52,168 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:52,169 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:52,169 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:52,170 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:52,171 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:52,171 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:52,171 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:52,171 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:52,171 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:52,172 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:52,172 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2022-02-21 04:21:52,355 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:52,368 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:52,372 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:52,372 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:52,374 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:52,375 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-02-21 04:21:52,421 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ff891d261/3c03dce22b9f45fbb9a42a66132cf7dd/FLAGb3e6a106c [2022-02-21 04:21:52,819 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:52,824 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2022-02-21 04:21:52,832 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ff891d261/3c03dce22b9f45fbb9a42a66132cf7dd/FLAGb3e6a106c [2022-02-21 04:21:52,841 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ff891d261/3c03dce22b9f45fbb9a42a66132cf7dd [2022-02-21 04:21:52,843 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:52,844 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:52,846 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:52,846 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:52,852 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:52,853 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:52" (1/1) ... [2022-02-21 04:21:52,854 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@33ad0259 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:52, skipping insertion in model container [2022-02-21 04:21:52,854 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:52" (1/1) ... [2022-02-21 04:21:52,858 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:52,894 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:53,051 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-02-21 04:21:53,160 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:53,172 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:53,182 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2022-02-21 04:21:53,216 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:53,241 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:53,241 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53 WrapperNode [2022-02-21 04:21:53,242 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:53,243 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:53,243 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:53,243 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:53,248 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,262 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,331 INFO L137 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 134, statements flattened = 1989 [2022-02-21 04:21:53,332 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:53,332 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:53,332 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:53,332 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:53,338 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,339 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,344 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,344 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,360 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,375 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,390 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,395 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:53,406 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:53,407 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:53,407 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:53,408 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (1/1) ... [2022-02-21 04:21:53,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:53,422 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:53,433 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:53,453 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:53,467 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:53,467 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:53,467 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:53,467 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:53,583 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:53,584 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:54,545 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:54,562 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:54,562 INFO L299 CfgBuilder]: Removed 10 assume(true) statements. [2022-02-21 04:21:54,565 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:54 BoogieIcfgContainer [2022-02-21 04:21:54,565 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:54,566 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:54,566 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:54,568 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:54,568 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:54,568 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:52" (1/3) ... [2022-02-21 04:21:54,569 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7605df6a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:54, skipping insertion in model container [2022-02-21 04:21:54,569 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:54,570 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:53" (2/3) ... [2022-02-21 04:21:54,570 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7605df6a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:54, skipping insertion in model container [2022-02-21 04:21:54,570 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:54,570 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:54" (3/3) ... [2022-02-21 04:21:54,571 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2022-02-21 04:21:54,610 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:54,610 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:54,611 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:54,611 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:54,611 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:54,611 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:54,611 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:54,611 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:54,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-02-21 04:21:54,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:54,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:54,768 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,768 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,768 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:54,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:54,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 729 [2022-02-21 04:21:54,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:54,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:54,837 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,838 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:54,848 INFO L791 eck$LassoCheckResult]: Stem: 412#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 753#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 307#L1141true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266#L529true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 562#L536true assume !(1 == ~m_i~0);~m_st~0 := 2; 779#L536-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 252#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 150#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 627#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 139#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 578#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 560#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 361#L571-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 649#L769true assume !(0 == ~M_E~0); 378#L769-2true assume !(0 == ~T1_E~0); 403#L774-1true assume !(0 == ~T2_E~0); 666#L779-1true assume !(0 == ~T3_E~0); 540#L784-1true assume !(0 == ~T4_E~0); 358#L789-1true assume !(0 == ~T5_E~0); 458#L794-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 816#L799-1true assume !(0 == ~T7_E~0); 363#L804-1true assume !(0 == ~E_M~0); 394#L809-1true assume !(0 == ~E_1~0); 571#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 186#L824-1true assume !(0 == ~E_4~0); 806#L829-1true assume !(0 == ~E_5~0); 663#L834-1true assume 0 == ~E_6~0;~E_6~0 := 1; 70#L839-1true assume !(0 == ~E_7~0); 464#L844-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 314#L376true assume !(1 == ~m_pc~0); 312#L376-2true is_master_triggered_~__retres1~0#1 := 0; 762#L387true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 626#L388true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46#L955true assume !(0 != activate_threads_~tmp~1#1); 245#L955-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 380#L395true assume 1 == ~t1_pc~0; 61#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 541#L406true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12#L407true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 586#L963true assume !(0 != activate_threads_~tmp___0~0#1); 320#L963-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 826#L414true assume !(1 == ~t2_pc~0); 570#L414-2true is_transmit2_triggered_~__retres1~2#1 := 0; 814#L425true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178#L426true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 568#L971true assume !(0 != activate_threads_~tmp___1~0#1); 680#L971-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 249#L433true assume 1 == ~t3_pc~0; 210#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 692#L444true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228#L445true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 505#L979true assume !(0 != activate_threads_~tmp___2~0#1); 56#L979-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 780#L452true assume !(1 == ~t4_pc~0); 137#L452-2true is_transmit4_triggered_~__retres1~4#1 := 0; 348#L463true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 402#L464true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 688#L987true assume !(0 != activate_threads_~tmp___3~0#1); 155#L987-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 444#L471true assume 1 == ~t5_pc~0; 744#L472true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 145#L482true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 395#L483true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 812#L995true assume !(0 != activate_threads_~tmp___4~0#1); 651#L995-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 729#L490true assume 1 == ~t6_pc~0; 609#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 353#L501true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 448#L502true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 355#L1003true assume !(0 != activate_threads_~tmp___5~0#1); 256#L1003-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 233#L509true assume !(1 == ~t7_pc~0); 572#L509-2true is_transmit7_triggered_~__retres1~7#1 := 0; 123#L520true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 685#L521true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157#L1011true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 690#L1011-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 583#L857true assume !(1 == ~M_E~0); 49#L857-2true assume !(1 == ~T1_E~0); 193#L862-1true assume !(1 == ~T2_E~0); 198#L867-1true assume !(1 == ~T3_E~0); 250#L872-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 422#L877-1true assume !(1 == ~T5_E~0); 608#L882-1true assume !(1 == ~T6_E~0); 736#L887-1true assume !(1 == ~T7_E~0); 479#L892-1true assume !(1 == ~E_M~0); 700#L897-1true assume !(1 == ~E_1~0); 205#L902-1true assume !(1 == ~E_2~0); 495#L907-1true assume !(1 == ~E_3~0); 434#L912-1true assume 1 == ~E_4~0;~E_4~0 := 2; 427#L917-1true assume !(1 == ~E_5~0); 671#L922-1true assume !(1 == ~E_6~0); 788#L927-1true assume !(1 == ~E_7~0); 418#L932-1true assume { :end_inline_reset_delta_events } true; 715#L1178-2true [2022-02-21 04:21:54,857 INFO L793 eck$LassoCheckResult]: Loop: 715#L1178-2true assume !false; 407#L1179true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227#L744true assume !true; 347#L759true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 89#L529-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 647#L769-3true assume 0 == ~M_E~0;~M_E~0 := 1; 247#L769-5true assume !(0 == ~T1_E~0); 385#L774-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 98#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 16#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 829#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 33#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 161#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 316#L809-3true assume !(0 == ~E_1~0); 31#L814-3true assume 0 == ~E_2~0;~E_2~0 := 1; 550#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 508#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 500#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 194#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 457#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 580#L844-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728#L376-27true assume !(1 == ~m_pc~0); 817#L376-29true is_master_triggered_~__retres1~0#1 := 0; 383#L387-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 485#L388-9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 681#L955-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 822#L955-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 807#L395-27true assume 1 == ~t1_pc~0; 784#L396-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 195#L406-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 517#L407-9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 377#L963-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 253#L963-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 644#L414-27true assume !(1 == ~t2_pc~0); 747#L414-29true is_transmit2_triggered_~__retres1~2#1 := 0; 426#L425-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 659#L426-9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L971-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39#L971-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84#L433-27true assume !(1 == ~t3_pc~0); 304#L433-29true is_transmit3_triggered_~__retres1~3#1 := 0; 258#L444-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 795#L445-9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 125#L979-27true assume !(0 != activate_threads_~tmp___2~0#1); 754#L979-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 740#L452-27true assume 1 == ~t4_pc~0; 835#L453-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 544#L463-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 674#L464-9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 639#L987-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 650#L987-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35#L471-27true assume 1 == ~t5_pc~0; 483#L472-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 823#L482-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 579#L483-9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 446#L995-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 381#L995-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313#L490-27true assume 1 == ~t6_pc~0; 229#L491-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 131#L501-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 614#L502-9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 433#L1003-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 709#L1003-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20#L509-27true assume 1 == ~t7_pc~0; 338#L510-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 533#L520-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 336#L521-9true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 331#L1011-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 802#L1011-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344#L857-3true assume 1 == ~M_E~0;~M_E~0 := 2; 375#L857-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 785#L862-3true assume !(1 == ~T2_E~0); 730#L867-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 259#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 337#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 763#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 372#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 109#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 530#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 825#L902-3true assume !(1 == ~E_2~0); 204#L907-3true assume 1 == ~E_3~0;~E_3~0 := 2; 293#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 565#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 262#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 138#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 211#L932-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 60#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 461#L626-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 798#L627-1true start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 241#L1197true assume !(0 == start_simulation_~tmp~3#1); 512#L1197-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 87#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 246#L626-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 36#L627-2true stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 742#L1152true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 526#L1159true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 632#L1160true start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 26#L1210true assume !(0 != start_simulation_~tmp___0~1#1); 715#L1178-2true [2022-02-21 04:21:54,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:54,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-02-21 04:21:54,868 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:54,868 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552088256] [2022-02-21 04:21:54,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:54,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:54,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,022 INFO L290 TraceCheckUtils]: 0: Hoare triple {840#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {840#true} is VALID [2022-02-21 04:21:55,022 INFO L290 TraceCheckUtils]: 1: Hoare triple {840#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {842#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:55,023 INFO L290 TraceCheckUtils]: 2: Hoare triple {842#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {842#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:55,024 INFO L290 TraceCheckUtils]: 3: Hoare triple {842#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {842#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:55,024 INFO L290 TraceCheckUtils]: 4: Hoare triple {842#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,024 INFO L290 TraceCheckUtils]: 5: Hoare triple {841#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {841#false} is VALID [2022-02-21 04:21:55,025 INFO L290 TraceCheckUtils]: 6: Hoare triple {841#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,025 INFO L290 TraceCheckUtils]: 7: Hoare triple {841#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,025 INFO L290 TraceCheckUtils]: 8: Hoare triple {841#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,025 INFO L290 TraceCheckUtils]: 9: Hoare triple {841#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,026 INFO L290 TraceCheckUtils]: 10: Hoare triple {841#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,026 INFO L290 TraceCheckUtils]: 11: Hoare triple {841#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,027 INFO L290 TraceCheckUtils]: 12: Hoare triple {841#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {841#false} is VALID [2022-02-21 04:21:55,027 INFO L290 TraceCheckUtils]: 13: Hoare triple {841#false} assume !(0 == ~M_E~0); {841#false} is VALID [2022-02-21 04:21:55,027 INFO L290 TraceCheckUtils]: 14: Hoare triple {841#false} assume !(0 == ~T1_E~0); {841#false} is VALID [2022-02-21 04:21:55,027 INFO L290 TraceCheckUtils]: 15: Hoare triple {841#false} assume !(0 == ~T2_E~0); {841#false} is VALID [2022-02-21 04:21:55,027 INFO L290 TraceCheckUtils]: 16: Hoare triple {841#false} assume !(0 == ~T3_E~0); {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 17: Hoare triple {841#false} assume !(0 == ~T4_E~0); {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 18: Hoare triple {841#false} assume !(0 == ~T5_E~0); {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 19: Hoare triple {841#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 20: Hoare triple {841#false} assume !(0 == ~T7_E~0); {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 21: Hoare triple {841#false} assume !(0 == ~E_M~0); {841#false} is VALID [2022-02-21 04:21:55,028 INFO L290 TraceCheckUtils]: 22: Hoare triple {841#false} assume !(0 == ~E_1~0); {841#false} is VALID [2022-02-21 04:21:55,029 INFO L290 TraceCheckUtils]: 23: Hoare triple {841#false} assume !(0 == ~E_2~0); {841#false} is VALID [2022-02-21 04:21:55,030 INFO L290 TraceCheckUtils]: 24: Hoare triple {841#false} assume !(0 == ~E_3~0); {841#false} is VALID [2022-02-21 04:21:55,030 INFO L290 TraceCheckUtils]: 25: Hoare triple {841#false} assume !(0 == ~E_4~0); {841#false} is VALID [2022-02-21 04:21:55,030 INFO L290 TraceCheckUtils]: 26: Hoare triple {841#false} assume !(0 == ~E_5~0); {841#false} is VALID [2022-02-21 04:21:55,030 INFO L290 TraceCheckUtils]: 27: Hoare triple {841#false} assume 0 == ~E_6~0;~E_6~0 := 1; {841#false} is VALID [2022-02-21 04:21:55,030 INFO L290 TraceCheckUtils]: 28: Hoare triple {841#false} assume !(0 == ~E_7~0); {841#false} is VALID [2022-02-21 04:21:55,031 INFO L290 TraceCheckUtils]: 29: Hoare triple {841#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {841#false} is VALID [2022-02-21 04:21:55,031 INFO L290 TraceCheckUtils]: 30: Hoare triple {841#false} assume !(1 == ~m_pc~0); {841#false} is VALID [2022-02-21 04:21:55,031 INFO L290 TraceCheckUtils]: 31: Hoare triple {841#false} is_master_triggered_~__retres1~0#1 := 0; {841#false} is VALID [2022-02-21 04:21:55,031 INFO L290 TraceCheckUtils]: 32: Hoare triple {841#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {841#false} is VALID [2022-02-21 04:21:55,031 INFO L290 TraceCheckUtils]: 33: Hoare triple {841#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {841#false} is VALID [2022-02-21 04:21:55,032 INFO L290 TraceCheckUtils]: 34: Hoare triple {841#false} assume !(0 != activate_threads_~tmp~1#1); {841#false} is VALID [2022-02-21 04:21:55,032 INFO L290 TraceCheckUtils]: 35: Hoare triple {841#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {841#false} is VALID [2022-02-21 04:21:55,032 INFO L290 TraceCheckUtils]: 36: Hoare triple {841#false} assume 1 == ~t1_pc~0; {841#false} is VALID [2022-02-21 04:21:55,032 INFO L290 TraceCheckUtils]: 37: Hoare triple {841#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {841#false} is VALID [2022-02-21 04:21:55,032 INFO L290 TraceCheckUtils]: 38: Hoare triple {841#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {841#false} is VALID [2022-02-21 04:21:55,033 INFO L290 TraceCheckUtils]: 39: Hoare triple {841#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {841#false} is VALID [2022-02-21 04:21:55,033 INFO L290 TraceCheckUtils]: 40: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___0~0#1); {841#false} is VALID [2022-02-21 04:21:55,033 INFO L290 TraceCheckUtils]: 41: Hoare triple {841#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {841#false} is VALID [2022-02-21 04:21:55,033 INFO L290 TraceCheckUtils]: 42: Hoare triple {841#false} assume !(1 == ~t2_pc~0); {841#false} is VALID [2022-02-21 04:21:55,033 INFO L290 TraceCheckUtils]: 43: Hoare triple {841#false} is_transmit2_triggered_~__retres1~2#1 := 0; {841#false} is VALID [2022-02-21 04:21:55,034 INFO L290 TraceCheckUtils]: 44: Hoare triple {841#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {841#false} is VALID [2022-02-21 04:21:55,034 INFO L290 TraceCheckUtils]: 45: Hoare triple {841#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {841#false} is VALID [2022-02-21 04:21:55,035 INFO L290 TraceCheckUtils]: 46: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___1~0#1); {841#false} is VALID [2022-02-21 04:21:55,035 INFO L290 TraceCheckUtils]: 47: Hoare triple {841#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {841#false} is VALID [2022-02-21 04:21:55,035 INFO L290 TraceCheckUtils]: 48: Hoare triple {841#false} assume 1 == ~t3_pc~0; {841#false} is VALID [2022-02-21 04:21:55,035 INFO L290 TraceCheckUtils]: 49: Hoare triple {841#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {841#false} is VALID [2022-02-21 04:21:55,038 INFO L290 TraceCheckUtils]: 50: Hoare triple {841#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {841#false} is VALID [2022-02-21 04:21:55,038 INFO L290 TraceCheckUtils]: 51: Hoare triple {841#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {841#false} is VALID [2022-02-21 04:21:55,039 INFO L290 TraceCheckUtils]: 52: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___2~0#1); {841#false} is VALID [2022-02-21 04:21:55,039 INFO L290 TraceCheckUtils]: 53: Hoare triple {841#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {841#false} is VALID [2022-02-21 04:21:55,039 INFO L290 TraceCheckUtils]: 54: Hoare triple {841#false} assume !(1 == ~t4_pc~0); {841#false} is VALID [2022-02-21 04:21:55,041 INFO L290 TraceCheckUtils]: 55: Hoare triple {841#false} is_transmit4_triggered_~__retres1~4#1 := 0; {841#false} is VALID [2022-02-21 04:21:55,042 INFO L290 TraceCheckUtils]: 56: Hoare triple {841#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {841#false} is VALID [2022-02-21 04:21:55,042 INFO L290 TraceCheckUtils]: 57: Hoare triple {841#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {841#false} is VALID [2022-02-21 04:21:55,042 INFO L290 TraceCheckUtils]: 58: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___3~0#1); {841#false} is VALID [2022-02-21 04:21:55,042 INFO L290 TraceCheckUtils]: 59: Hoare triple {841#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {841#false} is VALID [2022-02-21 04:21:55,042 INFO L290 TraceCheckUtils]: 60: Hoare triple {841#false} assume 1 == ~t5_pc~0; {841#false} is VALID [2022-02-21 04:21:55,043 INFO L290 TraceCheckUtils]: 61: Hoare triple {841#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {841#false} is VALID [2022-02-21 04:21:55,043 INFO L290 TraceCheckUtils]: 62: Hoare triple {841#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {841#false} is VALID [2022-02-21 04:21:55,044 INFO L290 TraceCheckUtils]: 63: Hoare triple {841#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {841#false} is VALID [2022-02-21 04:21:55,044 INFO L290 TraceCheckUtils]: 64: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___4~0#1); {841#false} is VALID [2022-02-21 04:21:55,046 INFO L290 TraceCheckUtils]: 65: Hoare triple {841#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {841#false} is VALID [2022-02-21 04:21:55,046 INFO L290 TraceCheckUtils]: 66: Hoare triple {841#false} assume 1 == ~t6_pc~0; {841#false} is VALID [2022-02-21 04:21:55,046 INFO L290 TraceCheckUtils]: 67: Hoare triple {841#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {841#false} is VALID [2022-02-21 04:21:55,046 INFO L290 TraceCheckUtils]: 68: Hoare triple {841#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {841#false} is VALID [2022-02-21 04:21:55,047 INFO L290 TraceCheckUtils]: 69: Hoare triple {841#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {841#false} is VALID [2022-02-21 04:21:55,047 INFO L290 TraceCheckUtils]: 70: Hoare triple {841#false} assume !(0 != activate_threads_~tmp___5~0#1); {841#false} is VALID [2022-02-21 04:21:55,047 INFO L290 TraceCheckUtils]: 71: Hoare triple {841#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {841#false} is VALID [2022-02-21 04:21:55,047 INFO L290 TraceCheckUtils]: 72: Hoare triple {841#false} assume !(1 == ~t7_pc~0); {841#false} is VALID [2022-02-21 04:21:55,048 INFO L290 TraceCheckUtils]: 73: Hoare triple {841#false} is_transmit7_triggered_~__retres1~7#1 := 0; {841#false} is VALID [2022-02-21 04:21:55,052 INFO L290 TraceCheckUtils]: 74: Hoare triple {841#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {841#false} is VALID [2022-02-21 04:21:55,052 INFO L290 TraceCheckUtils]: 75: Hoare triple {841#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {841#false} is VALID [2022-02-21 04:21:55,052 INFO L290 TraceCheckUtils]: 76: Hoare triple {841#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 77: Hoare triple {841#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 78: Hoare triple {841#false} assume !(1 == ~M_E~0); {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 79: Hoare triple {841#false} assume !(1 == ~T1_E~0); {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 80: Hoare triple {841#false} assume !(1 == ~T2_E~0); {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 81: Hoare triple {841#false} assume !(1 == ~T3_E~0); {841#false} is VALID [2022-02-21 04:21:55,053 INFO L290 TraceCheckUtils]: 82: Hoare triple {841#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,054 INFO L290 TraceCheckUtils]: 83: Hoare triple {841#false} assume !(1 == ~T5_E~0); {841#false} is VALID [2022-02-21 04:21:55,054 INFO L290 TraceCheckUtils]: 84: Hoare triple {841#false} assume !(1 == ~T6_E~0); {841#false} is VALID [2022-02-21 04:21:55,054 INFO L290 TraceCheckUtils]: 85: Hoare triple {841#false} assume !(1 == ~T7_E~0); {841#false} is VALID [2022-02-21 04:21:55,054 INFO L290 TraceCheckUtils]: 86: Hoare triple {841#false} assume !(1 == ~E_M~0); {841#false} is VALID [2022-02-21 04:21:55,054 INFO L290 TraceCheckUtils]: 87: Hoare triple {841#false} assume !(1 == ~E_1~0); {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 88: Hoare triple {841#false} assume !(1 == ~E_2~0); {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 89: Hoare triple {841#false} assume !(1 == ~E_3~0); {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 90: Hoare triple {841#false} assume 1 == ~E_4~0;~E_4~0 := 2; {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 91: Hoare triple {841#false} assume !(1 == ~E_5~0); {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 92: Hoare triple {841#false} assume !(1 == ~E_6~0); {841#false} is VALID [2022-02-21 04:21:55,055 INFO L290 TraceCheckUtils]: 93: Hoare triple {841#false} assume !(1 == ~E_7~0); {841#false} is VALID [2022-02-21 04:21:55,056 INFO L290 TraceCheckUtils]: 94: Hoare triple {841#false} assume { :end_inline_reset_delta_events } true; {841#false} is VALID [2022-02-21 04:21:55,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,057 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,057 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552088256] [2022-02-21 04:21:55,058 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552088256] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,058 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,059 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:55,061 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1310864619] [2022-02-21 04:21:55,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,065 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:55,066 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:55,067 INFO L85 PathProgramCache]: Analyzing trace with hash 1867582005, now seen corresponding path program 1 times [2022-02-21 04:21:55,067 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:55,067 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220650959] [2022-02-21 04:21:55,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:55,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:55,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:55,110 INFO L290 TraceCheckUtils]: 0: Hoare triple {843#true} assume !false; {843#true} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 1: Hoare triple {843#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {843#true} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 2: Hoare triple {843#true} assume !true; {844#false} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 3: Hoare triple {844#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {844#false} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 4: Hoare triple {844#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {844#false} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 5: Hoare triple {844#false} assume 0 == ~M_E~0;~M_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,111 INFO L290 TraceCheckUtils]: 6: Hoare triple {844#false} assume !(0 == ~T1_E~0); {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 7: Hoare triple {844#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 8: Hoare triple {844#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 9: Hoare triple {844#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 10: Hoare triple {844#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 11: Hoare triple {844#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 12: Hoare triple {844#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 13: Hoare triple {844#false} assume 0 == ~E_M~0;~E_M~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,112 INFO L290 TraceCheckUtils]: 14: Hoare triple {844#false} assume !(0 == ~E_1~0); {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 15: Hoare triple {844#false} assume 0 == ~E_2~0;~E_2~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 16: Hoare triple {844#false} assume 0 == ~E_3~0;~E_3~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 17: Hoare triple {844#false} assume 0 == ~E_4~0;~E_4~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 18: Hoare triple {844#false} assume 0 == ~E_5~0;~E_5~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 19: Hoare triple {844#false} assume 0 == ~E_6~0;~E_6~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 20: Hoare triple {844#false} assume 0 == ~E_7~0;~E_7~0 := 1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 21: Hoare triple {844#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {844#false} is VALID [2022-02-21 04:21:55,113 INFO L290 TraceCheckUtils]: 22: Hoare triple {844#false} assume !(1 == ~m_pc~0); {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 23: Hoare triple {844#false} is_master_triggered_~__retres1~0#1 := 0; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 24: Hoare triple {844#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 25: Hoare triple {844#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 26: Hoare triple {844#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 27: Hoare triple {844#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 28: Hoare triple {844#false} assume 1 == ~t1_pc~0; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 29: Hoare triple {844#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,114 INFO L290 TraceCheckUtils]: 30: Hoare triple {844#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 31: Hoare triple {844#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 32: Hoare triple {844#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 33: Hoare triple {844#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 34: Hoare triple {844#false} assume !(1 == ~t2_pc~0); {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 35: Hoare triple {844#false} is_transmit2_triggered_~__retres1~2#1 := 0; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 36: Hoare triple {844#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {844#false} is VALID [2022-02-21 04:21:55,115 INFO L290 TraceCheckUtils]: 37: Hoare triple {844#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 38: Hoare triple {844#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 39: Hoare triple {844#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 40: Hoare triple {844#false} assume !(1 == ~t3_pc~0); {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 41: Hoare triple {844#false} is_transmit3_triggered_~__retres1~3#1 := 0; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 42: Hoare triple {844#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 43: Hoare triple {844#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 44: Hoare triple {844#false} assume !(0 != activate_threads_~tmp___2~0#1); {844#false} is VALID [2022-02-21 04:21:55,116 INFO L290 TraceCheckUtils]: 45: Hoare triple {844#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 46: Hoare triple {844#false} assume 1 == ~t4_pc~0; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 47: Hoare triple {844#false} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 48: Hoare triple {844#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 49: Hoare triple {844#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 50: Hoare triple {844#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 51: Hoare triple {844#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 52: Hoare triple {844#false} assume 1 == ~t5_pc~0; {844#false} is VALID [2022-02-21 04:21:55,117 INFO L290 TraceCheckUtils]: 53: Hoare triple {844#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 54: Hoare triple {844#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 55: Hoare triple {844#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 56: Hoare triple {844#false} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 57: Hoare triple {844#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 58: Hoare triple {844#false} assume 1 == ~t6_pc~0; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 59: Hoare triple {844#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,118 INFO L290 TraceCheckUtils]: 60: Hoare triple {844#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 61: Hoare triple {844#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 62: Hoare triple {844#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 63: Hoare triple {844#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 64: Hoare triple {844#false} assume 1 == ~t7_pc~0; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 65: Hoare triple {844#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 66: Hoare triple {844#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 67: Hoare triple {844#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {844#false} is VALID [2022-02-21 04:21:55,119 INFO L290 TraceCheckUtils]: 68: Hoare triple {844#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 69: Hoare triple {844#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 70: Hoare triple {844#false} assume 1 == ~M_E~0;~M_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 71: Hoare triple {844#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 72: Hoare triple {844#false} assume !(1 == ~T2_E~0); {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 73: Hoare triple {844#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 74: Hoare triple {844#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 75: Hoare triple {844#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,120 INFO L290 TraceCheckUtils]: 76: Hoare triple {844#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 77: Hoare triple {844#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 78: Hoare triple {844#false} assume 1 == ~E_M~0;~E_M~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 79: Hoare triple {844#false} assume 1 == ~E_1~0;~E_1~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 80: Hoare triple {844#false} assume !(1 == ~E_2~0); {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 81: Hoare triple {844#false} assume 1 == ~E_3~0;~E_3~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 82: Hoare triple {844#false} assume 1 == ~E_4~0;~E_4~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 83: Hoare triple {844#false} assume 1 == ~E_5~0;~E_5~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,121 INFO L290 TraceCheckUtils]: 84: Hoare triple {844#false} assume 1 == ~E_6~0;~E_6~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 85: Hoare triple {844#false} assume 1 == ~E_7~0;~E_7~0 := 2; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 86: Hoare triple {844#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 87: Hoare triple {844#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 88: Hoare triple {844#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 89: Hoare triple {844#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 90: Hoare triple {844#false} assume !(0 == start_simulation_~tmp~3#1); {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 91: Hoare triple {844#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {844#false} is VALID [2022-02-21 04:21:55,122 INFO L290 TraceCheckUtils]: 92: Hoare triple {844#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {844#false} is VALID [2022-02-21 04:21:55,123 INFO L290 TraceCheckUtils]: 93: Hoare triple {844#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {844#false} is VALID [2022-02-21 04:21:55,123 INFO L290 TraceCheckUtils]: 94: Hoare triple {844#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {844#false} is VALID [2022-02-21 04:21:55,125 INFO L290 TraceCheckUtils]: 95: Hoare triple {844#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {844#false} is VALID [2022-02-21 04:21:55,126 INFO L290 TraceCheckUtils]: 96: Hoare triple {844#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {844#false} is VALID [2022-02-21 04:21:55,126 INFO L290 TraceCheckUtils]: 97: Hoare triple {844#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {844#false} is VALID [2022-02-21 04:21:55,126 INFO L290 TraceCheckUtils]: 98: Hoare triple {844#false} assume !(0 != start_simulation_~tmp___0~1#1); {844#false} is VALID [2022-02-21 04:21:55,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:55,127 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:55,127 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220650959] [2022-02-21 04:21:55,127 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220650959] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:55,128 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:55,128 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:55,128 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365728831] [2022-02-21 04:21:55,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:55,129 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:55,130 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:55,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:55,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:55,157 INFO L87 Difference]: Start difference. First operand has 836 states, 835 states have (on average 1.518562874251497) internal successors, (1268), 835 states have internal predecessors, (1268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:55,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:55,942 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-02-21 04:21:55,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:55,944 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,005 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:56,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-02-21 04:21:56,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:56,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 830 states and 1240 transitions. [2022-02-21 04:21:56,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:56,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:56,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1240 transitions. [2022-02-21 04:21:56,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:56,062 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-02-21 04:21:56,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1240 transitions. [2022-02-21 04:21:56,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:21:56,115 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:56,118 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1240 transitions. Second operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,120 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1240 transitions. Second operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,122 INFO L87 Difference]: Start difference. First operand 830 states and 1240 transitions. Second operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,163 INFO L93 Difference]: Finished difference Result 830 states and 1240 transitions. [2022-02-21 04:21:56,163 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1240 transitions. [2022-02-21 04:21:56,168 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,168 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,170 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1240 transitions. [2022-02-21 04:21:56,171 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1240 transitions. [2022-02-21 04:21:56,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,196 INFO L93 Difference]: Finished difference Result 830 states and 1240 transitions. [2022-02-21 04:21:56,196 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1240 transitions. [2022-02-21 04:21:56,197 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:56,197 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:56,198 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:56,198 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:56,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4939759036144578) internal successors, (1240), 829 states have internal predecessors, (1240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,228 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1240 transitions. [2022-02-21 04:21:56,229 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-02-21 04:21:56,229 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1240 transitions. [2022-02-21 04:21:56,229 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:56,230 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1240 transitions. [2022-02-21 04:21:56,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:56,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,236 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,237 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,237 INFO L791 eck$LassoCheckResult]: Stem: 2319#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2202#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2152#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2153#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 2436#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2135#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1975#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1976#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1957#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1958#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2435#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2260#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2261#L769 assume !(0 == ~M_E~0); 2283#L769-2 assume !(0 == ~T1_E~0); 2284#L774-1 assume !(0 == ~T2_E~0); 2311#L779-1 assume !(0 == ~T3_E~0); 2423#L784-1 assume !(0 == ~T4_E~0); 2256#L789-1 assume !(0 == ~T5_E~0); 2257#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2367#L799-1 assume !(0 == ~T7_E~0); 2263#L804-1 assume !(0 == ~E_M~0); 2264#L809-1 assume !(0 == ~E_1~0); 2304#L814-1 assume !(0 == ~E_2~0); 1693#L819-1 assume !(0 == ~E_3~0); 1694#L824-1 assume !(0 == ~E_4~0); 2045#L829-1 assume !(0 == ~E_5~0); 2482#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1829#L839-1 assume !(0 == ~E_7~0); 1830#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2208#L376 assume !(1 == ~m_pc~0); 2195#L376-2 is_master_triggered_~__retres1~0#1 := 0; 2194#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2465#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1776#L955 assume !(0 != activate_threads_~tmp~1#1); 1777#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2128#L395 assume 1 == ~t1_pc~0; 1806#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1807#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1699#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1700#L963 assume !(0 != activate_threads_~tmp___0~0#1); 2212#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2213#L414 assume !(1 == ~t2_pc~0); 1832#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1833#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2031#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2032#L971 assume !(0 != activate_threads_~tmp___1~0#1); 2439#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2131#L433 assume 1 == ~t3_pc~0; 2076#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1946#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2104#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2105#L979 assume !(0 != activate_threads_~tmp___2~0#1); 1797#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1798#L452 assume !(1 == ~t4_pc~0); 1953#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1954#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2244#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2310#L987 assume !(0 != activate_threads_~tmp___3~0#1); 1986#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1987#L471 assume 1 == ~t5_pc~0; 2355#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1969#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1970#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2305#L995 assume !(0 != activate_threads_~tmp___4~0#1); 2474#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2475#L490 assume 1 == ~t6_pc~0; 2458#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2211#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2251#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2254#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 2140#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2109#L509 assume !(1 == ~t7_pc~0); 2110#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1927#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1928#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1991#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1992#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2447#L857 assume !(1 == ~M_E~0); 1783#L857-2 assume !(1 == ~T1_E~0); 1784#L862-1 assume !(1 == ~T2_E~0); 2053#L867-1 assume !(1 == ~T3_E~0); 2058#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2132#L877-1 assume !(1 == ~T5_E~0); 2331#L882-1 assume !(1 == ~T6_E~0); 2457#L887-1 assume !(1 == ~T7_E~0); 2381#L892-1 assume !(1 == ~E_M~0); 2382#L897-1 assume !(1 == ~E_1~0); 2068#L902-1 assume !(1 == ~E_2~0); 2069#L907-1 assume !(1 == ~E_3~0); 2348#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2339#L917-1 assume !(1 == ~E_5~0); 2340#L922-1 assume !(1 == ~E_6~0); 2485#L927-1 assume !(1 == ~E_7~0); 2326#L932-1 assume { :end_inline_reset_delta_events } true; 1732#L1178-2 [2022-02-21 04:21:56,238 INFO L793 eck$LassoCheckResult]: Loop: 1732#L1178-2 assume !false; 2315#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1749#L744 assume !false; 2103#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2176#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1767#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1973#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2427#L641 assume !(0 != eval_~tmp~0#1); 2243#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1867#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1868#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2129#L769-5 assume !(0 == ~T1_E~0); 2130#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1884#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1708#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1709#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1695#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1696#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1747#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2001#L809-3 assume !(0 == ~E_1~0); 1743#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1744#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2403#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2398#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2054#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2055#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2366#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2445#L376-27 assume 1 == ~m_pc~0; 2344#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2290#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2291#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2385#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2488#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2509#L395-27 assume !(1 == ~t1_pc~0); 2148#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2056#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2057#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2282#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2136#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2137#L414-27 assume 1 == ~t2_pc~0; 2472#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2337#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2338#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2197#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1759#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1760#L433-27 assume 1 == ~t3_pc~0; 1856#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2142#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2143#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1930#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 1931#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2502#L452-27 assume 1 == ~t4_pc~0; 2503#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2302#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2426#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2468#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2469#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1750#L471-27 assume !(1 == ~t5_pc~0); 1751#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 2065#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2444#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2358#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2286#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2207#L490-27 assume 1 == ~t6_pc~0; 2106#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1942#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1943#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2346#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2347#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1717#L509-27 assume !(1 == ~t7_pc~0); 1718#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2108#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2233#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2224#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2225#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2239#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2240#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2280#L862-3 assume !(1 == ~T2_E~0); 2500#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2144#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2145#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2234#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2274#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1904#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1905#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2418#L902-3 assume !(1 == ~E_2~0); 2066#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2067#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2186#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2149#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1955#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1956#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1804#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1707#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2369#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 2119#L1197 assume !(0 == start_simulation_~tmp~3#1); 2120#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1863#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1827#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1753#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 1754#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2415#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2416#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1731#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 1732#L1178-2 [2022-02-21 04:21:56,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,239 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-02-21 04:21:56,240 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,240 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719951749] [2022-02-21 04:21:56,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,288 INFO L290 TraceCheckUtils]: 0: Hoare triple {4173#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {4173#true} is VALID [2022-02-21 04:21:56,289 INFO L290 TraceCheckUtils]: 1: Hoare triple {4173#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {4175#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:56,289 INFO L290 TraceCheckUtils]: 2: Hoare triple {4175#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4175#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 3: Hoare triple {4175#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4175#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 4: Hoare triple {4175#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {4175#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 5: Hoare triple {4175#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4175#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 6: Hoare triple {4175#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 7: Hoare triple {4174#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,290 INFO L290 TraceCheckUtils]: 8: Hoare triple {4174#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,291 INFO L290 TraceCheckUtils]: 9: Hoare triple {4174#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 10: Hoare triple {4174#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 11: Hoare triple {4174#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 12: Hoare triple {4174#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 13: Hoare triple {4174#false} assume !(0 == ~M_E~0); {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 14: Hoare triple {4174#false} assume !(0 == ~T1_E~0); {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 15: Hoare triple {4174#false} assume !(0 == ~T2_E~0); {4174#false} is VALID [2022-02-21 04:21:56,293 INFO L290 TraceCheckUtils]: 16: Hoare triple {4174#false} assume !(0 == ~T3_E~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 17: Hoare triple {4174#false} assume !(0 == ~T4_E~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 18: Hoare triple {4174#false} assume !(0 == ~T5_E~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 19: Hoare triple {4174#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 20: Hoare triple {4174#false} assume !(0 == ~T7_E~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 21: Hoare triple {4174#false} assume !(0 == ~E_M~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 22: Hoare triple {4174#false} assume !(0 == ~E_1~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 23: Hoare triple {4174#false} assume !(0 == ~E_2~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 24: Hoare triple {4174#false} assume !(0 == ~E_3~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 25: Hoare triple {4174#false} assume !(0 == ~E_4~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 26: Hoare triple {4174#false} assume !(0 == ~E_5~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 27: Hoare triple {4174#false} assume 0 == ~E_6~0;~E_6~0 := 1; {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 28: Hoare triple {4174#false} assume !(0 == ~E_7~0); {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 29: Hoare triple {4174#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4174#false} is VALID [2022-02-21 04:21:56,294 INFO L290 TraceCheckUtils]: 30: Hoare triple {4174#false} assume !(1 == ~m_pc~0); {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 31: Hoare triple {4174#false} is_master_triggered_~__retres1~0#1 := 0; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 32: Hoare triple {4174#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 33: Hoare triple {4174#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 34: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp~1#1); {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 35: Hoare triple {4174#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 36: Hoare triple {4174#false} assume 1 == ~t1_pc~0; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 37: Hoare triple {4174#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 38: Hoare triple {4174#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 39: Hoare triple {4174#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 40: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___0~0#1); {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 41: Hoare triple {4174#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 42: Hoare triple {4174#false} assume !(1 == ~t2_pc~0); {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 43: Hoare triple {4174#false} is_transmit2_triggered_~__retres1~2#1 := 0; {4174#false} is VALID [2022-02-21 04:21:56,295 INFO L290 TraceCheckUtils]: 44: Hoare triple {4174#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 45: Hoare triple {4174#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 46: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___1~0#1); {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 47: Hoare triple {4174#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 48: Hoare triple {4174#false} assume 1 == ~t3_pc~0; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 49: Hoare triple {4174#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 50: Hoare triple {4174#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 51: Hoare triple {4174#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 52: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___2~0#1); {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 53: Hoare triple {4174#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 54: Hoare triple {4174#false} assume !(1 == ~t4_pc~0); {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 55: Hoare triple {4174#false} is_transmit4_triggered_~__retres1~4#1 := 0; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 56: Hoare triple {4174#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4174#false} is VALID [2022-02-21 04:21:56,296 INFO L290 TraceCheckUtils]: 57: Hoare triple {4174#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 58: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___3~0#1); {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 59: Hoare triple {4174#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 60: Hoare triple {4174#false} assume 1 == ~t5_pc~0; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 61: Hoare triple {4174#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 62: Hoare triple {4174#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 63: Hoare triple {4174#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 64: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___4~0#1); {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 65: Hoare triple {4174#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 66: Hoare triple {4174#false} assume 1 == ~t6_pc~0; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 67: Hoare triple {4174#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 68: Hoare triple {4174#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 69: Hoare triple {4174#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 70: Hoare triple {4174#false} assume !(0 != activate_threads_~tmp___5~0#1); {4174#false} is VALID [2022-02-21 04:21:56,297 INFO L290 TraceCheckUtils]: 71: Hoare triple {4174#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 72: Hoare triple {4174#false} assume !(1 == ~t7_pc~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 73: Hoare triple {4174#false} is_transmit7_triggered_~__retres1~7#1 := 0; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 74: Hoare triple {4174#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 75: Hoare triple {4174#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 76: Hoare triple {4174#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 77: Hoare triple {4174#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 78: Hoare triple {4174#false} assume !(1 == ~M_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 79: Hoare triple {4174#false} assume !(1 == ~T1_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 80: Hoare triple {4174#false} assume !(1 == ~T2_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 81: Hoare triple {4174#false} assume !(1 == ~T3_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 82: Hoare triple {4174#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 83: Hoare triple {4174#false} assume !(1 == ~T5_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 84: Hoare triple {4174#false} assume !(1 == ~T6_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 85: Hoare triple {4174#false} assume !(1 == ~T7_E~0); {4174#false} is VALID [2022-02-21 04:21:56,298 INFO L290 TraceCheckUtils]: 86: Hoare triple {4174#false} assume !(1 == ~E_M~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 87: Hoare triple {4174#false} assume !(1 == ~E_1~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 88: Hoare triple {4174#false} assume !(1 == ~E_2~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 89: Hoare triple {4174#false} assume !(1 == ~E_3~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 90: Hoare triple {4174#false} assume 1 == ~E_4~0;~E_4~0 := 2; {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 91: Hoare triple {4174#false} assume !(1 == ~E_5~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 92: Hoare triple {4174#false} assume !(1 == ~E_6~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 93: Hoare triple {4174#false} assume !(1 == ~E_7~0); {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L290 TraceCheckUtils]: 94: Hoare triple {4174#false} assume { :end_inline_reset_delta_events } true; {4174#false} is VALID [2022-02-21 04:21:56,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,300 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,300 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1719951749] [2022-02-21 04:21:56,300 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1719951749] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,300 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,300 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,300 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814738452] [2022-02-21 04:21:56,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,300 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:56,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,301 INFO L85 PathProgramCache]: Analyzing trace with hash -802393431, now seen corresponding path program 1 times [2022-02-21 04:21:56,301 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,301 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626247105] [2022-02-21 04:21:56,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,373 INFO L290 TraceCheckUtils]: 0: Hoare triple {4176#true} assume !false; {4176#true} is VALID [2022-02-21 04:21:56,373 INFO L290 TraceCheckUtils]: 1: Hoare triple {4176#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4176#true} is VALID [2022-02-21 04:21:56,373 INFO L290 TraceCheckUtils]: 2: Hoare triple {4176#true} assume !false; {4176#true} is VALID [2022-02-21 04:21:56,373 INFO L290 TraceCheckUtils]: 3: Hoare triple {4176#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4176#true} is VALID [2022-02-21 04:21:56,373 INFO L290 TraceCheckUtils]: 4: Hoare triple {4176#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 5: Hoare triple {4176#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 6: Hoare triple {4176#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 7: Hoare triple {4176#true} assume !(0 != eval_~tmp~0#1); {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 8: Hoare triple {4176#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 9: Hoare triple {4176#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 10: Hoare triple {4176#true} assume 0 == ~M_E~0;~M_E~0 := 1; {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 11: Hoare triple {4176#true} assume !(0 == ~T1_E~0); {4176#true} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 12: Hoare triple {4176#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,374 INFO L290 TraceCheckUtils]: 13: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,375 INFO L290 TraceCheckUtils]: 14: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,375 INFO L290 TraceCheckUtils]: 15: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,375 INFO L290 TraceCheckUtils]: 16: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,375 INFO L290 TraceCheckUtils]: 17: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,376 INFO L290 TraceCheckUtils]: 18: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,376 INFO L290 TraceCheckUtils]: 19: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,376 INFO L290 TraceCheckUtils]: 20: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,376 INFO L290 TraceCheckUtils]: 21: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,377 INFO L290 TraceCheckUtils]: 22: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,377 INFO L290 TraceCheckUtils]: 23: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,377 INFO L290 TraceCheckUtils]: 24: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,377 INFO L290 TraceCheckUtils]: 25: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,378 INFO L290 TraceCheckUtils]: 26: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,378 INFO L290 TraceCheckUtils]: 27: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,378 INFO L290 TraceCheckUtils]: 28: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,378 INFO L290 TraceCheckUtils]: 29: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,379 INFO L290 TraceCheckUtils]: 30: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,379 INFO L290 TraceCheckUtils]: 31: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,379 INFO L290 TraceCheckUtils]: 32: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,379 INFO L290 TraceCheckUtils]: 33: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,380 INFO L290 TraceCheckUtils]: 34: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,380 INFO L290 TraceCheckUtils]: 35: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,380 INFO L290 TraceCheckUtils]: 36: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,380 INFO L290 TraceCheckUtils]: 37: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,380 INFO L290 TraceCheckUtils]: 38: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,381 INFO L290 TraceCheckUtils]: 39: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,381 INFO L290 TraceCheckUtils]: 40: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,381 INFO L290 TraceCheckUtils]: 41: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,381 INFO L290 TraceCheckUtils]: 42: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,382 INFO L290 TraceCheckUtils]: 43: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,382 INFO L290 TraceCheckUtils]: 44: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,382 INFO L290 TraceCheckUtils]: 45: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,382 INFO L290 TraceCheckUtils]: 46: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,383 INFO L290 TraceCheckUtils]: 47: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,383 INFO L290 TraceCheckUtils]: 48: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,383 INFO L290 TraceCheckUtils]: 49: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,383 INFO L290 TraceCheckUtils]: 50: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,384 INFO L290 TraceCheckUtils]: 51: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,384 INFO L290 TraceCheckUtils]: 52: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,384 INFO L290 TraceCheckUtils]: 53: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,384 INFO L290 TraceCheckUtils]: 54: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,385 INFO L290 TraceCheckUtils]: 55: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,385 INFO L290 TraceCheckUtils]: 56: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,385 INFO L290 TraceCheckUtils]: 57: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,385 INFO L290 TraceCheckUtils]: 58: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,385 INFO L290 TraceCheckUtils]: 59: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,386 INFO L290 TraceCheckUtils]: 60: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,386 INFO L290 TraceCheckUtils]: 61: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,386 INFO L290 TraceCheckUtils]: 62: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,386 INFO L290 TraceCheckUtils]: 63: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,387 INFO L290 TraceCheckUtils]: 64: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,387 INFO L290 TraceCheckUtils]: 65: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,387 INFO L290 TraceCheckUtils]: 66: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,387 INFO L290 TraceCheckUtils]: 67: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,388 INFO L290 TraceCheckUtils]: 68: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,388 INFO L290 TraceCheckUtils]: 69: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,388 INFO L290 TraceCheckUtils]: 70: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,388 INFO L290 TraceCheckUtils]: 71: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,389 INFO L290 TraceCheckUtils]: 72: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,389 INFO L290 TraceCheckUtils]: 73: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,397 INFO L290 TraceCheckUtils]: 74: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,399 INFO L290 TraceCheckUtils]: 75: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 76: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4178#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 77: Hoare triple {4178#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 78: Hoare triple {4177#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 79: Hoare triple {4177#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 80: Hoare triple {4177#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 81: Hoare triple {4177#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 82: Hoare triple {4177#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 83: Hoare triple {4177#false} assume 1 == ~E_M~0;~E_M~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 84: Hoare triple {4177#false} assume 1 == ~E_1~0;~E_1~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 85: Hoare triple {4177#false} assume !(1 == ~E_2~0); {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 86: Hoare triple {4177#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 87: Hoare triple {4177#false} assume 1 == ~E_4~0;~E_4~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,400 INFO L290 TraceCheckUtils]: 88: Hoare triple {4177#false} assume 1 == ~E_5~0;~E_5~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 89: Hoare triple {4177#false} assume 1 == ~E_6~0;~E_6~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 90: Hoare triple {4177#false} assume 1 == ~E_7~0;~E_7~0 := 2; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 91: Hoare triple {4177#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 92: Hoare triple {4177#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 93: Hoare triple {4177#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 94: Hoare triple {4177#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 95: Hoare triple {4177#false} assume !(0 == start_simulation_~tmp~3#1); {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 96: Hoare triple {4177#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 97: Hoare triple {4177#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 98: Hoare triple {4177#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 99: Hoare triple {4177#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 100: Hoare triple {4177#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 101: Hoare triple {4177#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 102: Hoare triple {4177#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {4177#false} is VALID [2022-02-21 04:21:56,401 INFO L290 TraceCheckUtils]: 103: Hoare triple {4177#false} assume !(0 != start_simulation_~tmp___0~1#1); {4177#false} is VALID [2022-02-21 04:21:56,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,402 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,402 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1626247105] [2022-02-21 04:21:56,402 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1626247105] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,402 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,402 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,402 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1675998106] [2022-02-21 04:21:56,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:56,403 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:56,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:56,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:56,404 INFO L87 Difference]: Start difference. First operand 830 states and 1240 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:56,975 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2022-02-21 04:21:56,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:56,976 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,023 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:57,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:57,064 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1239 transitions. [2022-02-21 04:21:57,064 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:57,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:57,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:57,066 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-02-21 04:21:57,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:21:57,080 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:57,081 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1239 transitions. Second operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,083 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1239 transitions. Second operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,084 INFO L87 Difference]: Start difference. First operand 830 states and 1239 transitions. Second operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,113 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2022-02-21 04:21:57,113 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,114 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:57,114 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:57,116 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1239 transitions. [2022-02-21 04:21:57,118 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1239 transitions. [2022-02-21 04:21:57,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,137 INFO L93 Difference]: Finished difference Result 830 states and 1239 transitions. [2022-02-21 04:21:57,137 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,138 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:57,138 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:57,138 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:57,138 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:57,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4927710843373494) internal successors, (1239), 829 states have internal predecessors, (1239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1239 transitions. [2022-02-21 04:21:57,157 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-02-21 04:21:57,158 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1239 transitions. [2022-02-21 04:21:57,158 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:57,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1239 transitions. [2022-02-21 04:21:57,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:57,160 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:57,160 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:57,162 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:57,162 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:57,163 INFO L791 eck$LassoCheckResult]: Stem: 5648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5531#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5481#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5482#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 5765#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5464#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5304#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5305#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5286#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5287#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5764#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5589#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5590#L769 assume !(0 == ~M_E~0); 5612#L769-2 assume !(0 == ~T1_E~0); 5613#L774-1 assume !(0 == ~T2_E~0); 5640#L779-1 assume !(0 == ~T3_E~0); 5752#L784-1 assume !(0 == ~T4_E~0); 5585#L789-1 assume !(0 == ~T5_E~0); 5586#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5696#L799-1 assume !(0 == ~T7_E~0); 5592#L804-1 assume !(0 == ~E_M~0); 5593#L809-1 assume !(0 == ~E_1~0); 5633#L814-1 assume !(0 == ~E_2~0); 5022#L819-1 assume !(0 == ~E_3~0); 5023#L824-1 assume !(0 == ~E_4~0); 5374#L829-1 assume !(0 == ~E_5~0); 5811#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5158#L839-1 assume !(0 == ~E_7~0); 5159#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5537#L376 assume !(1 == ~m_pc~0); 5524#L376-2 is_master_triggered_~__retres1~0#1 := 0; 5523#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5794#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5105#L955 assume !(0 != activate_threads_~tmp~1#1); 5106#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5457#L395 assume 1 == ~t1_pc~0; 5135#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5136#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5028#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5029#L963 assume !(0 != activate_threads_~tmp___0~0#1); 5541#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5542#L414 assume !(1 == ~t2_pc~0); 5161#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5162#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5360#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5361#L971 assume !(0 != activate_threads_~tmp___1~0#1); 5768#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5460#L433 assume 1 == ~t3_pc~0; 5405#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5275#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5433#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5434#L979 assume !(0 != activate_threads_~tmp___2~0#1); 5126#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5127#L452 assume !(1 == ~t4_pc~0); 5282#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5283#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5573#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5639#L987 assume !(0 != activate_threads_~tmp___3~0#1); 5315#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5316#L471 assume 1 == ~t5_pc~0; 5684#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5298#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5299#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5634#L995 assume !(0 != activate_threads_~tmp___4~0#1); 5803#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5804#L490 assume 1 == ~t6_pc~0; 5787#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5540#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5580#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5583#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 5469#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5438#L509 assume !(1 == ~t7_pc~0); 5439#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5256#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5257#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5320#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5321#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5776#L857 assume !(1 == ~M_E~0); 5112#L857-2 assume !(1 == ~T1_E~0); 5113#L862-1 assume !(1 == ~T2_E~0); 5382#L867-1 assume !(1 == ~T3_E~0); 5387#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5461#L877-1 assume !(1 == ~T5_E~0); 5660#L882-1 assume !(1 == ~T6_E~0); 5786#L887-1 assume !(1 == ~T7_E~0); 5710#L892-1 assume !(1 == ~E_M~0); 5711#L897-1 assume !(1 == ~E_1~0); 5397#L902-1 assume !(1 == ~E_2~0); 5398#L907-1 assume !(1 == ~E_3~0); 5677#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5668#L917-1 assume !(1 == ~E_5~0); 5669#L922-1 assume !(1 == ~E_6~0); 5814#L927-1 assume !(1 == ~E_7~0); 5655#L932-1 assume { :end_inline_reset_delta_events } true; 5061#L1178-2 [2022-02-21 04:21:57,163 INFO L793 eck$LassoCheckResult]: Loop: 5061#L1178-2 assume !false; 5644#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5078#L744 assume !false; 5432#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5505#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5096#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5302#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5756#L641 assume !(0 != eval_~tmp~0#1); 5572#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5196#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5197#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5458#L769-5 assume !(0 == ~T1_E~0); 5459#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5213#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5037#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5038#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5024#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5025#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5076#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5330#L809-3 assume !(0 == ~E_1~0); 5072#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5073#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5732#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5727#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5383#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5384#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5695#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5774#L376-27 assume 1 == ~m_pc~0; 5673#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5619#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5620#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5714#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5817#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5838#L395-27 assume !(1 == ~t1_pc~0); 5477#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5385#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5386#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5611#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5465#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5466#L414-27 assume 1 == ~t2_pc~0; 5801#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5666#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5667#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5526#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5088#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5089#L433-27 assume !(1 == ~t3_pc~0); 5184#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 5471#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5472#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5259#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 5260#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5831#L452-27 assume 1 == ~t4_pc~0; 5832#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5631#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5755#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5797#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5798#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5079#L471-27 assume !(1 == ~t5_pc~0); 5080#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 5394#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5773#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5687#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5615#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5536#L490-27 assume 1 == ~t6_pc~0; 5435#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5271#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5272#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5675#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5676#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5046#L509-27 assume !(1 == ~t7_pc~0); 5047#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5437#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5562#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5553#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5554#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5568#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5569#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5609#L862-3 assume !(1 == ~T2_E~0); 5829#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5473#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5474#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5563#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5603#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5233#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5234#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5747#L902-3 assume !(1 == ~E_2~0); 5395#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5396#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5515#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5478#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5284#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5285#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5133#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5036#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5698#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5448#L1197 assume !(0 == start_simulation_~tmp~3#1); 5449#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5192#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5156#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5082#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 5083#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5744#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5745#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5060#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 5061#L1178-2 [2022-02-21 04:21:57,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:57,164 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-02-21 04:21:57,164 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:57,164 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902514725] [2022-02-21 04:21:57,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:57,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:57,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:57,215 INFO L290 TraceCheckUtils]: 0: Hoare triple {7502#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {7502#true} is VALID [2022-02-21 04:21:57,215 INFO L290 TraceCheckUtils]: 1: Hoare triple {7502#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,216 INFO L290 TraceCheckUtils]: 2: Hoare triple {7504#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,216 INFO L290 TraceCheckUtils]: 3: Hoare triple {7504#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,216 INFO L290 TraceCheckUtils]: 4: Hoare triple {7504#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,216 INFO L290 TraceCheckUtils]: 5: Hoare triple {7504#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 6: Hoare triple {7504#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {7504#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 7: Hoare triple {7504#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 8: Hoare triple {7503#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 9: Hoare triple {7503#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 10: Hoare triple {7503#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,217 INFO L290 TraceCheckUtils]: 11: Hoare triple {7503#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,218 INFO L290 TraceCheckUtils]: 12: Hoare triple {7503#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7503#false} is VALID [2022-02-21 04:21:57,218 INFO L290 TraceCheckUtils]: 13: Hoare triple {7503#false} assume !(0 == ~M_E~0); {7503#false} is VALID [2022-02-21 04:21:57,218 INFO L290 TraceCheckUtils]: 14: Hoare triple {7503#false} assume !(0 == ~T1_E~0); {7503#false} is VALID [2022-02-21 04:21:57,218 INFO L290 TraceCheckUtils]: 15: Hoare triple {7503#false} assume !(0 == ~T2_E~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 16: Hoare triple {7503#false} assume !(0 == ~T3_E~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 17: Hoare triple {7503#false} assume !(0 == ~T4_E~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 18: Hoare triple {7503#false} assume !(0 == ~T5_E~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 19: Hoare triple {7503#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 20: Hoare triple {7503#false} assume !(0 == ~T7_E~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 21: Hoare triple {7503#false} assume !(0 == ~E_M~0); {7503#false} is VALID [2022-02-21 04:21:57,219 INFO L290 TraceCheckUtils]: 22: Hoare triple {7503#false} assume !(0 == ~E_1~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 23: Hoare triple {7503#false} assume !(0 == ~E_2~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 24: Hoare triple {7503#false} assume !(0 == ~E_3~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 25: Hoare triple {7503#false} assume !(0 == ~E_4~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 26: Hoare triple {7503#false} assume !(0 == ~E_5~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 27: Hoare triple {7503#false} assume 0 == ~E_6~0;~E_6~0 := 1; {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 28: Hoare triple {7503#false} assume !(0 == ~E_7~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 29: Hoare triple {7503#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 30: Hoare triple {7503#false} assume !(1 == ~m_pc~0); {7503#false} is VALID [2022-02-21 04:21:57,221 INFO L290 TraceCheckUtils]: 31: Hoare triple {7503#false} is_master_triggered_~__retres1~0#1 := 0; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 32: Hoare triple {7503#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 33: Hoare triple {7503#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 34: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp~1#1); {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 35: Hoare triple {7503#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 36: Hoare triple {7503#false} assume 1 == ~t1_pc~0; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 37: Hoare triple {7503#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 38: Hoare triple {7503#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7503#false} is VALID [2022-02-21 04:21:57,222 INFO L290 TraceCheckUtils]: 39: Hoare triple {7503#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 40: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___0~0#1); {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 41: Hoare triple {7503#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 42: Hoare triple {7503#false} assume !(1 == ~t2_pc~0); {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 43: Hoare triple {7503#false} is_transmit2_triggered_~__retres1~2#1 := 0; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 44: Hoare triple {7503#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 45: Hoare triple {7503#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 46: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___1~0#1); {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 47: Hoare triple {7503#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7503#false} is VALID [2022-02-21 04:21:57,223 INFO L290 TraceCheckUtils]: 48: Hoare triple {7503#false} assume 1 == ~t3_pc~0; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 49: Hoare triple {7503#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 50: Hoare triple {7503#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 51: Hoare triple {7503#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 52: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___2~0#1); {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 53: Hoare triple {7503#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 54: Hoare triple {7503#false} assume !(1 == ~t4_pc~0); {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 55: Hoare triple {7503#false} is_transmit4_triggered_~__retres1~4#1 := 0; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 56: Hoare triple {7503#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7503#false} is VALID [2022-02-21 04:21:57,224 INFO L290 TraceCheckUtils]: 57: Hoare triple {7503#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 58: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___3~0#1); {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 59: Hoare triple {7503#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 60: Hoare triple {7503#false} assume 1 == ~t5_pc~0; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 61: Hoare triple {7503#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 62: Hoare triple {7503#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 63: Hoare triple {7503#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 64: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___4~0#1); {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 65: Hoare triple {7503#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7503#false} is VALID [2022-02-21 04:21:57,225 INFO L290 TraceCheckUtils]: 66: Hoare triple {7503#false} assume 1 == ~t6_pc~0; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 67: Hoare triple {7503#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 68: Hoare triple {7503#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 69: Hoare triple {7503#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 70: Hoare triple {7503#false} assume !(0 != activate_threads_~tmp___5~0#1); {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 71: Hoare triple {7503#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 72: Hoare triple {7503#false} assume !(1 == ~t7_pc~0); {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 73: Hoare triple {7503#false} is_transmit7_triggered_~__retres1~7#1 := 0; {7503#false} is VALID [2022-02-21 04:21:57,226 INFO L290 TraceCheckUtils]: 74: Hoare triple {7503#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 75: Hoare triple {7503#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 76: Hoare triple {7503#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 77: Hoare triple {7503#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 78: Hoare triple {7503#false} assume !(1 == ~M_E~0); {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 79: Hoare triple {7503#false} assume !(1 == ~T1_E~0); {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 80: Hoare triple {7503#false} assume !(1 == ~T2_E~0); {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 81: Hoare triple {7503#false} assume !(1 == ~T3_E~0); {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 82: Hoare triple {7503#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,227 INFO L290 TraceCheckUtils]: 83: Hoare triple {7503#false} assume !(1 == ~T5_E~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 84: Hoare triple {7503#false} assume !(1 == ~T6_E~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 85: Hoare triple {7503#false} assume !(1 == ~T7_E~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 86: Hoare triple {7503#false} assume !(1 == ~E_M~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 87: Hoare triple {7503#false} assume !(1 == ~E_1~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 88: Hoare triple {7503#false} assume !(1 == ~E_2~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 89: Hoare triple {7503#false} assume !(1 == ~E_3~0); {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 90: Hoare triple {7503#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7503#false} is VALID [2022-02-21 04:21:57,228 INFO L290 TraceCheckUtils]: 91: Hoare triple {7503#false} assume !(1 == ~E_5~0); {7503#false} is VALID [2022-02-21 04:21:57,229 INFO L290 TraceCheckUtils]: 92: Hoare triple {7503#false} assume !(1 == ~E_6~0); {7503#false} is VALID [2022-02-21 04:21:57,229 INFO L290 TraceCheckUtils]: 93: Hoare triple {7503#false} assume !(1 == ~E_7~0); {7503#false} is VALID [2022-02-21 04:21:57,229 INFO L290 TraceCheckUtils]: 94: Hoare triple {7503#false} assume { :end_inline_reset_delta_events } true; {7503#false} is VALID [2022-02-21 04:21:57,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:57,230 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:57,230 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902514725] [2022-02-21 04:21:57,230 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902514725] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:57,230 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:57,231 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:57,231 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1244423974] [2022-02-21 04:21:57,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:57,231 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:57,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:57,232 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 1 times [2022-02-21 04:21:57,232 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:57,232 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656169978] [2022-02-21 04:21:57,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:57,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:57,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:57,314 INFO L290 TraceCheckUtils]: 0: Hoare triple {7505#true} assume !false; {7505#true} is VALID [2022-02-21 04:21:57,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {7505#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7505#true} is VALID [2022-02-21 04:21:57,314 INFO L290 TraceCheckUtils]: 2: Hoare triple {7505#true} assume !false; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 3: Hoare triple {7505#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 4: Hoare triple {7505#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 5: Hoare triple {7505#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 6: Hoare triple {7505#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 7: Hoare triple {7505#true} assume !(0 != eval_~tmp~0#1); {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 8: Hoare triple {7505#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 9: Hoare triple {7505#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 10: Hoare triple {7505#true} assume 0 == ~M_E~0;~M_E~0 := 1; {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 11: Hoare triple {7505#true} assume !(0 == ~T1_E~0); {7505#true} is VALID [2022-02-21 04:21:57,315 INFO L290 TraceCheckUtils]: 12: Hoare triple {7505#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,316 INFO L290 TraceCheckUtils]: 13: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,317 INFO L290 TraceCheckUtils]: 14: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,321 INFO L290 TraceCheckUtils]: 15: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,322 INFO L290 TraceCheckUtils]: 16: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,322 INFO L290 TraceCheckUtils]: 17: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,322 INFO L290 TraceCheckUtils]: 18: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,322 INFO L290 TraceCheckUtils]: 19: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,323 INFO L290 TraceCheckUtils]: 20: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,323 INFO L290 TraceCheckUtils]: 21: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,323 INFO L290 TraceCheckUtils]: 22: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,324 INFO L290 TraceCheckUtils]: 23: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,324 INFO L290 TraceCheckUtils]: 24: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,324 INFO L290 TraceCheckUtils]: 25: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,325 INFO L290 TraceCheckUtils]: 26: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,325 INFO L290 TraceCheckUtils]: 27: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,325 INFO L290 TraceCheckUtils]: 28: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,326 INFO L290 TraceCheckUtils]: 29: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,326 INFO L290 TraceCheckUtils]: 30: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,326 INFO L290 TraceCheckUtils]: 31: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,327 INFO L290 TraceCheckUtils]: 32: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,327 INFO L290 TraceCheckUtils]: 33: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,327 INFO L290 TraceCheckUtils]: 34: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,328 INFO L290 TraceCheckUtils]: 35: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,328 INFO L290 TraceCheckUtils]: 36: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,328 INFO L290 TraceCheckUtils]: 37: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,329 INFO L290 TraceCheckUtils]: 38: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,331 INFO L290 TraceCheckUtils]: 39: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,331 INFO L290 TraceCheckUtils]: 40: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,331 INFO L290 TraceCheckUtils]: 41: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,332 INFO L290 TraceCheckUtils]: 42: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,332 INFO L290 TraceCheckUtils]: 43: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,332 INFO L290 TraceCheckUtils]: 44: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,332 INFO L290 TraceCheckUtils]: 45: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,332 INFO L290 TraceCheckUtils]: 46: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,333 INFO L290 TraceCheckUtils]: 47: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,333 INFO L290 TraceCheckUtils]: 48: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,333 INFO L290 TraceCheckUtils]: 49: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,333 INFO L290 TraceCheckUtils]: 50: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,334 INFO L290 TraceCheckUtils]: 51: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,334 INFO L290 TraceCheckUtils]: 52: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,334 INFO L290 TraceCheckUtils]: 53: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,334 INFO L290 TraceCheckUtils]: 54: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,335 INFO L290 TraceCheckUtils]: 55: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,335 INFO L290 TraceCheckUtils]: 56: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,335 INFO L290 TraceCheckUtils]: 57: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,335 INFO L290 TraceCheckUtils]: 58: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,335 INFO L290 TraceCheckUtils]: 59: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,336 INFO L290 TraceCheckUtils]: 60: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,336 INFO L290 TraceCheckUtils]: 61: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,336 INFO L290 TraceCheckUtils]: 62: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,336 INFO L290 TraceCheckUtils]: 63: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,337 INFO L290 TraceCheckUtils]: 64: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,337 INFO L290 TraceCheckUtils]: 65: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,337 INFO L290 TraceCheckUtils]: 66: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,337 INFO L290 TraceCheckUtils]: 67: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,338 INFO L290 TraceCheckUtils]: 68: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,338 INFO L290 TraceCheckUtils]: 69: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,338 INFO L290 TraceCheckUtils]: 70: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,338 INFO L290 TraceCheckUtils]: 71: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,338 INFO L290 TraceCheckUtils]: 72: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,339 INFO L290 TraceCheckUtils]: 73: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,339 INFO L290 TraceCheckUtils]: 74: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,339 INFO L290 TraceCheckUtils]: 75: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,339 INFO L290 TraceCheckUtils]: 76: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {7507#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 77: Hoare triple {7507#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 78: Hoare triple {7506#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 79: Hoare triple {7506#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 80: Hoare triple {7506#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 81: Hoare triple {7506#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 82: Hoare triple {7506#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 83: Hoare triple {7506#false} assume 1 == ~E_M~0;~E_M~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 84: Hoare triple {7506#false} assume 1 == ~E_1~0;~E_1~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 85: Hoare triple {7506#false} assume !(1 == ~E_2~0); {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 86: Hoare triple {7506#false} assume 1 == ~E_3~0;~E_3~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 87: Hoare triple {7506#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 88: Hoare triple {7506#false} assume 1 == ~E_5~0;~E_5~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 89: Hoare triple {7506#false} assume 1 == ~E_6~0;~E_6~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 90: Hoare triple {7506#false} assume 1 == ~E_7~0;~E_7~0 := 2; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 91: Hoare triple {7506#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 92: Hoare triple {7506#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 93: Hoare triple {7506#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 94: Hoare triple {7506#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {7506#false} is VALID [2022-02-21 04:21:57,340 INFO L290 TraceCheckUtils]: 95: Hoare triple {7506#false} assume !(0 == start_simulation_~tmp~3#1); {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 96: Hoare triple {7506#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 97: Hoare triple {7506#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 98: Hoare triple {7506#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 99: Hoare triple {7506#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 100: Hoare triple {7506#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 101: Hoare triple {7506#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 102: Hoare triple {7506#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L290 TraceCheckUtils]: 103: Hoare triple {7506#false} assume !(0 != start_simulation_~tmp___0~1#1); {7506#false} is VALID [2022-02-21 04:21:57,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:57,341 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:57,341 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [656169978] [2022-02-21 04:21:57,341 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [656169978] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:57,342 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:57,342 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:57,342 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726112547] [2022-02-21 04:21:57,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:57,342 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:57,342 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:57,342 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:57,343 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:57,343 INFO L87 Difference]: Start difference. First operand 830 states and 1239 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:57,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:57,955 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2022-02-21 04:21:57,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:57,955 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,015 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:58,017 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,039 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:58,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1238 transitions. [2022-02-21 04:21:58,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:58,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:58,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:58,060 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-02-21 04:21:58,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:21:58,069 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:58,071 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1238 transitions. Second operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,073 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1238 transitions. Second operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,074 INFO L87 Difference]: Start difference. First operand 830 states and 1238 transitions. Second operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,095 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2022-02-21 04:21:58,095 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,096 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,096 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,098 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1238 transitions. [2022-02-21 04:21:58,099 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1238 transitions. [2022-02-21 04:21:58,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,118 INFO L93 Difference]: Finished difference Result 830 states and 1238 transitions. [2022-02-21 04:21:58,118 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,119 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,119 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,119 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:58,119 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:58,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.491566265060241) internal successors, (1238), 829 states have internal predecessors, (1238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1238 transitions. [2022-02-21 04:21:58,138 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-02-21 04:21:58,138 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1238 transitions. [2022-02-21 04:21:58,138 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:21:58,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1238 transitions. [2022-02-21 04:21:58,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:58,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:58,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:58,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,145 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,146 INFO L791 eck$LassoCheckResult]: Stem: 8977#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8860#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8810#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8811#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 9094#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8793#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8633#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8634#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8615#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8616#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9093#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8918#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8919#L769 assume !(0 == ~M_E~0); 8941#L769-2 assume !(0 == ~T1_E~0); 8942#L774-1 assume !(0 == ~T2_E~0); 8969#L779-1 assume !(0 == ~T3_E~0); 9081#L784-1 assume !(0 == ~T4_E~0); 8914#L789-1 assume !(0 == ~T5_E~0); 8915#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9025#L799-1 assume !(0 == ~T7_E~0); 8921#L804-1 assume !(0 == ~E_M~0); 8922#L809-1 assume !(0 == ~E_1~0); 8962#L814-1 assume !(0 == ~E_2~0); 8353#L819-1 assume !(0 == ~E_3~0); 8354#L824-1 assume !(0 == ~E_4~0); 8703#L829-1 assume !(0 == ~E_5~0); 9140#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8487#L839-1 assume !(0 == ~E_7~0); 8488#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8866#L376 assume !(1 == ~m_pc~0); 8853#L376-2 is_master_triggered_~__retres1~0#1 := 0; 8852#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9123#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8434#L955 assume !(0 != activate_threads_~tmp~1#1); 8435#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8786#L395 assume 1 == ~t1_pc~0; 8464#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8465#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8357#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8358#L963 assume !(0 != activate_threads_~tmp___0~0#1); 8870#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8871#L414 assume !(1 == ~t2_pc~0); 8490#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8491#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8689#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8690#L971 assume !(0 != activate_threads_~tmp___1~0#1); 9097#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8789#L433 assume 1 == ~t3_pc~0; 8734#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8606#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8764#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8765#L979 assume !(0 != activate_threads_~tmp___2~0#1); 8455#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8456#L452 assume !(1 == ~t4_pc~0); 8611#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8612#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8902#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8968#L987 assume !(0 != activate_threads_~tmp___3~0#1); 8644#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8645#L471 assume 1 == ~t5_pc~0; 9013#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8627#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8628#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8963#L995 assume !(0 != activate_threads_~tmp___4~0#1); 9132#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9133#L490 assume 1 == ~t6_pc~0; 9116#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8869#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8909#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8912#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 8798#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8767#L509 assume !(1 == ~t7_pc~0); 8768#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8587#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8588#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8649#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8650#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9105#L857 assume !(1 == ~M_E~0); 8441#L857-2 assume !(1 == ~T1_E~0); 8442#L862-1 assume !(1 == ~T2_E~0); 8711#L867-1 assume !(1 == ~T3_E~0); 8716#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8790#L877-1 assume !(1 == ~T5_E~0); 8989#L882-1 assume !(1 == ~T6_E~0); 9115#L887-1 assume !(1 == ~T7_E~0); 9039#L892-1 assume !(1 == ~E_M~0); 9040#L897-1 assume !(1 == ~E_1~0); 8726#L902-1 assume !(1 == ~E_2~0); 8727#L907-1 assume !(1 == ~E_3~0); 9008#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8997#L917-1 assume !(1 == ~E_5~0); 8998#L922-1 assume !(1 == ~E_6~0); 9143#L927-1 assume !(1 == ~E_7~0); 8984#L932-1 assume { :end_inline_reset_delta_events } true; 8390#L1178-2 [2022-02-21 04:21:58,146 INFO L793 eck$LassoCheckResult]: Loop: 8390#L1178-2 assume !false; 8973#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8407#L744 assume !false; 8761#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8835#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8425#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8631#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9087#L641 assume !(0 != eval_~tmp~0#1); 8901#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8525#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8526#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8787#L769-5 assume !(0 == ~T1_E~0); 8788#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8542#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8366#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8367#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8355#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8356#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8405#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8660#L809-3 assume !(0 == ~E_1~0); 8401#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8402#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9061#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9056#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8712#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8713#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9024#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9103#L376-27 assume 1 == ~m_pc~0; 9002#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8948#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8949#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9043#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9146#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9167#L395-27 assume !(1 == ~t1_pc~0); 8807#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 8714#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8715#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8940#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8794#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8795#L414-27 assume 1 == ~t2_pc~0; 9130#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8995#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8996#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8855#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8417#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8418#L433-27 assume !(1 == ~t3_pc~0); 8513#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 8800#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8801#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8590#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 8591#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9160#L452-27 assume 1 == ~t4_pc~0; 9161#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8960#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9084#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9126#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9127#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8408#L471-27 assume !(1 == ~t5_pc~0); 8409#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 8723#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9102#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9016#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8944#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8865#L490-27 assume 1 == ~t6_pc~0; 8762#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8600#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8601#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9004#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9005#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8375#L509-27 assume !(1 == ~t7_pc~0); 8376#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8766#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8891#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8882#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8883#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8897#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8898#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8936#L862-3 assume !(1 == ~T2_E~0); 9158#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8802#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8803#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8892#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8931#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8560#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8561#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9076#L902-3 assume !(1 == ~E_2~0); 8724#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8725#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8844#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8806#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8613#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8614#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8462#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8363#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9027#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8776#L1197 assume !(0 == start_simulation_~tmp~3#1); 8777#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8518#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8485#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8411#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 8412#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9073#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9074#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8389#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 8390#L1178-2 [2022-02-21 04:21:58,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-02-21 04:21:58,148 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,148 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132383542] [2022-02-21 04:21:58,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,191 INFO L290 TraceCheckUtils]: 0: Hoare triple {10831#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {10831#true} is VALID [2022-02-21 04:21:58,191 INFO L290 TraceCheckUtils]: 1: Hoare triple {10831#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,192 INFO L290 TraceCheckUtils]: 2: Hoare triple {10833#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,192 INFO L290 TraceCheckUtils]: 3: Hoare triple {10833#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,192 INFO L290 TraceCheckUtils]: 4: Hoare triple {10833#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,192 INFO L290 TraceCheckUtils]: 5: Hoare triple {10833#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 6: Hoare triple {10833#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 7: Hoare triple {10833#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10833#(= ~t4_i~0 1)} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 8: Hoare triple {10833#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 9: Hoare triple {10832#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 10: Hoare triple {10832#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,193 INFO L290 TraceCheckUtils]: 11: Hoare triple {10832#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 12: Hoare triple {10832#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 13: Hoare triple {10832#false} assume !(0 == ~M_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 14: Hoare triple {10832#false} assume !(0 == ~T1_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 15: Hoare triple {10832#false} assume !(0 == ~T2_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 16: Hoare triple {10832#false} assume !(0 == ~T3_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 17: Hoare triple {10832#false} assume !(0 == ~T4_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 18: Hoare triple {10832#false} assume !(0 == ~T5_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 19: Hoare triple {10832#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 20: Hoare triple {10832#false} assume !(0 == ~T7_E~0); {10832#false} is VALID [2022-02-21 04:21:58,194 INFO L290 TraceCheckUtils]: 21: Hoare triple {10832#false} assume !(0 == ~E_M~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 22: Hoare triple {10832#false} assume !(0 == ~E_1~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 23: Hoare triple {10832#false} assume !(0 == ~E_2~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 24: Hoare triple {10832#false} assume !(0 == ~E_3~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 25: Hoare triple {10832#false} assume !(0 == ~E_4~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 26: Hoare triple {10832#false} assume !(0 == ~E_5~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 27: Hoare triple {10832#false} assume 0 == ~E_6~0;~E_6~0 := 1; {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 28: Hoare triple {10832#false} assume !(0 == ~E_7~0); {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 29: Hoare triple {10832#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10832#false} is VALID [2022-02-21 04:21:58,195 INFO L290 TraceCheckUtils]: 30: Hoare triple {10832#false} assume !(1 == ~m_pc~0); {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 31: Hoare triple {10832#false} is_master_triggered_~__retres1~0#1 := 0; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 32: Hoare triple {10832#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 33: Hoare triple {10832#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 34: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp~1#1); {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 35: Hoare triple {10832#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 36: Hoare triple {10832#false} assume 1 == ~t1_pc~0; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 37: Hoare triple {10832#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 38: Hoare triple {10832#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 39: Hoare triple {10832#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10832#false} is VALID [2022-02-21 04:21:58,196 INFO L290 TraceCheckUtils]: 40: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___0~0#1); {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 41: Hoare triple {10832#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 42: Hoare triple {10832#false} assume !(1 == ~t2_pc~0); {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 43: Hoare triple {10832#false} is_transmit2_triggered_~__retres1~2#1 := 0; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 44: Hoare triple {10832#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 45: Hoare triple {10832#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 46: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___1~0#1); {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 47: Hoare triple {10832#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 48: Hoare triple {10832#false} assume 1 == ~t3_pc~0; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 49: Hoare triple {10832#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10832#false} is VALID [2022-02-21 04:21:58,197 INFO L290 TraceCheckUtils]: 50: Hoare triple {10832#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 51: Hoare triple {10832#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 52: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___2~0#1); {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 53: Hoare triple {10832#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 54: Hoare triple {10832#false} assume !(1 == ~t4_pc~0); {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 55: Hoare triple {10832#false} is_transmit4_triggered_~__retres1~4#1 := 0; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 56: Hoare triple {10832#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 57: Hoare triple {10832#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 58: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___3~0#1); {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 59: Hoare triple {10832#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10832#false} is VALID [2022-02-21 04:21:58,198 INFO L290 TraceCheckUtils]: 60: Hoare triple {10832#false} assume 1 == ~t5_pc~0; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 61: Hoare triple {10832#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 62: Hoare triple {10832#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 63: Hoare triple {10832#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 64: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___4~0#1); {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 65: Hoare triple {10832#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 66: Hoare triple {10832#false} assume 1 == ~t6_pc~0; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 67: Hoare triple {10832#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 68: Hoare triple {10832#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10832#false} is VALID [2022-02-21 04:21:58,199 INFO L290 TraceCheckUtils]: 69: Hoare triple {10832#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 70: Hoare triple {10832#false} assume !(0 != activate_threads_~tmp___5~0#1); {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 71: Hoare triple {10832#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 72: Hoare triple {10832#false} assume !(1 == ~t7_pc~0); {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 73: Hoare triple {10832#false} is_transmit7_triggered_~__retres1~7#1 := 0; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 74: Hoare triple {10832#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 75: Hoare triple {10832#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 76: Hoare triple {10832#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 77: Hoare triple {10832#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 78: Hoare triple {10832#false} assume !(1 == ~M_E~0); {10832#false} is VALID [2022-02-21 04:21:58,200 INFO L290 TraceCheckUtils]: 79: Hoare triple {10832#false} assume !(1 == ~T1_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 80: Hoare triple {10832#false} assume !(1 == ~T2_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 81: Hoare triple {10832#false} assume !(1 == ~T3_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 82: Hoare triple {10832#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 83: Hoare triple {10832#false} assume !(1 == ~T5_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 84: Hoare triple {10832#false} assume !(1 == ~T6_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 85: Hoare triple {10832#false} assume !(1 == ~T7_E~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 86: Hoare triple {10832#false} assume !(1 == ~E_M~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 87: Hoare triple {10832#false} assume !(1 == ~E_1~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 88: Hoare triple {10832#false} assume !(1 == ~E_2~0); {10832#false} is VALID [2022-02-21 04:21:58,201 INFO L290 TraceCheckUtils]: 89: Hoare triple {10832#false} assume !(1 == ~E_3~0); {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L290 TraceCheckUtils]: 90: Hoare triple {10832#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L290 TraceCheckUtils]: 91: Hoare triple {10832#false} assume !(1 == ~E_5~0); {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L290 TraceCheckUtils]: 92: Hoare triple {10832#false} assume !(1 == ~E_6~0); {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L290 TraceCheckUtils]: 93: Hoare triple {10832#false} assume !(1 == ~E_7~0); {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L290 TraceCheckUtils]: 94: Hoare triple {10832#false} assume { :end_inline_reset_delta_events } true; {10832#false} is VALID [2022-02-21 04:21:58,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,202 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,203 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132383542] [2022-02-21 04:21:58,203 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132383542] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,203 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,203 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,204 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1684255178] [2022-02-21 04:21:58,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,204 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:58,204 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1833724246, now seen corresponding path program 2 times [2022-02-21 04:21:58,205 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,208 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1912064181] [2022-02-21 04:21:58,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,255 INFO L290 TraceCheckUtils]: 0: Hoare triple {10834#true} assume !false; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 1: Hoare triple {10834#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 2: Hoare triple {10834#true} assume !false; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 3: Hoare triple {10834#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 4: Hoare triple {10834#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 5: Hoare triple {10834#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 6: Hoare triple {10834#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 7: Hoare triple {10834#true} assume !(0 != eval_~tmp~0#1); {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 8: Hoare triple {10834#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10834#true} is VALID [2022-02-21 04:21:58,256 INFO L290 TraceCheckUtils]: 9: Hoare triple {10834#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10834#true} is VALID [2022-02-21 04:21:58,257 INFO L290 TraceCheckUtils]: 10: Hoare triple {10834#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10834#true} is VALID [2022-02-21 04:21:58,257 INFO L290 TraceCheckUtils]: 11: Hoare triple {10834#true} assume !(0 == ~T1_E~0); {10834#true} is VALID [2022-02-21 04:21:58,257 INFO L290 TraceCheckUtils]: 12: Hoare triple {10834#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,257 INFO L290 TraceCheckUtils]: 13: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,257 INFO L290 TraceCheckUtils]: 14: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,258 INFO L290 TraceCheckUtils]: 15: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,258 INFO L290 TraceCheckUtils]: 16: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,269 INFO L290 TraceCheckUtils]: 17: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,270 INFO L290 TraceCheckUtils]: 18: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,270 INFO L290 TraceCheckUtils]: 19: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,271 INFO L290 TraceCheckUtils]: 20: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,271 INFO L290 TraceCheckUtils]: 21: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,271 INFO L290 TraceCheckUtils]: 22: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,281 INFO L290 TraceCheckUtils]: 23: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,281 INFO L290 TraceCheckUtils]: 24: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,282 INFO L290 TraceCheckUtils]: 25: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,282 INFO L290 TraceCheckUtils]: 26: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,282 INFO L290 TraceCheckUtils]: 27: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,282 INFO L290 TraceCheckUtils]: 28: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,283 INFO L290 TraceCheckUtils]: 29: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,283 INFO L290 TraceCheckUtils]: 30: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,283 INFO L290 TraceCheckUtils]: 31: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,283 INFO L290 TraceCheckUtils]: 32: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,284 INFO L290 TraceCheckUtils]: 33: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,284 INFO L290 TraceCheckUtils]: 34: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,284 INFO L290 TraceCheckUtils]: 35: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,284 INFO L290 TraceCheckUtils]: 36: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,285 INFO L290 TraceCheckUtils]: 37: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,285 INFO L290 TraceCheckUtils]: 38: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,285 INFO L290 TraceCheckUtils]: 39: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,285 INFO L290 TraceCheckUtils]: 40: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,286 INFO L290 TraceCheckUtils]: 41: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,286 INFO L290 TraceCheckUtils]: 42: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,286 INFO L290 TraceCheckUtils]: 43: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,286 INFO L290 TraceCheckUtils]: 44: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,287 INFO L290 TraceCheckUtils]: 45: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,287 INFO L290 TraceCheckUtils]: 46: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,287 INFO L290 TraceCheckUtils]: 47: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,287 INFO L290 TraceCheckUtils]: 48: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,287 INFO L290 TraceCheckUtils]: 49: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,288 INFO L290 TraceCheckUtils]: 50: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,288 INFO L290 TraceCheckUtils]: 51: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,288 INFO L290 TraceCheckUtils]: 52: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,289 INFO L290 TraceCheckUtils]: 53: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,289 INFO L290 TraceCheckUtils]: 54: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,289 INFO L290 TraceCheckUtils]: 55: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,289 INFO L290 TraceCheckUtils]: 56: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,289 INFO L290 TraceCheckUtils]: 57: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,290 INFO L290 TraceCheckUtils]: 58: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,290 INFO L290 TraceCheckUtils]: 59: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,290 INFO L290 TraceCheckUtils]: 60: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,290 INFO L290 TraceCheckUtils]: 61: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,291 INFO L290 TraceCheckUtils]: 62: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,291 INFO L290 TraceCheckUtils]: 63: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,291 INFO L290 TraceCheckUtils]: 64: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,291 INFO L290 TraceCheckUtils]: 65: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,292 INFO L290 TraceCheckUtils]: 66: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,292 INFO L290 TraceCheckUtils]: 67: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,292 INFO L290 TraceCheckUtils]: 68: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,292 INFO L290 TraceCheckUtils]: 69: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,293 INFO L290 TraceCheckUtils]: 70: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,293 INFO L290 TraceCheckUtils]: 71: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,293 INFO L290 TraceCheckUtils]: 72: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,293 INFO L290 TraceCheckUtils]: 73: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,294 INFO L290 TraceCheckUtils]: 74: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,294 INFO L290 TraceCheckUtils]: 75: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,294 INFO L290 TraceCheckUtils]: 76: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10836#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:58,294 INFO L290 TraceCheckUtils]: 77: Hoare triple {10836#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 78: Hoare triple {10835#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 79: Hoare triple {10835#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 80: Hoare triple {10835#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 81: Hoare triple {10835#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 82: Hoare triple {10835#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 83: Hoare triple {10835#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 84: Hoare triple {10835#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 85: Hoare triple {10835#false} assume !(1 == ~E_2~0); {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 86: Hoare triple {10835#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,295 INFO L290 TraceCheckUtils]: 87: Hoare triple {10835#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 88: Hoare triple {10835#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 89: Hoare triple {10835#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 90: Hoare triple {10835#false} assume 1 == ~E_7~0;~E_7~0 := 2; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 91: Hoare triple {10835#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 92: Hoare triple {10835#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 93: Hoare triple {10835#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 94: Hoare triple {10835#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 95: Hoare triple {10835#false} assume !(0 == start_simulation_~tmp~3#1); {10835#false} is VALID [2022-02-21 04:21:58,296 INFO L290 TraceCheckUtils]: 96: Hoare triple {10835#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 97: Hoare triple {10835#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 98: Hoare triple {10835#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 99: Hoare triple {10835#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 100: Hoare triple {10835#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 101: Hoare triple {10835#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 102: Hoare triple {10835#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {10835#false} is VALID [2022-02-21 04:21:58,297 INFO L290 TraceCheckUtils]: 103: Hoare triple {10835#false} assume !(0 != start_simulation_~tmp___0~1#1); {10835#false} is VALID [2022-02-21 04:21:58,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,298 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,298 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1912064181] [2022-02-21 04:21:58,298 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1912064181] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,299 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,299 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,299 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223077730] [2022-02-21 04:21:58,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,299 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:58,299 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:58,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:58,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:58,300 INFO L87 Difference]: Start difference. First operand 830 states and 1238 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,868 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2022-02-21 04:21:58,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:58,868 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,933 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:58,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1237 transitions. [2022-02-21 04:21:58,954 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:58,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1237 transitions. [2022-02-21 04:21:58,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:58,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:58,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1237 transitions. [2022-02-21 04:21:58,974 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:58,975 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-02-21 04:21:58,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1237 transitions. [2022-02-21 04:21:58,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:21:58,982 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:58,983 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1237 transitions. Second operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,984 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1237 transitions. Second operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,985 INFO L87 Difference]: Start difference. First operand 830 states and 1237 transitions. Second operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,005 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2022-02-21 04:21:59,005 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1237 transitions. [2022-02-21 04:21:59,006 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,006 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,007 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1237 transitions. [2022-02-21 04:21:59,008 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1237 transitions. [2022-02-21 04:21:59,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,027 INFO L93 Difference]: Finished difference Result 830 states and 1237 transitions. [2022-02-21 04:21:59,028 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1237 transitions. [2022-02-21 04:21:59,029 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,029 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,029 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:59,029 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:59,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4903614457831325) internal successors, (1237), 829 states have internal predecessors, (1237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1237 transitions. [2022-02-21 04:21:59,050 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-02-21 04:21:59,050 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1237 transitions. [2022-02-21 04:21:59,050 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:21:59,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1237 transitions. [2022-02-21 04:21:59,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:59,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:59,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:59,054 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,054 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,054 INFO L791 eck$LassoCheckResult]: Stem: 12306#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12307#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12189#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12139#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12140#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 12423#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12122#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11962#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11963#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11944#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11945#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12422#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12247#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12248#L769 assume !(0 == ~M_E~0); 12270#L769-2 assume !(0 == ~T1_E~0); 12271#L774-1 assume !(0 == ~T2_E~0); 12298#L779-1 assume !(0 == ~T3_E~0); 12410#L784-1 assume !(0 == ~T4_E~0); 12243#L789-1 assume !(0 == ~T5_E~0); 12244#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12354#L799-1 assume !(0 == ~T7_E~0); 12250#L804-1 assume !(0 == ~E_M~0); 12251#L809-1 assume !(0 == ~E_1~0); 12291#L814-1 assume !(0 == ~E_2~0); 11680#L819-1 assume !(0 == ~E_3~0); 11681#L824-1 assume !(0 == ~E_4~0); 12032#L829-1 assume !(0 == ~E_5~0); 12469#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11816#L839-1 assume !(0 == ~E_7~0); 11817#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12195#L376 assume !(1 == ~m_pc~0); 12182#L376-2 is_master_triggered_~__retres1~0#1 := 0; 12181#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12452#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11763#L955 assume !(0 != activate_threads_~tmp~1#1); 11764#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12115#L395 assume 1 == ~t1_pc~0; 11793#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11794#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11686#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11687#L963 assume !(0 != activate_threads_~tmp___0~0#1); 12199#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12200#L414 assume !(1 == ~t2_pc~0); 11819#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11820#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12018#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12019#L971 assume !(0 != activate_threads_~tmp___1~0#1); 12426#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12118#L433 assume 1 == ~t3_pc~0; 12063#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11933#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12091#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12092#L979 assume !(0 != activate_threads_~tmp___2~0#1); 11784#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11785#L452 assume !(1 == ~t4_pc~0); 11940#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11941#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12231#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12297#L987 assume !(0 != activate_threads_~tmp___3~0#1); 11973#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11974#L471 assume 1 == ~t5_pc~0; 12342#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11956#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11957#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12292#L995 assume !(0 != activate_threads_~tmp___4~0#1); 12461#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12462#L490 assume 1 == ~t6_pc~0; 12445#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12198#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12238#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12241#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 12127#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12096#L509 assume !(1 == ~t7_pc~0); 12097#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11914#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11915#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11978#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11979#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12434#L857 assume !(1 == ~M_E~0); 11770#L857-2 assume !(1 == ~T1_E~0); 11771#L862-1 assume !(1 == ~T2_E~0); 12040#L867-1 assume !(1 == ~T3_E~0); 12045#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12119#L877-1 assume !(1 == ~T5_E~0); 12318#L882-1 assume !(1 == ~T6_E~0); 12444#L887-1 assume !(1 == ~T7_E~0); 12368#L892-1 assume !(1 == ~E_M~0); 12369#L897-1 assume !(1 == ~E_1~0); 12055#L902-1 assume !(1 == ~E_2~0); 12056#L907-1 assume !(1 == ~E_3~0); 12335#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12326#L917-1 assume !(1 == ~E_5~0); 12327#L922-1 assume !(1 == ~E_6~0); 12472#L927-1 assume !(1 == ~E_7~0); 12313#L932-1 assume { :end_inline_reset_delta_events } true; 11719#L1178-2 [2022-02-21 04:21:59,054 INFO L793 eck$LassoCheckResult]: Loop: 11719#L1178-2 assume !false; 12302#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11736#L744 assume !false; 12090#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12163#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11754#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11960#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12414#L641 assume !(0 != eval_~tmp~0#1); 12230#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11854#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11855#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12116#L769-5 assume !(0 == ~T1_E~0); 12117#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11871#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11695#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11696#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11682#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11683#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11734#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11988#L809-3 assume !(0 == ~E_1~0); 11730#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11731#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12390#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12385#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12041#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12042#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12353#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12432#L376-27 assume 1 == ~m_pc~0; 12331#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12277#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12278#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12372#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12475#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12496#L395-27 assume !(1 == ~t1_pc~0); 12135#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 12043#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12044#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12269#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12123#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12124#L414-27 assume 1 == ~t2_pc~0; 12459#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12324#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12325#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12184#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11746#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11747#L433-27 assume !(1 == ~t3_pc~0); 11842#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 12129#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12130#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11917#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 11918#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12489#L452-27 assume !(1 == ~t4_pc~0); 12288#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 12289#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12413#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12455#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12456#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11737#L471-27 assume !(1 == ~t5_pc~0); 11738#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 12052#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12431#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12345#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12273#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12194#L490-27 assume 1 == ~t6_pc~0; 12093#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11930#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12333#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12334#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11704#L509-27 assume !(1 == ~t7_pc~0); 11705#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12095#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12220#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12211#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12212#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12226#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12227#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12267#L862-3 assume !(1 == ~T2_E~0); 12487#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12131#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12132#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12221#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12261#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11891#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11892#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12405#L902-3 assume !(1 == ~E_2~0); 12053#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12054#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12173#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12136#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11942#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11943#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11791#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11694#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12356#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12106#L1197 assume !(0 == start_simulation_~tmp~3#1); 12107#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11850#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11814#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11740#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 11741#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12402#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12403#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11718#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 11719#L1178-2 [2022-02-21 04:21:59,055 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-02-21 04:21:59,055 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,055 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360872367] [2022-02-21 04:21:59,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,073 INFO L290 TraceCheckUtils]: 0: Hoare triple {14160#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {14160#true} is VALID [2022-02-21 04:21:59,073 INFO L290 TraceCheckUtils]: 1: Hoare triple {14160#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,074 INFO L290 TraceCheckUtils]: 2: Hoare triple {14162#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,074 INFO L290 TraceCheckUtils]: 3: Hoare triple {14162#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,074 INFO L290 TraceCheckUtils]: 4: Hoare triple {14162#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,074 INFO L290 TraceCheckUtils]: 5: Hoare triple {14162#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,075 INFO L290 TraceCheckUtils]: 6: Hoare triple {14162#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,075 INFO L290 TraceCheckUtils]: 7: Hoare triple {14162#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,075 INFO L290 TraceCheckUtils]: 8: Hoare triple {14162#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {14162#(= ~t5_i~0 1)} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 9: Hoare triple {14162#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 10: Hoare triple {14161#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 11: Hoare triple {14161#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 12: Hoare triple {14161#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 13: Hoare triple {14161#false} assume !(0 == ~M_E~0); {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 14: Hoare triple {14161#false} assume !(0 == ~T1_E~0); {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 15: Hoare triple {14161#false} assume !(0 == ~T2_E~0); {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 16: Hoare triple {14161#false} assume !(0 == ~T3_E~0); {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 17: Hoare triple {14161#false} assume !(0 == ~T4_E~0); {14161#false} is VALID [2022-02-21 04:21:59,076 INFO L290 TraceCheckUtils]: 18: Hoare triple {14161#false} assume !(0 == ~T5_E~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 19: Hoare triple {14161#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 20: Hoare triple {14161#false} assume !(0 == ~T7_E~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 21: Hoare triple {14161#false} assume !(0 == ~E_M~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 22: Hoare triple {14161#false} assume !(0 == ~E_1~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 23: Hoare triple {14161#false} assume !(0 == ~E_2~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 24: Hoare triple {14161#false} assume !(0 == ~E_3~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 25: Hoare triple {14161#false} assume !(0 == ~E_4~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 26: Hoare triple {14161#false} assume !(0 == ~E_5~0); {14161#false} is VALID [2022-02-21 04:21:59,077 INFO L290 TraceCheckUtils]: 27: Hoare triple {14161#false} assume 0 == ~E_6~0;~E_6~0 := 1; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 28: Hoare triple {14161#false} assume !(0 == ~E_7~0); {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 29: Hoare triple {14161#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 30: Hoare triple {14161#false} assume !(1 == ~m_pc~0); {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 31: Hoare triple {14161#false} is_master_triggered_~__retres1~0#1 := 0; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 32: Hoare triple {14161#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 33: Hoare triple {14161#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 34: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp~1#1); {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 35: Hoare triple {14161#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 36: Hoare triple {14161#false} assume 1 == ~t1_pc~0; {14161#false} is VALID [2022-02-21 04:21:59,078 INFO L290 TraceCheckUtils]: 37: Hoare triple {14161#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 38: Hoare triple {14161#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 39: Hoare triple {14161#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 40: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___0~0#1); {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 41: Hoare triple {14161#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 42: Hoare triple {14161#false} assume !(1 == ~t2_pc~0); {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 43: Hoare triple {14161#false} is_transmit2_triggered_~__retres1~2#1 := 0; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 44: Hoare triple {14161#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 45: Hoare triple {14161#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14161#false} is VALID [2022-02-21 04:21:59,079 INFO L290 TraceCheckUtils]: 46: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___1~0#1); {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 47: Hoare triple {14161#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 48: Hoare triple {14161#false} assume 1 == ~t3_pc~0; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 49: Hoare triple {14161#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 50: Hoare triple {14161#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 51: Hoare triple {14161#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 52: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___2~0#1); {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 53: Hoare triple {14161#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 54: Hoare triple {14161#false} assume !(1 == ~t4_pc~0); {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 55: Hoare triple {14161#false} is_transmit4_triggered_~__retres1~4#1 := 0; {14161#false} is VALID [2022-02-21 04:21:59,080 INFO L290 TraceCheckUtils]: 56: Hoare triple {14161#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 57: Hoare triple {14161#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 58: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___3~0#1); {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 59: Hoare triple {14161#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 60: Hoare triple {14161#false} assume 1 == ~t5_pc~0; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 61: Hoare triple {14161#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 62: Hoare triple {14161#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 63: Hoare triple {14161#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 64: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___4~0#1); {14161#false} is VALID [2022-02-21 04:21:59,081 INFO L290 TraceCheckUtils]: 65: Hoare triple {14161#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 66: Hoare triple {14161#false} assume 1 == ~t6_pc~0; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 67: Hoare triple {14161#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 68: Hoare triple {14161#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 69: Hoare triple {14161#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 70: Hoare triple {14161#false} assume !(0 != activate_threads_~tmp___5~0#1); {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 71: Hoare triple {14161#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 72: Hoare triple {14161#false} assume !(1 == ~t7_pc~0); {14161#false} is VALID [2022-02-21 04:21:59,082 INFO L290 TraceCheckUtils]: 73: Hoare triple {14161#false} is_transmit7_triggered_~__retres1~7#1 := 0; {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 74: Hoare triple {14161#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 75: Hoare triple {14161#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 76: Hoare triple {14161#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 77: Hoare triple {14161#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 78: Hoare triple {14161#false} assume !(1 == ~M_E~0); {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 79: Hoare triple {14161#false} assume !(1 == ~T1_E~0); {14161#false} is VALID [2022-02-21 04:21:59,083 INFO L290 TraceCheckUtils]: 80: Hoare triple {14161#false} assume !(1 == ~T2_E~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 81: Hoare triple {14161#false} assume !(1 == ~T3_E~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 82: Hoare triple {14161#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 83: Hoare triple {14161#false} assume !(1 == ~T5_E~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 84: Hoare triple {14161#false} assume !(1 == ~T6_E~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 85: Hoare triple {14161#false} assume !(1 == ~T7_E~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 86: Hoare triple {14161#false} assume !(1 == ~E_M~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 87: Hoare triple {14161#false} assume !(1 == ~E_1~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 88: Hoare triple {14161#false} assume !(1 == ~E_2~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 89: Hoare triple {14161#false} assume !(1 == ~E_3~0); {14161#false} is VALID [2022-02-21 04:21:59,084 INFO L290 TraceCheckUtils]: 90: Hoare triple {14161#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14161#false} is VALID [2022-02-21 04:21:59,085 INFO L290 TraceCheckUtils]: 91: Hoare triple {14161#false} assume !(1 == ~E_5~0); {14161#false} is VALID [2022-02-21 04:21:59,085 INFO L290 TraceCheckUtils]: 92: Hoare triple {14161#false} assume !(1 == ~E_6~0); {14161#false} is VALID [2022-02-21 04:21:59,085 INFO L290 TraceCheckUtils]: 93: Hoare triple {14161#false} assume !(1 == ~E_7~0); {14161#false} is VALID [2022-02-21 04:21:59,085 INFO L290 TraceCheckUtils]: 94: Hoare triple {14161#false} assume { :end_inline_reset_delta_events } true; {14161#false} is VALID [2022-02-21 04:21:59,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,085 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,085 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360872367] [2022-02-21 04:21:59,086 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360872367] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,086 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,086 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,086 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [823207830] [2022-02-21 04:21:59,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,086 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:59,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,087 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 1 times [2022-02-21 04:21:59,087 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,087 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775649573] [2022-02-21 04:21:59,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 0: Hoare triple {14163#true} assume !false; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 1: Hoare triple {14163#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 2: Hoare triple {14163#true} assume !false; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 3: Hoare triple {14163#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 4: Hoare triple {14163#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 5: Hoare triple {14163#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 6: Hoare triple {14163#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {14163#true} is VALID [2022-02-21 04:21:59,110 INFO L290 TraceCheckUtils]: 7: Hoare triple {14163#true} assume !(0 != eval_~tmp~0#1); {14163#true} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 8: Hoare triple {14163#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14163#true} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 9: Hoare triple {14163#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14163#true} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 10: Hoare triple {14163#true} assume 0 == ~M_E~0;~M_E~0 := 1; {14163#true} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 11: Hoare triple {14163#true} assume !(0 == ~T1_E~0); {14163#true} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 12: Hoare triple {14163#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,111 INFO L290 TraceCheckUtils]: 13: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,112 INFO L290 TraceCheckUtils]: 14: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,112 INFO L290 TraceCheckUtils]: 15: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,112 INFO L290 TraceCheckUtils]: 16: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,113 INFO L290 TraceCheckUtils]: 17: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,113 INFO L290 TraceCheckUtils]: 18: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,113 INFO L290 TraceCheckUtils]: 19: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,113 INFO L290 TraceCheckUtils]: 20: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,114 INFO L290 TraceCheckUtils]: 21: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,114 INFO L290 TraceCheckUtils]: 22: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,114 INFO L290 TraceCheckUtils]: 23: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,114 INFO L290 TraceCheckUtils]: 24: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,115 INFO L290 TraceCheckUtils]: 25: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,115 INFO L290 TraceCheckUtils]: 26: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,115 INFO L290 TraceCheckUtils]: 27: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,116 INFO L290 TraceCheckUtils]: 28: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,116 INFO L290 TraceCheckUtils]: 29: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,116 INFO L290 TraceCheckUtils]: 30: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,116 INFO L290 TraceCheckUtils]: 31: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,117 INFO L290 TraceCheckUtils]: 32: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,117 INFO L290 TraceCheckUtils]: 33: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,117 INFO L290 TraceCheckUtils]: 34: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,117 INFO L290 TraceCheckUtils]: 35: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,118 INFO L290 TraceCheckUtils]: 36: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,118 INFO L290 TraceCheckUtils]: 37: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,118 INFO L290 TraceCheckUtils]: 38: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,119 INFO L290 TraceCheckUtils]: 39: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,119 INFO L290 TraceCheckUtils]: 40: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,119 INFO L290 TraceCheckUtils]: 41: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,119 INFO L290 TraceCheckUtils]: 42: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,120 INFO L290 TraceCheckUtils]: 43: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,120 INFO L290 TraceCheckUtils]: 44: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,120 INFO L290 TraceCheckUtils]: 45: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,120 INFO L290 TraceCheckUtils]: 46: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,121 INFO L290 TraceCheckUtils]: 47: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,121 INFO L290 TraceCheckUtils]: 48: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,121 INFO L290 TraceCheckUtils]: 49: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,121 INFO L290 TraceCheckUtils]: 50: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,122 INFO L290 TraceCheckUtils]: 51: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,122 INFO L290 TraceCheckUtils]: 52: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,122 INFO L290 TraceCheckUtils]: 53: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,133 INFO L290 TraceCheckUtils]: 54: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,134 INFO L290 TraceCheckUtils]: 55: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,134 INFO L290 TraceCheckUtils]: 56: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,134 INFO L290 TraceCheckUtils]: 57: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,134 INFO L290 TraceCheckUtils]: 58: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,135 INFO L290 TraceCheckUtils]: 59: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,135 INFO L290 TraceCheckUtils]: 60: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,135 INFO L290 TraceCheckUtils]: 61: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,135 INFO L290 TraceCheckUtils]: 62: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,136 INFO L290 TraceCheckUtils]: 63: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,136 INFO L290 TraceCheckUtils]: 64: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,136 INFO L290 TraceCheckUtils]: 65: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,137 INFO L290 TraceCheckUtils]: 66: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,137 INFO L290 TraceCheckUtils]: 67: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,137 INFO L290 TraceCheckUtils]: 68: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,137 INFO L290 TraceCheckUtils]: 69: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,138 INFO L290 TraceCheckUtils]: 70: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,138 INFO L290 TraceCheckUtils]: 71: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,138 INFO L290 TraceCheckUtils]: 72: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,138 INFO L290 TraceCheckUtils]: 73: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,139 INFO L290 TraceCheckUtils]: 74: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,139 INFO L290 TraceCheckUtils]: 75: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,139 INFO L290 TraceCheckUtils]: 76: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {14165#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 77: Hoare triple {14165#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 78: Hoare triple {14164#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 79: Hoare triple {14164#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 80: Hoare triple {14164#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 81: Hoare triple {14164#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 82: Hoare triple {14164#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 83: Hoare triple {14164#false} assume 1 == ~E_M~0;~E_M~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 84: Hoare triple {14164#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 85: Hoare triple {14164#false} assume !(1 == ~E_2~0); {14164#false} is VALID [2022-02-21 04:21:59,140 INFO L290 TraceCheckUtils]: 86: Hoare triple {14164#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 87: Hoare triple {14164#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 88: Hoare triple {14164#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 89: Hoare triple {14164#false} assume 1 == ~E_6~0;~E_6~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 90: Hoare triple {14164#false} assume 1 == ~E_7~0;~E_7~0 := 2; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 91: Hoare triple {14164#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 92: Hoare triple {14164#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 93: Hoare triple {14164#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 94: Hoare triple {14164#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {14164#false} is VALID [2022-02-21 04:21:59,141 INFO L290 TraceCheckUtils]: 95: Hoare triple {14164#false} assume !(0 == start_simulation_~tmp~3#1); {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 96: Hoare triple {14164#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 97: Hoare triple {14164#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 98: Hoare triple {14164#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 99: Hoare triple {14164#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 100: Hoare triple {14164#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 101: Hoare triple {14164#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 102: Hoare triple {14164#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {14164#false} is VALID [2022-02-21 04:21:59,142 INFO L290 TraceCheckUtils]: 103: Hoare triple {14164#false} assume !(0 != start_simulation_~tmp___0~1#1); {14164#false} is VALID [2022-02-21 04:21:59,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,143 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,143 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775649573] [2022-02-21 04:21:59,143 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775649573] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,143 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,143 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,143 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629322455] [2022-02-21 04:21:59,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,144 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:59,144 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:59,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:59,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:59,145 INFO L87 Difference]: Start difference. First operand 830 states and 1237 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,769 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2022-02-21 04:21:59,769 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:59,769 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,829 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:59,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,848 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:59,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1236 transitions. [2022-02-21 04:21:59,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:21:59,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:21:59,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:59,866 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-02-21 04:21:59,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:21:59,873 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:59,874 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1236 transitions. Second operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,875 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1236 transitions. Second operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,876 INFO L87 Difference]: Start difference. First operand 830 states and 1236 transitions. Second operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,892 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2022-02-21 04:21:59,892 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,893 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,893 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,895 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1236 transitions. [2022-02-21 04:21:59,896 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1236 transitions. [2022-02-21 04:21:59,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,917 INFO L93 Difference]: Finished difference Result 830 states and 1236 transitions. [2022-02-21 04:21:59,917 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,918 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,918 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,918 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:59,918 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:59,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.489156626506024) internal successors, (1236), 829 states have internal predecessors, (1236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1236 transitions. [2022-02-21 04:21:59,936 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-02-21 04:21:59,936 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1236 transitions. [2022-02-21 04:21:59,936 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:21:59,936 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1236 transitions. [2022-02-21 04:21:59,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:21:59,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:59,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:59,939 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,940 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,940 INFO L791 eck$LassoCheckResult]: Stem: 15635#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15518#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15468#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15469#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 15752#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15451#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15291#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15292#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15273#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15274#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15751#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15577#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15578#L769 assume !(0 == ~M_E~0); 15600#L769-2 assume !(0 == ~T1_E~0); 15601#L774-1 assume !(0 == ~T2_E~0); 15627#L779-1 assume !(0 == ~T3_E~0); 15739#L784-1 assume !(0 == ~T4_E~0); 15572#L789-1 assume !(0 == ~T5_E~0); 15573#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15683#L799-1 assume !(0 == ~T7_E~0); 15579#L804-1 assume !(0 == ~E_M~0); 15580#L809-1 assume !(0 == ~E_1~0); 15620#L814-1 assume !(0 == ~E_2~0); 15013#L819-1 assume !(0 == ~E_3~0); 15014#L824-1 assume !(0 == ~E_4~0); 15361#L829-1 assume !(0 == ~E_5~0); 15798#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 15145#L839-1 assume !(0 == ~E_7~0); 15146#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15524#L376 assume !(1 == ~m_pc~0); 15514#L376-2 is_master_triggered_~__retres1~0#1 := 0; 15513#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15781#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15094#L955 assume !(0 != activate_threads_~tmp~1#1); 15095#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15444#L395 assume 1 == ~t1_pc~0; 15122#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15123#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15017#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15018#L963 assume !(0 != activate_threads_~tmp___0~0#1); 15529#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15530#L414 assume !(1 == ~t2_pc~0); 15148#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15149#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15347#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15348#L971 assume !(0 != activate_threads_~tmp___1~0#1); 15756#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15447#L433 assume 1 == ~t3_pc~0; 15392#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15264#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15422#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15423#L979 assume !(0 != activate_threads_~tmp___2~0#1); 15113#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15114#L452 assume !(1 == ~t4_pc~0); 15269#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15270#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15561#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15626#L987 assume !(0 != activate_threads_~tmp___3~0#1); 15302#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15303#L471 assume 1 == ~t5_pc~0; 15671#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15285#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15286#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15621#L995 assume !(0 != activate_threads_~tmp___4~0#1); 15790#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15791#L490 assume 1 == ~t6_pc~0; 15775#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15527#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15569#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15570#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 15459#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15425#L509 assume !(1 == ~t7_pc~0); 15426#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15248#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15249#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15307#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15308#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15764#L857 assume !(1 == ~M_E~0); 15099#L857-2 assume !(1 == ~T1_E~0); 15100#L862-1 assume !(1 == ~T2_E~0); 15369#L867-1 assume !(1 == ~T3_E~0); 15374#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15448#L877-1 assume !(1 == ~T5_E~0); 15647#L882-1 assume !(1 == ~T6_E~0); 15773#L887-1 assume !(1 == ~T7_E~0); 15697#L892-1 assume !(1 == ~E_M~0); 15698#L897-1 assume !(1 == ~E_1~0); 15386#L902-1 assume !(1 == ~E_2~0); 15387#L907-1 assume !(1 == ~E_3~0); 15666#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15655#L917-1 assume !(1 == ~E_5~0); 15656#L922-1 assume !(1 == ~E_6~0); 15801#L927-1 assume !(1 == ~E_7~0); 15642#L932-1 assume { :end_inline_reset_delta_events } true; 15048#L1178-2 [2022-02-21 04:21:59,940 INFO L793 eck$LassoCheckResult]: Loop: 15048#L1178-2 assume !false; 15632#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15065#L744 assume !false; 15419#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15493#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15083#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15289#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15745#L641 assume !(0 != eval_~tmp~0#1); 15559#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15183#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15184#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15445#L769-5 assume !(0 == ~T1_E~0); 15446#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15202#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15024#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15025#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15009#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15010#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15063#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15317#L809-3 assume !(0 == ~E_1~0); 15059#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15060#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15719#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15714#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15370#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15371#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15682#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15761#L376-27 assume 1 == ~m_pc~0; 15660#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15606#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15607#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15701#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15804#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15825#L395-27 assume !(1 == ~t1_pc~0); 15464#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15372#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15373#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15598#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15452#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15453#L414-27 assume 1 == ~t2_pc~0; 15788#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15653#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15654#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15510#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15075#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15076#L433-27 assume !(1 == ~t3_pc~0); 15171#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 15457#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15458#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15244#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 15245#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15818#L452-27 assume !(1 == ~t4_pc~0); 15617#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15618#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15742#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15784#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15785#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15066#L471-27 assume !(1 == ~t5_pc~0); 15067#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15378#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15760#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15674#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15602#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15523#L490-27 assume 1 == ~t6_pc~0; 15420#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15258#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15259#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15662#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15663#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15033#L509-27 assume !(1 == ~t7_pc~0); 15034#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15424#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15549#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15540#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15541#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15555#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15556#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15596#L862-3 assume !(1 == ~T2_E~0); 15816#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15460#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15461#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15550#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15590#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15220#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15221#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15734#L902-3 assume !(1 == ~E_2~0); 15382#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15383#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15502#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15465#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15271#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15272#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15120#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15023#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15685#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15435#L1197 assume !(0 == start_simulation_~tmp~3#1); 15436#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15179#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15143#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15069#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 15070#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15731#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15732#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15047#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 15048#L1178-2 [2022-02-21 04:21:59,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,941 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-02-21 04:21:59,941 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,941 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357885927] [2022-02-21 04:21:59,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,959 INFO L290 TraceCheckUtils]: 0: Hoare triple {17489#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {17489#true} is VALID [2022-02-21 04:21:59,960 INFO L290 TraceCheckUtils]: 1: Hoare triple {17489#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,960 INFO L290 TraceCheckUtils]: 2: Hoare triple {17491#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,960 INFO L290 TraceCheckUtils]: 3: Hoare triple {17491#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,960 INFO L290 TraceCheckUtils]: 4: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,961 INFO L290 TraceCheckUtils]: 5: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,961 INFO L290 TraceCheckUtils]: 6: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,961 INFO L290 TraceCheckUtils]: 7: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,961 INFO L290 TraceCheckUtils]: 8: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,961 INFO L290 TraceCheckUtils]: 9: Hoare triple {17491#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {17491#(= ~t6_i~0 1)} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 10: Hoare triple {17491#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 11: Hoare triple {17490#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 12: Hoare triple {17490#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 13: Hoare triple {17490#false} assume !(0 == ~M_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 14: Hoare triple {17490#false} assume !(0 == ~T1_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 15: Hoare triple {17490#false} assume !(0 == ~T2_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 16: Hoare triple {17490#false} assume !(0 == ~T3_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 17: Hoare triple {17490#false} assume !(0 == ~T4_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 18: Hoare triple {17490#false} assume !(0 == ~T5_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 19: Hoare triple {17490#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 20: Hoare triple {17490#false} assume !(0 == ~T7_E~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 21: Hoare triple {17490#false} assume !(0 == ~E_M~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 22: Hoare triple {17490#false} assume !(0 == ~E_1~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 23: Hoare triple {17490#false} assume !(0 == ~E_2~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 24: Hoare triple {17490#false} assume !(0 == ~E_3~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 25: Hoare triple {17490#false} assume !(0 == ~E_4~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 26: Hoare triple {17490#false} assume !(0 == ~E_5~0); {17490#false} is VALID [2022-02-21 04:21:59,962 INFO L290 TraceCheckUtils]: 27: Hoare triple {17490#false} assume 0 == ~E_6~0;~E_6~0 := 1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 28: Hoare triple {17490#false} assume !(0 == ~E_7~0); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 29: Hoare triple {17490#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 30: Hoare triple {17490#false} assume !(1 == ~m_pc~0); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 31: Hoare triple {17490#false} is_master_triggered_~__retres1~0#1 := 0; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 32: Hoare triple {17490#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 33: Hoare triple {17490#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 34: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp~1#1); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 35: Hoare triple {17490#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 36: Hoare triple {17490#false} assume 1 == ~t1_pc~0; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 37: Hoare triple {17490#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 38: Hoare triple {17490#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 39: Hoare triple {17490#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 40: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___0~0#1); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 41: Hoare triple {17490#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 42: Hoare triple {17490#false} assume !(1 == ~t2_pc~0); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 43: Hoare triple {17490#false} is_transmit2_triggered_~__retres1~2#1 := 0; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 44: Hoare triple {17490#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 45: Hoare triple {17490#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 46: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___1~0#1); {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 47: Hoare triple {17490#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 48: Hoare triple {17490#false} assume 1 == ~t3_pc~0; {17490#false} is VALID [2022-02-21 04:21:59,963 INFO L290 TraceCheckUtils]: 49: Hoare triple {17490#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 50: Hoare triple {17490#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 51: Hoare triple {17490#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 52: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___2~0#1); {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 53: Hoare triple {17490#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 54: Hoare triple {17490#false} assume !(1 == ~t4_pc~0); {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 55: Hoare triple {17490#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 56: Hoare triple {17490#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 57: Hoare triple {17490#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 58: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___3~0#1); {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 59: Hoare triple {17490#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 60: Hoare triple {17490#false} assume 1 == ~t5_pc~0; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 61: Hoare triple {17490#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 62: Hoare triple {17490#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 63: Hoare triple {17490#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 64: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___4~0#1); {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 65: Hoare triple {17490#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 66: Hoare triple {17490#false} assume 1 == ~t6_pc~0; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 67: Hoare triple {17490#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 68: Hoare triple {17490#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 69: Hoare triple {17490#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 70: Hoare triple {17490#false} assume !(0 != activate_threads_~tmp___5~0#1); {17490#false} is VALID [2022-02-21 04:21:59,964 INFO L290 TraceCheckUtils]: 71: Hoare triple {17490#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 72: Hoare triple {17490#false} assume !(1 == ~t7_pc~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 73: Hoare triple {17490#false} is_transmit7_triggered_~__retres1~7#1 := 0; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 74: Hoare triple {17490#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 75: Hoare triple {17490#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 76: Hoare triple {17490#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 77: Hoare triple {17490#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 78: Hoare triple {17490#false} assume !(1 == ~M_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 79: Hoare triple {17490#false} assume !(1 == ~T1_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 80: Hoare triple {17490#false} assume !(1 == ~T2_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 81: Hoare triple {17490#false} assume !(1 == ~T3_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 82: Hoare triple {17490#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 83: Hoare triple {17490#false} assume !(1 == ~T5_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 84: Hoare triple {17490#false} assume !(1 == ~T6_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 85: Hoare triple {17490#false} assume !(1 == ~T7_E~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 86: Hoare triple {17490#false} assume !(1 == ~E_M~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 87: Hoare triple {17490#false} assume !(1 == ~E_1~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 88: Hoare triple {17490#false} assume !(1 == ~E_2~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 89: Hoare triple {17490#false} assume !(1 == ~E_3~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 90: Hoare triple {17490#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 91: Hoare triple {17490#false} assume !(1 == ~E_5~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 92: Hoare triple {17490#false} assume !(1 == ~E_6~0); {17490#false} is VALID [2022-02-21 04:21:59,965 INFO L290 TraceCheckUtils]: 93: Hoare triple {17490#false} assume !(1 == ~E_7~0); {17490#false} is VALID [2022-02-21 04:21:59,966 INFO L290 TraceCheckUtils]: 94: Hoare triple {17490#false} assume { :end_inline_reset_delta_events } true; {17490#false} is VALID [2022-02-21 04:21:59,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,966 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,966 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [357885927] [2022-02-21 04:21:59,966 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [357885927] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,966 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,966 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,966 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825925412] [2022-02-21 04:21:59,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,966 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:59,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,967 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 2 times [2022-02-21 04:21:59,967 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,970 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982730525] [2022-02-21 04:21:59,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,992 INFO L290 TraceCheckUtils]: 0: Hoare triple {17492#true} assume !false; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 1: Hoare triple {17492#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 2: Hoare triple {17492#true} assume !false; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 3: Hoare triple {17492#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 4: Hoare triple {17492#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 5: Hoare triple {17492#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 6: Hoare triple {17492#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 7: Hoare triple {17492#true} assume !(0 != eval_~tmp~0#1); {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 8: Hoare triple {17492#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17492#true} is VALID [2022-02-21 04:21:59,993 INFO L290 TraceCheckUtils]: 9: Hoare triple {17492#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17492#true} is VALID [2022-02-21 04:21:59,994 INFO L290 TraceCheckUtils]: 10: Hoare triple {17492#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17492#true} is VALID [2022-02-21 04:21:59,994 INFO L290 TraceCheckUtils]: 11: Hoare triple {17492#true} assume !(0 == ~T1_E~0); {17492#true} is VALID [2022-02-21 04:21:59,994 INFO L290 TraceCheckUtils]: 12: Hoare triple {17492#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,994 INFO L290 TraceCheckUtils]: 13: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,994 INFO L290 TraceCheckUtils]: 14: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,995 INFO L290 TraceCheckUtils]: 15: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,995 INFO L290 TraceCheckUtils]: 16: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,995 INFO L290 TraceCheckUtils]: 17: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,995 INFO L290 TraceCheckUtils]: 18: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,996 INFO L290 TraceCheckUtils]: 19: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,996 INFO L290 TraceCheckUtils]: 20: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,996 INFO L290 TraceCheckUtils]: 21: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,996 INFO L290 TraceCheckUtils]: 22: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,997 INFO L290 TraceCheckUtils]: 23: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,997 INFO L290 TraceCheckUtils]: 24: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,997 INFO L290 TraceCheckUtils]: 25: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,997 INFO L290 TraceCheckUtils]: 26: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,998 INFO L290 TraceCheckUtils]: 27: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,998 INFO L290 TraceCheckUtils]: 28: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,998 INFO L290 TraceCheckUtils]: 29: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,998 INFO L290 TraceCheckUtils]: 30: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,999 INFO L290 TraceCheckUtils]: 31: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,999 INFO L290 TraceCheckUtils]: 32: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,999 INFO L290 TraceCheckUtils]: 33: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:21:59,999 INFO L290 TraceCheckUtils]: 34: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,000 INFO L290 TraceCheckUtils]: 35: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,000 INFO L290 TraceCheckUtils]: 36: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,000 INFO L290 TraceCheckUtils]: 37: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,001 INFO L290 TraceCheckUtils]: 38: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,001 INFO L290 TraceCheckUtils]: 39: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,001 INFO L290 TraceCheckUtils]: 40: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,001 INFO L290 TraceCheckUtils]: 41: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,002 INFO L290 TraceCheckUtils]: 42: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,002 INFO L290 TraceCheckUtils]: 43: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,002 INFO L290 TraceCheckUtils]: 44: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,003 INFO L290 TraceCheckUtils]: 45: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,003 INFO L290 TraceCheckUtils]: 46: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,003 INFO L290 TraceCheckUtils]: 47: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,004 INFO L290 TraceCheckUtils]: 48: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,004 INFO L290 TraceCheckUtils]: 49: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,004 INFO L290 TraceCheckUtils]: 50: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,004 INFO L290 TraceCheckUtils]: 51: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,005 INFO L290 TraceCheckUtils]: 52: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,005 INFO L290 TraceCheckUtils]: 53: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,005 INFO L290 TraceCheckUtils]: 54: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,005 INFO L290 TraceCheckUtils]: 55: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,006 INFO L290 TraceCheckUtils]: 56: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,006 INFO L290 TraceCheckUtils]: 57: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,006 INFO L290 TraceCheckUtils]: 58: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,006 INFO L290 TraceCheckUtils]: 59: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,007 INFO L290 TraceCheckUtils]: 60: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,007 INFO L290 TraceCheckUtils]: 61: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,007 INFO L290 TraceCheckUtils]: 62: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,007 INFO L290 TraceCheckUtils]: 63: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,008 INFO L290 TraceCheckUtils]: 64: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,008 INFO L290 TraceCheckUtils]: 65: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,008 INFO L290 TraceCheckUtils]: 66: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,009 INFO L290 TraceCheckUtils]: 67: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,009 INFO L290 TraceCheckUtils]: 68: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,009 INFO L290 TraceCheckUtils]: 69: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,009 INFO L290 TraceCheckUtils]: 70: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,010 INFO L290 TraceCheckUtils]: 71: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,010 INFO L290 TraceCheckUtils]: 72: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,010 INFO L290 TraceCheckUtils]: 73: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,011 INFO L290 TraceCheckUtils]: 74: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,011 INFO L290 TraceCheckUtils]: 75: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,011 INFO L290 TraceCheckUtils]: 76: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17494#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 77: Hoare triple {17494#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 78: Hoare triple {17493#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 79: Hoare triple {17493#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 80: Hoare triple {17493#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 81: Hoare triple {17493#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 82: Hoare triple {17493#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 83: Hoare triple {17493#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,012 INFO L290 TraceCheckUtils]: 84: Hoare triple {17493#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 85: Hoare triple {17493#false} assume !(1 == ~E_2~0); {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 86: Hoare triple {17493#false} assume 1 == ~E_3~0;~E_3~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 87: Hoare triple {17493#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 88: Hoare triple {17493#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 89: Hoare triple {17493#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 90: Hoare triple {17493#false} assume 1 == ~E_7~0;~E_7~0 := 2; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 91: Hoare triple {17493#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17493#false} is VALID [2022-02-21 04:22:00,013 INFO L290 TraceCheckUtils]: 92: Hoare triple {17493#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 93: Hoare triple {17493#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 94: Hoare triple {17493#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 95: Hoare triple {17493#false} assume !(0 == start_simulation_~tmp~3#1); {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 96: Hoare triple {17493#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 97: Hoare triple {17493#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 98: Hoare triple {17493#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 99: Hoare triple {17493#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {17493#false} is VALID [2022-02-21 04:22:00,014 INFO L290 TraceCheckUtils]: 100: Hoare triple {17493#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17493#false} is VALID [2022-02-21 04:22:00,015 INFO L290 TraceCheckUtils]: 101: Hoare triple {17493#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17493#false} is VALID [2022-02-21 04:22:00,015 INFO L290 TraceCheckUtils]: 102: Hoare triple {17493#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {17493#false} is VALID [2022-02-21 04:22:00,015 INFO L290 TraceCheckUtils]: 103: Hoare triple {17493#false} assume !(0 != start_simulation_~tmp___0~1#1); {17493#false} is VALID [2022-02-21 04:22:00,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:00,015 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:00,016 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982730525] [2022-02-21 04:22:00,016 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982730525] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:00,016 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:00,016 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:00,016 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184720766] [2022-02-21 04:22:00,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:00,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:00,017 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:00,017 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:00,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:00,018 INFO L87 Difference]: Start difference. First operand 830 states and 1236 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,579 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2022-02-21 04:22:00,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:00,579 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,642 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:00,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:22:00,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1235 transitions. [2022-02-21 04:22:00,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:22:00,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:22:00,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:00,680 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-02-21 04:22:00,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:22:00,687 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:00,688 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1235 transitions. Second operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,689 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1235 transitions. Second operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,689 INFO L87 Difference]: Start difference. First operand 830 states and 1235 transitions. Second operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,705 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2022-02-21 04:22:00,705 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,706 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,706 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,707 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1235 transitions. [2022-02-21 04:22:00,708 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1235 transitions. [2022-02-21 04:22:00,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,724 INFO L93 Difference]: Finished difference Result 830 states and 1235 transitions. [2022-02-21 04:22:00,724 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,725 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,725 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,725 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:00,725 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:00,726 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4879518072289157) internal successors, (1235), 829 states have internal predecessors, (1235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1235 transitions. [2022-02-21 04:22:00,742 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-02-21 04:22:00,742 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1235 transitions. [2022-02-21 04:22:00,742 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:22:00,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1235 transitions. [2022-02-21 04:22:00,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:22:00,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:00,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:00,745 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,745 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,745 INFO L791 eck$LassoCheckResult]: Stem: 18964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 18965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18847#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18797#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18798#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 19081#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18780#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18620#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18621#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18602#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18603#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19080#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18905#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18906#L769 assume !(0 == ~M_E~0); 18928#L769-2 assume !(0 == ~T1_E~0); 18929#L774-1 assume !(0 == ~T2_E~0); 18956#L779-1 assume !(0 == ~T3_E~0); 19068#L784-1 assume !(0 == ~T4_E~0); 18901#L789-1 assume !(0 == ~T5_E~0); 18902#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19012#L799-1 assume !(0 == ~T7_E~0); 18908#L804-1 assume !(0 == ~E_M~0); 18909#L809-1 assume !(0 == ~E_1~0); 18949#L814-1 assume !(0 == ~E_2~0); 18338#L819-1 assume !(0 == ~E_3~0); 18339#L824-1 assume !(0 == ~E_4~0); 18690#L829-1 assume !(0 == ~E_5~0); 19127#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 18474#L839-1 assume !(0 == ~E_7~0); 18475#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18853#L376 assume !(1 == ~m_pc~0); 18840#L376-2 is_master_triggered_~__retres1~0#1 := 0; 18839#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19110#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18421#L955 assume !(0 != activate_threads_~tmp~1#1); 18422#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18773#L395 assume 1 == ~t1_pc~0; 18451#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18452#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18344#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18345#L963 assume !(0 != activate_threads_~tmp___0~0#1); 18857#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18858#L414 assume !(1 == ~t2_pc~0); 18477#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18478#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18676#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18677#L971 assume !(0 != activate_threads_~tmp___1~0#1); 19084#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18776#L433 assume 1 == ~t3_pc~0; 18721#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18591#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18749#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18750#L979 assume !(0 != activate_threads_~tmp___2~0#1); 18442#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18443#L452 assume !(1 == ~t4_pc~0); 18598#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18599#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18889#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18955#L987 assume !(0 != activate_threads_~tmp___3~0#1); 18631#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18632#L471 assume 1 == ~t5_pc~0; 19000#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18614#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18615#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18950#L995 assume !(0 != activate_threads_~tmp___4~0#1); 19119#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19120#L490 assume 1 == ~t6_pc~0; 19103#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18856#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18896#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18899#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 18785#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18754#L509 assume !(1 == ~t7_pc~0); 18755#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18572#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18573#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18636#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18637#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19092#L857 assume !(1 == ~M_E~0); 18428#L857-2 assume !(1 == ~T1_E~0); 18429#L862-1 assume !(1 == ~T2_E~0); 18698#L867-1 assume !(1 == ~T3_E~0); 18703#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18777#L877-1 assume !(1 == ~T5_E~0); 18976#L882-1 assume !(1 == ~T6_E~0); 19102#L887-1 assume !(1 == ~T7_E~0); 19026#L892-1 assume !(1 == ~E_M~0); 19027#L897-1 assume !(1 == ~E_1~0); 18713#L902-1 assume !(1 == ~E_2~0); 18714#L907-1 assume !(1 == ~E_3~0); 18993#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18984#L917-1 assume !(1 == ~E_5~0); 18985#L922-1 assume !(1 == ~E_6~0); 19130#L927-1 assume !(1 == ~E_7~0); 18971#L932-1 assume { :end_inline_reset_delta_events } true; 18377#L1178-2 [2022-02-21 04:22:00,745 INFO L793 eck$LassoCheckResult]: Loop: 18377#L1178-2 assume !false; 18960#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18394#L744 assume !false; 18748#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 18821#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18412#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 18618#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 19072#L641 assume !(0 != eval_~tmp~0#1); 18888#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18512#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18513#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18774#L769-5 assume !(0 == ~T1_E~0); 18775#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18529#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18353#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18354#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18340#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18341#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18392#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18646#L809-3 assume !(0 == ~E_1~0); 18388#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18389#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19048#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19043#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18699#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18700#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19011#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19090#L376-27 assume 1 == ~m_pc~0; 18989#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18935#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18936#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19030#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19133#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19154#L395-27 assume !(1 == ~t1_pc~0); 18793#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 18701#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18702#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18927#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18781#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18782#L414-27 assume 1 == ~t2_pc~0; 19117#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18982#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18983#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18842#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18404#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18405#L433-27 assume !(1 == ~t3_pc~0); 18500#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 18787#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18788#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18575#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 18576#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19147#L452-27 assume !(1 == ~t4_pc~0); 18946#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 18947#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19071#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19113#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19114#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18395#L471-27 assume !(1 == ~t5_pc~0); 18396#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 18710#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19089#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19003#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18931#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18852#L490-27 assume !(1 == ~t6_pc~0); 18752#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 18587#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18588#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18991#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18992#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18362#L509-27 assume !(1 == ~t7_pc~0); 18363#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 18753#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18878#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18869#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18870#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18884#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18885#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18925#L862-3 assume !(1 == ~T2_E~0); 19145#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18789#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18790#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18879#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18919#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18549#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18550#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19063#L902-3 assume !(1 == ~E_2~0); 18711#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18712#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18831#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18794#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18600#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18601#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 18449#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18352#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19014#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 18764#L1197 assume !(0 == start_simulation_~tmp~3#1); 18765#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 18508#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18472#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 18398#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 18399#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19060#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19061#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 18376#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 18377#L1178-2 [2022-02-21 04:22:00,746 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-02-21 04:22:00,746 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,746 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105452880] [2022-02-21 04:22:00,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:00,764 INFO L290 TraceCheckUtils]: 0: Hoare triple {20818#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {20818#true} is VALID [2022-02-21 04:22:00,765 INFO L290 TraceCheckUtils]: 1: Hoare triple {20818#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,765 INFO L290 TraceCheckUtils]: 2: Hoare triple {20820#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,765 INFO L290 TraceCheckUtils]: 3: Hoare triple {20820#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,765 INFO L290 TraceCheckUtils]: 4: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,765 INFO L290 TraceCheckUtils]: 5: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,766 INFO L290 TraceCheckUtils]: 6: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,766 INFO L290 TraceCheckUtils]: 7: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,766 INFO L290 TraceCheckUtils]: 8: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,766 INFO L290 TraceCheckUtils]: 9: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 10: Hoare triple {20820#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {20820#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 11: Hoare triple {20820#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 12: Hoare triple {20819#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 13: Hoare triple {20819#false} assume !(0 == ~M_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 14: Hoare triple {20819#false} assume !(0 == ~T1_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 15: Hoare triple {20819#false} assume !(0 == ~T2_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 16: Hoare triple {20819#false} assume !(0 == ~T3_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 17: Hoare triple {20819#false} assume !(0 == ~T4_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 18: Hoare triple {20819#false} assume !(0 == ~T5_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 19: Hoare triple {20819#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 20: Hoare triple {20819#false} assume !(0 == ~T7_E~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 21: Hoare triple {20819#false} assume !(0 == ~E_M~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 22: Hoare triple {20819#false} assume !(0 == ~E_1~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 23: Hoare triple {20819#false} assume !(0 == ~E_2~0); {20819#false} is VALID [2022-02-21 04:22:00,767 INFO L290 TraceCheckUtils]: 24: Hoare triple {20819#false} assume !(0 == ~E_3~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 25: Hoare triple {20819#false} assume !(0 == ~E_4~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 26: Hoare triple {20819#false} assume !(0 == ~E_5~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 27: Hoare triple {20819#false} assume 0 == ~E_6~0;~E_6~0 := 1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 28: Hoare triple {20819#false} assume !(0 == ~E_7~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 29: Hoare triple {20819#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 30: Hoare triple {20819#false} assume !(1 == ~m_pc~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 31: Hoare triple {20819#false} is_master_triggered_~__retres1~0#1 := 0; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 32: Hoare triple {20819#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 33: Hoare triple {20819#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 34: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp~1#1); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 35: Hoare triple {20819#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 36: Hoare triple {20819#false} assume 1 == ~t1_pc~0; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 37: Hoare triple {20819#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 38: Hoare triple {20819#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 39: Hoare triple {20819#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 40: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___0~0#1); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 41: Hoare triple {20819#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 42: Hoare triple {20819#false} assume !(1 == ~t2_pc~0); {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 43: Hoare triple {20819#false} is_transmit2_triggered_~__retres1~2#1 := 0; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 44: Hoare triple {20819#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 45: Hoare triple {20819#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20819#false} is VALID [2022-02-21 04:22:00,768 INFO L290 TraceCheckUtils]: 46: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___1~0#1); {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 47: Hoare triple {20819#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 48: Hoare triple {20819#false} assume 1 == ~t3_pc~0; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 49: Hoare triple {20819#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 50: Hoare triple {20819#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 51: Hoare triple {20819#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 52: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___2~0#1); {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 53: Hoare triple {20819#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 54: Hoare triple {20819#false} assume !(1 == ~t4_pc~0); {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 55: Hoare triple {20819#false} is_transmit4_triggered_~__retres1~4#1 := 0; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 56: Hoare triple {20819#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 57: Hoare triple {20819#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 58: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___3~0#1); {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 59: Hoare triple {20819#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 60: Hoare triple {20819#false} assume 1 == ~t5_pc~0; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 61: Hoare triple {20819#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 62: Hoare triple {20819#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 63: Hoare triple {20819#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 64: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___4~0#1); {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 65: Hoare triple {20819#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 66: Hoare triple {20819#false} assume 1 == ~t6_pc~0; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 67: Hoare triple {20819#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 68: Hoare triple {20819#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20819#false} is VALID [2022-02-21 04:22:00,769 INFO L290 TraceCheckUtils]: 69: Hoare triple {20819#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 70: Hoare triple {20819#false} assume !(0 != activate_threads_~tmp___5~0#1); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 71: Hoare triple {20819#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 72: Hoare triple {20819#false} assume !(1 == ~t7_pc~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 73: Hoare triple {20819#false} is_transmit7_triggered_~__retres1~7#1 := 0; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 74: Hoare triple {20819#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 75: Hoare triple {20819#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 76: Hoare triple {20819#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 77: Hoare triple {20819#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 78: Hoare triple {20819#false} assume !(1 == ~M_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 79: Hoare triple {20819#false} assume !(1 == ~T1_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 80: Hoare triple {20819#false} assume !(1 == ~T2_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 81: Hoare triple {20819#false} assume !(1 == ~T3_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 82: Hoare triple {20819#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 83: Hoare triple {20819#false} assume !(1 == ~T5_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 84: Hoare triple {20819#false} assume !(1 == ~T6_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 85: Hoare triple {20819#false} assume !(1 == ~T7_E~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 86: Hoare triple {20819#false} assume !(1 == ~E_M~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 87: Hoare triple {20819#false} assume !(1 == ~E_1~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 88: Hoare triple {20819#false} assume !(1 == ~E_2~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 89: Hoare triple {20819#false} assume !(1 == ~E_3~0); {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 90: Hoare triple {20819#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20819#false} is VALID [2022-02-21 04:22:00,770 INFO L290 TraceCheckUtils]: 91: Hoare triple {20819#false} assume !(1 == ~E_5~0); {20819#false} is VALID [2022-02-21 04:22:00,771 INFO L290 TraceCheckUtils]: 92: Hoare triple {20819#false} assume !(1 == ~E_6~0); {20819#false} is VALID [2022-02-21 04:22:00,771 INFO L290 TraceCheckUtils]: 93: Hoare triple {20819#false} assume !(1 == ~E_7~0); {20819#false} is VALID [2022-02-21 04:22:00,771 INFO L290 TraceCheckUtils]: 94: Hoare triple {20819#false} assume { :end_inline_reset_delta_events } true; {20819#false} is VALID [2022-02-21 04:22:00,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:00,771 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:00,771 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105452880] [2022-02-21 04:22:00,771 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105452880] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:00,771 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:00,771 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:00,771 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741175423] [2022-02-21 04:22:00,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:00,771 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:00,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,772 INFO L85 PathProgramCache]: Analyzing trace with hash 1702289836, now seen corresponding path program 1 times [2022-02-21 04:22:00,772 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,772 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1606119318] [2022-02-21 04:22:00,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 0: Hoare triple {20821#true} assume !false; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 1: Hoare triple {20821#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 2: Hoare triple {20821#true} assume !false; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 3: Hoare triple {20821#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 4: Hoare triple {20821#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 5: Hoare triple {20821#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 6: Hoare triple {20821#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 7: Hoare triple {20821#true} assume !(0 != eval_~tmp~0#1); {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 8: Hoare triple {20821#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 9: Hoare triple {20821#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 10: Hoare triple {20821#true} assume 0 == ~M_E~0;~M_E~0 := 1; {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 11: Hoare triple {20821#true} assume !(0 == ~T1_E~0); {20821#true} is VALID [2022-02-21 04:22:00,791 INFO L290 TraceCheckUtils]: 12: Hoare triple {20821#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,792 INFO L290 TraceCheckUtils]: 13: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,792 INFO L290 TraceCheckUtils]: 14: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,792 INFO L290 TraceCheckUtils]: 15: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,792 INFO L290 TraceCheckUtils]: 16: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,792 INFO L290 TraceCheckUtils]: 17: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,793 INFO L290 TraceCheckUtils]: 18: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,793 INFO L290 TraceCheckUtils]: 19: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,793 INFO L290 TraceCheckUtils]: 20: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,793 INFO L290 TraceCheckUtils]: 21: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,794 INFO L290 TraceCheckUtils]: 22: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,794 INFO L290 TraceCheckUtils]: 23: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,794 INFO L290 TraceCheckUtils]: 24: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,794 INFO L290 TraceCheckUtils]: 25: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,794 INFO L290 TraceCheckUtils]: 26: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,795 INFO L290 TraceCheckUtils]: 27: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,795 INFO L290 TraceCheckUtils]: 28: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,795 INFO L290 TraceCheckUtils]: 29: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,795 INFO L290 TraceCheckUtils]: 30: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,796 INFO L290 TraceCheckUtils]: 31: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,796 INFO L290 TraceCheckUtils]: 32: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,796 INFO L290 TraceCheckUtils]: 33: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,796 INFO L290 TraceCheckUtils]: 34: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,796 INFO L290 TraceCheckUtils]: 35: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,797 INFO L290 TraceCheckUtils]: 36: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,797 INFO L290 TraceCheckUtils]: 37: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,797 INFO L290 TraceCheckUtils]: 38: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,797 INFO L290 TraceCheckUtils]: 39: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,798 INFO L290 TraceCheckUtils]: 40: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,798 INFO L290 TraceCheckUtils]: 41: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,798 INFO L290 TraceCheckUtils]: 42: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,798 INFO L290 TraceCheckUtils]: 43: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,798 INFO L290 TraceCheckUtils]: 44: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,799 INFO L290 TraceCheckUtils]: 45: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,799 INFO L290 TraceCheckUtils]: 46: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,799 INFO L290 TraceCheckUtils]: 47: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,799 INFO L290 TraceCheckUtils]: 48: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,799 INFO L290 TraceCheckUtils]: 49: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,800 INFO L290 TraceCheckUtils]: 50: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,800 INFO L290 TraceCheckUtils]: 51: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,800 INFO L290 TraceCheckUtils]: 52: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,800 INFO L290 TraceCheckUtils]: 53: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,801 INFO L290 TraceCheckUtils]: 54: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,801 INFO L290 TraceCheckUtils]: 55: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,801 INFO L290 TraceCheckUtils]: 56: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,801 INFO L290 TraceCheckUtils]: 57: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,801 INFO L290 TraceCheckUtils]: 58: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,802 INFO L290 TraceCheckUtils]: 59: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,802 INFO L290 TraceCheckUtils]: 60: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,802 INFO L290 TraceCheckUtils]: 61: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,802 INFO L290 TraceCheckUtils]: 62: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,803 INFO L290 TraceCheckUtils]: 63: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,803 INFO L290 TraceCheckUtils]: 64: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,803 INFO L290 TraceCheckUtils]: 65: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,803 INFO L290 TraceCheckUtils]: 66: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,803 INFO L290 TraceCheckUtils]: 67: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,804 INFO L290 TraceCheckUtils]: 68: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,804 INFO L290 TraceCheckUtils]: 69: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,804 INFO L290 TraceCheckUtils]: 70: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,804 INFO L290 TraceCheckUtils]: 71: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,805 INFO L290 TraceCheckUtils]: 72: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,805 INFO L290 TraceCheckUtils]: 73: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,805 INFO L290 TraceCheckUtils]: 74: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,805 INFO L290 TraceCheckUtils]: 75: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,805 INFO L290 TraceCheckUtils]: 76: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {20823#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 77: Hoare triple {20823#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 78: Hoare triple {20822#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 79: Hoare triple {20822#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 80: Hoare triple {20822#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 81: Hoare triple {20822#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 82: Hoare triple {20822#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 83: Hoare triple {20822#false} assume 1 == ~E_M~0;~E_M~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 84: Hoare triple {20822#false} assume 1 == ~E_1~0;~E_1~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 85: Hoare triple {20822#false} assume !(1 == ~E_2~0); {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 86: Hoare triple {20822#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 87: Hoare triple {20822#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 88: Hoare triple {20822#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 89: Hoare triple {20822#false} assume 1 == ~E_6~0;~E_6~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 90: Hoare triple {20822#false} assume 1 == ~E_7~0;~E_7~0 := 2; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 91: Hoare triple {20822#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 92: Hoare triple {20822#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 93: Hoare triple {20822#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20822#false} is VALID [2022-02-21 04:22:00,806 INFO L290 TraceCheckUtils]: 94: Hoare triple {20822#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 95: Hoare triple {20822#false} assume !(0 == start_simulation_~tmp~3#1); {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 96: Hoare triple {20822#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 97: Hoare triple {20822#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 98: Hoare triple {20822#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 99: Hoare triple {20822#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 100: Hoare triple {20822#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 101: Hoare triple {20822#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 102: Hoare triple {20822#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L290 TraceCheckUtils]: 103: Hoare triple {20822#false} assume !(0 != start_simulation_~tmp___0~1#1); {20822#false} is VALID [2022-02-21 04:22:00,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:00,807 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:00,807 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1606119318] [2022-02-21 04:22:00,807 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1606119318] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:00,807 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:00,807 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:00,808 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763334694] [2022-02-21 04:22:00,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:00,808 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:00,808 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:00,808 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:00,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:00,808 INFO L87 Difference]: Start difference. First operand 830 states and 1235 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,332 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2022-02-21 04:22:01,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:01,332 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,380 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:01,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:22:01,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 830 states to 830 states and 1234 transitions. [2022-02-21 04:22:01,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 830 [2022-02-21 04:22:01,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 830 [2022-02-21 04:22:01,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:01,416 INFO L681 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-02-21 04:22:01,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 830 to 830. [2022-02-21 04:22:01,423 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:01,424 INFO L82 GeneralOperation]: Start isEquivalent. First operand 830 states and 1234 transitions. Second operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,425 INFO L74 IsIncluded]: Start isIncluded. First operand 830 states and 1234 transitions. Second operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,425 INFO L87 Difference]: Start difference. First operand 830 states and 1234 transitions. Second operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,441 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2022-02-21 04:22:01,441 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,442 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:01,442 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:01,443 INFO L74 IsIncluded]: Start isIncluded. First operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1234 transitions. [2022-02-21 04:22:01,444 INFO L87 Difference]: Start difference. First operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 830 states and 1234 transitions. [2022-02-21 04:22:01,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,461 INFO L93 Difference]: Finished difference Result 830 states and 1234 transitions. [2022-02-21 04:22:01,461 INFO L276 IsEmpty]: Start isEmpty. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,462 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:01,462 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:01,462 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:01,462 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:01,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 830 states, 830 states have (on average 1.4867469879518072) internal successors, (1234), 829 states have internal predecessors, (1234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 830 states to 830 states and 1234 transitions. [2022-02-21 04:22:01,479 INFO L704 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-02-21 04:22:01,479 INFO L587 BuchiCegarLoop]: Abstraction has 830 states and 1234 transitions. [2022-02-21 04:22:01,479 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:22:01,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 830 states and 1234 transitions. [2022-02-21 04:22:01,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 727 [2022-02-21 04:22:01,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:01,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:01,482 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,482 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:01,482 INFO L791 eck$LassoCheckResult]: Stem: 22293#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 22294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 22176#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22126#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22127#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 22410#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22109#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21949#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21950#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21931#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21932#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22409#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22234#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22235#L769 assume !(0 == ~M_E~0); 22257#L769-2 assume !(0 == ~T1_E~0); 22258#L774-1 assume !(0 == ~T2_E~0); 22285#L779-1 assume !(0 == ~T3_E~0); 22397#L784-1 assume !(0 == ~T4_E~0); 22230#L789-1 assume !(0 == ~T5_E~0); 22231#L794-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22341#L799-1 assume !(0 == ~T7_E~0); 22237#L804-1 assume !(0 == ~E_M~0); 22238#L809-1 assume !(0 == ~E_1~0); 22278#L814-1 assume !(0 == ~E_2~0); 21667#L819-1 assume !(0 == ~E_3~0); 21668#L824-1 assume !(0 == ~E_4~0); 22019#L829-1 assume !(0 == ~E_5~0); 22456#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 21803#L839-1 assume !(0 == ~E_7~0); 21804#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22182#L376 assume !(1 == ~m_pc~0); 22169#L376-2 is_master_triggered_~__retres1~0#1 := 0; 22168#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22439#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21750#L955 assume !(0 != activate_threads_~tmp~1#1); 21751#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22102#L395 assume 1 == ~t1_pc~0; 21780#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21781#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21673#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21674#L963 assume !(0 != activate_threads_~tmp___0~0#1); 22186#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22187#L414 assume !(1 == ~t2_pc~0); 21806#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21807#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22005#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22006#L971 assume !(0 != activate_threads_~tmp___1~0#1); 22413#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22105#L433 assume 1 == ~t3_pc~0; 22050#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21920#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22078#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22079#L979 assume !(0 != activate_threads_~tmp___2~0#1); 21771#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21772#L452 assume !(1 == ~t4_pc~0); 21927#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21928#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22218#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22284#L987 assume !(0 != activate_threads_~tmp___3~0#1); 21960#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21961#L471 assume 1 == ~t5_pc~0; 22329#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21943#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21944#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22279#L995 assume !(0 != activate_threads_~tmp___4~0#1); 22448#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22449#L490 assume 1 == ~t6_pc~0; 22432#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22185#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22225#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22228#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 22114#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22083#L509 assume !(1 == ~t7_pc~0); 22084#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21901#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21902#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21965#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21966#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22421#L857 assume !(1 == ~M_E~0); 21757#L857-2 assume !(1 == ~T1_E~0); 21758#L862-1 assume !(1 == ~T2_E~0); 22027#L867-1 assume !(1 == ~T3_E~0); 22032#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22106#L877-1 assume !(1 == ~T5_E~0); 22305#L882-1 assume !(1 == ~T6_E~0); 22431#L887-1 assume !(1 == ~T7_E~0); 22355#L892-1 assume !(1 == ~E_M~0); 22356#L897-1 assume !(1 == ~E_1~0); 22042#L902-1 assume !(1 == ~E_2~0); 22043#L907-1 assume !(1 == ~E_3~0); 22322#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 22313#L917-1 assume !(1 == ~E_5~0); 22314#L922-1 assume !(1 == ~E_6~0); 22459#L927-1 assume !(1 == ~E_7~0); 22300#L932-1 assume { :end_inline_reset_delta_events } true; 21706#L1178-2 [2022-02-21 04:22:01,482 INFO L793 eck$LassoCheckResult]: Loop: 21706#L1178-2 assume !false; 22289#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21723#L744 assume !false; 22077#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 22150#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21741#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21947#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22401#L641 assume !(0 != eval_~tmp~0#1); 22217#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21841#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21842#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22103#L769-5 assume !(0 == ~T1_E~0); 22104#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21858#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21682#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21683#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21669#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21670#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21721#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21975#L809-3 assume !(0 == ~E_1~0); 21717#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21718#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22377#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22372#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22028#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22029#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 22340#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22419#L376-27 assume 1 == ~m_pc~0; 22318#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22264#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22265#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22359#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22462#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22483#L395-27 assume !(1 == ~t1_pc~0); 22122#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 22030#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22031#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22256#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22110#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22111#L414-27 assume 1 == ~t2_pc~0; 22446#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22311#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22312#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22171#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21733#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21734#L433-27 assume !(1 == ~t3_pc~0); 21829#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 22116#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22117#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21904#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 21905#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22476#L452-27 assume !(1 == ~t4_pc~0); 22275#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 22276#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22400#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22442#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22443#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21724#L471-27 assume !(1 == ~t5_pc~0); 21725#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 22039#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22418#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22332#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22260#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22181#L490-27 assume 1 == ~t6_pc~0; 22080#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21916#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21917#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22320#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22321#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21691#L509-27 assume !(1 == ~t7_pc~0); 21692#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 22082#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22207#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22198#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22199#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22213#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22214#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22254#L862-3 assume !(1 == ~T2_E~0); 22474#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22118#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22119#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22208#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22248#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21878#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21879#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22392#L902-3 assume !(1 == ~E_2~0); 22040#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22041#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22160#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22123#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21929#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21930#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21778#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21681#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22343#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 22093#L1197 assume !(0 == start_simulation_~tmp~3#1); 22094#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21837#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21801#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 21727#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 21728#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22389#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22390#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 21705#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 21706#L1178-2 [2022-02-21 04:22:01,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,482 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-02-21 04:22:01,482 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,483 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212168006] [2022-02-21 04:22:01,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,506 INFO L290 TraceCheckUtils]: 0: Hoare triple {24147#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,506 INFO L290 TraceCheckUtils]: 1: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,506 INFO L290 TraceCheckUtils]: 2: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,506 INFO L290 TraceCheckUtils]: 3: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,507 INFO L290 TraceCheckUtils]: 4: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,507 INFO L290 TraceCheckUtils]: 5: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,507 INFO L290 TraceCheckUtils]: 6: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,507 INFO L290 TraceCheckUtils]: 7: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,508 INFO L290 TraceCheckUtils]: 8: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,508 INFO L290 TraceCheckUtils]: 9: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,508 INFO L290 TraceCheckUtils]: 10: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,508 INFO L290 TraceCheckUtils]: 11: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,509 INFO L290 TraceCheckUtils]: 12: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24149#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:01,509 INFO L290 TraceCheckUtils]: 13: Hoare triple {24149#(= ~T6_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,509 INFO L290 TraceCheckUtils]: 14: Hoare triple {24150#(not (= ~T6_E~0 0))} assume !(0 == ~T1_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,509 INFO L290 TraceCheckUtils]: 15: Hoare triple {24150#(not (= ~T6_E~0 0))} assume !(0 == ~T2_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 16: Hoare triple {24150#(not (= ~T6_E~0 0))} assume !(0 == ~T3_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 17: Hoare triple {24150#(not (= ~T6_E~0 0))} assume !(0 == ~T4_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 18: Hoare triple {24150#(not (= ~T6_E~0 0))} assume !(0 == ~T5_E~0); {24150#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 19: Hoare triple {24150#(not (= ~T6_E~0 0))} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24148#false} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 20: Hoare triple {24148#false} assume !(0 == ~T7_E~0); {24148#false} is VALID [2022-02-21 04:22:01,510 INFO L290 TraceCheckUtils]: 21: Hoare triple {24148#false} assume !(0 == ~E_M~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 22: Hoare triple {24148#false} assume !(0 == ~E_1~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 23: Hoare triple {24148#false} assume !(0 == ~E_2~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 24: Hoare triple {24148#false} assume !(0 == ~E_3~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 25: Hoare triple {24148#false} assume !(0 == ~E_4~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 26: Hoare triple {24148#false} assume !(0 == ~E_5~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 27: Hoare triple {24148#false} assume 0 == ~E_6~0;~E_6~0 := 1; {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 28: Hoare triple {24148#false} assume !(0 == ~E_7~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 29: Hoare triple {24148#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 30: Hoare triple {24148#false} assume !(1 == ~m_pc~0); {24148#false} is VALID [2022-02-21 04:22:01,511 INFO L290 TraceCheckUtils]: 31: Hoare triple {24148#false} is_master_triggered_~__retres1~0#1 := 0; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 32: Hoare triple {24148#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 33: Hoare triple {24148#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 34: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp~1#1); {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 35: Hoare triple {24148#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 36: Hoare triple {24148#false} assume 1 == ~t1_pc~0; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 37: Hoare triple {24148#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 38: Hoare triple {24148#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 39: Hoare triple {24148#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 40: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___0~0#1); {24148#false} is VALID [2022-02-21 04:22:01,512 INFO L290 TraceCheckUtils]: 41: Hoare triple {24148#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 42: Hoare triple {24148#false} assume !(1 == ~t2_pc~0); {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 43: Hoare triple {24148#false} is_transmit2_triggered_~__retres1~2#1 := 0; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 44: Hoare triple {24148#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 45: Hoare triple {24148#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 46: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___1~0#1); {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 47: Hoare triple {24148#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 48: Hoare triple {24148#false} assume 1 == ~t3_pc~0; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 49: Hoare triple {24148#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 50: Hoare triple {24148#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24148#false} is VALID [2022-02-21 04:22:01,513 INFO L290 TraceCheckUtils]: 51: Hoare triple {24148#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 52: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___2~0#1); {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 53: Hoare triple {24148#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 54: Hoare triple {24148#false} assume !(1 == ~t4_pc~0); {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 55: Hoare triple {24148#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 56: Hoare triple {24148#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 57: Hoare triple {24148#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 58: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___3~0#1); {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 59: Hoare triple {24148#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 60: Hoare triple {24148#false} assume 1 == ~t5_pc~0; {24148#false} is VALID [2022-02-21 04:22:01,514 INFO L290 TraceCheckUtils]: 61: Hoare triple {24148#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 62: Hoare triple {24148#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 63: Hoare triple {24148#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 64: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___4~0#1); {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 65: Hoare triple {24148#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 66: Hoare triple {24148#false} assume 1 == ~t6_pc~0; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 67: Hoare triple {24148#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 68: Hoare triple {24148#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 69: Hoare triple {24148#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24148#false} is VALID [2022-02-21 04:22:01,515 INFO L290 TraceCheckUtils]: 70: Hoare triple {24148#false} assume !(0 != activate_threads_~tmp___5~0#1); {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 71: Hoare triple {24148#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 72: Hoare triple {24148#false} assume !(1 == ~t7_pc~0); {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 73: Hoare triple {24148#false} is_transmit7_triggered_~__retres1~7#1 := 0; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 74: Hoare triple {24148#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 75: Hoare triple {24148#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 76: Hoare triple {24148#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 77: Hoare triple {24148#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 78: Hoare triple {24148#false} assume !(1 == ~M_E~0); {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 79: Hoare triple {24148#false} assume !(1 == ~T1_E~0); {24148#false} is VALID [2022-02-21 04:22:01,516 INFO L290 TraceCheckUtils]: 80: Hoare triple {24148#false} assume !(1 == ~T2_E~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 81: Hoare triple {24148#false} assume !(1 == ~T3_E~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 82: Hoare triple {24148#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 83: Hoare triple {24148#false} assume !(1 == ~T5_E~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 84: Hoare triple {24148#false} assume !(1 == ~T6_E~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 85: Hoare triple {24148#false} assume !(1 == ~T7_E~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 86: Hoare triple {24148#false} assume !(1 == ~E_M~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 87: Hoare triple {24148#false} assume !(1 == ~E_1~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 88: Hoare triple {24148#false} assume !(1 == ~E_2~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 89: Hoare triple {24148#false} assume !(1 == ~E_3~0); {24148#false} is VALID [2022-02-21 04:22:01,517 INFO L290 TraceCheckUtils]: 90: Hoare triple {24148#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24148#false} is VALID [2022-02-21 04:22:01,518 INFO L290 TraceCheckUtils]: 91: Hoare triple {24148#false} assume !(1 == ~E_5~0); {24148#false} is VALID [2022-02-21 04:22:01,518 INFO L290 TraceCheckUtils]: 92: Hoare triple {24148#false} assume !(1 == ~E_6~0); {24148#false} is VALID [2022-02-21 04:22:01,518 INFO L290 TraceCheckUtils]: 93: Hoare triple {24148#false} assume !(1 == ~E_7~0); {24148#false} is VALID [2022-02-21 04:22:01,518 INFO L290 TraceCheckUtils]: 94: Hoare triple {24148#false} assume { :end_inline_reset_delta_events } true; {24148#false} is VALID [2022-02-21 04:22:01,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,518 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,518 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212168006] [2022-02-21 04:22:01,518 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212168006] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,519 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,519 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,519 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808388478] [2022-02-21 04:22:01,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,519 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:01,519 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:01,519 INFO L85 PathProgramCache]: Analyzing trace with hash -2107502741, now seen corresponding path program 3 times [2022-02-21 04:22:01,520 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:01,520 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757909525] [2022-02-21 04:22:01,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:01,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:01,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 0: Hoare triple {24151#true} assume !false; {24151#true} is VALID [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 1: Hoare triple {24151#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24151#true} is VALID [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 2: Hoare triple {24151#true} assume !false; {24151#true} is VALID [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 3: Hoare triple {24151#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24151#true} is VALID [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 4: Hoare triple {24151#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24151#true} is VALID [2022-02-21 04:22:01,540 INFO L290 TraceCheckUtils]: 5: Hoare triple {24151#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 6: Hoare triple {24151#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 7: Hoare triple {24151#true} assume !(0 != eval_~tmp~0#1); {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 8: Hoare triple {24151#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 9: Hoare triple {24151#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 10: Hoare triple {24151#true} assume 0 == ~M_E~0;~M_E~0 := 1; {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 11: Hoare triple {24151#true} assume !(0 == ~T1_E~0); {24151#true} is VALID [2022-02-21 04:22:01,541 INFO L290 TraceCheckUtils]: 12: Hoare triple {24151#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,542 INFO L290 TraceCheckUtils]: 13: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,542 INFO L290 TraceCheckUtils]: 14: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,542 INFO L290 TraceCheckUtils]: 15: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,542 INFO L290 TraceCheckUtils]: 16: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,543 INFO L290 TraceCheckUtils]: 17: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,543 INFO L290 TraceCheckUtils]: 18: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,543 INFO L290 TraceCheckUtils]: 19: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,543 INFO L290 TraceCheckUtils]: 20: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,543 INFO L290 TraceCheckUtils]: 21: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,544 INFO L290 TraceCheckUtils]: 22: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,544 INFO L290 TraceCheckUtils]: 23: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,544 INFO L290 TraceCheckUtils]: 24: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,544 INFO L290 TraceCheckUtils]: 25: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,545 INFO L290 TraceCheckUtils]: 26: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,545 INFO L290 TraceCheckUtils]: 27: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~m_pc~0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,545 INFO L290 TraceCheckUtils]: 28: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,545 INFO L290 TraceCheckUtils]: 29: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,546 INFO L290 TraceCheckUtils]: 30: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,546 INFO L290 TraceCheckUtils]: 31: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,546 INFO L290 TraceCheckUtils]: 32: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,546 INFO L290 TraceCheckUtils]: 33: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,547 INFO L290 TraceCheckUtils]: 34: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,547 INFO L290 TraceCheckUtils]: 35: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,547 INFO L290 TraceCheckUtils]: 36: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,547 INFO L290 TraceCheckUtils]: 37: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,547 INFO L290 TraceCheckUtils]: 38: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,549 INFO L290 TraceCheckUtils]: 39: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,549 INFO L290 TraceCheckUtils]: 40: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,549 INFO L290 TraceCheckUtils]: 41: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,549 INFO L290 TraceCheckUtils]: 42: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,550 INFO L290 TraceCheckUtils]: 43: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,550 INFO L290 TraceCheckUtils]: 44: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,550 INFO L290 TraceCheckUtils]: 45: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,550 INFO L290 TraceCheckUtils]: 46: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,551 INFO L290 TraceCheckUtils]: 47: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,551 INFO L290 TraceCheckUtils]: 48: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,551 INFO L290 TraceCheckUtils]: 49: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,551 INFO L290 TraceCheckUtils]: 50: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,551 INFO L290 TraceCheckUtils]: 51: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,552 INFO L290 TraceCheckUtils]: 52: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,552 INFO L290 TraceCheckUtils]: 53: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,552 INFO L290 TraceCheckUtils]: 54: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,552 INFO L290 TraceCheckUtils]: 55: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,553 INFO L290 TraceCheckUtils]: 56: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,553 INFO L290 TraceCheckUtils]: 57: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,553 INFO L290 TraceCheckUtils]: 58: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,553 INFO L290 TraceCheckUtils]: 59: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,554 INFO L290 TraceCheckUtils]: 60: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,554 INFO L290 TraceCheckUtils]: 61: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,554 INFO L290 TraceCheckUtils]: 62: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,554 INFO L290 TraceCheckUtils]: 63: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,554 INFO L290 TraceCheckUtils]: 64: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,555 INFO L290 TraceCheckUtils]: 65: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,555 INFO L290 TraceCheckUtils]: 66: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,555 INFO L290 TraceCheckUtils]: 67: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,555 INFO L290 TraceCheckUtils]: 68: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,556 INFO L290 TraceCheckUtils]: 69: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,556 INFO L290 TraceCheckUtils]: 70: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,556 INFO L290 TraceCheckUtils]: 71: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,556 INFO L290 TraceCheckUtils]: 72: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,557 INFO L290 TraceCheckUtils]: 73: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,557 INFO L290 TraceCheckUtils]: 74: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,557 INFO L290 TraceCheckUtils]: 75: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,557 INFO L290 TraceCheckUtils]: 76: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24153#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 77: Hoare triple {24153#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 78: Hoare triple {24152#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 79: Hoare triple {24152#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 80: Hoare triple {24152#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 81: Hoare triple {24152#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 82: Hoare triple {24152#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 83: Hoare triple {24152#false} assume 1 == ~E_M~0;~E_M~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 84: Hoare triple {24152#false} assume 1 == ~E_1~0;~E_1~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 85: Hoare triple {24152#false} assume !(1 == ~E_2~0); {24152#false} is VALID [2022-02-21 04:22:01,558 INFO L290 TraceCheckUtils]: 86: Hoare triple {24152#false} assume 1 == ~E_3~0;~E_3~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 87: Hoare triple {24152#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 88: Hoare triple {24152#false} assume 1 == ~E_5~0;~E_5~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 89: Hoare triple {24152#false} assume 1 == ~E_6~0;~E_6~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 90: Hoare triple {24152#false} assume 1 == ~E_7~0;~E_7~0 := 2; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 91: Hoare triple {24152#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 92: Hoare triple {24152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 93: Hoare triple {24152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 94: Hoare triple {24152#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 95: Hoare triple {24152#false} assume !(0 == start_simulation_~tmp~3#1); {24152#false} is VALID [2022-02-21 04:22:01,559 INFO L290 TraceCheckUtils]: 96: Hoare triple {24152#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 97: Hoare triple {24152#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 98: Hoare triple {24152#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 99: Hoare triple {24152#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 100: Hoare triple {24152#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 101: Hoare triple {24152#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 102: Hoare triple {24152#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L290 TraceCheckUtils]: 103: Hoare triple {24152#false} assume !(0 != start_simulation_~tmp___0~1#1); {24152#false} is VALID [2022-02-21 04:22:01,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,561 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,561 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757909525] [2022-02-21 04:22:01,561 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757909525] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,561 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,561 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,561 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243759574] [2022-02-21 04:22:01,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,562 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:01,562 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:01,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:01,562 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:01,562 INFO L87 Difference]: Start difference. First operand 830 states and 1234 transitions. cyclomatic complexity: 405 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,925 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2022-02-21 04:22:02,925 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:02,926 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,979 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:02,979 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,030 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-02-21 04:22:03,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-02-21 04:22:03,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1499 [2022-02-21 04:22:03,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1499 [2022-02-21 04:22:03,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:03,082 INFO L681 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-02-21 04:22:03,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 1499. [2022-02-21 04:22:03,098 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:03,099 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1499 states and 2220 transitions. Second operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,101 INFO L74 IsIncluded]: Start isIncluded. First operand 1499 states and 2220 transitions. Second operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,102 INFO L87 Difference]: Start difference. First operand 1499 states and 2220 transitions. Second operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:03,150 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2022-02-21 04:22:03,150 INFO L276 IsEmpty]: Start isEmpty. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,152 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:03,153 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:03,154 INFO L74 IsIncluded]: Start isIncluded. First operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,156 INFO L87 Difference]: Start difference. First operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:03,204 INFO L93 Difference]: Finished difference Result 1499 states and 2220 transitions. [2022-02-21 04:22:03,204 INFO L276 IsEmpty]: Start isEmpty. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,206 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:03,206 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:03,206 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:03,206 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:03,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1499 states, 1499 states have (on average 1.4809873248832555) internal successors, (2220), 1498 states have internal predecessors, (2220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1499 states to 1499 states and 2220 transitions. [2022-02-21 04:22:03,254 INFO L704 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-02-21 04:22:03,254 INFO L587 BuchiCegarLoop]: Abstraction has 1499 states and 2220 transitions. [2022-02-21 04:22:03,254 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:22:03,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1499 states and 2220 transitions. [2022-02-21 04:22:03,258 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1380 [2022-02-21 04:22:03,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:03,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:03,259 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:03,259 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:03,259 INFO L791 eck$LassoCheckResult]: Stem: 26302#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26183#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26130#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26131#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 26427#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26113#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25950#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25951#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25932#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25933#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26426#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26243#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26244#L769 assume !(0 == ~M_E~0); 26267#L769-2 assume !(0 == ~T1_E~0); 26268#L774-1 assume !(0 == ~T2_E~0); 26294#L779-1 assume !(0 == ~T3_E~0); 26413#L784-1 assume !(0 == ~T4_E~0); 26238#L789-1 assume !(0 == ~T5_E~0); 26239#L794-1 assume !(0 == ~T6_E~0); 26353#L799-1 assume !(0 == ~T7_E~0); 26245#L804-1 assume !(0 == ~E_M~0); 26246#L809-1 assume !(0 == ~E_1~0); 26287#L814-1 assume !(0 == ~E_2~0); 25670#L819-1 assume !(0 == ~E_3~0); 25671#L824-1 assume !(0 == ~E_4~0); 26022#L829-1 assume !(0 == ~E_5~0); 26496#L834-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25804#L839-1 assume !(0 == ~E_7~0); 25805#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26189#L376 assume !(1 == ~m_pc~0); 26178#L376-2 is_master_triggered_~__retres1~0#1 := 0; 26177#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26473#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25753#L955 assume !(0 != activate_threads_~tmp~1#1); 25754#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26106#L395 assume 1 == ~t1_pc~0; 25781#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25782#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25676#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25677#L963 assume !(0 != activate_threads_~tmp___0~0#1); 26194#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26195#L414 assume !(1 == ~t2_pc~0); 25807#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25808#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26008#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26009#L971 assume !(0 != activate_threads_~tmp___1~0#1); 26430#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26109#L433 assume 1 == ~t3_pc~0; 26053#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25923#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26084#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26085#L979 assume !(0 != activate_threads_~tmp___2~0#1); 25772#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25773#L452 assume !(1 == ~t4_pc~0); 25928#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25929#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26227#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26293#L987 assume !(0 != activate_threads_~tmp___3~0#1); 25962#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25963#L471 assume 1 == ~t5_pc~0; 26340#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25944#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25945#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26288#L995 assume !(0 != activate_threads_~tmp___4~0#1); 26485#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26486#L490 assume 1 == ~t6_pc~0; 26461#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26192#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26233#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26236#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 26120#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26087#L509 assume !(1 == ~t7_pc~0); 26088#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25907#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25908#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25967#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25968#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26440#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 26441#L857-2 assume !(1 == ~T1_E~0); 26685#L862-1 assume !(1 == ~T2_E~0); 26683#L867-1 assume !(1 == ~T3_E~0); 26680#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26678#L877-1 assume !(1 == ~T5_E~0); 26676#L882-1 assume !(1 == ~T6_E~0); 26458#L887-1 assume !(1 == ~T7_E~0); 26673#L892-1 assume !(1 == ~E_M~0); 26672#L897-1 assume !(1 == ~E_1~0); 26671#L902-1 assume !(1 == ~E_2~0); 26670#L907-1 assume !(1 == ~E_3~0); 26667#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26565#L917-1 assume !(1 == ~E_5~0); 26561#L922-1 assume !(1 == ~E_6~0); 26560#L927-1 assume !(1 == ~E_7~0); 26555#L932-1 assume { :end_inline_reset_delta_events } true; 26549#L1178-2 [2022-02-21 04:22:03,259 INFO L793 eck$LassoCheckResult]: Loop: 26549#L1178-2 assume !false; 26545#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26544#L744 assume !false; 26155#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26156#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 25742#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 25948#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26419#L641 assume !(0 != eval_~tmp~0#1); 26225#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25842#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25843#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26531#L769-5 assume !(0 == ~T1_E~0); 27153#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27152#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27151#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27150#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27149#L794-3 assume !(0 == ~T6_E~0); 27148#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27147#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27146#L809-3 assume !(0 == ~E_1~0); 27145#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27144#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27143#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27142#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27141#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27140#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27139#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27138#L376-27 assume !(1 == ~m_pc~0); 27136#L376-29 is_master_triggered_~__retres1~0#1 := 0; 27135#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27134#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27133#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27132#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27131#L395-27 assume 1 == ~t1_pc~0; 27129#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27128#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27127#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27126#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27125#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27124#L414-27 assume !(1 == ~t2_pc~0); 27122#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 27121#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27120#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27119#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27118#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27117#L433-27 assume 1 == ~t3_pc~0; 27115#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26118#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26119#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25903#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 25904#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26518#L452-27 assume 1 == ~t4_pc~0; 26519#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26285#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26416#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26478#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26479#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25725#L471-27 assume !(1 == ~t5_pc~0); 25726#L471-29 is_transmit5_triggered_~__retres1~5#1 := 0; 26039#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26435#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26343#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26269#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26188#L490-27 assume 1 == ~t6_pc~0; 26082#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25917#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25918#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26330#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26331#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25692#L509-27 assume !(1 == ~t7_pc~0); 25693#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 26086#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26214#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26205#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26206#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26221#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26222#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26263#L862-3 assume !(1 == ~T2_E~0); 26516#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26122#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26123#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26215#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26257#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25877#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25878#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26408#L902-3 assume !(1 == ~E_2~0); 26043#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26044#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26166#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26127#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25930#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25931#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 25779#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 25682#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26355#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 26097#L1197 assume !(0 == start_simulation_~tmp~3#1); 26098#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 25838#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 25802#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 25728#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 25729#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26404#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26405#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 26556#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 26549#L1178-2 [2022-02-21 04:22:03,260 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,260 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-02-21 04:22:03,260 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,260 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607445714] [2022-02-21 04:22:03,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:03,295 INFO L290 TraceCheckUtils]: 0: Hoare triple {30155#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,296 INFO L290 TraceCheckUtils]: 1: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,296 INFO L290 TraceCheckUtils]: 2: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,296 INFO L290 TraceCheckUtils]: 3: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,296 INFO L290 TraceCheckUtils]: 4: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,297 INFO L290 TraceCheckUtils]: 5: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,297 INFO L290 TraceCheckUtils]: 6: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,297 INFO L290 TraceCheckUtils]: 7: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,298 INFO L290 TraceCheckUtils]: 8: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,298 INFO L290 TraceCheckUtils]: 9: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,298 INFO L290 TraceCheckUtils]: 10: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,298 INFO L290 TraceCheckUtils]: 11: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,299 INFO L290 TraceCheckUtils]: 12: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {30157#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:03,299 INFO L290 TraceCheckUtils]: 13: Hoare triple {30157#(= ~E_6~0 ~M_E~0)} assume !(0 == ~M_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,299 INFO L290 TraceCheckUtils]: 14: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T1_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,299 INFO L290 TraceCheckUtils]: 15: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T2_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,300 INFO L290 TraceCheckUtils]: 16: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T3_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,300 INFO L290 TraceCheckUtils]: 17: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T4_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,300 INFO L290 TraceCheckUtils]: 18: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T5_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,300 INFO L290 TraceCheckUtils]: 19: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T6_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,301 INFO L290 TraceCheckUtils]: 20: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~T7_E~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,301 INFO L290 TraceCheckUtils]: 21: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_M~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,301 INFO L290 TraceCheckUtils]: 22: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_1~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,301 INFO L290 TraceCheckUtils]: 23: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_2~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 24: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_3~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 25: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_4~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 26: Hoare triple {30158#(not (= ~E_6~0 0))} assume !(0 == ~E_5~0); {30158#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 27: Hoare triple {30158#(not (= ~E_6~0 0))} assume 0 == ~E_6~0;~E_6~0 := 1; {30156#false} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 28: Hoare triple {30156#false} assume !(0 == ~E_7~0); {30156#false} is VALID [2022-02-21 04:22:03,302 INFO L290 TraceCheckUtils]: 29: Hoare triple {30156#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 30: Hoare triple {30156#false} assume !(1 == ~m_pc~0); {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 31: Hoare triple {30156#false} is_master_triggered_~__retres1~0#1 := 0; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 32: Hoare triple {30156#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 33: Hoare triple {30156#false} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 34: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp~1#1); {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 35: Hoare triple {30156#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 36: Hoare triple {30156#false} assume 1 == ~t1_pc~0; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 37: Hoare triple {30156#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30156#false} is VALID [2022-02-21 04:22:03,303 INFO L290 TraceCheckUtils]: 38: Hoare triple {30156#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 39: Hoare triple {30156#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 40: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___0~0#1); {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 41: Hoare triple {30156#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 42: Hoare triple {30156#false} assume !(1 == ~t2_pc~0); {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 43: Hoare triple {30156#false} is_transmit2_triggered_~__retres1~2#1 := 0; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 44: Hoare triple {30156#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 45: Hoare triple {30156#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 46: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___1~0#1); {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 47: Hoare triple {30156#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30156#false} is VALID [2022-02-21 04:22:03,304 INFO L290 TraceCheckUtils]: 48: Hoare triple {30156#false} assume 1 == ~t3_pc~0; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 49: Hoare triple {30156#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 50: Hoare triple {30156#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 51: Hoare triple {30156#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 52: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___2~0#1); {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 53: Hoare triple {30156#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 54: Hoare triple {30156#false} assume !(1 == ~t4_pc~0); {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 55: Hoare triple {30156#false} is_transmit4_triggered_~__retres1~4#1 := 0; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 56: Hoare triple {30156#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 57: Hoare triple {30156#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30156#false} is VALID [2022-02-21 04:22:03,305 INFO L290 TraceCheckUtils]: 58: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___3~0#1); {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 59: Hoare triple {30156#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 60: Hoare triple {30156#false} assume 1 == ~t5_pc~0; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 61: Hoare triple {30156#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 62: Hoare triple {30156#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 63: Hoare triple {30156#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 64: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___4~0#1); {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 65: Hoare triple {30156#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 66: Hoare triple {30156#false} assume 1 == ~t6_pc~0; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 67: Hoare triple {30156#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30156#false} is VALID [2022-02-21 04:22:03,306 INFO L290 TraceCheckUtils]: 68: Hoare triple {30156#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 69: Hoare triple {30156#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 70: Hoare triple {30156#false} assume !(0 != activate_threads_~tmp___5~0#1); {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 71: Hoare triple {30156#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 72: Hoare triple {30156#false} assume !(1 == ~t7_pc~0); {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 73: Hoare triple {30156#false} is_transmit7_triggered_~__retres1~7#1 := 0; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 74: Hoare triple {30156#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 75: Hoare triple {30156#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 76: Hoare triple {30156#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 77: Hoare triple {30156#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30156#false} is VALID [2022-02-21 04:22:03,307 INFO L290 TraceCheckUtils]: 78: Hoare triple {30156#false} assume 1 == ~M_E~0;~M_E~0 := 2; {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 79: Hoare triple {30156#false} assume !(1 == ~T1_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 80: Hoare triple {30156#false} assume !(1 == ~T2_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 81: Hoare triple {30156#false} assume !(1 == ~T3_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 82: Hoare triple {30156#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 83: Hoare triple {30156#false} assume !(1 == ~T5_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 84: Hoare triple {30156#false} assume !(1 == ~T6_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 85: Hoare triple {30156#false} assume !(1 == ~T7_E~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 86: Hoare triple {30156#false} assume !(1 == ~E_M~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 87: Hoare triple {30156#false} assume !(1 == ~E_1~0); {30156#false} is VALID [2022-02-21 04:22:03,308 INFO L290 TraceCheckUtils]: 88: Hoare triple {30156#false} assume !(1 == ~E_2~0); {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 89: Hoare triple {30156#false} assume !(1 == ~E_3~0); {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 90: Hoare triple {30156#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 91: Hoare triple {30156#false} assume !(1 == ~E_5~0); {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 92: Hoare triple {30156#false} assume !(1 == ~E_6~0); {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 93: Hoare triple {30156#false} assume !(1 == ~E_7~0); {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L290 TraceCheckUtils]: 94: Hoare triple {30156#false} assume { :end_inline_reset_delta_events } true; {30156#false} is VALID [2022-02-21 04:22:03,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:03,309 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:03,310 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607445714] [2022-02-21 04:22:03,310 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607445714] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:03,310 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:03,310 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:03,310 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079893068] [2022-02-21 04:22:03,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:03,311 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:03,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1306436888, now seen corresponding path program 1 times [2022-02-21 04:22:03,311 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,311 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343994881] [2022-02-21 04:22:03,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:03,332 INFO L290 TraceCheckUtils]: 0: Hoare triple {30159#true} assume !false; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 1: Hoare triple {30159#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 2: Hoare triple {30159#true} assume !false; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 3: Hoare triple {30159#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 4: Hoare triple {30159#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 5: Hoare triple {30159#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 6: Hoare triple {30159#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {30159#true} is VALID [2022-02-21 04:22:03,333 INFO L290 TraceCheckUtils]: 7: Hoare triple {30159#true} assume !(0 != eval_~tmp~0#1); {30159#true} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 8: Hoare triple {30159#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {30159#true} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 9: Hoare triple {30159#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {30159#true} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 10: Hoare triple {30159#true} assume 0 == ~M_E~0;~M_E~0 := 1; {30159#true} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 11: Hoare triple {30159#true} assume !(0 == ~T1_E~0); {30159#true} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 12: Hoare triple {30159#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,334 INFO L290 TraceCheckUtils]: 13: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,335 INFO L290 TraceCheckUtils]: 14: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,335 INFO L290 TraceCheckUtils]: 15: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,335 INFO L290 TraceCheckUtils]: 16: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,335 INFO L290 TraceCheckUtils]: 17: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,336 INFO L290 TraceCheckUtils]: 18: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,336 INFO L290 TraceCheckUtils]: 19: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,336 INFO L290 TraceCheckUtils]: 20: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,336 INFO L290 TraceCheckUtils]: 21: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,337 INFO L290 TraceCheckUtils]: 22: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,337 INFO L290 TraceCheckUtils]: 23: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,337 INFO L290 TraceCheckUtils]: 24: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,337 INFO L290 TraceCheckUtils]: 25: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,338 INFO L290 TraceCheckUtils]: 26: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,338 INFO L290 TraceCheckUtils]: 27: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,338 INFO L290 TraceCheckUtils]: 28: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,338 INFO L290 TraceCheckUtils]: 29: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,339 INFO L290 TraceCheckUtils]: 30: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,339 INFO L290 TraceCheckUtils]: 31: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,339 INFO L290 TraceCheckUtils]: 32: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,339 INFO L290 TraceCheckUtils]: 33: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,340 INFO L290 TraceCheckUtils]: 34: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,340 INFO L290 TraceCheckUtils]: 35: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,340 INFO L290 TraceCheckUtils]: 36: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,340 INFO L290 TraceCheckUtils]: 37: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,341 INFO L290 TraceCheckUtils]: 38: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,341 INFO L290 TraceCheckUtils]: 39: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,341 INFO L290 TraceCheckUtils]: 40: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,341 INFO L290 TraceCheckUtils]: 41: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,342 INFO L290 TraceCheckUtils]: 42: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,342 INFO L290 TraceCheckUtils]: 43: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,342 INFO L290 TraceCheckUtils]: 44: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,342 INFO L290 TraceCheckUtils]: 45: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,343 INFO L290 TraceCheckUtils]: 46: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,343 INFO L290 TraceCheckUtils]: 47: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,343 INFO L290 TraceCheckUtils]: 48: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,343 INFO L290 TraceCheckUtils]: 49: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,344 INFO L290 TraceCheckUtils]: 50: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,344 INFO L290 TraceCheckUtils]: 51: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,344 INFO L290 TraceCheckUtils]: 52: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,344 INFO L290 TraceCheckUtils]: 53: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,345 INFO L290 TraceCheckUtils]: 54: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,345 INFO L290 TraceCheckUtils]: 55: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,345 INFO L290 TraceCheckUtils]: 56: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,345 INFO L290 TraceCheckUtils]: 57: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t5_pc~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,346 INFO L290 TraceCheckUtils]: 58: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_~__retres1~5#1 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,346 INFO L290 TraceCheckUtils]: 59: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,346 INFO L290 TraceCheckUtils]: 60: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,346 INFO L290 TraceCheckUtils]: 61: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,347 INFO L290 TraceCheckUtils]: 62: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,347 INFO L290 TraceCheckUtils]: 63: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,347 INFO L290 TraceCheckUtils]: 64: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,347 INFO L290 TraceCheckUtils]: 65: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,348 INFO L290 TraceCheckUtils]: 66: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,348 INFO L290 TraceCheckUtils]: 67: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,348 INFO L290 TraceCheckUtils]: 68: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,348 INFO L290 TraceCheckUtils]: 69: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,348 INFO L290 TraceCheckUtils]: 70: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,349 INFO L290 TraceCheckUtils]: 71: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,349 INFO L290 TraceCheckUtils]: 72: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,349 INFO L290 TraceCheckUtils]: 73: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,349 INFO L290 TraceCheckUtils]: 74: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,350 INFO L290 TraceCheckUtils]: 75: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,350 INFO L290 TraceCheckUtils]: 76: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30161#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:03,350 INFO L290 TraceCheckUtils]: 77: Hoare triple {30161#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {30160#false} is VALID [2022-02-21 04:22:03,350 INFO L290 TraceCheckUtils]: 78: Hoare triple {30160#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,350 INFO L290 TraceCheckUtils]: 79: Hoare triple {30160#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 80: Hoare triple {30160#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 81: Hoare triple {30160#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 82: Hoare triple {30160#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 83: Hoare triple {30160#false} assume 1 == ~E_M~0;~E_M~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 84: Hoare triple {30160#false} assume 1 == ~E_1~0;~E_1~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 85: Hoare triple {30160#false} assume !(1 == ~E_2~0); {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 86: Hoare triple {30160#false} assume 1 == ~E_3~0;~E_3~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 87: Hoare triple {30160#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 88: Hoare triple {30160#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,351 INFO L290 TraceCheckUtils]: 89: Hoare triple {30160#false} assume 1 == ~E_6~0;~E_6~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 90: Hoare triple {30160#false} assume 1 == ~E_7~0;~E_7~0 := 2; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 91: Hoare triple {30160#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 92: Hoare triple {30160#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 93: Hoare triple {30160#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 94: Hoare triple {30160#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 95: Hoare triple {30160#false} assume !(0 == start_simulation_~tmp~3#1); {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 96: Hoare triple {30160#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 97: Hoare triple {30160#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 98: Hoare triple {30160#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30160#false} is VALID [2022-02-21 04:22:03,352 INFO L290 TraceCheckUtils]: 99: Hoare triple {30160#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {30160#false} is VALID [2022-02-21 04:22:03,353 INFO L290 TraceCheckUtils]: 100: Hoare triple {30160#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {30160#false} is VALID [2022-02-21 04:22:03,353 INFO L290 TraceCheckUtils]: 101: Hoare triple {30160#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {30160#false} is VALID [2022-02-21 04:22:03,353 INFO L290 TraceCheckUtils]: 102: Hoare triple {30160#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {30160#false} is VALID [2022-02-21 04:22:03,353 INFO L290 TraceCheckUtils]: 103: Hoare triple {30160#false} assume !(0 != start_simulation_~tmp___0~1#1); {30160#false} is VALID [2022-02-21 04:22:03,353 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:03,353 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:03,353 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1343994881] [2022-02-21 04:22:03,354 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1343994881] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:03,354 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:03,354 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:03,354 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1397474964] [2022-02-21 04:22:03,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:03,354 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:03,354 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:03,355 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:03,355 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:03,355 INFO L87 Difference]: Start difference. First operand 1499 states and 2220 transitions. cyclomatic complexity: 723 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,834 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2022-02-21 04:22:04,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:04,836 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,902 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:04,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-02-21 04:22:05,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2703 states to 2703 states and 3991 transitions. [2022-02-21 04:22:05,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2703 [2022-02-21 04:22:05,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2703 [2022-02-21 04:22:05,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:05,255 INFO L681 BuchiCegarLoop]: Abstraction has 2703 states and 3991 transitions. [2022-02-21 04:22:05,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2703 to 2701. [2022-02-21 04:22:05,277 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:05,280 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2703 states and 3991 transitions. Second operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,294 INFO L74 IsIncluded]: Start isIncluded. First operand 2703 states and 3991 transitions. Second operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,297 INFO L87 Difference]: Start difference. First operand 2703 states and 3991 transitions. Second operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:05,450 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2022-02-21 04:22:05,450 INFO L276 IsEmpty]: Start isEmpty. Operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,453 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:05,453 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:05,455 INFO L74 IsIncluded]: Start isIncluded. First operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,457 INFO L87 Difference]: Start difference. First operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:05,619 INFO L93 Difference]: Finished difference Result 2703 states and 3991 transitions. [2022-02-21 04:22:05,619 INFO L276 IsEmpty]: Start isEmpty. Operand 2703 states and 3991 transitions. [2022-02-21 04:22:05,621 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:05,622 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:05,622 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:05,622 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:05,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2701 states, 2701 states have (on average 1.4768604220659016) internal successors, (3989), 2700 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2701 states to 2701 states and 3989 transitions. [2022-02-21 04:22:05,772 INFO L704 BuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-02-21 04:22:05,772 INFO L587 BuchiCegarLoop]: Abstraction has 2701 states and 3989 transitions. [2022-02-21 04:22:05,772 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:22:05,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2701 states and 3989 transitions. [2022-02-21 04:22:05,777 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2570 [2022-02-21 04:22:05,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:05,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:05,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,778 INFO L791 eck$LassoCheckResult]: Stem: 33517#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 33518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 33397#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33345#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33346#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 33641#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33328#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33164#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33165#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33146#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33147#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33640#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33458#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33459#L769 assume !(0 == ~M_E~0); 33481#L769-2 assume !(0 == ~T1_E~0); 33482#L774-1 assume !(0 == ~T2_E~0); 33509#L779-1 assume !(0 == ~T3_E~0); 33628#L784-1 assume !(0 == ~T4_E~0); 33454#L789-1 assume !(0 == ~T5_E~0); 33455#L794-1 assume !(0 == ~T6_E~0); 33568#L799-1 assume !(0 == ~T7_E~0); 33461#L804-1 assume !(0 == ~E_M~0); 33462#L809-1 assume !(0 == ~E_1~0); 33502#L814-1 assume !(0 == ~E_2~0); 32880#L819-1 assume !(0 == ~E_3~0); 32881#L824-1 assume !(0 == ~E_4~0); 33234#L829-1 assume !(0 == ~E_5~0); 33690#L834-1 assume !(0 == ~E_6~0); 33017#L839-1 assume !(0 == ~E_7~0); 33018#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33404#L376 assume !(1 == ~m_pc~0); 33390#L376-2 is_master_triggered_~__retres1~0#1 := 0; 33389#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33673#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32963#L955 assume !(0 != activate_threads_~tmp~1#1); 32964#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33320#L395 assume 1 == ~t1_pc~0; 32994#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32995#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32886#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32887#L963 assume !(0 != activate_threads_~tmp___0~0#1); 33408#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33409#L414 assume !(1 == ~t2_pc~0); 33020#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33021#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33220#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33221#L971 assume !(0 != activate_threads_~tmp___1~0#1); 33645#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33323#L433 assume 1 == ~t3_pc~0; 33267#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33137#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33295#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33296#L979 assume !(0 != activate_threads_~tmp___2~0#1); 32984#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32985#L452 assume !(1 == ~t4_pc~0); 33142#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33143#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33442#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33508#L987 assume !(0 != activate_threads_~tmp___3~0#1); 33175#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33176#L471 assume 1 == ~t5_pc~0; 33554#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33158#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33159#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33503#L995 assume !(0 != activate_threads_~tmp___4~0#1); 33682#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33683#L490 assume 1 == ~t6_pc~0; 33665#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33407#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33449#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33452#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 33333#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33301#L509 assume !(1 == ~t7_pc~0); 33302#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33118#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33119#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33180#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33181#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33653#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 33654#L857-2 assume !(1 == ~T1_E~0); 33242#L862-1 assume !(1 == ~T2_E~0); 33243#L867-1 assume !(1 == ~T3_E~0); 33324#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33325#L877-1 assume !(1 == ~T5_E~0); 33529#L882-1 assume !(1 == ~T6_E~0); 33664#L887-1 assume !(1 == ~T7_E~0); 33842#L892-1 assume !(1 == ~E_M~0); 33706#L897-1 assume !(1 == ~E_1~0); 33707#L902-1 assume !(1 == ~E_2~0); 33802#L907-1 assume !(1 == ~E_3~0); 33800#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33537#L917-1 assume !(1 == ~E_5~0); 33538#L922-1 assume !(1 == ~E_6~0); 33770#L927-1 assume !(1 == ~E_7~0); 33762#L932-1 assume { :end_inline_reset_delta_events } true; 33756#L1178-2 [2022-02-21 04:22:05,778 INFO L793 eck$LassoCheckResult]: Loop: 33756#L1178-2 assume !false; 33751#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33750#L744 assume !false; 33749#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33748#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33740#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33739#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33737#L641 assume !(0 != eval_~tmp~0#1); 33736#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33735#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33733#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33734#L769-5 assume !(0 == ~T1_E~0); 34934#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34929#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34922#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34917#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34911#L794-3 assume !(0 == ~T6_E~0); 34906#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34900#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34895#L809-3 assume !(0 == ~E_1~0); 34888#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34883#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34877#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34872#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34866#L834-3 assume !(0 == ~E_6~0); 34861#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34854#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34849#L376-27 assume !(1 == ~m_pc~0); 34842#L376-29 is_master_triggered_~__retres1~0#1 := 0; 34837#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34832#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34829#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34579#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34570#L395-27 assume 1 == ~t1_pc~0; 34567#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34565#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34563#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34561#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34560#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34549#L414-27 assume !(1 == ~t2_pc~0); 34539#L414-29 is_transmit2_triggered_~__retres1~2#1 := 0; 34532#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34526#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34524#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34522#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34513#L433-27 assume 1 == ~t3_pc~0; 34510#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34508#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34505#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34503#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 34501#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34499#L452-27 assume 1 == ~t4_pc~0; 34496#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34494#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34492#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34490#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34488#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34486#L471-27 assume 1 == ~t5_pc~0; 34483#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34277#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34231#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34228#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34226#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34204#L490-27 assume 1 == ~t6_pc~0; 34179#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34176#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34174#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34172#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34170#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34168#L509-27 assume !(1 == ~t7_pc~0); 34165#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 34149#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34147#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34145#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34142#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34125#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33437#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34122#L862-3 assume !(1 == ~T2_E~0); 34120#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34118#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34116#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34088#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34085#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34083#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34062#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34060#L902-3 assume !(1 == ~E_2~0); 34035#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34033#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34004#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34002#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33956#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33954#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33905#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33873#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33871#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 33868#L1197 assume !(0 == start_simulation_~tmp~3#1); 33722#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33836#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33830#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33828#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 33804#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33783#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33771#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 33763#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 33756#L1178-2 [2022-02-21 04:22:05,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,779 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-02-21 04:22:05,779 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,779 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674612244] [2022-02-21 04:22:05,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,801 INFO L290 TraceCheckUtils]: 0: Hoare triple {40977#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,802 INFO L290 TraceCheckUtils]: 1: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,802 INFO L290 TraceCheckUtils]: 2: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,802 INFO L290 TraceCheckUtils]: 3: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,803 INFO L290 TraceCheckUtils]: 4: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,803 INFO L290 TraceCheckUtils]: 5: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,803 INFO L290 TraceCheckUtils]: 6: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,804 INFO L290 TraceCheckUtils]: 7: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,804 INFO L290 TraceCheckUtils]: 8: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,804 INFO L290 TraceCheckUtils]: 9: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,805 INFO L290 TraceCheckUtils]: 10: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,805 INFO L290 TraceCheckUtils]: 11: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,805 INFO L290 TraceCheckUtils]: 12: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,805 INFO L290 TraceCheckUtils]: 13: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,806 INFO L290 TraceCheckUtils]: 14: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,806 INFO L290 TraceCheckUtils]: 15: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,806 INFO L290 TraceCheckUtils]: 16: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,807 INFO L290 TraceCheckUtils]: 17: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,807 INFO L290 TraceCheckUtils]: 18: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,807 INFO L290 TraceCheckUtils]: 19: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,808 INFO L290 TraceCheckUtils]: 20: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,808 INFO L290 TraceCheckUtils]: 21: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,808 INFO L290 TraceCheckUtils]: 22: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,809 INFO L290 TraceCheckUtils]: 23: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,809 INFO L290 TraceCheckUtils]: 24: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,809 INFO L290 TraceCheckUtils]: 25: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,810 INFO L290 TraceCheckUtils]: 26: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,810 INFO L290 TraceCheckUtils]: 27: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,811 INFO L290 TraceCheckUtils]: 28: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,811 INFO L290 TraceCheckUtils]: 29: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40979#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:05,811 INFO L290 TraceCheckUtils]: 30: Hoare triple {40979#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,812 INFO L290 TraceCheckUtils]: 31: Hoare triple {40980#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,812 INFO L290 TraceCheckUtils]: 32: Hoare triple {40980#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,812 INFO L290 TraceCheckUtils]: 33: Hoare triple {40980#(not (= ~t1_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,812 INFO L290 TraceCheckUtils]: 34: Hoare triple {40980#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 35: Hoare triple {40980#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40980#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 36: Hoare triple {40980#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {40978#false} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 37: Hoare triple {40978#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40978#false} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 38: Hoare triple {40978#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40978#false} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 39: Hoare triple {40978#false} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {40978#false} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 40: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___0~0#1); {40978#false} is VALID [2022-02-21 04:22:05,813 INFO L290 TraceCheckUtils]: 41: Hoare triple {40978#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 42: Hoare triple {40978#false} assume !(1 == ~t2_pc~0); {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 43: Hoare triple {40978#false} is_transmit2_triggered_~__retres1~2#1 := 0; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 44: Hoare triple {40978#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 45: Hoare triple {40978#false} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 46: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___1~0#1); {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 47: Hoare triple {40978#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 48: Hoare triple {40978#false} assume 1 == ~t3_pc~0; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 49: Hoare triple {40978#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40978#false} is VALID [2022-02-21 04:22:05,814 INFO L290 TraceCheckUtils]: 50: Hoare triple {40978#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 51: Hoare triple {40978#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 52: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___2~0#1); {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 53: Hoare triple {40978#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 54: Hoare triple {40978#false} assume !(1 == ~t4_pc~0); {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 55: Hoare triple {40978#false} is_transmit4_triggered_~__retres1~4#1 := 0; {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 56: Hoare triple {40978#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40978#false} is VALID [2022-02-21 04:22:05,815 INFO L290 TraceCheckUtils]: 57: Hoare triple {40978#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 58: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___3~0#1); {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 59: Hoare triple {40978#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 60: Hoare triple {40978#false} assume 1 == ~t5_pc~0; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 61: Hoare triple {40978#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 62: Hoare triple {40978#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 63: Hoare triple {40978#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 64: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___4~0#1); {40978#false} is VALID [2022-02-21 04:22:05,816 INFO L290 TraceCheckUtils]: 65: Hoare triple {40978#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 66: Hoare triple {40978#false} assume 1 == ~t6_pc~0; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 67: Hoare triple {40978#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 68: Hoare triple {40978#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 69: Hoare triple {40978#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 70: Hoare triple {40978#false} assume !(0 != activate_threads_~tmp___5~0#1); {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 71: Hoare triple {40978#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 72: Hoare triple {40978#false} assume !(1 == ~t7_pc~0); {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 73: Hoare triple {40978#false} is_transmit7_triggered_~__retres1~7#1 := 0; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 74: Hoare triple {40978#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40978#false} is VALID [2022-02-21 04:22:05,817 INFO L290 TraceCheckUtils]: 75: Hoare triple {40978#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 76: Hoare triple {40978#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 77: Hoare triple {40978#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 78: Hoare triple {40978#false} assume 1 == ~M_E~0;~M_E~0 := 2; {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 79: Hoare triple {40978#false} assume !(1 == ~T1_E~0); {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 80: Hoare triple {40978#false} assume !(1 == ~T2_E~0); {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 81: Hoare triple {40978#false} assume !(1 == ~T3_E~0); {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 82: Hoare triple {40978#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40978#false} is VALID [2022-02-21 04:22:05,818 INFO L290 TraceCheckUtils]: 83: Hoare triple {40978#false} assume !(1 == ~T5_E~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 84: Hoare triple {40978#false} assume !(1 == ~T6_E~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 85: Hoare triple {40978#false} assume !(1 == ~T7_E~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 86: Hoare triple {40978#false} assume !(1 == ~E_M~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 87: Hoare triple {40978#false} assume !(1 == ~E_1~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 88: Hoare triple {40978#false} assume !(1 == ~E_2~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 89: Hoare triple {40978#false} assume !(1 == ~E_3~0); {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 90: Hoare triple {40978#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40978#false} is VALID [2022-02-21 04:22:05,819 INFO L290 TraceCheckUtils]: 91: Hoare triple {40978#false} assume !(1 == ~E_5~0); {40978#false} is VALID [2022-02-21 04:22:05,820 INFO L290 TraceCheckUtils]: 92: Hoare triple {40978#false} assume !(1 == ~E_6~0); {40978#false} is VALID [2022-02-21 04:22:05,820 INFO L290 TraceCheckUtils]: 93: Hoare triple {40978#false} assume !(1 == ~E_7~0); {40978#false} is VALID [2022-02-21 04:22:05,820 INFO L290 TraceCheckUtils]: 94: Hoare triple {40978#false} assume { :end_inline_reset_delta_events } true; {40978#false} is VALID [2022-02-21 04:22:05,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,821 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,821 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [674612244] [2022-02-21 04:22:05,821 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [674612244] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,821 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,821 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:05,821 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131001164] [2022-02-21 04:22:05,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,822 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:05,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,822 INFO L85 PathProgramCache]: Analyzing trace with hash -555497179, now seen corresponding path program 1 times [2022-02-21 04:22:05,822 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,823 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471321995] [2022-02-21 04:22:05,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,849 INFO L290 TraceCheckUtils]: 0: Hoare triple {40981#true} assume !false; {40981#true} is VALID [2022-02-21 04:22:05,849 INFO L290 TraceCheckUtils]: 1: Hoare triple {40981#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {40981#true} is VALID [2022-02-21 04:22:05,849 INFO L290 TraceCheckUtils]: 2: Hoare triple {40981#true} assume !false; {40981#true} is VALID [2022-02-21 04:22:05,849 INFO L290 TraceCheckUtils]: 3: Hoare triple {40981#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 4: Hoare triple {40981#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 5: Hoare triple {40981#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 6: Hoare triple {40981#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 7: Hoare triple {40981#true} assume !(0 != eval_~tmp~0#1); {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 8: Hoare triple {40981#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 9: Hoare triple {40981#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 10: Hoare triple {40981#true} assume 0 == ~M_E~0;~M_E~0 := 1; {40981#true} is VALID [2022-02-21 04:22:05,850 INFO L290 TraceCheckUtils]: 11: Hoare triple {40981#true} assume !(0 == ~T1_E~0); {40981#true} is VALID [2022-02-21 04:22:05,851 INFO L290 TraceCheckUtils]: 12: Hoare triple {40981#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,851 INFO L290 TraceCheckUtils]: 13: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,851 INFO L290 TraceCheckUtils]: 14: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,851 INFO L290 TraceCheckUtils]: 15: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,852 INFO L290 TraceCheckUtils]: 16: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,852 INFO L290 TraceCheckUtils]: 17: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,852 INFO L290 TraceCheckUtils]: 18: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,852 INFO L290 TraceCheckUtils]: 19: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,853 INFO L290 TraceCheckUtils]: 20: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,853 INFO L290 TraceCheckUtils]: 21: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,853 INFO L290 TraceCheckUtils]: 22: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,853 INFO L290 TraceCheckUtils]: 23: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,854 INFO L290 TraceCheckUtils]: 24: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,854 INFO L290 TraceCheckUtils]: 25: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,854 INFO L290 TraceCheckUtils]: 26: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,854 INFO L290 TraceCheckUtils]: 27: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,855 INFO L290 TraceCheckUtils]: 28: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,855 INFO L290 TraceCheckUtils]: 29: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,855 INFO L290 TraceCheckUtils]: 30: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,855 INFO L290 TraceCheckUtils]: 31: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,856 INFO L290 TraceCheckUtils]: 32: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,856 INFO L290 TraceCheckUtils]: 33: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t1_pc~0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,856 INFO L290 TraceCheckUtils]: 34: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,856 INFO L290 TraceCheckUtils]: 35: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,857 INFO L290 TraceCheckUtils]: 36: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,857 INFO L290 TraceCheckUtils]: 37: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,857 INFO L290 TraceCheckUtils]: 38: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,857 INFO L290 TraceCheckUtils]: 39: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t2_pc~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,858 INFO L290 TraceCheckUtils]: 40: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,858 INFO L290 TraceCheckUtils]: 41: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,858 INFO L290 TraceCheckUtils]: 42: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,858 INFO L290 TraceCheckUtils]: 43: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,859 INFO L290 TraceCheckUtils]: 44: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,859 INFO L290 TraceCheckUtils]: 45: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,859 INFO L290 TraceCheckUtils]: 46: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,860 INFO L290 TraceCheckUtils]: 47: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,860 INFO L290 TraceCheckUtils]: 48: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,860 INFO L290 TraceCheckUtils]: 49: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,860 INFO L290 TraceCheckUtils]: 50: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,861 INFO L290 TraceCheckUtils]: 51: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,861 INFO L290 TraceCheckUtils]: 52: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,861 INFO L290 TraceCheckUtils]: 53: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,861 INFO L290 TraceCheckUtils]: 54: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,861 INFO L290 TraceCheckUtils]: 55: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,862 INFO L290 TraceCheckUtils]: 56: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,862 INFO L290 TraceCheckUtils]: 57: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,862 INFO L290 TraceCheckUtils]: 58: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,862 INFO L290 TraceCheckUtils]: 59: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,863 INFO L290 TraceCheckUtils]: 60: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,863 INFO L290 TraceCheckUtils]: 61: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,863 INFO L290 TraceCheckUtils]: 62: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,863 INFO L290 TraceCheckUtils]: 63: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,864 INFO L290 TraceCheckUtils]: 64: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,864 INFO L290 TraceCheckUtils]: 65: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,864 INFO L290 TraceCheckUtils]: 66: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,865 INFO L290 TraceCheckUtils]: 67: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,865 INFO L290 TraceCheckUtils]: 68: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,865 INFO L290 TraceCheckUtils]: 69: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,865 INFO L290 TraceCheckUtils]: 70: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,866 INFO L290 TraceCheckUtils]: 71: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,866 INFO L290 TraceCheckUtils]: 72: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,866 INFO L290 TraceCheckUtils]: 73: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,866 INFO L290 TraceCheckUtils]: 74: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,867 INFO L290 TraceCheckUtils]: 75: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,867 INFO L290 TraceCheckUtils]: 76: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {40983#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:05,867 INFO L290 TraceCheckUtils]: 77: Hoare triple {40983#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {40982#false} is VALID [2022-02-21 04:22:05,867 INFO L290 TraceCheckUtils]: 78: Hoare triple {40982#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,867 INFO L290 TraceCheckUtils]: 79: Hoare triple {40982#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 80: Hoare triple {40982#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 81: Hoare triple {40982#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 82: Hoare triple {40982#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 83: Hoare triple {40982#false} assume 1 == ~E_M~0;~E_M~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 84: Hoare triple {40982#false} assume 1 == ~E_1~0;~E_1~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 85: Hoare triple {40982#false} assume !(1 == ~E_2~0); {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 86: Hoare triple {40982#false} assume 1 == ~E_3~0;~E_3~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 87: Hoare triple {40982#false} assume 1 == ~E_4~0;~E_4~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 88: Hoare triple {40982#false} assume 1 == ~E_5~0;~E_5~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,868 INFO L290 TraceCheckUtils]: 89: Hoare triple {40982#false} assume 1 == ~E_6~0;~E_6~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,869 INFO L290 TraceCheckUtils]: 90: Hoare triple {40982#false} assume 1 == ~E_7~0;~E_7~0 := 2; {40982#false} is VALID [2022-02-21 04:22:05,869 INFO L290 TraceCheckUtils]: 91: Hoare triple {40982#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {40982#false} is VALID [2022-02-21 04:22:05,869 INFO L290 TraceCheckUtils]: 92: Hoare triple {40982#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {40982#false} is VALID [2022-02-21 04:22:05,869 INFO L290 TraceCheckUtils]: 93: Hoare triple {40982#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {40982#false} is VALID [2022-02-21 04:22:05,870 INFO L290 TraceCheckUtils]: 94: Hoare triple {40982#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {40982#false} is VALID [2022-02-21 04:22:05,870 INFO L290 TraceCheckUtils]: 95: Hoare triple {40982#false} assume !(0 == start_simulation_~tmp~3#1); {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 96: Hoare triple {40982#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 97: Hoare triple {40982#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 98: Hoare triple {40982#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 99: Hoare triple {40982#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 100: Hoare triple {40982#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 101: Hoare triple {40982#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 102: Hoare triple {40982#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {40982#false} is VALID [2022-02-21 04:22:05,871 INFO L290 TraceCheckUtils]: 103: Hoare triple {40982#false} assume !(0 != start_simulation_~tmp___0~1#1); {40982#false} is VALID [2022-02-21 04:22:05,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,872 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,872 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471321995] [2022-02-21 04:22:05,872 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471321995] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,872 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,872 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:05,872 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017433753] [2022-02-21 04:22:05,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,873 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:05,873 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:05,873 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:05,873 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:05,873 INFO L87 Difference]: Start difference. First operand 2701 states and 3989 transitions. cyclomatic complexity: 1292 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:08,750 INFO L93 Difference]: Finished difference Result 7458 states and 10846 transitions. [2022-02-21 04:22:08,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:08,750 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:08,811 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:08,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7458 states and 10846 transitions. [2022-02-21 04:22:09,939 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7077 [2022-02-21 04:22:11,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7458 states to 7458 states and 10846 transitions. [2022-02-21 04:22:11,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7458 [2022-02-21 04:22:11,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7458 [2022-02-21 04:22:11,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7458 states and 10846 transitions. [2022-02-21 04:22:11,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:11,081 INFO L681 BuchiCegarLoop]: Abstraction has 7458 states and 10846 transitions. [2022-02-21 04:22:11,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7458 states and 10846 transitions. [2022-02-21 04:22:11,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7458 to 7026. [2022-02-21 04:22:11,150 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:11,157 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7458 states and 10846 transitions. Second operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,163 INFO L74 IsIncluded]: Start isIncluded. First operand 7458 states and 10846 transitions. Second operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:11,169 INFO L87 Difference]: Start difference. First operand 7458 states and 10846 transitions. Second operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:12,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:12,380 INFO L93 Difference]: Finished difference Result 7458 states and 10846 transitions. [2022-02-21 04:22:12,380 INFO L276 IsEmpty]: Start isEmpty. Operand 7458 states and 10846 transitions. [2022-02-21 04:22:12,384 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:12,384 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:12,390 INFO L74 IsIncluded]: Start isIncluded. First operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7458 states and 10846 transitions. [2022-02-21 04:22:12,394 INFO L87 Difference]: Start difference. First operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7458 states and 10846 transitions. [2022-02-21 04:22:13,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,589 INFO L93 Difference]: Finished difference Result 7458 states and 10846 transitions. [2022-02-21 04:22:13,589 INFO L276 IsEmpty]: Start isEmpty. Operand 7458 states and 10846 transitions. [2022-02-21 04:22:13,596 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:13,596 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:13,596 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:13,596 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:13,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7026 states, 7026 states have (on average 1.4594363791631084) internal successors, (10254), 7025 states have internal predecessors, (10254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:14,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7026 states to 7026 states and 10254 transitions. [2022-02-21 04:22:14,660 INFO L704 BuchiCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-02-21 04:22:14,661 INFO L587 BuchiCegarLoop]: Abstraction has 7026 states and 10254 transitions. [2022-02-21 04:22:14,661 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:14,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7026 states and 10254 transitions. [2022-02-21 04:22:14,672 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6877 [2022-02-21 04:22:14,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:14,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:14,673 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,673 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:14,674 INFO L791 eck$LassoCheckResult]: Stem: 49127#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 49128#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 48988#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48933#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48934#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 49304#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48914#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48744#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48745#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48724#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48725#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49303#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49061#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49062#L769 assume !(0 == ~M_E~0); 49085#L769-2 assume !(0 == ~T1_E~0); 49086#L774-1 assume !(0 == ~T2_E~0); 49117#L779-1 assume !(0 == ~T3_E~0); 49274#L784-1 assume !(0 == ~T4_E~0); 49056#L789-1 assume !(0 == ~T5_E~0); 49057#L794-1 assume !(0 == ~T6_E~0); 49191#L799-1 assume !(0 == ~T7_E~0); 49064#L804-1 assume !(0 == ~E_M~0); 49065#L809-1 assume !(0 == ~E_1~0); 49108#L814-1 assume !(0 == ~E_2~0); 48457#L819-1 assume !(0 == ~E_3~0); 48458#L824-1 assume !(0 == ~E_4~0); 48818#L829-1 assume !(0 == ~E_5~0); 49401#L834-1 assume !(0 == ~E_6~0); 48591#L839-1 assume !(0 == ~E_7~0); 48592#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48998#L376 assume !(1 == ~m_pc~0); 48995#L376-2 is_master_triggered_~__retres1~0#1 := 0; 48996#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49366#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48538#L955 assume !(0 != activate_threads_~tmp~1#1); 48539#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48906#L395 assume !(1 == ~t1_pc~0); 49088#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 49258#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48463#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48464#L963 assume !(0 != activate_threads_~tmp___0~0#1); 49002#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49003#L414 assume !(1 == ~t2_pc~0); 48594#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48595#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48805#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48806#L971 assume !(0 != activate_threads_~tmp___1~0#1); 49311#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48910#L433 assume 1 == ~t3_pc~0; 48851#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48712#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48882#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48883#L979 assume !(0 != activate_threads_~tmp___2~0#1); 48561#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48562#L452 assume !(1 == ~t4_pc~0); 48720#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48721#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49041#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49116#L987 assume !(0 != activate_threads_~tmp___3~0#1); 48756#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48757#L471 assume 1 == ~t5_pc~0; 49171#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48738#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48739#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49109#L995 assume !(0 != activate_threads_~tmp___4~0#1); 49387#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49388#L490 assume 1 == ~t6_pc~0; 49348#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49001#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49049#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49052#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 48919#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48887#L509 assume !(1 == ~t7_pc~0); 48888#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48690#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48691#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48761#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48762#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49321#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 48545#L857-2 assume !(1 == ~T1_E~0); 48546#L862-1 assume !(1 == ~T2_E~0); 50690#L867-1 assume !(1 == ~T3_E~0); 50688#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49139#L877-1 assume !(1 == ~T5_E~0); 49140#L882-1 assume !(1 == ~T6_E~0); 49347#L887-1 assume !(1 == ~T7_E~0); 50616#L892-1 assume !(1 == ~E_M~0); 50614#L897-1 assume !(1 == ~E_1~0); 50613#L902-1 assume !(1 == ~E_2~0); 50612#L907-1 assume !(1 == ~E_3~0); 50611#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 50589#L917-1 assume !(1 == ~E_5~0); 50587#L922-1 assume !(1 == ~E_6~0); 50576#L927-1 assume !(1 == ~E_7~0); 50568#L932-1 assume { :end_inline_reset_delta_events } true; 50562#L1178-2 [2022-02-21 04:22:14,674 INFO L793 eck$LassoCheckResult]: Loop: 50562#L1178-2 assume !false; 50557#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50556#L744 assume !false; 50555#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 50554#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 50546#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 50545#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50543#L641 assume !(0 != eval_~tmp~0#1); 50542#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 50541#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 50538#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 50537#L769-5 assume !(0 == ~T1_E~0); 50536#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50535#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50534#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50533#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50532#L794-3 assume !(0 == ~T6_E~0); 50531#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 50530#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50529#L809-3 assume !(0 == ~E_1~0); 50527#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50525#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50523#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 50521#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50517#L834-3 assume !(0 == ~E_6~0); 50514#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50512#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50510#L376-27 assume !(1 == ~m_pc~0); 50508#L376-29 is_master_triggered_~__retres1~0#1 := 0; 50506#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50504#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50503#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50500#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50498#L395-27 assume !(1 == ~t1_pc~0); 50496#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 50494#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50492#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50488#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50485#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50481#L414-27 assume 1 == ~t2_pc~0; 50482#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51345#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51344#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51343#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51342#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51341#L433-27 assume 1 == ~t3_pc~0; 51099#L434-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51094#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51092#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50439#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 50431#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50428#L452-27 assume 1 == ~t4_pc~0; 50423#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50424#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51081#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51077#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51073#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51068#L471-27 assume 1 == ~t5_pc~0; 51062#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51058#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51054#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51050#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51045#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51040#L490-27 assume 1 == ~t6_pc~0; 51033#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51028#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51022#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 51016#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51009#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51002#L509-27 assume !(1 == ~t7_pc~0); 50996#L509-29 is_transmit7_triggered_~__retres1~7#1 := 0; 50990#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50984#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50978#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50971#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50963#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49662#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50952#L862-3 assume !(1 == ~T2_E~0); 50948#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50911#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50909#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 50907#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49644#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50893#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50887#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50877#L902-3 assume !(1 == ~E_2~0); 50869#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50864#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49599#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49600#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 50811#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 50781#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 50737#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 50727#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 50714#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 50706#L1197 assume !(0 == start_simulation_~tmp~3#1); 49474#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 50622#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 50617#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 50615#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 50590#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50588#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50577#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 50569#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 50562#L1178-2 [2022-02-21 04:22:14,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,674 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-02-21 04:22:14,675 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,675 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552310090] [2022-02-21 04:22:14,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,709 INFO L290 TraceCheckUtils]: 0: Hoare triple {70389#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,710 INFO L290 TraceCheckUtils]: 1: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,710 INFO L290 TraceCheckUtils]: 2: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,711 INFO L290 TraceCheckUtils]: 3: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,711 INFO L290 TraceCheckUtils]: 4: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,711 INFO L290 TraceCheckUtils]: 5: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,711 INFO L290 TraceCheckUtils]: 6: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,712 INFO L290 TraceCheckUtils]: 7: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,712 INFO L290 TraceCheckUtils]: 8: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,712 INFO L290 TraceCheckUtils]: 9: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,713 INFO L290 TraceCheckUtils]: 10: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,713 INFO L290 TraceCheckUtils]: 11: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,713 INFO L290 TraceCheckUtils]: 12: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,713 INFO L290 TraceCheckUtils]: 13: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,714 INFO L290 TraceCheckUtils]: 14: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,714 INFO L290 TraceCheckUtils]: 15: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,714 INFO L290 TraceCheckUtils]: 16: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,715 INFO L290 TraceCheckUtils]: 17: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,715 INFO L290 TraceCheckUtils]: 18: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,715 INFO L290 TraceCheckUtils]: 19: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,715 INFO L290 TraceCheckUtils]: 20: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,716 INFO L290 TraceCheckUtils]: 21: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,716 INFO L290 TraceCheckUtils]: 22: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,716 INFO L290 TraceCheckUtils]: 23: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,716 INFO L290 TraceCheckUtils]: 24: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,717 INFO L290 TraceCheckUtils]: 25: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,717 INFO L290 TraceCheckUtils]: 26: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,717 INFO L290 TraceCheckUtils]: 27: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,718 INFO L290 TraceCheckUtils]: 28: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,718 INFO L290 TraceCheckUtils]: 29: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70391#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:14,718 INFO L290 TraceCheckUtils]: 30: Hoare triple {70391#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,718 INFO L290 TraceCheckUtils]: 31: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,719 INFO L290 TraceCheckUtils]: 32: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,719 INFO L290 TraceCheckUtils]: 33: Hoare triple {70392#(not (= ~t3_pc~0 1))} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,719 INFO L290 TraceCheckUtils]: 34: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,719 INFO L290 TraceCheckUtils]: 35: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,720 INFO L290 TraceCheckUtils]: 36: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,720 INFO L290 TraceCheckUtils]: 37: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,720 INFO L290 TraceCheckUtils]: 38: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,720 INFO L290 TraceCheckUtils]: 39: Hoare triple {70392#(not (= ~t3_pc~0 1))} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,721 INFO L290 TraceCheckUtils]: 40: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,721 INFO L290 TraceCheckUtils]: 41: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,721 INFO L290 TraceCheckUtils]: 42: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,721 INFO L290 TraceCheckUtils]: 43: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,722 INFO L290 TraceCheckUtils]: 44: Hoare triple {70392#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,722 INFO L290 TraceCheckUtils]: 45: Hoare triple {70392#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,722 INFO L290 TraceCheckUtils]: 46: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,722 INFO L290 TraceCheckUtils]: 47: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70392#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 48: Hoare triple {70392#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 49: Hoare triple {70390#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 50: Hoare triple {70390#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 51: Hoare triple {70390#false} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 52: Hoare triple {70390#false} assume !(0 != activate_threads_~tmp___2~0#1); {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 53: Hoare triple {70390#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 54: Hoare triple {70390#false} assume !(1 == ~t4_pc~0); {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 55: Hoare triple {70390#false} is_transmit4_triggered_~__retres1~4#1 := 0; {70390#false} is VALID [2022-02-21 04:22:14,723 INFO L290 TraceCheckUtils]: 56: Hoare triple {70390#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 57: Hoare triple {70390#false} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 58: Hoare triple {70390#false} assume !(0 != activate_threads_~tmp___3~0#1); {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 59: Hoare triple {70390#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 60: Hoare triple {70390#false} assume 1 == ~t5_pc~0; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 61: Hoare triple {70390#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 62: Hoare triple {70390#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 63: Hoare triple {70390#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 64: Hoare triple {70390#false} assume !(0 != activate_threads_~tmp___4~0#1); {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 65: Hoare triple {70390#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70390#false} is VALID [2022-02-21 04:22:14,724 INFO L290 TraceCheckUtils]: 66: Hoare triple {70390#false} assume 1 == ~t6_pc~0; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 67: Hoare triple {70390#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 68: Hoare triple {70390#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 69: Hoare triple {70390#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 70: Hoare triple {70390#false} assume !(0 != activate_threads_~tmp___5~0#1); {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 71: Hoare triple {70390#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 72: Hoare triple {70390#false} assume !(1 == ~t7_pc~0); {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 73: Hoare triple {70390#false} is_transmit7_triggered_~__retres1~7#1 := 0; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 74: Hoare triple {70390#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 75: Hoare triple {70390#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70390#false} is VALID [2022-02-21 04:22:14,725 INFO L290 TraceCheckUtils]: 76: Hoare triple {70390#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 77: Hoare triple {70390#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 78: Hoare triple {70390#false} assume 1 == ~M_E~0;~M_E~0 := 2; {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 79: Hoare triple {70390#false} assume !(1 == ~T1_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 80: Hoare triple {70390#false} assume !(1 == ~T2_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 81: Hoare triple {70390#false} assume !(1 == ~T3_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 82: Hoare triple {70390#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 83: Hoare triple {70390#false} assume !(1 == ~T5_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 84: Hoare triple {70390#false} assume !(1 == ~T6_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 85: Hoare triple {70390#false} assume !(1 == ~T7_E~0); {70390#false} is VALID [2022-02-21 04:22:14,726 INFO L290 TraceCheckUtils]: 86: Hoare triple {70390#false} assume !(1 == ~E_M~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 87: Hoare triple {70390#false} assume !(1 == ~E_1~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 88: Hoare triple {70390#false} assume !(1 == ~E_2~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 89: Hoare triple {70390#false} assume !(1 == ~E_3~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 90: Hoare triple {70390#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 91: Hoare triple {70390#false} assume !(1 == ~E_5~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 92: Hoare triple {70390#false} assume !(1 == ~E_6~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 93: Hoare triple {70390#false} assume !(1 == ~E_7~0); {70390#false} is VALID [2022-02-21 04:22:14,727 INFO L290 TraceCheckUtils]: 94: Hoare triple {70390#false} assume { :end_inline_reset_delta_events } true; {70390#false} is VALID [2022-02-21 04:22:14,728 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,728 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,728 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552310090] [2022-02-21 04:22:14,728 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552310090] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,728 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,728 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,728 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480138660] [2022-02-21 04:22:14,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,729 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:14,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:14,729 INFO L85 PathProgramCache]: Analyzing trace with hash 1406506085, now seen corresponding path program 1 times [2022-02-21 04:22:14,729 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:14,729 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097744343] [2022-02-21 04:22:14,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:14,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:14,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:14,775 INFO L290 TraceCheckUtils]: 0: Hoare triple {70393#true} assume !false; {70393#true} is VALID [2022-02-21 04:22:14,775 INFO L290 TraceCheckUtils]: 1: Hoare triple {70393#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {70393#true} is VALID [2022-02-21 04:22:14,775 INFO L290 TraceCheckUtils]: 2: Hoare triple {70393#true} assume !false; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 3: Hoare triple {70393#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 4: Hoare triple {70393#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 5: Hoare triple {70393#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 6: Hoare triple {70393#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 7: Hoare triple {70393#true} assume !(0 != eval_~tmp~0#1); {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 8: Hoare triple {70393#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 9: Hoare triple {70393#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {70393#true} is VALID [2022-02-21 04:22:14,776 INFO L290 TraceCheckUtils]: 10: Hoare triple {70393#true} assume 0 == ~M_E~0;~M_E~0 := 1; {70393#true} is VALID [2022-02-21 04:22:14,777 INFO L290 TraceCheckUtils]: 11: Hoare triple {70393#true} assume !(0 == ~T1_E~0); {70393#true} is VALID [2022-02-21 04:22:14,777 INFO L290 TraceCheckUtils]: 12: Hoare triple {70393#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,777 INFO L290 TraceCheckUtils]: 13: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,777 INFO L290 TraceCheckUtils]: 14: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,778 INFO L290 TraceCheckUtils]: 15: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,778 INFO L290 TraceCheckUtils]: 16: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,778 INFO L290 TraceCheckUtils]: 17: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,779 INFO L290 TraceCheckUtils]: 18: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,779 INFO L290 TraceCheckUtils]: 19: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,779 INFO L290 TraceCheckUtils]: 20: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,779 INFO L290 TraceCheckUtils]: 21: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,780 INFO L290 TraceCheckUtils]: 22: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,780 INFO L290 TraceCheckUtils]: 23: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,780 INFO L290 TraceCheckUtils]: 24: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,781 INFO L290 TraceCheckUtils]: 25: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,781 INFO L290 TraceCheckUtils]: 26: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,781 INFO L290 TraceCheckUtils]: 27: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,781 INFO L290 TraceCheckUtils]: 28: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,782 INFO L290 TraceCheckUtils]: 29: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,782 INFO L290 TraceCheckUtils]: 30: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,782 INFO L290 TraceCheckUtils]: 31: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,783 INFO L290 TraceCheckUtils]: 32: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,783 INFO L290 TraceCheckUtils]: 33: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,783 INFO L290 TraceCheckUtils]: 34: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,783 INFO L290 TraceCheckUtils]: 35: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,784 INFO L290 TraceCheckUtils]: 36: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,784 INFO L290 TraceCheckUtils]: 37: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,784 INFO L290 TraceCheckUtils]: 38: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,785 INFO L290 TraceCheckUtils]: 39: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,785 INFO L290 TraceCheckUtils]: 40: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,785 INFO L290 TraceCheckUtils]: 41: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,786 INFO L290 TraceCheckUtils]: 42: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,786 INFO L290 TraceCheckUtils]: 43: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,786 INFO L290 TraceCheckUtils]: 44: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,786 INFO L290 TraceCheckUtils]: 45: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t3_pc~0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,787 INFO L290 TraceCheckUtils]: 46: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,787 INFO L290 TraceCheckUtils]: 47: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,787 INFO L290 TraceCheckUtils]: 48: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,788 INFO L290 TraceCheckUtils]: 49: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,788 INFO L290 TraceCheckUtils]: 50: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,788 INFO L290 TraceCheckUtils]: 51: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t4_pc~0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,788 INFO L290 TraceCheckUtils]: 52: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,789 INFO L290 TraceCheckUtils]: 53: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,789 INFO L290 TraceCheckUtils]: 54: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,789 INFO L290 TraceCheckUtils]: 55: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,790 INFO L290 TraceCheckUtils]: 56: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,790 INFO L290 TraceCheckUtils]: 57: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,790 INFO L290 TraceCheckUtils]: 58: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,790 INFO L290 TraceCheckUtils]: 59: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,791 INFO L290 TraceCheckUtils]: 60: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,791 INFO L290 TraceCheckUtils]: 61: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,791 INFO L290 TraceCheckUtils]: 62: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,792 INFO L290 TraceCheckUtils]: 63: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t6_pc~0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,792 INFO L290 TraceCheckUtils]: 64: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,792 INFO L290 TraceCheckUtils]: 65: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,792 INFO L290 TraceCheckUtils]: 66: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,793 INFO L290 TraceCheckUtils]: 67: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,793 INFO L290 TraceCheckUtils]: 68: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,793 INFO L290 TraceCheckUtils]: 69: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t7_pc~0); {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,794 INFO L290 TraceCheckUtils]: 70: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,794 INFO L290 TraceCheckUtils]: 71: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,794 INFO L290 TraceCheckUtils]: 72: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,794 INFO L290 TraceCheckUtils]: 73: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,795 INFO L290 TraceCheckUtils]: 74: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,795 INFO L290 TraceCheckUtils]: 75: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,795 INFO L290 TraceCheckUtils]: 76: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {70395#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:22:14,795 INFO L290 TraceCheckUtils]: 77: Hoare triple {70395#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 78: Hoare triple {70394#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 79: Hoare triple {70394#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 80: Hoare triple {70394#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 81: Hoare triple {70394#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 82: Hoare triple {70394#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 83: Hoare triple {70394#false} assume 1 == ~E_M~0;~E_M~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,796 INFO L290 TraceCheckUtils]: 84: Hoare triple {70394#false} assume 1 == ~E_1~0;~E_1~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,797 INFO L290 TraceCheckUtils]: 85: Hoare triple {70394#false} assume !(1 == ~E_2~0); {70394#false} is VALID [2022-02-21 04:22:14,797 INFO L290 TraceCheckUtils]: 86: Hoare triple {70394#false} assume 1 == ~E_3~0;~E_3~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,798 INFO L290 TraceCheckUtils]: 87: Hoare triple {70394#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 88: Hoare triple {70394#false} assume 1 == ~E_5~0;~E_5~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 89: Hoare triple {70394#false} assume 1 == ~E_6~0;~E_6~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 90: Hoare triple {70394#false} assume 1 == ~E_7~0;~E_7~0 := 2; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 91: Hoare triple {70394#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 92: Hoare triple {70394#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 93: Hoare triple {70394#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 94: Hoare triple {70394#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {70394#false} is VALID [2022-02-21 04:22:14,799 INFO L290 TraceCheckUtils]: 95: Hoare triple {70394#false} assume !(0 == start_simulation_~tmp~3#1); {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 96: Hoare triple {70394#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 97: Hoare triple {70394#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 98: Hoare triple {70394#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 99: Hoare triple {70394#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 100: Hoare triple {70394#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 101: Hoare triple {70394#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 102: Hoare triple {70394#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {70394#false} is VALID [2022-02-21 04:22:14,800 INFO L290 TraceCheckUtils]: 103: Hoare triple {70394#false} assume !(0 != start_simulation_~tmp___0~1#1); {70394#false} is VALID [2022-02-21 04:22:14,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:14,801 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:14,801 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097744343] [2022-02-21 04:22:14,802 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097744343] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:14,802 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:14,802 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:14,802 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575187062] [2022-02-21 04:22:14,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:14,802 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:14,802 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:14,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:14,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:14,803 INFO L87 Difference]: Start difference. First operand 7026 states and 10254 transitions. cyclomatic complexity: 3236 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:24,515 INFO L93 Difference]: Finished difference Result 19599 states and 28287 transitions. [2022-02-21 04:22:24,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:24,515 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:24,566 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:24,566 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19599 states and 28287 transitions. [2022-02-21 04:22:32,731 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18895 [2022-02-21 04:22:40,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19599 states to 19599 states and 28287 transitions. [2022-02-21 04:22:40,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19599 [2022-02-21 04:22:40,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19599 [2022-02-21 04:22:40,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19599 states and 28287 transitions. [2022-02-21 04:22:40,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:40,607 INFO L681 BuchiCegarLoop]: Abstraction has 19599 states and 28287 transitions. [2022-02-21 04:22:40,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19599 states and 28287 transitions. [2022-02-21 04:22:40,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19599 to 18651. [2022-02-21 04:22:40,765 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:40,836 INFO L82 GeneralOperation]: Start isEquivalent. First operand 19599 states and 28287 transitions. Second operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:40,852 INFO L74 IsIncluded]: Start isIncluded. First operand 19599 states and 28287 transitions. Second operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:40,866 INFO L87 Difference]: Start difference. First operand 19599 states and 28287 transitions. Second operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:48,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:48,830 INFO L93 Difference]: Finished difference Result 19599 states and 28287 transitions. [2022-02-21 04:22:48,830 INFO L276 IsEmpty]: Start isEmpty. Operand 19599 states and 28287 transitions. [2022-02-21 04:22:48,846 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:48,846 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:48,860 INFO L74 IsIncluded]: Start isIncluded. First operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 19599 states and 28287 transitions. [2022-02-21 04:22:48,874 INFO L87 Difference]: Start difference. First operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 19599 states and 28287 transitions. [2022-02-21 04:22:57,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:57,010 INFO L93 Difference]: Finished difference Result 19599 states and 28287 transitions. [2022-02-21 04:22:57,010 INFO L276 IsEmpty]: Start isEmpty. Operand 19599 states and 28287 transitions. [2022-02-21 04:22:57,024 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:57,024 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:57,024 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:57,024 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:57,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18651 states, 18651 states have (on average 1.4482333386949762) internal successors, (27011), 18650 states have internal predecessors, (27011), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:23:04,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18651 states to 18651 states and 27011 transitions. [2022-02-21 04:23:04,382 INFO L704 BuchiCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-02-21 04:23:04,382 INFO L587 BuchiCegarLoop]: Abstraction has 18651 states and 27011 transitions. [2022-02-21 04:23:04,382 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2022-02-21 04:23:04,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18651 states and 27011 transitions. [2022-02-21 04:23:04,415 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18463 [2022-02-21 04:23:04,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:23:04,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:23:04,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,427 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:23:04,427 INFO L791 eck$LassoCheckResult]: Stem: 90678#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 90679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 90535#L1141 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 90478#L529 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90479#L536 assume 1 == ~m_i~0;~m_st~0 := 0; 90840#L536-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 90461#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90295#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90296#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90276#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90277#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 90839#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 90609#L571-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 90610#L769 assume !(0 == ~M_E~0); 90634#L769-2 assume !(0 == ~T1_E~0); 90635#L774-1 assume !(0 == ~T2_E~0); 90668#L779-1 assume !(0 == ~T3_E~0); 90814#L784-1 assume !(0 == ~T4_E~0); 90604#L789-1 assume !(0 == ~T5_E~0); 90605#L794-1 assume !(0 == ~T6_E~0); 90737#L799-1 assume !(0 == ~T7_E~0); 90612#L804-1 assume !(0 == ~E_M~0); 90613#L809-1 assume !(0 == ~E_1~0); 90658#L814-1 assume !(0 == ~E_2~0); 90010#L819-1 assume !(0 == ~E_3~0); 90011#L824-1 assume !(0 == ~E_4~0); 90369#L829-1 assume !(0 == ~E_5~0); 90921#L834-1 assume !(0 == ~E_6~0); 90141#L839-1 assume !(0 == ~E_7~0); 90142#L844-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90547#L376 assume !(1 == ~m_pc~0); 90542#L376-2 is_master_triggered_~__retres1~0#1 := 0; 90543#L387 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90891#L388 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 90092#L955 assume !(0 != activate_threads_~tmp~1#1); 90093#L955-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 90453#L395 assume !(1 == ~t1_pc~0); 90637#L395-2 is_transmit1_triggered_~__retres1~1#1 := 0; 90798#L406 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 90016#L407 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 90017#L963 assume !(0 != activate_threads_~tmp___0~0#1); 90553#L963-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 90554#L414 assume !(1 == ~t2_pc~0); 90144#L414-2 is_transmit2_triggered_~__retres1~2#1 := 0; 90145#L425 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 90356#L426 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 90357#L971 assume !(0 != activate_threads_~tmp___1~0#1); 90845#L971-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 90456#L433 assume !(1 == ~t3_pc~0); 90263#L433-2 is_transmit3_triggered_~__retres1~3#1 := 0; 90264#L444 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 90429#L445 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 90430#L979 assume !(0 != activate_threads_~tmp___2~0#1); 90112#L979-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 90113#L452 assume !(1 == ~t4_pc~0); 90272#L452-2 is_transmit4_triggered_~__retres1~4#1 := 0; 90273#L463 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 90588#L464 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 90667#L987 assume !(0 != activate_threads_~tmp___3~0#1); 90307#L987-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 90308#L471 assume 1 == ~t5_pc~0; 90723#L472 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 90288#L482 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 90289#L483 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90659#L995 assume !(0 != activate_threads_~tmp___4~0#1); 90911#L995-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 90912#L490 assume 1 == ~t6_pc~0; 90873#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 90552#L501 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 90596#L502 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 90600#L1003 assume !(0 != activate_threads_~tmp___5~0#1); 90466#L1003-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 90434#L509 assume !(1 == ~t7_pc~0); 90435#L509-2 is_transmit7_triggered_~__retres1~7#1 := 0; 90241#L520 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 90242#L521 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 90312#L1011 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 90313#L1011-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90853#L857 assume 1 == ~M_E~0;~M_E~0 := 2; 90854#L857-2 assume !(1 == ~T1_E~0); 90377#L862-1 assume !(1 == ~T2_E~0); 90378#L867-1 assume !(1 == ~T3_E~0); 90457#L872-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90458#L877-1 assume !(1 == ~T5_E~0); 90871#L882-1 assume !(1 == ~T6_E~0); 90872#L887-1 assume !(1 == ~T7_E~0); 93576#L892-1 assume !(1 == ~E_M~0); 93574#L897-1 assume !(1 == ~E_1~0); 93572#L902-1 assume !(1 == ~E_2~0); 93570#L907-1 assume !(1 == ~E_3~0); 93568#L912-1 assume 1 == ~E_4~0;~E_4~0 := 2; 93566#L917-1 assume !(1 == ~E_5~0); 93564#L922-1 assume !(1 == ~E_6~0); 93562#L927-1 assume !(1 == ~E_7~0); 93559#L932-1 assume { :end_inline_reset_delta_events } true; 93560#L1178-2 [2022-02-21 04:23:04,427 INFO L793 eck$LassoCheckResult]: Loop: 93560#L1178-2 assume !false; 93536#L1179 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93537#L744 assume !false; 93526#L637 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 93527#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 93487#L626 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 93488#L627 eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 92759#L641 assume !(0 != eval_~tmp~0#1); 92761#L759 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 107711#L529-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 107710#L769-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107709#L769-5 assume !(0 == ~T1_E~0); 107708#L774-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 107707#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 107706#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 107705#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107704#L794-3 assume !(0 == ~T6_E~0); 107703#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 107702#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107701#L809-3 assume !(0 == ~E_1~0); 107700#L814-3 assume 0 == ~E_2~0;~E_2~0 := 1; 107699#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107698#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 107697#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107696#L834-3 assume !(0 == ~E_6~0); 107695#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107694#L844-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107693#L376-27 assume !(1 == ~m_pc~0); 107692#L376-29 is_master_triggered_~__retres1~0#1 := 0; 107691#L387-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107690#L388-9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107689#L955-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 107688#L955-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107687#L395-27 assume !(1 == ~t1_pc~0); 107686#L395-29 is_transmit1_triggered_~__retres1~1#1 := 0; 107685#L406-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107684#L407-9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107683#L963-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 107682#L963-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107681#L414-27 assume 1 == ~t2_pc~0; 107680#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 107678#L425-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107677#L426-9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107676#L971-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 107675#L971-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107674#L433-27 assume !(1 == ~t3_pc~0); 107673#L433-29 is_transmit3_triggered_~__retres1~3#1 := 0; 107672#L444-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107671#L445-9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 107670#L979-27 assume !(0 != activate_threads_~tmp___2~0#1); 107669#L979-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107668#L452-27 assume !(1 == ~t4_pc~0); 107667#L452-29 is_transmit4_triggered_~__retres1~4#1 := 0; 107665#L463-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107664#L464-9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 107663#L987-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 107662#L987-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 107661#L471-27 assume 1 == ~t5_pc~0; 107659#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 107658#L482-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 107657#L483-9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 107656#L995-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 107655#L995-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 107654#L490-27 assume !(1 == ~t6_pc~0); 107653#L490-29 is_transmit6_triggered_~__retres1~6#1 := 0; 107651#L501-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 107650#L502-9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 107649#L1003-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 107647#L1003-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 107646#L509-27 assume 1 == ~t7_pc~0; 107645#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 107643#L520-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 107642#L521-9 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 107641#L1011-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 107640#L1011-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107639#L857-3 assume 1 == ~M_E~0;~M_E~0 := 2; 101999#L857-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107638#L862-3 assume !(1 == ~T2_E~0); 107637#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 107636#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 107635#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107634#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 107482#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107633#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107632#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107631#L902-3 assume !(1 == ~E_2~0); 94963#L907-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94964#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94948#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 94949#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 94938#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 94939#L932-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 94816#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 94812#L626-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 94800#L627-1 start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 94794#L1197 assume !(0 == start_simulation_~tmp~3#1); 94792#L1197-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 94793#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 107320#L626-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 107319#L627-2 stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; 107318#L1152 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 107317#L1159 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 107316#L1160 start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 107315#L1210 assume !(0 != start_simulation_~tmp___0~1#1); 93560#L1178-2 [2022-02-21 04:23:04,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1116257915, now seen corresponding path program 1 times [2022-02-21 04:23:04,428 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,428 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [35964853] [2022-02-21 04:23:04,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,481 INFO L290 TraceCheckUtils]: 0: Hoare triple {147849#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,481 INFO L290 TraceCheckUtils]: 1: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,482 INFO L290 TraceCheckUtils]: 2: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret23#1, start_simulation_#t~ret24#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,482 INFO L290 TraceCheckUtils]: 3: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,482 INFO L290 TraceCheckUtils]: 4: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~m_i~0;~m_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,483 INFO L290 TraceCheckUtils]: 5: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,483 INFO L290 TraceCheckUtils]: 6: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,483 INFO L290 TraceCheckUtils]: 7: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,483 INFO L290 TraceCheckUtils]: 8: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,484 INFO L290 TraceCheckUtils]: 9: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,484 INFO L290 TraceCheckUtils]: 10: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,484 INFO L290 TraceCheckUtils]: 11: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,484 INFO L290 TraceCheckUtils]: 12: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,485 INFO L290 TraceCheckUtils]: 13: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~M_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,485 INFO L290 TraceCheckUtils]: 14: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T1_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,485 INFO L290 TraceCheckUtils]: 15: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T2_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,485 INFO L290 TraceCheckUtils]: 16: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T3_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,486 INFO L290 TraceCheckUtils]: 17: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T4_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,486 INFO L290 TraceCheckUtils]: 18: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T5_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,486 INFO L290 TraceCheckUtils]: 19: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T6_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,486 INFO L290 TraceCheckUtils]: 20: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~T7_E~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,487 INFO L290 TraceCheckUtils]: 21: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_M~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,487 INFO L290 TraceCheckUtils]: 22: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_1~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,487 INFO L290 TraceCheckUtils]: 23: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_2~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,487 INFO L290 TraceCheckUtils]: 24: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_3~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,488 INFO L290 TraceCheckUtils]: 25: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_4~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,488 INFO L290 TraceCheckUtils]: 26: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_5~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,488 INFO L290 TraceCheckUtils]: 27: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_6~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,488 INFO L290 TraceCheckUtils]: 28: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 == ~E_7~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,489 INFO L290 TraceCheckUtils]: 29: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,489 INFO L290 TraceCheckUtils]: 30: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(1 == ~m_pc~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,489 INFO L290 TraceCheckUtils]: 31: Hoare triple {147851#(<= ~t5_pc~0 0)} is_master_triggered_~__retres1~0#1 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,489 INFO L290 TraceCheckUtils]: 32: Hoare triple {147851#(<= ~t5_pc~0 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,490 INFO L290 TraceCheckUtils]: 33: Hoare triple {147851#(<= ~t5_pc~0 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,490 INFO L290 TraceCheckUtils]: 34: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp~1#1); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,490 INFO L290 TraceCheckUtils]: 35: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,490 INFO L290 TraceCheckUtils]: 36: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(1 == ~t1_pc~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,491 INFO L290 TraceCheckUtils]: 37: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,491 INFO L290 TraceCheckUtils]: 38: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,491 INFO L290 TraceCheckUtils]: 39: Hoare triple {147851#(<= ~t5_pc~0 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,492 INFO L290 TraceCheckUtils]: 40: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___0~0#1); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,492 INFO L290 TraceCheckUtils]: 41: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,492 INFO L290 TraceCheckUtils]: 42: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(1 == ~t2_pc~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,492 INFO L290 TraceCheckUtils]: 43: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,493 INFO L290 TraceCheckUtils]: 44: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,493 INFO L290 TraceCheckUtils]: 45: Hoare triple {147851#(<= ~t5_pc~0 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,493 INFO L290 TraceCheckUtils]: 46: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___1~0#1); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,493 INFO L290 TraceCheckUtils]: 47: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,494 INFO L290 TraceCheckUtils]: 48: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(1 == ~t3_pc~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,494 INFO L290 TraceCheckUtils]: 49: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,494 INFO L290 TraceCheckUtils]: 50: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,494 INFO L290 TraceCheckUtils]: 51: Hoare triple {147851#(<= ~t5_pc~0 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,495 INFO L290 TraceCheckUtils]: 52: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___2~0#1); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,495 INFO L290 TraceCheckUtils]: 53: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,495 INFO L290 TraceCheckUtils]: 54: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(1 == ~t4_pc~0); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,495 INFO L290 TraceCheckUtils]: 55: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,496 INFO L290 TraceCheckUtils]: 56: Hoare triple {147851#(<= ~t5_pc~0 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,496 INFO L290 TraceCheckUtils]: 57: Hoare triple {147851#(<= ~t5_pc~0 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,496 INFO L290 TraceCheckUtils]: 58: Hoare triple {147851#(<= ~t5_pc~0 0)} assume !(0 != activate_threads_~tmp___3~0#1); {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,496 INFO L290 TraceCheckUtils]: 59: Hoare triple {147851#(<= ~t5_pc~0 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {147851#(<= ~t5_pc~0 0)} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 60: Hoare triple {147851#(<= ~t5_pc~0 0)} assume 1 == ~t5_pc~0; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 61: Hoare triple {147850#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 62: Hoare triple {147850#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 63: Hoare triple {147850#false} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 64: Hoare triple {147850#false} assume !(0 != activate_threads_~tmp___4~0#1); {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 65: Hoare triple {147850#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 66: Hoare triple {147850#false} assume 1 == ~t6_pc~0; {147850#false} is VALID [2022-02-21 04:23:04,497 INFO L290 TraceCheckUtils]: 67: Hoare triple {147850#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 68: Hoare triple {147850#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 69: Hoare triple {147850#false} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 70: Hoare triple {147850#false} assume !(0 != activate_threads_~tmp___5~0#1); {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 71: Hoare triple {147850#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 72: Hoare triple {147850#false} assume !(1 == ~t7_pc~0); {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 73: Hoare triple {147850#false} is_transmit7_triggered_~__retres1~7#1 := 0; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 74: Hoare triple {147850#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 75: Hoare triple {147850#false} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 76: Hoare triple {147850#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {147850#false} is VALID [2022-02-21 04:23:04,498 INFO L290 TraceCheckUtils]: 77: Hoare triple {147850#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 78: Hoare triple {147850#false} assume 1 == ~M_E~0;~M_E~0 := 2; {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 79: Hoare triple {147850#false} assume !(1 == ~T1_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 80: Hoare triple {147850#false} assume !(1 == ~T2_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 81: Hoare triple {147850#false} assume !(1 == ~T3_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 82: Hoare triple {147850#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 83: Hoare triple {147850#false} assume !(1 == ~T5_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 84: Hoare triple {147850#false} assume !(1 == ~T6_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 85: Hoare triple {147850#false} assume !(1 == ~T7_E~0); {147850#false} is VALID [2022-02-21 04:23:04,499 INFO L290 TraceCheckUtils]: 86: Hoare triple {147850#false} assume !(1 == ~E_M~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 87: Hoare triple {147850#false} assume !(1 == ~E_1~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 88: Hoare triple {147850#false} assume !(1 == ~E_2~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 89: Hoare triple {147850#false} assume !(1 == ~E_3~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 90: Hoare triple {147850#false} assume 1 == ~E_4~0;~E_4~0 := 2; {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 91: Hoare triple {147850#false} assume !(1 == ~E_5~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 92: Hoare triple {147850#false} assume !(1 == ~E_6~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 93: Hoare triple {147850#false} assume !(1 == ~E_7~0); {147850#false} is VALID [2022-02-21 04:23:04,500 INFO L290 TraceCheckUtils]: 94: Hoare triple {147850#false} assume { :end_inline_reset_delta_events } true; {147850#false} is VALID [2022-02-21 04:23:04,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,523 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,523 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [35964853] [2022-02-21 04:23:04,523 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [35964853] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,524 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,524 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:23:04,524 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462250010] [2022-02-21 04:23:04,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:23:04,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:23:04,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1435227033, now seen corresponding path program 1 times [2022-02-21 04:23:04,525 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:23:04,525 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973934475] [2022-02-21 04:23:04,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:23:04,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:23:04,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 0: Hoare triple {147852#true} assume !false; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 1: Hoare triple {147852#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 2: Hoare triple {147852#true} assume !false; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 3: Hoare triple {147852#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 4: Hoare triple {147852#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 5: Hoare triple {147852#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 6: Hoare triple {147852#true} eval_#t~ret5#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 7: Hoare triple {147852#true} assume !(0 != eval_~tmp~0#1); {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 8: Hoare triple {147852#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 9: Hoare triple {147852#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 10: Hoare triple {147852#true} assume 0 == ~M_E~0;~M_E~0 := 1; {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 11: Hoare triple {147852#true} assume !(0 == ~T1_E~0); {147852#true} is VALID [2022-02-21 04:23:04,556 INFO L290 TraceCheckUtils]: 12: Hoare triple {147852#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,557 INFO L290 TraceCheckUtils]: 13: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T3_E~0;~T3_E~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,557 INFO L290 TraceCheckUtils]: 14: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T4_E~0;~T4_E~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,557 INFO L290 TraceCheckUtils]: 15: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T5_E~0;~T5_E~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,557 INFO L290 TraceCheckUtils]: 16: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~T6_E~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,558 INFO L290 TraceCheckUtils]: 17: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~T7_E~0;~T7_E~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,558 INFO L290 TraceCheckUtils]: 18: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,558 INFO L290 TraceCheckUtils]: 19: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_1~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,558 INFO L290 TraceCheckUtils]: 20: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,558 INFO L290 TraceCheckUtils]: 21: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,571 INFO L290 TraceCheckUtils]: 22: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,572 INFO L290 TraceCheckUtils]: 23: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,572 INFO L290 TraceCheckUtils]: 24: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 == ~E_6~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,572 INFO L290 TraceCheckUtils]: 25: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,572 INFO L290 TraceCheckUtils]: 26: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,572 INFO L290 TraceCheckUtils]: 27: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~m_pc~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,573 INFO L290 TraceCheckUtils]: 28: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,573 INFO L290 TraceCheckUtils]: 29: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,573 INFO L290 TraceCheckUtils]: 30: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret14#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,573 INFO L290 TraceCheckUtils]: 31: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,574 INFO L290 TraceCheckUtils]: 32: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,574 INFO L290 TraceCheckUtils]: 33: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t1_pc~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,574 INFO L290 TraceCheckUtils]: 34: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,574 INFO L290 TraceCheckUtils]: 35: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,575 INFO L290 TraceCheckUtils]: 36: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,575 INFO L290 TraceCheckUtils]: 37: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,575 INFO L290 TraceCheckUtils]: 38: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,575 INFO L290 TraceCheckUtils]: 39: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t2_pc~0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,575 INFO L290 TraceCheckUtils]: 40: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,576 INFO L290 TraceCheckUtils]: 41: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,576 INFO L290 TraceCheckUtils]: 42: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,576 INFO L290 TraceCheckUtils]: 43: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,576 INFO L290 TraceCheckUtils]: 44: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,577 INFO L290 TraceCheckUtils]: 45: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t3_pc~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,577 INFO L290 TraceCheckUtils]: 46: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_~__retres1~3#1 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,577 INFO L290 TraceCheckUtils]: 47: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,577 INFO L290 TraceCheckUtils]: 48: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,578 INFO L290 TraceCheckUtils]: 49: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(0 != activate_threads_~tmp___2~0#1); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,578 INFO L290 TraceCheckUtils]: 50: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,578 INFO L290 TraceCheckUtils]: 51: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t4_pc~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,578 INFO L290 TraceCheckUtils]: 52: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,578 INFO L290 TraceCheckUtils]: 53: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,579 INFO L290 TraceCheckUtils]: 54: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,579 INFO L290 TraceCheckUtils]: 55: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,579 INFO L290 TraceCheckUtils]: 56: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,579 INFO L290 TraceCheckUtils]: 57: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t5_pc~0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,580 INFO L290 TraceCheckUtils]: 58: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,580 INFO L290 TraceCheckUtils]: 59: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,580 INFO L290 TraceCheckUtils]: 60: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,580 INFO L290 TraceCheckUtils]: 61: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,581 INFO L290 TraceCheckUtils]: 62: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,581 INFO L290 TraceCheckUtils]: 63: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~t6_pc~0); {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,581 INFO L290 TraceCheckUtils]: 64: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,581 INFO L290 TraceCheckUtils]: 65: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,582 INFO L290 TraceCheckUtils]: 66: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,582 INFO L290 TraceCheckUtils]: 67: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,582 INFO L290 TraceCheckUtils]: 68: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,582 INFO L290 TraceCheckUtils]: 69: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~t7_pc~0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,582 INFO L290 TraceCheckUtils]: 70: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,583 INFO L290 TraceCheckUtils]: 71: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,583 INFO L290 TraceCheckUtils]: 72: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,583 INFO L290 TraceCheckUtils]: 73: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,583 INFO L290 TraceCheckUtils]: 74: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,584 INFO L290 TraceCheckUtils]: 75: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,584 INFO L290 TraceCheckUtils]: 76: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {147854#(= (+ (- 1) ~T2_E~0) 0)} is VALID [2022-02-21 04:23:04,584 INFO L290 TraceCheckUtils]: 77: Hoare triple {147854#(= (+ (- 1) ~T2_E~0) 0)} assume !(1 == ~T2_E~0); {147853#false} is VALID [2022-02-21 04:23:04,584 INFO L290 TraceCheckUtils]: 78: Hoare triple {147853#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,584 INFO L290 TraceCheckUtils]: 79: Hoare triple {147853#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 80: Hoare triple {147853#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 81: Hoare triple {147853#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 82: Hoare triple {147853#false} assume 1 == ~T7_E~0;~T7_E~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 83: Hoare triple {147853#false} assume 1 == ~E_M~0;~E_M~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 84: Hoare triple {147853#false} assume 1 == ~E_1~0;~E_1~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 85: Hoare triple {147853#false} assume !(1 == ~E_2~0); {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 86: Hoare triple {147853#false} assume 1 == ~E_3~0;~E_3~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 87: Hoare triple {147853#false} assume 1 == ~E_4~0;~E_4~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 88: Hoare triple {147853#false} assume 1 == ~E_5~0;~E_5~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 89: Hoare triple {147853#false} assume 1 == ~E_6~0;~E_6~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 90: Hoare triple {147853#false} assume 1 == ~E_7~0;~E_7~0 := 2; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 91: Hoare triple {147853#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 92: Hoare triple {147853#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 93: Hoare triple {147853#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {147853#false} is VALID [2022-02-21 04:23:04,585 INFO L290 TraceCheckUtils]: 94: Hoare triple {147853#false} start_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 95: Hoare triple {147853#false} assume !(0 == start_simulation_~tmp~3#1); {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 96: Hoare triple {147853#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret22#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 97: Hoare triple {147853#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 98: Hoare triple {147853#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 99: Hoare triple {147853#false} stop_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret22#1;havoc stop_simulation_#t~ret22#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 100: Hoare triple {147853#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 101: Hoare triple {147853#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 102: Hoare triple {147853#false} start_simulation_#t~ret24#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L290 TraceCheckUtils]: 103: Hoare triple {147853#false} assume !(0 != start_simulation_~tmp___0~1#1); {147853#false} is VALID [2022-02-21 04:23:04,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:23:04,587 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:23:04,587 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973934475] [2022-02-21 04:23:04,587 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973934475] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:23:04,587 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:23:04,587 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:23:04,587 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596320765] [2022-02-21 04:23:04,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:23:04,587 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:23:04,587 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:23:04,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:23:04,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:23:04,588 INFO L87 Difference]: Start difference. First operand 18651 states and 27011 transitions. cyclomatic complexity: 8376 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 2 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)