./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c --full-output -ea --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 03d7b7b3 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -ea -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.07.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b --- Real Ultimate output --- This is Ultimate 0.2.2-dev-03d7b7b [2022-02-21 04:21:52,675 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-02-21 04:21:52,678 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-02-21 04:21:52,710 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-02-21 04:21:52,715 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-02-21 04:21:52,717 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-02-21 04:21:52,718 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-02-21 04:21:52,719 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-02-21 04:21:52,721 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-02-21 04:21:52,724 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-02-21 04:21:52,725 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-02-21 04:21:52,726 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-02-21 04:21:52,727 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-02-21 04:21:52,730 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-02-21 04:21:52,732 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-02-21 04:21:52,734 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-02-21 04:21:52,735 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-02-21 04:21:52,739 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-02-21 04:21:52,741 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-02-21 04:21:52,742 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-02-21 04:21:52,748 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-02-21 04:21:52,749 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-02-21 04:21:52,750 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-02-21 04:21:52,751 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-02-21 04:21:52,754 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-02-21 04:21:52,760 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-02-21 04:21:52,760 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-02-21 04:21:52,761 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-02-21 04:21:52,762 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-02-21 04:21:52,762 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-02-21 04:21:52,763 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-02-21 04:21:52,763 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-02-21 04:21:52,764 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-02-21 04:21:52,766 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-02-21 04:21:52,767 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-02-21 04:21:52,767 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-02-21 04:21:52,768 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-02-21 04:21:52,769 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-02-21 04:21:52,769 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-02-21 04:21:52,770 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-02-21 04:21:52,771 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-02-21 04:21:52,772 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2022-02-21 04:21:52,807 INFO L113 SettingsManager]: Loading preferences was successful [2022-02-21 04:21:52,808 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-02-21 04:21:52,808 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-02-21 04:21:52,809 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-02-21 04:21:52,810 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-02-21 04:21:52,810 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-02-21 04:21:52,810 INFO L138 SettingsManager]: * Use SBE=true [2022-02-21 04:21:52,810 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2022-02-21 04:21:52,810 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2022-02-21 04:21:52,811 INFO L138 SettingsManager]: * Use old map elimination=false [2022-02-21 04:21:52,815 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2022-02-21 04:21:52,815 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2022-02-21 04:21:52,815 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2022-02-21 04:21:52,816 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-02-21 04:21:52,816 INFO L138 SettingsManager]: * sizeof long=4 [2022-02-21 04:21:52,816 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2022-02-21 04:21:52,816 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-02-21 04:21:52,816 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-02-21 04:21:52,816 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-02-21 04:21:52,817 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2022-02-21 04:21:52,817 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2022-02-21 04:21:52,817 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2022-02-21 04:21:52,817 INFO L138 SettingsManager]: * sizeof long double=12 [2022-02-21 04:21:52,817 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-02-21 04:21:52,818 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2022-02-21 04:21:52,818 INFO L138 SettingsManager]: * Use constant arrays=true [2022-02-21 04:21:52,818 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2022-02-21 04:21:52,818 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-02-21 04:21:52,818 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-02-21 04:21:52,819 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-02-21 04:21:52,819 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-02-21 04:21:52,820 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-02-21 04:21:52,820 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32b030e5f1b46150870f8dd8e24821389f0ffe4175e43053767dc9109bffcf9b [2022-02-21 04:21:53,085 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-02-21 04:21:53,108 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-02-21 04:21:53,110 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-02-21 04:21:53,111 INFO L271 PluginConnector]: Initializing CDTParser... [2022-02-21 04:21:53,112 INFO L275 PluginConnector]: CDTParser initialized [2022-02-21 04:21:53,113 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-02-21 04:21:53,178 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efb60cd15/7f43d2fd3a3d4368b97399acae14c049/FLAGe41cf6c67 [2022-02-21 04:21:53,672 INFO L306 CDTParser]: Found 1 translation units. [2022-02-21 04:21:53,672 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c [2022-02-21 04:21:53,687 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efb60cd15/7f43d2fd3a3d4368b97399acae14c049/FLAGe41cf6c67 [2022-02-21 04:21:54,139 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/efb60cd15/7f43d2fd3a3d4368b97399acae14c049 [2022-02-21 04:21:54,142 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-02-21 04:21:54,144 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-02-21 04:21:54,147 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:54,147 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-02-21 04:21:54,150 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-02-21 04:21:54,151 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,152 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5030fa93 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54, skipping insertion in model container [2022-02-21 04:21:54,152 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,158 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-02-21 04:21:54,193 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-02-21 04:21:54,343 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-02-21 04:21:54,431 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:54,448 INFO L203 MainTranslator]: Completed pre-run [2022-02-21 04:21:54,458 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.07.cil-2.c[671,684] [2022-02-21 04:21:54,547 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-02-21 04:21:54,576 INFO L208 MainTranslator]: Completed translation [2022-02-21 04:21:54,577 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54 WrapperNode [2022-02-21 04:21:54,577 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-02-21 04:21:54,578 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:54,578 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-02-21 04:21:54,579 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-02-21 04:21:54,584 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,597 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,692 INFO L137 Inliner]: procedures = 42, calls = 53, calls flagged for inlining = 48, calls inlined = 135, statements flattened = 2001 [2022-02-21 04:21:54,698 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-02-21 04:21:54,699 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-02-21 04:21:54,699 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-02-21 04:21:54,700 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-02-21 04:21:54,706 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,706 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,712 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,716 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,767 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,817 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,821 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,830 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-02-21 04:21:54,837 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-02-21 04:21:54,838 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-02-21 04:21:54,838 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-02-21 04:21:54,839 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (1/1) ... [2022-02-21 04:21:54,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2022-02-21 04:21:54,855 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-02-21 04:21:54,868 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2022-02-21 04:21:54,919 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2022-02-21 04:21:54,928 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-02-21 04:21:54,928 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-02-21 04:21:54,928 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-02-21 04:21:54,928 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-02-21 04:21:55,071 INFO L234 CfgBuilder]: Building ICFG [2022-02-21 04:21:55,072 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-02-21 04:21:56,292 INFO L275 CfgBuilder]: Performing block encoding [2022-02-21 04:21:56,305 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-02-21 04:21:56,305 INFO L299 CfgBuilder]: Removed 10 assume(true) statements. [2022-02-21 04:21:56,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:56 BoogieIcfgContainer [2022-02-21 04:21:56,307 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-02-21 04:21:56,308 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2022-02-21 04:21:56,308 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2022-02-21 04:21:56,311 INFO L275 PluginConnector]: BuchiAutomizer initialized [2022-02-21 04:21:56,312 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:56,312 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 21.02 04:21:54" (1/3) ... [2022-02-21 04:21:56,313 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@331b8992 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:56, skipping insertion in model container [2022-02-21 04:21:56,313 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:56,313 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 21.02 04:21:54" (2/3) ... [2022-02-21 04:21:56,314 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@331b8992 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 21.02 04:21:56, skipping insertion in model container [2022-02-21 04:21:56,314 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2022-02-21 04:21:56,314 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 21.02 04:21:56" (3/3) ... [2022-02-21 04:21:56,315 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-2.c [2022-02-21 04:21:56,364 INFO L359 BuchiCegarLoop]: Interprodecural is true [2022-02-21 04:21:56,364 INFO L360 BuchiCegarLoop]: Hoare is false [2022-02-21 04:21:56,364 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2022-02-21 04:21:56,364 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2022-02-21 04:21:56,364 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2022-02-21 04:21:56,364 INFO L364 BuchiCegarLoop]: Difference is false [2022-02-21 04:21:56,365 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2022-02-21 04:21:56,365 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2022-02-21 04:21:56,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-02-21 04:21:56,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,596 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2022-02-21 04:21:56,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:56,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 736 [2022-02-21 04:21:56,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:56,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:56,678 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,678 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:56,692 INFO L791 eck$LassoCheckResult]: Stem: 411#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 770#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 44#L1153true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 683#L541true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 790#L548true assume !(1 == ~m_i~0);~m_st~0 := 2; 212#L548-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 389#L553-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 288#L558-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 747#L563-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 157#L568-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 42#L573-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 777#L578-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 132#L583-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 492#L781true assume !(0 == ~M_E~0); 808#L781-2true assume !(0 == ~T1_E~0); 836#L786-1true assume !(0 == ~T2_E~0); 23#L791-1true assume !(0 == ~T3_E~0); 375#L796-1true assume !(0 == ~T4_E~0); 346#L801-1true assume !(0 == ~T5_E~0); 377#L806-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 753#L811-1true assume !(0 == ~T7_E~0); 136#L816-1true assume !(0 == ~E_M~0); 614#L821-1true assume !(0 == ~E_1~0); 37#L826-1true assume !(0 == ~E_2~0); 345#L831-1true assume !(0 == ~E_3~0); 210#L836-1true assume !(0 == ~E_4~0); 494#L841-1true assume !(0 == ~E_5~0); 110#L846-1true assume 0 == ~E_6~0;~E_6~0 := 1; 783#L851-1true assume !(0 == ~E_7~0); 122#L856-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 634#L388true assume !(1 == ~m_pc~0); 119#L388-2true is_master_triggered_~__retres1~0#1 := 0; 464#L399true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 674#L400true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46#L967true assume !(0 != activate_threads_~tmp~1#1); 754#L967-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12#L407true assume 1 == ~t1_pc~0; 401#L408true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14#L418true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3#L419true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 604#L975true assume !(0 != activate_threads_~tmp___0~0#1); 628#L975-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 187#L426true assume !(1 == ~t2_pc~0); 644#L426-2true is_transmit2_triggered_~__retres1~2#1 := 0; 738#L437true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 819#L438true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 730#L983true assume !(0 != activate_threads_~tmp___1~0#1); 837#L983-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238#L445true assume 1 == ~t3_pc~0; 828#L446true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 502#L456true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 120#L457true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425#L991true assume !(0 != activate_threads_~tmp___2~0#1); 498#L991-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 402#L464true assume !(1 == ~t4_pc~0); 124#L464-2true is_transmit4_triggered_~__retres1~4#1 := 0; 55#L475true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 244#L476true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 835#L999true assume !(0 != activate_threads_~tmp___3~0#1); 222#L999-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 398#L483true assume 1 == ~t5_pc~0; 722#L484true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 578#L494true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 327#L495true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 682#L1007true assume !(0 != activate_threads_~tmp___4~0#1); 177#L1007-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 442#L502true assume 1 == ~t6_pc~0; 373#L503true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 70#L513true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472#L514true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 313#L1015true assume !(0 != activate_threads_~tmp___5~0#1); 545#L1015-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 692#L521true assume !(1 == ~t7_pc~0); 647#L521-2true is_transmit7_triggered_~__retres1~7#1 := 0; 43#L532true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 98#L533true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 594#L1023true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 555#L1023-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 450#L869true assume !(1 == ~M_E~0); 218#L869-2true assume !(1 == ~T1_E~0); 723#L874-1true assume !(1 == ~T2_E~0); 667#L879-1true assume !(1 == ~T3_E~0); 268#L884-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 7#L889-1true assume !(1 == ~T5_E~0); 140#L894-1true assume !(1 == ~T6_E~0); 825#L899-1true assume !(1 == ~T7_E~0); 416#L904-1true assume !(1 == ~E_M~0); 232#L909-1true assume !(1 == ~E_1~0); 361#L914-1true assume !(1 == ~E_2~0); 382#L919-1true assume !(1 == ~E_3~0); 186#L924-1true assume 1 == ~E_4~0;~E_4~0 := 2; 90#L929-1true assume !(1 == ~E_5~0); 687#L934-1true assume !(1 == ~E_6~0); 220#L939-1true assume !(1 == ~E_7~0); 543#L944-1true assume { :end_inline_reset_delta_events } true; 539#L1190-2true [2022-02-21 04:21:56,695 INFO L793 eck$LassoCheckResult]: Loop: 539#L1190-2true assume !false; 137#L1191true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 276#L756true assume !true; 823#L771true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#L541-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 386#L781-3true assume 0 == ~M_E~0;~M_E~0 := 1; 61#L781-5true assume !(0 == ~T1_E~0); 251#L786-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 299#L791-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 35#L796-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 618#L801-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 178#L806-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 294#L811-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 484#L816-3true assume 0 == ~E_M~0;~E_M~0 := 1; 645#L821-3true assume !(0 == ~E_1~0); 765#L826-3true assume 0 == ~E_2~0;~E_2~0 := 1; 422#L831-3true assume 0 == ~E_3~0;~E_3~0 := 1; 660#L836-3true assume 0 == ~E_4~0;~E_4~0 := 1; 115#L841-3true assume 0 == ~E_5~0;~E_5~0 := 1; 593#L846-3true assume 0 == ~E_6~0;~E_6~0 := 1; 312#L851-3true assume 0 == ~E_7~0;~E_7~0 := 1; 58#L856-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 746#L388-27true assume !(1 == ~m_pc~0); 793#L388-29true is_master_triggered_~__retres1~0#1 := 0; 761#L399-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 554#L400-9true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 690#L967-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 159#L967-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 440#L407-27true assume !(1 == ~t1_pc~0); 677#L407-29true is_transmit1_triggered_~__retres1~1#1 := 0; 526#L418-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 303#L419-9true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 468#L975-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 329#L975-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112#L426-27true assume 1 == ~t2_pc~0; 671#L427-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 116#L437-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 571#L438-9true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 689#L983-27true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 589#L983-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 291#L445-27true assume 1 == ~t3_pc~0; 274#L446-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33#L456-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 275#L457-9true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 845#L991-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 366#L991-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 173#L464-27true assume !(1 == ~t4_pc~0); 32#L464-29true is_transmit4_triggered_~__retres1~4#1 := 0; 64#L475-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 439#L476-9true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 295#L999-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108#L999-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 780#L483-27true assume !(1 == ~t5_pc~0); 572#L483-29true is_transmit5_triggered_~__retres1~5#1 := 0; 59#L494-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 625#L495-9true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 536#L1007-27true assume !(0 != activate_threads_~tmp___4~0#1); 811#L1007-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 699#L502-27true assume !(1 == ~t6_pc~0); 309#L502-29true is_transmit6_triggered_~__retres1~6#1 := 0; 688#L513-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 613#L514-9true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 445#L1015-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 735#L1015-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8#L521-27true assume 1 == ~t7_pc~0; 193#L522-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 771#L532-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 284#L533-9true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30#L1023-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 321#L1023-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L869-3true assume 1 == ~M_E~0;~M_E~0 := 2; 443#L869-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 250#L874-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 287#L879-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 311#L884-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 282#L889-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 84#L894-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 412#L899-3true assume !(1 == ~T7_E~0); 100#L904-3true assume 1 == ~E_M~0;~E_M~0 := 2; 265#L909-3true assume 1 == ~E_1~0;~E_1~0 := 2; 71#L914-3true assume 1 == ~E_2~0;~E_2~0 := 2; 95#L919-3true assume 1 == ~E_3~0;~E_3~0 := 2; 605#L924-3true assume 1 == ~E_4~0;~E_4~0 := 2; 431#L929-3true assume 1 == ~E_5~0;~E_5~0 := 2; 363#L934-3true assume 1 == ~E_6~0;~E_6~0 := 2; 550#L939-3true assume !(1 == ~E_7~0); 104#L944-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 588#L596-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 653#L638-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 255#L639-1true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 776#L1209true assume !(0 == start_simulation_~tmp~3#1); 307#L1209-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 293#L596-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 530#L638-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 334#L639-2true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 596#L1164true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27#L1171true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 156#L1172true start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 130#L1222true assume !(0 != start_simulation_~tmp___0~1#1); 539#L1190-2true [2022-02-21 04:21:56,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:56,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2022-02-21 04:21:56,708 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:56,708 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2032193283] [2022-02-21 04:21:56,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:56,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:56,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:56,949 INFO L290 TraceCheckUtils]: 0: Hoare triple {847#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {847#true} is VALID [2022-02-21 04:21:56,950 INFO L290 TraceCheckUtils]: 1: Hoare triple {847#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {849#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:56,951 INFO L290 TraceCheckUtils]: 2: Hoare triple {849#(= ~m_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {849#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:56,952 INFO L290 TraceCheckUtils]: 3: Hoare triple {849#(= ~m_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {849#(= ~m_i~0 1)} is VALID [2022-02-21 04:21:56,952 INFO L290 TraceCheckUtils]: 4: Hoare triple {849#(= ~m_i~0 1)} assume !(1 == ~m_i~0);~m_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,953 INFO L290 TraceCheckUtils]: 5: Hoare triple {848#false} assume 1 == ~t1_i~0;~t1_st~0 := 0; {848#false} is VALID [2022-02-21 04:21:56,953 INFO L290 TraceCheckUtils]: 6: Hoare triple {848#false} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,954 INFO L290 TraceCheckUtils]: 7: Hoare triple {848#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,954 INFO L290 TraceCheckUtils]: 8: Hoare triple {848#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,954 INFO L290 TraceCheckUtils]: 9: Hoare triple {848#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,955 INFO L290 TraceCheckUtils]: 10: Hoare triple {848#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,955 INFO L290 TraceCheckUtils]: 11: Hoare triple {848#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,955 INFO L290 TraceCheckUtils]: 12: Hoare triple {848#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {848#false} is VALID [2022-02-21 04:21:56,955 INFO L290 TraceCheckUtils]: 13: Hoare triple {848#false} assume !(0 == ~M_E~0); {848#false} is VALID [2022-02-21 04:21:56,956 INFO L290 TraceCheckUtils]: 14: Hoare triple {848#false} assume !(0 == ~T1_E~0); {848#false} is VALID [2022-02-21 04:21:56,956 INFO L290 TraceCheckUtils]: 15: Hoare triple {848#false} assume !(0 == ~T2_E~0); {848#false} is VALID [2022-02-21 04:21:56,956 INFO L290 TraceCheckUtils]: 16: Hoare triple {848#false} assume !(0 == ~T3_E~0); {848#false} is VALID [2022-02-21 04:21:56,956 INFO L290 TraceCheckUtils]: 17: Hoare triple {848#false} assume !(0 == ~T4_E~0); {848#false} is VALID [2022-02-21 04:21:56,957 INFO L290 TraceCheckUtils]: 18: Hoare triple {848#false} assume !(0 == ~T5_E~0); {848#false} is VALID [2022-02-21 04:21:56,957 INFO L290 TraceCheckUtils]: 19: Hoare triple {848#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {848#false} is VALID [2022-02-21 04:21:56,957 INFO L290 TraceCheckUtils]: 20: Hoare triple {848#false} assume !(0 == ~T7_E~0); {848#false} is VALID [2022-02-21 04:21:56,958 INFO L290 TraceCheckUtils]: 21: Hoare triple {848#false} assume !(0 == ~E_M~0); {848#false} is VALID [2022-02-21 04:21:56,958 INFO L290 TraceCheckUtils]: 22: Hoare triple {848#false} assume !(0 == ~E_1~0); {848#false} is VALID [2022-02-21 04:21:56,958 INFO L290 TraceCheckUtils]: 23: Hoare triple {848#false} assume !(0 == ~E_2~0); {848#false} is VALID [2022-02-21 04:21:56,959 INFO L290 TraceCheckUtils]: 24: Hoare triple {848#false} assume !(0 == ~E_3~0); {848#false} is VALID [2022-02-21 04:21:56,959 INFO L290 TraceCheckUtils]: 25: Hoare triple {848#false} assume !(0 == ~E_4~0); {848#false} is VALID [2022-02-21 04:21:56,959 INFO L290 TraceCheckUtils]: 26: Hoare triple {848#false} assume !(0 == ~E_5~0); {848#false} is VALID [2022-02-21 04:21:56,960 INFO L290 TraceCheckUtils]: 27: Hoare triple {848#false} assume 0 == ~E_6~0;~E_6~0 := 1; {848#false} is VALID [2022-02-21 04:21:56,960 INFO L290 TraceCheckUtils]: 28: Hoare triple {848#false} assume !(0 == ~E_7~0); {848#false} is VALID [2022-02-21 04:21:56,960 INFO L290 TraceCheckUtils]: 29: Hoare triple {848#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {848#false} is VALID [2022-02-21 04:21:56,960 INFO L290 TraceCheckUtils]: 30: Hoare triple {848#false} assume !(1 == ~m_pc~0); {848#false} is VALID [2022-02-21 04:21:56,961 INFO L290 TraceCheckUtils]: 31: Hoare triple {848#false} is_master_triggered_~__retres1~0#1 := 0; {848#false} is VALID [2022-02-21 04:21:56,961 INFO L290 TraceCheckUtils]: 32: Hoare triple {848#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {848#false} is VALID [2022-02-21 04:21:56,961 INFO L290 TraceCheckUtils]: 33: Hoare triple {848#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {848#false} is VALID [2022-02-21 04:21:56,961 INFO L290 TraceCheckUtils]: 34: Hoare triple {848#false} assume !(0 != activate_threads_~tmp~1#1); {848#false} is VALID [2022-02-21 04:21:56,962 INFO L290 TraceCheckUtils]: 35: Hoare triple {848#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {848#false} is VALID [2022-02-21 04:21:56,962 INFO L290 TraceCheckUtils]: 36: Hoare triple {848#false} assume 1 == ~t1_pc~0; {848#false} is VALID [2022-02-21 04:21:56,962 INFO L290 TraceCheckUtils]: 37: Hoare triple {848#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {848#false} is VALID [2022-02-21 04:21:56,962 INFO L290 TraceCheckUtils]: 38: Hoare triple {848#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {848#false} is VALID [2022-02-21 04:21:56,963 INFO L290 TraceCheckUtils]: 39: Hoare triple {848#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {848#false} is VALID [2022-02-21 04:21:56,963 INFO L290 TraceCheckUtils]: 40: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___0~0#1); {848#false} is VALID [2022-02-21 04:21:56,963 INFO L290 TraceCheckUtils]: 41: Hoare triple {848#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {848#false} is VALID [2022-02-21 04:21:56,964 INFO L290 TraceCheckUtils]: 42: Hoare triple {848#false} assume !(1 == ~t2_pc~0); {848#false} is VALID [2022-02-21 04:21:56,964 INFO L290 TraceCheckUtils]: 43: Hoare triple {848#false} is_transmit2_triggered_~__retres1~2#1 := 0; {848#false} is VALID [2022-02-21 04:21:56,965 INFO L290 TraceCheckUtils]: 44: Hoare triple {848#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {848#false} is VALID [2022-02-21 04:21:56,965 INFO L290 TraceCheckUtils]: 45: Hoare triple {848#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {848#false} is VALID [2022-02-21 04:21:56,965 INFO L290 TraceCheckUtils]: 46: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___1~0#1); {848#false} is VALID [2022-02-21 04:21:56,965 INFO L290 TraceCheckUtils]: 47: Hoare triple {848#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {848#false} is VALID [2022-02-21 04:21:56,966 INFO L290 TraceCheckUtils]: 48: Hoare triple {848#false} assume 1 == ~t3_pc~0; {848#false} is VALID [2022-02-21 04:21:56,968 INFO L290 TraceCheckUtils]: 49: Hoare triple {848#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {848#false} is VALID [2022-02-21 04:21:56,969 INFO L290 TraceCheckUtils]: 50: Hoare triple {848#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {848#false} is VALID [2022-02-21 04:21:56,969 INFO L290 TraceCheckUtils]: 51: Hoare triple {848#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {848#false} is VALID [2022-02-21 04:21:56,971 INFO L290 TraceCheckUtils]: 52: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___2~0#1); {848#false} is VALID [2022-02-21 04:21:56,971 INFO L290 TraceCheckUtils]: 53: Hoare triple {848#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {848#false} is VALID [2022-02-21 04:21:56,972 INFO L290 TraceCheckUtils]: 54: Hoare triple {848#false} assume !(1 == ~t4_pc~0); {848#false} is VALID [2022-02-21 04:21:56,972 INFO L290 TraceCheckUtils]: 55: Hoare triple {848#false} is_transmit4_triggered_~__retres1~4#1 := 0; {848#false} is VALID [2022-02-21 04:21:56,972 INFO L290 TraceCheckUtils]: 56: Hoare triple {848#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {848#false} is VALID [2022-02-21 04:21:56,972 INFO L290 TraceCheckUtils]: 57: Hoare triple {848#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {848#false} is VALID [2022-02-21 04:21:56,973 INFO L290 TraceCheckUtils]: 58: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___3~0#1); {848#false} is VALID [2022-02-21 04:21:56,973 INFO L290 TraceCheckUtils]: 59: Hoare triple {848#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {848#false} is VALID [2022-02-21 04:21:56,973 INFO L290 TraceCheckUtils]: 60: Hoare triple {848#false} assume 1 == ~t5_pc~0; {848#false} is VALID [2022-02-21 04:21:56,974 INFO L290 TraceCheckUtils]: 61: Hoare triple {848#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {848#false} is VALID [2022-02-21 04:21:56,974 INFO L290 TraceCheckUtils]: 62: Hoare triple {848#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {848#false} is VALID [2022-02-21 04:21:56,975 INFO L290 TraceCheckUtils]: 63: Hoare triple {848#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {848#false} is VALID [2022-02-21 04:21:56,975 INFO L290 TraceCheckUtils]: 64: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___4~0#1); {848#false} is VALID [2022-02-21 04:21:56,977 INFO L290 TraceCheckUtils]: 65: Hoare triple {848#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {848#false} is VALID [2022-02-21 04:21:56,978 INFO L290 TraceCheckUtils]: 66: Hoare triple {848#false} assume 1 == ~t6_pc~0; {848#false} is VALID [2022-02-21 04:21:56,978 INFO L290 TraceCheckUtils]: 67: Hoare triple {848#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {848#false} is VALID [2022-02-21 04:21:56,978 INFO L290 TraceCheckUtils]: 68: Hoare triple {848#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {848#false} is VALID [2022-02-21 04:21:56,979 INFO L290 TraceCheckUtils]: 69: Hoare triple {848#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {848#false} is VALID [2022-02-21 04:21:56,979 INFO L290 TraceCheckUtils]: 70: Hoare triple {848#false} assume !(0 != activate_threads_~tmp___5~0#1); {848#false} is VALID [2022-02-21 04:21:56,979 INFO L290 TraceCheckUtils]: 71: Hoare triple {848#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {848#false} is VALID [2022-02-21 04:21:56,980 INFO L290 TraceCheckUtils]: 72: Hoare triple {848#false} assume !(1 == ~t7_pc~0); {848#false} is VALID [2022-02-21 04:21:56,980 INFO L290 TraceCheckUtils]: 73: Hoare triple {848#false} is_transmit7_triggered_~__retres1~7#1 := 0; {848#false} is VALID [2022-02-21 04:21:56,985 INFO L290 TraceCheckUtils]: 74: Hoare triple {848#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {848#false} is VALID [2022-02-21 04:21:56,985 INFO L290 TraceCheckUtils]: 75: Hoare triple {848#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {848#false} is VALID [2022-02-21 04:21:56,985 INFO L290 TraceCheckUtils]: 76: Hoare triple {848#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {848#false} is VALID [2022-02-21 04:21:56,985 INFO L290 TraceCheckUtils]: 77: Hoare triple {848#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {848#false} is VALID [2022-02-21 04:21:56,986 INFO L290 TraceCheckUtils]: 78: Hoare triple {848#false} assume !(1 == ~M_E~0); {848#false} is VALID [2022-02-21 04:21:56,986 INFO L290 TraceCheckUtils]: 79: Hoare triple {848#false} assume !(1 == ~T1_E~0); {848#false} is VALID [2022-02-21 04:21:56,986 INFO L290 TraceCheckUtils]: 80: Hoare triple {848#false} assume !(1 == ~T2_E~0); {848#false} is VALID [2022-02-21 04:21:56,986 INFO L290 TraceCheckUtils]: 81: Hoare triple {848#false} assume !(1 == ~T3_E~0); {848#false} is VALID [2022-02-21 04:21:56,986 INFO L290 TraceCheckUtils]: 82: Hoare triple {848#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,987 INFO L290 TraceCheckUtils]: 83: Hoare triple {848#false} assume !(1 == ~T5_E~0); {848#false} is VALID [2022-02-21 04:21:56,987 INFO L290 TraceCheckUtils]: 84: Hoare triple {848#false} assume !(1 == ~T6_E~0); {848#false} is VALID [2022-02-21 04:21:56,987 INFO L290 TraceCheckUtils]: 85: Hoare triple {848#false} assume !(1 == ~T7_E~0); {848#false} is VALID [2022-02-21 04:21:56,988 INFO L290 TraceCheckUtils]: 86: Hoare triple {848#false} assume !(1 == ~E_M~0); {848#false} is VALID [2022-02-21 04:21:56,988 INFO L290 TraceCheckUtils]: 87: Hoare triple {848#false} assume !(1 == ~E_1~0); {848#false} is VALID [2022-02-21 04:21:56,988 INFO L290 TraceCheckUtils]: 88: Hoare triple {848#false} assume !(1 == ~E_2~0); {848#false} is VALID [2022-02-21 04:21:56,988 INFO L290 TraceCheckUtils]: 89: Hoare triple {848#false} assume !(1 == ~E_3~0); {848#false} is VALID [2022-02-21 04:21:56,989 INFO L290 TraceCheckUtils]: 90: Hoare triple {848#false} assume 1 == ~E_4~0;~E_4~0 := 2; {848#false} is VALID [2022-02-21 04:21:56,989 INFO L290 TraceCheckUtils]: 91: Hoare triple {848#false} assume !(1 == ~E_5~0); {848#false} is VALID [2022-02-21 04:21:56,989 INFO L290 TraceCheckUtils]: 92: Hoare triple {848#false} assume !(1 == ~E_6~0); {848#false} is VALID [2022-02-21 04:21:56,989 INFO L290 TraceCheckUtils]: 93: Hoare triple {848#false} assume !(1 == ~E_7~0); {848#false} is VALID [2022-02-21 04:21:56,989 INFO L290 TraceCheckUtils]: 94: Hoare triple {848#false} assume { :end_inline_reset_delta_events } true; {848#false} is VALID [2022-02-21 04:21:56,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:56,991 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:56,992 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2032193283] [2022-02-21 04:21:56,993 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2032193283] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:56,993 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:56,993 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:56,995 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600576636] [2022-02-21 04:21:56,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:56,999 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:57,002 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:57,003 INFO L85 PathProgramCache]: Analyzing trace with hash -432739696, now seen corresponding path program 1 times [2022-02-21 04:21:57,003 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:57,003 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39232338] [2022-02-21 04:21:57,003 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:57,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:57,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:57,068 INFO L290 TraceCheckUtils]: 0: Hoare triple {850#true} assume !false; {850#true} is VALID [2022-02-21 04:21:57,068 INFO L290 TraceCheckUtils]: 1: Hoare triple {850#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {850#true} is VALID [2022-02-21 04:21:57,069 INFO L290 TraceCheckUtils]: 2: Hoare triple {850#true} assume !true; {851#false} is VALID [2022-02-21 04:21:57,069 INFO L290 TraceCheckUtils]: 3: Hoare triple {851#false} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {851#false} is VALID [2022-02-21 04:21:57,070 INFO L290 TraceCheckUtils]: 4: Hoare triple {851#false} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {851#false} is VALID [2022-02-21 04:21:57,070 INFO L290 TraceCheckUtils]: 5: Hoare triple {851#false} assume 0 == ~M_E~0;~M_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,070 INFO L290 TraceCheckUtils]: 6: Hoare triple {851#false} assume !(0 == ~T1_E~0); {851#false} is VALID [2022-02-21 04:21:57,070 INFO L290 TraceCheckUtils]: 7: Hoare triple {851#false} assume 0 == ~T2_E~0;~T2_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,071 INFO L290 TraceCheckUtils]: 8: Hoare triple {851#false} assume 0 == ~T3_E~0;~T3_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,071 INFO L290 TraceCheckUtils]: 9: Hoare triple {851#false} assume 0 == ~T4_E~0;~T4_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,073 INFO L290 TraceCheckUtils]: 10: Hoare triple {851#false} assume 0 == ~T5_E~0;~T5_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,073 INFO L290 TraceCheckUtils]: 11: Hoare triple {851#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,074 INFO L290 TraceCheckUtils]: 12: Hoare triple {851#false} assume 0 == ~T7_E~0;~T7_E~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,074 INFO L290 TraceCheckUtils]: 13: Hoare triple {851#false} assume 0 == ~E_M~0;~E_M~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,074 INFO L290 TraceCheckUtils]: 14: Hoare triple {851#false} assume !(0 == ~E_1~0); {851#false} is VALID [2022-02-21 04:21:57,074 INFO L290 TraceCheckUtils]: 15: Hoare triple {851#false} assume 0 == ~E_2~0;~E_2~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,076 INFO L290 TraceCheckUtils]: 16: Hoare triple {851#false} assume 0 == ~E_3~0;~E_3~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,076 INFO L290 TraceCheckUtils]: 17: Hoare triple {851#false} assume 0 == ~E_4~0;~E_4~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,076 INFO L290 TraceCheckUtils]: 18: Hoare triple {851#false} assume 0 == ~E_5~0;~E_5~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,077 INFO L290 TraceCheckUtils]: 19: Hoare triple {851#false} assume 0 == ~E_6~0;~E_6~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,078 INFO L290 TraceCheckUtils]: 20: Hoare triple {851#false} assume 0 == ~E_7~0;~E_7~0 := 1; {851#false} is VALID [2022-02-21 04:21:57,085 INFO L290 TraceCheckUtils]: 21: Hoare triple {851#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {851#false} is VALID [2022-02-21 04:21:57,086 INFO L290 TraceCheckUtils]: 22: Hoare triple {851#false} assume !(1 == ~m_pc~0); {851#false} is VALID [2022-02-21 04:21:57,086 INFO L290 TraceCheckUtils]: 23: Hoare triple {851#false} is_master_triggered_~__retres1~0#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,087 INFO L290 TraceCheckUtils]: 24: Hoare triple {851#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {851#false} is VALID [2022-02-21 04:21:57,087 INFO L290 TraceCheckUtils]: 25: Hoare triple {851#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {851#false} is VALID [2022-02-21 04:21:57,087 INFO L290 TraceCheckUtils]: 26: Hoare triple {851#false} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,087 INFO L290 TraceCheckUtils]: 27: Hoare triple {851#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {851#false} is VALID [2022-02-21 04:21:57,087 INFO L290 TraceCheckUtils]: 28: Hoare triple {851#false} assume !(1 == ~t1_pc~0); {851#false} is VALID [2022-02-21 04:21:57,088 INFO L290 TraceCheckUtils]: 29: Hoare triple {851#false} is_transmit1_triggered_~__retres1~1#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,088 INFO L290 TraceCheckUtils]: 30: Hoare triple {851#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {851#false} is VALID [2022-02-21 04:21:57,088 INFO L290 TraceCheckUtils]: 31: Hoare triple {851#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {851#false} is VALID [2022-02-21 04:21:57,088 INFO L290 TraceCheckUtils]: 32: Hoare triple {851#false} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,089 INFO L290 TraceCheckUtils]: 33: Hoare triple {851#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {851#false} is VALID [2022-02-21 04:21:57,089 INFO L290 TraceCheckUtils]: 34: Hoare triple {851#false} assume 1 == ~t2_pc~0; {851#false} is VALID [2022-02-21 04:21:57,089 INFO L290 TraceCheckUtils]: 35: Hoare triple {851#false} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {851#false} is VALID [2022-02-21 04:21:57,089 INFO L290 TraceCheckUtils]: 36: Hoare triple {851#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {851#false} is VALID [2022-02-21 04:21:57,089 INFO L290 TraceCheckUtils]: 37: Hoare triple {851#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {851#false} is VALID [2022-02-21 04:21:57,090 INFO L290 TraceCheckUtils]: 38: Hoare triple {851#false} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,090 INFO L290 TraceCheckUtils]: 39: Hoare triple {851#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {851#false} is VALID [2022-02-21 04:21:57,093 INFO L290 TraceCheckUtils]: 40: Hoare triple {851#false} assume 1 == ~t3_pc~0; {851#false} is VALID [2022-02-21 04:21:57,094 INFO L290 TraceCheckUtils]: 41: Hoare triple {851#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {851#false} is VALID [2022-02-21 04:21:57,094 INFO L290 TraceCheckUtils]: 42: Hoare triple {851#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {851#false} is VALID [2022-02-21 04:21:57,094 INFO L290 TraceCheckUtils]: 43: Hoare triple {851#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {851#false} is VALID [2022-02-21 04:21:57,094 INFO L290 TraceCheckUtils]: 44: Hoare triple {851#false} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,095 INFO L290 TraceCheckUtils]: 45: Hoare triple {851#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {851#false} is VALID [2022-02-21 04:21:57,095 INFO L290 TraceCheckUtils]: 46: Hoare triple {851#false} assume !(1 == ~t4_pc~0); {851#false} is VALID [2022-02-21 04:21:57,095 INFO L290 TraceCheckUtils]: 47: Hoare triple {851#false} is_transmit4_triggered_~__retres1~4#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,095 INFO L290 TraceCheckUtils]: 48: Hoare triple {851#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {851#false} is VALID [2022-02-21 04:21:57,095 INFO L290 TraceCheckUtils]: 49: Hoare triple {851#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {851#false} is VALID [2022-02-21 04:21:57,096 INFO L290 TraceCheckUtils]: 50: Hoare triple {851#false} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,096 INFO L290 TraceCheckUtils]: 51: Hoare triple {851#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {851#false} is VALID [2022-02-21 04:21:57,096 INFO L290 TraceCheckUtils]: 52: Hoare triple {851#false} assume !(1 == ~t5_pc~0); {851#false} is VALID [2022-02-21 04:21:57,096 INFO L290 TraceCheckUtils]: 53: Hoare triple {851#false} is_transmit5_triggered_~__retres1~5#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,097 INFO L290 TraceCheckUtils]: 54: Hoare triple {851#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {851#false} is VALID [2022-02-21 04:21:57,097 INFO L290 TraceCheckUtils]: 55: Hoare triple {851#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {851#false} is VALID [2022-02-21 04:21:57,097 INFO L290 TraceCheckUtils]: 56: Hoare triple {851#false} assume !(0 != activate_threads_~tmp___4~0#1); {851#false} is VALID [2022-02-21 04:21:57,097 INFO L290 TraceCheckUtils]: 57: Hoare triple {851#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {851#false} is VALID [2022-02-21 04:21:57,097 INFO L290 TraceCheckUtils]: 58: Hoare triple {851#false} assume !(1 == ~t6_pc~0); {851#false} is VALID [2022-02-21 04:21:57,098 INFO L290 TraceCheckUtils]: 59: Hoare triple {851#false} is_transmit6_triggered_~__retres1~6#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,098 INFO L290 TraceCheckUtils]: 60: Hoare triple {851#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {851#false} is VALID [2022-02-21 04:21:57,098 INFO L290 TraceCheckUtils]: 61: Hoare triple {851#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {851#false} is VALID [2022-02-21 04:21:57,098 INFO L290 TraceCheckUtils]: 62: Hoare triple {851#false} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,098 INFO L290 TraceCheckUtils]: 63: Hoare triple {851#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {851#false} is VALID [2022-02-21 04:21:57,099 INFO L290 TraceCheckUtils]: 64: Hoare triple {851#false} assume 1 == ~t7_pc~0; {851#false} is VALID [2022-02-21 04:21:57,099 INFO L290 TraceCheckUtils]: 65: Hoare triple {851#false} assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; {851#false} is VALID [2022-02-21 04:21:57,099 INFO L290 TraceCheckUtils]: 66: Hoare triple {851#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {851#false} is VALID [2022-02-21 04:21:57,099 INFO L290 TraceCheckUtils]: 67: Hoare triple {851#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {851#false} is VALID [2022-02-21 04:21:57,099 INFO L290 TraceCheckUtils]: 68: Hoare triple {851#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {851#false} is VALID [2022-02-21 04:21:57,100 INFO L290 TraceCheckUtils]: 69: Hoare triple {851#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {851#false} is VALID [2022-02-21 04:21:57,100 INFO L290 TraceCheckUtils]: 70: Hoare triple {851#false} assume 1 == ~M_E~0;~M_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,100 INFO L290 TraceCheckUtils]: 71: Hoare triple {851#false} assume 1 == ~T1_E~0;~T1_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,100 INFO L290 TraceCheckUtils]: 72: Hoare triple {851#false} assume 1 == ~T2_E~0;~T2_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,100 INFO L290 TraceCheckUtils]: 73: Hoare triple {851#false} assume 1 == ~T3_E~0;~T3_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,101 INFO L290 TraceCheckUtils]: 74: Hoare triple {851#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,101 INFO L290 TraceCheckUtils]: 75: Hoare triple {851#false} assume 1 == ~T5_E~0;~T5_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,101 INFO L290 TraceCheckUtils]: 76: Hoare triple {851#false} assume 1 == ~T6_E~0;~T6_E~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,101 INFO L290 TraceCheckUtils]: 77: Hoare triple {851#false} assume !(1 == ~T7_E~0); {851#false} is VALID [2022-02-21 04:21:57,102 INFO L290 TraceCheckUtils]: 78: Hoare triple {851#false} assume 1 == ~E_M~0;~E_M~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,102 INFO L290 TraceCheckUtils]: 79: Hoare triple {851#false} assume 1 == ~E_1~0;~E_1~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,102 INFO L290 TraceCheckUtils]: 80: Hoare triple {851#false} assume 1 == ~E_2~0;~E_2~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,105 INFO L290 TraceCheckUtils]: 81: Hoare triple {851#false} assume 1 == ~E_3~0;~E_3~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,105 INFO L290 TraceCheckUtils]: 82: Hoare triple {851#false} assume 1 == ~E_4~0;~E_4~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,105 INFO L290 TraceCheckUtils]: 83: Hoare triple {851#false} assume 1 == ~E_5~0;~E_5~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,106 INFO L290 TraceCheckUtils]: 84: Hoare triple {851#false} assume 1 == ~E_6~0;~E_6~0 := 2; {851#false} is VALID [2022-02-21 04:21:57,106 INFO L290 TraceCheckUtils]: 85: Hoare triple {851#false} assume !(1 == ~E_7~0); {851#false} is VALID [2022-02-21 04:21:57,106 INFO L290 TraceCheckUtils]: 86: Hoare triple {851#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {851#false} is VALID [2022-02-21 04:21:57,106 INFO L290 TraceCheckUtils]: 87: Hoare triple {851#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {851#false} is VALID [2022-02-21 04:21:57,107 INFO L290 TraceCheckUtils]: 88: Hoare triple {851#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {851#false} is VALID [2022-02-21 04:21:57,107 INFO L290 TraceCheckUtils]: 89: Hoare triple {851#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {851#false} is VALID [2022-02-21 04:21:57,108 INFO L290 TraceCheckUtils]: 90: Hoare triple {851#false} assume !(0 == start_simulation_~tmp~3#1); {851#false} is VALID [2022-02-21 04:21:57,109 INFO L290 TraceCheckUtils]: 91: Hoare triple {851#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {851#false} is VALID [2022-02-21 04:21:57,109 INFO L290 TraceCheckUtils]: 92: Hoare triple {851#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {851#false} is VALID [2022-02-21 04:21:57,109 INFO L290 TraceCheckUtils]: 93: Hoare triple {851#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {851#false} is VALID [2022-02-21 04:21:57,110 INFO L290 TraceCheckUtils]: 94: Hoare triple {851#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {851#false} is VALID [2022-02-21 04:21:57,110 INFO L290 TraceCheckUtils]: 95: Hoare triple {851#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {851#false} is VALID [2022-02-21 04:21:57,110 INFO L290 TraceCheckUtils]: 96: Hoare triple {851#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {851#false} is VALID [2022-02-21 04:21:57,111 INFO L290 TraceCheckUtils]: 97: Hoare triple {851#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {851#false} is VALID [2022-02-21 04:21:57,111 INFO L290 TraceCheckUtils]: 98: Hoare triple {851#false} assume !(0 != start_simulation_~tmp___0~1#1); {851#false} is VALID [2022-02-21 04:21:57,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:57,112 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:57,113 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [39232338] [2022-02-21 04:21:57,113 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [39232338] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:57,113 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:57,113 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-02-21 04:21:57,114 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275299551] [2022-02-21 04:21:57,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:57,115 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:57,116 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:57,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:57,142 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:57,146 INFO L87 Difference]: Start difference. First operand has 843 states, 842 states have (on average 1.520190023752969) internal successors, (1280), 842 states have internal predecessors, (1280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,095 INFO L93 Difference]: Finished difference Result 841 states and 1255 transitions. [2022-02-21 04:21:58,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:58,096 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,181 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:58,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 841 states and 1255 transitions. [2022-02-21 04:21:58,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:21:58,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 841 states to 835 states and 1249 transitions. [2022-02-21 04:21:58,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:21:58,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:21:58,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1249 transitions. [2022-02-21 04:21:58,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:58,284 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-02-21 04:21:58,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1249 transitions. [2022-02-21 04:21:58,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:21:58,340 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:58,345 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1249 transitions. Second operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,348 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1249 transitions. Second operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,352 INFO L87 Difference]: Start difference. First operand 835 states and 1249 transitions. Second operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,393 INFO L93 Difference]: Finished difference Result 835 states and 1249 transitions. [2022-02-21 04:21:58,394 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1249 transitions. [2022-02-21 04:21:58,397 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,398 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,400 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1249 transitions. [2022-02-21 04:21:58,402 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1249 transitions. [2022-02-21 04:21:58,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:58,434 INFO L93 Difference]: Finished difference Result 835 states and 1249 transitions. [2022-02-21 04:21:58,434 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1249 transitions. [2022-02-21 04:21:58,436 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:58,436 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:58,436 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:58,436 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:58,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.495808383233533) internal successors, (1249), 834 states have internal predecessors, (1249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:58,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1249 transitions. [2022-02-21 04:21:58,472 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-02-21 04:21:58,472 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1249 transitions. [2022-02-21 04:21:58,472 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2022-02-21 04:21:58,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1249 transitions. [2022-02-21 04:21:58,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:21:58,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:58,478 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:58,480 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,480 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:58,480 INFO L791 eck$LassoCheckResult]: Stem: 2328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2329#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1782#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1783#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2503#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 2078#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2079#L553-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2198#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2199#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1991#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1778#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1779#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1948#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1949#L781 assume !(0 == ~M_E~0); 2403#L781-2 assume !(0 == ~T1_E~0); 2526#L786-1 assume !(0 == ~T2_E~0); 1739#L791-1 assume !(0 == ~T3_E~0); 1740#L796-1 assume !(0 == ~T4_E~0); 2265#L801-1 assume !(0 == ~T5_E~0); 2266#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2292#L811-1 assume !(0 == ~T7_E~0); 1957#L816-1 assume !(0 == ~E_M~0); 1958#L821-1 assume !(0 == ~E_1~0); 1767#L826-1 assume !(0 == ~E_2~0); 1768#L831-1 assume !(0 == ~E_3~0); 2075#L836-1 assume !(0 == ~E_4~0); 2076#L841-1 assume !(0 == ~E_5~0); 1910#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 1911#L851-1 assume !(0 == ~E_7~0); 1933#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1934#L388 assume !(1 == ~m_pc~0); 1927#L388-2 is_master_triggered_~__retres1~0#1 := 0; 1928#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2376#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1786#L967 assume !(0 != activate_threads_~tmp~1#1); 1787#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1714#L407 assume 1 == ~t1_pc~0; 1715#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1719#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1693#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1694#L975 assume !(0 != activate_threads_~tmp___0~0#1); 2474#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2037#L426 assume !(1 == ~t2_pc~0); 2038#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2489#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2518#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2516#L983 assume !(0 != activate_threads_~tmp___1~0#1); 2517#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2117#L445 assume 1 == ~t3_pc~0; 2118#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2407#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1929#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1930#L991 assume !(0 != activate_threads_~tmp___2~0#1); 2344#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2315#L464 assume !(1 == ~t4_pc~0); 1936#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1807#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1808#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2128#L999 assume !(0 != activate_threads_~tmp___3~0#1); 2093#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2094#L483 assume 1 == ~t5_pc~0; 2312#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2454#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2247#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2248#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 2021#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2022#L502 assume 1 == ~t6_pc~0; 2289#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1838#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1839#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2231#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 2232#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2431#L521 assume !(1 == ~t7_pc~0); 2470#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1780#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1781#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1888#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2438#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2365#L869 assume !(1 == ~M_E~0); 2086#L869-2 assume !(1 == ~T1_E~0); 2087#L874-1 assume !(1 == ~T2_E~0); 2499#L879-1 assume !(1 == ~T3_E~0); 2167#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1702#L889-1 assume !(1 == ~T5_E~0); 1703#L894-1 assume !(1 == ~T6_E~0); 1964#L899-1 assume !(1 == ~T7_E~0); 2332#L904-1 assume !(1 == ~E_M~0); 2109#L909-1 assume !(1 == ~E_1~0); 2110#L914-1 assume !(1 == ~E_2~0); 2279#L919-1 assume !(1 == ~E_3~0); 2036#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1876#L929-1 assume !(1 == ~E_5~0); 1877#L934-1 assume !(1 == ~E_6~0); 2089#L939-1 assume !(1 == ~E_7~0); 2090#L944-1 assume { :end_inline_reset_delta_events } true; 1946#L1190-2 [2022-02-21 04:21:58,481 INFO L793 eck$LassoCheckResult]: Loop: 1946#L1190-2 assume !false; 1959#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1960#L756 assume !false; 2182#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2522#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1800#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2308#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2131#L653 assume !(0 != eval_~tmp~0#1); 2133#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2173#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2174#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1819#L781-5 assume !(0 == ~T1_E~0); 1820#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2140#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1763#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1764#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2023#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2024#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2206#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2393#L821-3 assume !(0 == ~E_1~0); 2490#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2339#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2340#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1920#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1921#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2230#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1814#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1815#L388-27 assume 1 == ~m_pc~0; 2465#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2467#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2436#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2437#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1994#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1995#L407-27 assume 1 == ~t1_pc~0; 2345#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2346#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2218#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2219#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2250#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1914#L426-27 assume !(1 == ~t2_pc~0); 1915#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1925#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1926#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2450#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2463#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2201#L445-27 assume 1 == ~t3_pc~0; 2179#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1760#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1761#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2181#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2284#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2015#L464-27 assume 1 == ~t4_pc~0; 2016#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1759#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1826#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2207#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1906#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1907#L483-27 assume 1 == ~t5_pc~0; 2412#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1816#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1817#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2426#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 2427#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2506#L502-27 assume !(1 == ~t6_pc~0); 2226#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2227#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2476#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2362#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2363#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1704#L521-27 assume !(1 == ~t7_pc~0); 1705#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2047#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2194#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1754#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1755#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2242#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2359#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2138#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2139#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2197#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2193#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1864#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1865#L899-3 assume !(1 == ~T7_E~0); 1892#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1893#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1840#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1841#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1884#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2351#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2280#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2281#L939-3 assume !(1 == ~E_7~0); 1899#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1900#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1721#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2147#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2148#L1209 assume !(0 == start_simulation_~tmp~3#1); 2222#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2205#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1857#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2253#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2254#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1748#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1749#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1945#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 1946#L1190-2 [2022-02-21 04:21:58,482 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,482 INFO L85 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2022-02-21 04:21:58,482 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,482 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598519986] [2022-02-21 04:21:58,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,528 INFO L290 TraceCheckUtils]: 0: Hoare triple {4201#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {4201#true} is VALID [2022-02-21 04:21:58,529 INFO L290 TraceCheckUtils]: 1: Hoare triple {4201#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {4203#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:58,529 INFO L290 TraceCheckUtils]: 2: Hoare triple {4203#(= ~t2_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {4203#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:58,530 INFO L290 TraceCheckUtils]: 3: Hoare triple {4203#(= ~t2_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {4203#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:58,530 INFO L290 TraceCheckUtils]: 4: Hoare triple {4203#(= ~t2_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {4203#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:58,531 INFO L290 TraceCheckUtils]: 5: Hoare triple {4203#(= ~t2_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {4203#(= ~t2_i~0 1)} is VALID [2022-02-21 04:21:58,531 INFO L290 TraceCheckUtils]: 6: Hoare triple {4203#(= ~t2_i~0 1)} assume !(1 == ~t2_i~0);~t2_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,531 INFO L290 TraceCheckUtils]: 7: Hoare triple {4202#false} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,532 INFO L290 TraceCheckUtils]: 8: Hoare triple {4202#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,532 INFO L290 TraceCheckUtils]: 9: Hoare triple {4202#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,532 INFO L290 TraceCheckUtils]: 10: Hoare triple {4202#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,532 INFO L290 TraceCheckUtils]: 11: Hoare triple {4202#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,532 INFO L290 TraceCheckUtils]: 12: Hoare triple {4202#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 13: Hoare triple {4202#false} assume !(0 == ~M_E~0); {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 14: Hoare triple {4202#false} assume !(0 == ~T1_E~0); {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 15: Hoare triple {4202#false} assume !(0 == ~T2_E~0); {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 16: Hoare triple {4202#false} assume !(0 == ~T3_E~0); {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 17: Hoare triple {4202#false} assume !(0 == ~T4_E~0); {4202#false} is VALID [2022-02-21 04:21:58,533 INFO L290 TraceCheckUtils]: 18: Hoare triple {4202#false} assume !(0 == ~T5_E~0); {4202#false} is VALID [2022-02-21 04:21:58,534 INFO L290 TraceCheckUtils]: 19: Hoare triple {4202#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4202#false} is VALID [2022-02-21 04:21:58,534 INFO L290 TraceCheckUtils]: 20: Hoare triple {4202#false} assume !(0 == ~T7_E~0); {4202#false} is VALID [2022-02-21 04:21:58,534 INFO L290 TraceCheckUtils]: 21: Hoare triple {4202#false} assume !(0 == ~E_M~0); {4202#false} is VALID [2022-02-21 04:21:58,534 INFO L290 TraceCheckUtils]: 22: Hoare triple {4202#false} assume !(0 == ~E_1~0); {4202#false} is VALID [2022-02-21 04:21:58,534 INFO L290 TraceCheckUtils]: 23: Hoare triple {4202#false} assume !(0 == ~E_2~0); {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 24: Hoare triple {4202#false} assume !(0 == ~E_3~0); {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 25: Hoare triple {4202#false} assume !(0 == ~E_4~0); {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 26: Hoare triple {4202#false} assume !(0 == ~E_5~0); {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 27: Hoare triple {4202#false} assume 0 == ~E_6~0;~E_6~0 := 1; {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 28: Hoare triple {4202#false} assume !(0 == ~E_7~0); {4202#false} is VALID [2022-02-21 04:21:58,535 INFO L290 TraceCheckUtils]: 29: Hoare triple {4202#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4202#false} is VALID [2022-02-21 04:21:58,536 INFO L290 TraceCheckUtils]: 30: Hoare triple {4202#false} assume !(1 == ~m_pc~0); {4202#false} is VALID [2022-02-21 04:21:58,536 INFO L290 TraceCheckUtils]: 31: Hoare triple {4202#false} is_master_triggered_~__retres1~0#1 := 0; {4202#false} is VALID [2022-02-21 04:21:58,536 INFO L290 TraceCheckUtils]: 32: Hoare triple {4202#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4202#false} is VALID [2022-02-21 04:21:58,536 INFO L290 TraceCheckUtils]: 33: Hoare triple {4202#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4202#false} is VALID [2022-02-21 04:21:58,536 INFO L290 TraceCheckUtils]: 34: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp~1#1); {4202#false} is VALID [2022-02-21 04:21:58,537 INFO L290 TraceCheckUtils]: 35: Hoare triple {4202#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4202#false} is VALID [2022-02-21 04:21:58,537 INFO L290 TraceCheckUtils]: 36: Hoare triple {4202#false} assume 1 == ~t1_pc~0; {4202#false} is VALID [2022-02-21 04:21:58,537 INFO L290 TraceCheckUtils]: 37: Hoare triple {4202#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4202#false} is VALID [2022-02-21 04:21:58,537 INFO L290 TraceCheckUtils]: 38: Hoare triple {4202#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4202#false} is VALID [2022-02-21 04:21:58,537 INFO L290 TraceCheckUtils]: 39: Hoare triple {4202#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 40: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___0~0#1); {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 41: Hoare triple {4202#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 42: Hoare triple {4202#false} assume !(1 == ~t2_pc~0); {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 43: Hoare triple {4202#false} is_transmit2_triggered_~__retres1~2#1 := 0; {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 44: Hoare triple {4202#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4202#false} is VALID [2022-02-21 04:21:58,538 INFO L290 TraceCheckUtils]: 45: Hoare triple {4202#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4202#false} is VALID [2022-02-21 04:21:58,539 INFO L290 TraceCheckUtils]: 46: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___1~0#1); {4202#false} is VALID [2022-02-21 04:21:58,539 INFO L290 TraceCheckUtils]: 47: Hoare triple {4202#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4202#false} is VALID [2022-02-21 04:21:58,539 INFO L290 TraceCheckUtils]: 48: Hoare triple {4202#false} assume 1 == ~t3_pc~0; {4202#false} is VALID [2022-02-21 04:21:58,539 INFO L290 TraceCheckUtils]: 49: Hoare triple {4202#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4202#false} is VALID [2022-02-21 04:21:58,539 INFO L290 TraceCheckUtils]: 50: Hoare triple {4202#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 51: Hoare triple {4202#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 52: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___2~0#1); {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 53: Hoare triple {4202#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 54: Hoare triple {4202#false} assume !(1 == ~t4_pc~0); {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 55: Hoare triple {4202#false} is_transmit4_triggered_~__retres1~4#1 := 0; {4202#false} is VALID [2022-02-21 04:21:58,540 INFO L290 TraceCheckUtils]: 56: Hoare triple {4202#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 57: Hoare triple {4202#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 58: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___3~0#1); {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 59: Hoare triple {4202#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 60: Hoare triple {4202#false} assume 1 == ~t5_pc~0; {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 61: Hoare triple {4202#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4202#false} is VALID [2022-02-21 04:21:58,541 INFO L290 TraceCheckUtils]: 62: Hoare triple {4202#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4202#false} is VALID [2022-02-21 04:21:58,542 INFO L290 TraceCheckUtils]: 63: Hoare triple {4202#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4202#false} is VALID [2022-02-21 04:21:58,542 INFO L290 TraceCheckUtils]: 64: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___4~0#1); {4202#false} is VALID [2022-02-21 04:21:58,542 INFO L290 TraceCheckUtils]: 65: Hoare triple {4202#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4202#false} is VALID [2022-02-21 04:21:58,542 INFO L290 TraceCheckUtils]: 66: Hoare triple {4202#false} assume 1 == ~t6_pc~0; {4202#false} is VALID [2022-02-21 04:21:58,542 INFO L290 TraceCheckUtils]: 67: Hoare triple {4202#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {4202#false} is VALID [2022-02-21 04:21:58,543 INFO L290 TraceCheckUtils]: 68: Hoare triple {4202#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4202#false} is VALID [2022-02-21 04:21:58,543 INFO L290 TraceCheckUtils]: 69: Hoare triple {4202#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4202#false} is VALID [2022-02-21 04:21:58,543 INFO L290 TraceCheckUtils]: 70: Hoare triple {4202#false} assume !(0 != activate_threads_~tmp___5~0#1); {4202#false} is VALID [2022-02-21 04:21:58,544 INFO L290 TraceCheckUtils]: 71: Hoare triple {4202#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4202#false} is VALID [2022-02-21 04:21:58,544 INFO L290 TraceCheckUtils]: 72: Hoare triple {4202#false} assume !(1 == ~t7_pc~0); {4202#false} is VALID [2022-02-21 04:21:58,545 INFO L290 TraceCheckUtils]: 73: Hoare triple {4202#false} is_transmit7_triggered_~__retres1~7#1 := 0; {4202#false} is VALID [2022-02-21 04:21:58,545 INFO L290 TraceCheckUtils]: 74: Hoare triple {4202#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4202#false} is VALID [2022-02-21 04:21:58,545 INFO L290 TraceCheckUtils]: 75: Hoare triple {4202#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4202#false} is VALID [2022-02-21 04:21:58,545 INFO L290 TraceCheckUtils]: 76: Hoare triple {4202#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4202#false} is VALID [2022-02-21 04:21:58,545 INFO L290 TraceCheckUtils]: 77: Hoare triple {4202#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4202#false} is VALID [2022-02-21 04:21:58,546 INFO L290 TraceCheckUtils]: 78: Hoare triple {4202#false} assume !(1 == ~M_E~0); {4202#false} is VALID [2022-02-21 04:21:58,546 INFO L290 TraceCheckUtils]: 79: Hoare triple {4202#false} assume !(1 == ~T1_E~0); {4202#false} is VALID [2022-02-21 04:21:58,546 INFO L290 TraceCheckUtils]: 80: Hoare triple {4202#false} assume !(1 == ~T2_E~0); {4202#false} is VALID [2022-02-21 04:21:58,546 INFO L290 TraceCheckUtils]: 81: Hoare triple {4202#false} assume !(1 == ~T3_E~0); {4202#false} is VALID [2022-02-21 04:21:58,546 INFO L290 TraceCheckUtils]: 82: Hoare triple {4202#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,547 INFO L290 TraceCheckUtils]: 83: Hoare triple {4202#false} assume !(1 == ~T5_E~0); {4202#false} is VALID [2022-02-21 04:21:58,547 INFO L290 TraceCheckUtils]: 84: Hoare triple {4202#false} assume !(1 == ~T6_E~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 85: Hoare triple {4202#false} assume !(1 == ~T7_E~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 86: Hoare triple {4202#false} assume !(1 == ~E_M~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 87: Hoare triple {4202#false} assume !(1 == ~E_1~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 88: Hoare triple {4202#false} assume !(1 == ~E_2~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 89: Hoare triple {4202#false} assume !(1 == ~E_3~0); {4202#false} is VALID [2022-02-21 04:21:58,548 INFO L290 TraceCheckUtils]: 90: Hoare triple {4202#false} assume 1 == ~E_4~0;~E_4~0 := 2; {4202#false} is VALID [2022-02-21 04:21:58,549 INFO L290 TraceCheckUtils]: 91: Hoare triple {4202#false} assume !(1 == ~E_5~0); {4202#false} is VALID [2022-02-21 04:21:58,549 INFO L290 TraceCheckUtils]: 92: Hoare triple {4202#false} assume !(1 == ~E_6~0); {4202#false} is VALID [2022-02-21 04:21:58,549 INFO L290 TraceCheckUtils]: 93: Hoare triple {4202#false} assume !(1 == ~E_7~0); {4202#false} is VALID [2022-02-21 04:21:58,549 INFO L290 TraceCheckUtils]: 94: Hoare triple {4202#false} assume { :end_inline_reset_delta_events } true; {4202#false} is VALID [2022-02-21 04:21:58,550 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,551 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,552 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598519986] [2022-02-21 04:21:58,552 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598519986] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,552 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,552 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,552 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507720586] [2022-02-21 04:21:58,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,553 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:58,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:58,555 INFO L85 PathProgramCache]: Analyzing trace with hash -350291807, now seen corresponding path program 1 times [2022-02-21 04:21:58,555 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:58,556 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944168559] [2022-02-21 04:21:58,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:58,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:58,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:58,635 INFO L290 TraceCheckUtils]: 0: Hoare triple {4204#true} assume !false; {4204#true} is VALID [2022-02-21 04:21:58,636 INFO L290 TraceCheckUtils]: 1: Hoare triple {4204#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {4204#true} is VALID [2022-02-21 04:21:58,636 INFO L290 TraceCheckUtils]: 2: Hoare triple {4204#true} assume !false; {4204#true} is VALID [2022-02-21 04:21:58,636 INFO L290 TraceCheckUtils]: 3: Hoare triple {4204#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4204#true} is VALID [2022-02-21 04:21:58,636 INFO L290 TraceCheckUtils]: 4: Hoare triple {4204#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4204#true} is VALID [2022-02-21 04:21:58,636 INFO L290 TraceCheckUtils]: 5: Hoare triple {4204#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 6: Hoare triple {4204#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 7: Hoare triple {4204#true} assume !(0 != eval_~tmp~0#1); {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 8: Hoare triple {4204#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 9: Hoare triple {4204#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 10: Hoare triple {4204#true} assume 0 == ~M_E~0;~M_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,637 INFO L290 TraceCheckUtils]: 11: Hoare triple {4204#true} assume !(0 == ~T1_E~0); {4204#true} is VALID [2022-02-21 04:21:58,638 INFO L290 TraceCheckUtils]: 12: Hoare triple {4204#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,638 INFO L290 TraceCheckUtils]: 13: Hoare triple {4204#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,638 INFO L290 TraceCheckUtils]: 14: Hoare triple {4204#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,638 INFO L290 TraceCheckUtils]: 15: Hoare triple {4204#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,638 INFO L290 TraceCheckUtils]: 16: Hoare triple {4204#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {4204#true} is VALID [2022-02-21 04:21:58,639 INFO L290 TraceCheckUtils]: 17: Hoare triple {4204#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,639 INFO L290 TraceCheckUtils]: 18: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,640 INFO L290 TraceCheckUtils]: 19: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,640 INFO L290 TraceCheckUtils]: 20: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,640 INFO L290 TraceCheckUtils]: 21: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,641 INFO L290 TraceCheckUtils]: 22: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,641 INFO L290 TraceCheckUtils]: 23: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,641 INFO L290 TraceCheckUtils]: 24: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,642 INFO L290 TraceCheckUtils]: 25: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,642 INFO L290 TraceCheckUtils]: 26: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,643 INFO L290 TraceCheckUtils]: 27: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,643 INFO L290 TraceCheckUtils]: 28: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,643 INFO L290 TraceCheckUtils]: 29: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,644 INFO L290 TraceCheckUtils]: 30: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,644 INFO L290 TraceCheckUtils]: 31: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,644 INFO L290 TraceCheckUtils]: 32: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,645 INFO L290 TraceCheckUtils]: 33: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,645 INFO L290 TraceCheckUtils]: 34: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,645 INFO L290 TraceCheckUtils]: 35: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,646 INFO L290 TraceCheckUtils]: 36: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,646 INFO L290 TraceCheckUtils]: 37: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,647 INFO L290 TraceCheckUtils]: 38: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,647 INFO L290 TraceCheckUtils]: 39: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,647 INFO L290 TraceCheckUtils]: 40: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,648 INFO L290 TraceCheckUtils]: 41: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,648 INFO L290 TraceCheckUtils]: 42: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,648 INFO L290 TraceCheckUtils]: 43: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,649 INFO L290 TraceCheckUtils]: 44: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,649 INFO L290 TraceCheckUtils]: 45: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,650 INFO L290 TraceCheckUtils]: 46: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,650 INFO L290 TraceCheckUtils]: 47: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,650 INFO L290 TraceCheckUtils]: 48: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,651 INFO L290 TraceCheckUtils]: 49: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,651 INFO L290 TraceCheckUtils]: 50: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,651 INFO L290 TraceCheckUtils]: 51: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,652 INFO L290 TraceCheckUtils]: 52: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,652 INFO L290 TraceCheckUtils]: 53: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,652 INFO L290 TraceCheckUtils]: 54: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,653 INFO L290 TraceCheckUtils]: 55: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,653 INFO L290 TraceCheckUtils]: 56: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,654 INFO L290 TraceCheckUtils]: 57: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,654 INFO L290 TraceCheckUtils]: 58: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,654 INFO L290 TraceCheckUtils]: 59: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,655 INFO L290 TraceCheckUtils]: 60: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,655 INFO L290 TraceCheckUtils]: 61: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,655 INFO L290 TraceCheckUtils]: 62: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,656 INFO L290 TraceCheckUtils]: 63: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,656 INFO L290 TraceCheckUtils]: 64: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,656 INFO L290 TraceCheckUtils]: 65: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,657 INFO L290 TraceCheckUtils]: 66: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,657 INFO L290 TraceCheckUtils]: 67: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,658 INFO L290 TraceCheckUtils]: 68: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,658 INFO L290 TraceCheckUtils]: 69: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,658 INFO L290 TraceCheckUtils]: 70: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,659 INFO L290 TraceCheckUtils]: 71: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,659 INFO L290 TraceCheckUtils]: 72: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,659 INFO L290 TraceCheckUtils]: 73: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,660 INFO L290 TraceCheckUtils]: 74: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,660 INFO L290 TraceCheckUtils]: 75: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,661 INFO L290 TraceCheckUtils]: 76: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,661 INFO L290 TraceCheckUtils]: 77: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,661 INFO L290 TraceCheckUtils]: 78: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,662 INFO L290 TraceCheckUtils]: 79: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,662 INFO L290 TraceCheckUtils]: 80: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,662 INFO L290 TraceCheckUtils]: 81: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {4206#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:58,663 INFO L290 TraceCheckUtils]: 82: Hoare triple {4206#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {4205#false} is VALID [2022-02-21 04:21:58,663 INFO L290 TraceCheckUtils]: 83: Hoare triple {4205#false} assume 1 == ~E_M~0;~E_M~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,663 INFO L290 TraceCheckUtils]: 84: Hoare triple {4205#false} assume 1 == ~E_1~0;~E_1~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,663 INFO L290 TraceCheckUtils]: 85: Hoare triple {4205#false} assume 1 == ~E_2~0;~E_2~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 86: Hoare triple {4205#false} assume 1 == ~E_3~0;~E_3~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 87: Hoare triple {4205#false} assume 1 == ~E_4~0;~E_4~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 88: Hoare triple {4205#false} assume 1 == ~E_5~0;~E_5~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 89: Hoare triple {4205#false} assume 1 == ~E_6~0;~E_6~0 := 2; {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 90: Hoare triple {4205#false} assume !(1 == ~E_7~0); {4205#false} is VALID [2022-02-21 04:21:58,664 INFO L290 TraceCheckUtils]: 91: Hoare triple {4205#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 92: Hoare triple {4205#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 93: Hoare triple {4205#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 94: Hoare triple {4205#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 95: Hoare triple {4205#false} assume !(0 == start_simulation_~tmp~3#1); {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 96: Hoare triple {4205#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {4205#false} is VALID [2022-02-21 04:21:58,665 INFO L290 TraceCheckUtils]: 97: Hoare triple {4205#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 98: Hoare triple {4205#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 99: Hoare triple {4205#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 100: Hoare triple {4205#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 101: Hoare triple {4205#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 102: Hoare triple {4205#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {4205#false} is VALID [2022-02-21 04:21:58,666 INFO L290 TraceCheckUtils]: 103: Hoare triple {4205#false} assume !(0 != start_simulation_~tmp___0~1#1); {4205#false} is VALID [2022-02-21 04:21:58,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:58,667 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:58,668 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944168559] [2022-02-21 04:21:58,668 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944168559] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:58,668 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:58,668 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:58,668 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514206838] [2022-02-21 04:21:58,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:58,669 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:58,669 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:58,670 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:58,670 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:58,670 INFO L87 Difference]: Start difference. First operand 835 states and 1249 transitions. cyclomatic complexity: 415 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,451 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2022-02-21 04:21:59,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:21:59,451 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,522 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:21:59,523 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:21:59,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1248 transitions. [2022-02-21 04:21:59,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:21:59,589 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:21:59,589 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:21:59,590 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-02-21 04:21:59,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:21:59,627 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:21:59,629 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1248 transitions. Second operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,631 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1248 transitions. Second operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,632 INFO L87 Difference]: Start difference. First operand 835 states and 1248 transitions. Second operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,660 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2022-02-21 04:21:59,660 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,661 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,661 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,663 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1248 transitions. [2022-02-21 04:21:59,665 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1248 transitions. [2022-02-21 04:21:59,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:21:59,693 INFO L93 Difference]: Finished difference Result 835 states and 1248 transitions. [2022-02-21 04:21:59,693 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,694 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:21:59,694 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:21:59,694 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:21:59,694 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:21:59,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4946107784431137) internal successors, (1248), 834 states have internal predecessors, (1248), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:21:59,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1248 transitions. [2022-02-21 04:21:59,724 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-02-21 04:21:59,724 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1248 transitions. [2022-02-21 04:21:59,724 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2022-02-21 04:21:59,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1248 transitions. [2022-02-21 04:21:59,728 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:21:59,728 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:21:59,728 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:21:59,730 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,730 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:21:59,730 INFO L791 eck$LassoCheckResult]: Stem: 5677#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5678#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5131#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5132#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5852#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 5427#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5428#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5547#L558-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5548#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5340#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5127#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5128#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5297#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5298#L781 assume !(0 == ~M_E~0); 5752#L781-2 assume !(0 == ~T1_E~0); 5875#L786-1 assume !(0 == ~T2_E~0); 5088#L791-1 assume !(0 == ~T3_E~0); 5089#L796-1 assume !(0 == ~T4_E~0); 5614#L801-1 assume !(0 == ~T5_E~0); 5615#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5641#L811-1 assume !(0 == ~T7_E~0); 5306#L816-1 assume !(0 == ~E_M~0); 5307#L821-1 assume !(0 == ~E_1~0); 5116#L826-1 assume !(0 == ~E_2~0); 5117#L831-1 assume !(0 == ~E_3~0); 5424#L836-1 assume !(0 == ~E_4~0); 5425#L841-1 assume !(0 == ~E_5~0); 5259#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5260#L851-1 assume !(0 == ~E_7~0); 5282#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5283#L388 assume !(1 == ~m_pc~0); 5276#L388-2 is_master_triggered_~__retres1~0#1 := 0; 5277#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5725#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5135#L967 assume !(0 != activate_threads_~tmp~1#1); 5136#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5063#L407 assume 1 == ~t1_pc~0; 5064#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5068#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5042#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5043#L975 assume !(0 != activate_threads_~tmp___0~0#1); 5823#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5386#L426 assume !(1 == ~t2_pc~0); 5387#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5838#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5867#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5865#L983 assume !(0 != activate_threads_~tmp___1~0#1); 5866#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5466#L445 assume 1 == ~t3_pc~0; 5467#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5756#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5278#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5279#L991 assume !(0 != activate_threads_~tmp___2~0#1); 5693#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5664#L464 assume !(1 == ~t4_pc~0); 5285#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5156#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5477#L999 assume !(0 != activate_threads_~tmp___3~0#1); 5442#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5443#L483 assume 1 == ~t5_pc~0; 5661#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5803#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5596#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5597#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 5370#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5371#L502 assume 1 == ~t6_pc~0; 5638#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5187#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5188#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5580#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 5581#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5780#L521 assume !(1 == ~t7_pc~0); 5819#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5129#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5130#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5237#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5787#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5714#L869 assume !(1 == ~M_E~0); 5435#L869-2 assume !(1 == ~T1_E~0); 5436#L874-1 assume !(1 == ~T2_E~0); 5848#L879-1 assume !(1 == ~T3_E~0); 5516#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5051#L889-1 assume !(1 == ~T5_E~0); 5052#L894-1 assume !(1 == ~T6_E~0); 5313#L899-1 assume !(1 == ~T7_E~0); 5681#L904-1 assume !(1 == ~E_M~0); 5458#L909-1 assume !(1 == ~E_1~0); 5459#L914-1 assume !(1 == ~E_2~0); 5628#L919-1 assume !(1 == ~E_3~0); 5385#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5225#L929-1 assume !(1 == ~E_5~0); 5226#L934-1 assume !(1 == ~E_6~0); 5438#L939-1 assume !(1 == ~E_7~0); 5439#L944-1 assume { :end_inline_reset_delta_events } true; 5295#L1190-2 [2022-02-21 04:21:59,730 INFO L793 eck$LassoCheckResult]: Loop: 5295#L1190-2 assume !false; 5308#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5309#L756 assume !false; 5531#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5871#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5149#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5657#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5480#L653 assume !(0 != eval_~tmp~0#1); 5482#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5522#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5523#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5168#L781-5 assume !(0 == ~T1_E~0); 5169#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5489#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5112#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5113#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5372#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5373#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5555#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5742#L821-3 assume !(0 == ~E_1~0); 5839#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5688#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5689#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5269#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5270#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5579#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5163#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5164#L388-27 assume 1 == ~m_pc~0; 5814#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5816#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5785#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5786#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5343#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5344#L407-27 assume !(1 == ~t1_pc~0); 5696#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5695#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5567#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5568#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5599#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5263#L426-27 assume !(1 == ~t2_pc~0); 5264#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 5274#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5275#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5799#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5812#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5550#L445-27 assume 1 == ~t3_pc~0; 5528#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5109#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5110#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5530#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5633#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5364#L464-27 assume !(1 == ~t4_pc~0); 5107#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 5108#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5175#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5556#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5255#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5256#L483-27 assume 1 == ~t5_pc~0; 5761#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5165#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5166#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5775#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 5776#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5855#L502-27 assume 1 == ~t6_pc~0; 5856#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5576#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5825#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5711#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5712#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5053#L521-27 assume !(1 == ~t7_pc~0); 5054#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 5396#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5543#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5103#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5104#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5591#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5708#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5487#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5488#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5546#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5542#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5213#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5214#L899-3 assume !(1 == ~T7_E~0); 5241#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5242#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5189#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5190#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5233#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5700#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5629#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5630#L939-3 assume !(1 == ~E_7~0); 5248#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5249#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5070#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5496#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5497#L1209 assume !(0 == start_simulation_~tmp~3#1); 5571#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5554#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5206#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5602#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5603#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5097#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5098#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 5294#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 5295#L1190-2 [2022-02-21 04:21:59,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,731 INFO L85 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2022-02-21 04:21:59,731 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,732 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354779766] [2022-02-21 04:21:59,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,762 INFO L290 TraceCheckUtils]: 0: Hoare triple {7550#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {7550#true} is VALID [2022-02-21 04:21:59,763 INFO L290 TraceCheckUtils]: 1: Hoare triple {7550#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,763 INFO L290 TraceCheckUtils]: 2: Hoare triple {7552#(= ~t3_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,764 INFO L290 TraceCheckUtils]: 3: Hoare triple {7552#(= ~t3_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,764 INFO L290 TraceCheckUtils]: 4: Hoare triple {7552#(= ~t3_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,764 INFO L290 TraceCheckUtils]: 5: Hoare triple {7552#(= ~t3_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,765 INFO L290 TraceCheckUtils]: 6: Hoare triple {7552#(= ~t3_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {7552#(= ~t3_i~0 1)} is VALID [2022-02-21 04:21:59,765 INFO L290 TraceCheckUtils]: 7: Hoare triple {7552#(= ~t3_i~0 1)} assume !(1 == ~t3_i~0);~t3_st~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,765 INFO L290 TraceCheckUtils]: 8: Hoare triple {7551#false} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,765 INFO L290 TraceCheckUtils]: 9: Hoare triple {7551#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 10: Hoare triple {7551#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 11: Hoare triple {7551#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 12: Hoare triple {7551#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 13: Hoare triple {7551#false} assume !(0 == ~M_E~0); {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 14: Hoare triple {7551#false} assume !(0 == ~T1_E~0); {7551#false} is VALID [2022-02-21 04:21:59,766 INFO L290 TraceCheckUtils]: 15: Hoare triple {7551#false} assume !(0 == ~T2_E~0); {7551#false} is VALID [2022-02-21 04:21:59,767 INFO L290 TraceCheckUtils]: 16: Hoare triple {7551#false} assume !(0 == ~T3_E~0); {7551#false} is VALID [2022-02-21 04:21:59,767 INFO L290 TraceCheckUtils]: 17: Hoare triple {7551#false} assume !(0 == ~T4_E~0); {7551#false} is VALID [2022-02-21 04:21:59,767 INFO L290 TraceCheckUtils]: 18: Hoare triple {7551#false} assume !(0 == ~T5_E~0); {7551#false} is VALID [2022-02-21 04:21:59,767 INFO L290 TraceCheckUtils]: 19: Hoare triple {7551#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {7551#false} is VALID [2022-02-21 04:21:59,767 INFO L290 TraceCheckUtils]: 20: Hoare triple {7551#false} assume !(0 == ~T7_E~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 21: Hoare triple {7551#false} assume !(0 == ~E_M~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 22: Hoare triple {7551#false} assume !(0 == ~E_1~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 23: Hoare triple {7551#false} assume !(0 == ~E_2~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 24: Hoare triple {7551#false} assume !(0 == ~E_3~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 25: Hoare triple {7551#false} assume !(0 == ~E_4~0); {7551#false} is VALID [2022-02-21 04:21:59,768 INFO L290 TraceCheckUtils]: 26: Hoare triple {7551#false} assume !(0 == ~E_5~0); {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 27: Hoare triple {7551#false} assume 0 == ~E_6~0;~E_6~0 := 1; {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 28: Hoare triple {7551#false} assume !(0 == ~E_7~0); {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 29: Hoare triple {7551#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 30: Hoare triple {7551#false} assume !(1 == ~m_pc~0); {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 31: Hoare triple {7551#false} is_master_triggered_~__retres1~0#1 := 0; {7551#false} is VALID [2022-02-21 04:21:59,769 INFO L290 TraceCheckUtils]: 32: Hoare triple {7551#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 33: Hoare triple {7551#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 34: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp~1#1); {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 35: Hoare triple {7551#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 36: Hoare triple {7551#false} assume 1 == ~t1_pc~0; {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 37: Hoare triple {7551#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {7551#false} is VALID [2022-02-21 04:21:59,770 INFO L290 TraceCheckUtils]: 38: Hoare triple {7551#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7551#false} is VALID [2022-02-21 04:21:59,771 INFO L290 TraceCheckUtils]: 39: Hoare triple {7551#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {7551#false} is VALID [2022-02-21 04:21:59,771 INFO L290 TraceCheckUtils]: 40: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___0~0#1); {7551#false} is VALID [2022-02-21 04:21:59,771 INFO L290 TraceCheckUtils]: 41: Hoare triple {7551#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7551#false} is VALID [2022-02-21 04:21:59,771 INFO L290 TraceCheckUtils]: 42: Hoare triple {7551#false} assume !(1 == ~t2_pc~0); {7551#false} is VALID [2022-02-21 04:21:59,771 INFO L290 TraceCheckUtils]: 43: Hoare triple {7551#false} is_transmit2_triggered_~__retres1~2#1 := 0; {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 44: Hoare triple {7551#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 45: Hoare triple {7551#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 46: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___1~0#1); {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 47: Hoare triple {7551#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 48: Hoare triple {7551#false} assume 1 == ~t3_pc~0; {7551#false} is VALID [2022-02-21 04:21:59,772 INFO L290 TraceCheckUtils]: 49: Hoare triple {7551#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 50: Hoare triple {7551#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 51: Hoare triple {7551#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 52: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___2~0#1); {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 53: Hoare triple {7551#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 54: Hoare triple {7551#false} assume !(1 == ~t4_pc~0); {7551#false} is VALID [2022-02-21 04:21:59,773 INFO L290 TraceCheckUtils]: 55: Hoare triple {7551#false} is_transmit4_triggered_~__retres1~4#1 := 0; {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 56: Hoare triple {7551#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 57: Hoare triple {7551#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 58: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___3~0#1); {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 59: Hoare triple {7551#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 60: Hoare triple {7551#false} assume 1 == ~t5_pc~0; {7551#false} is VALID [2022-02-21 04:21:59,774 INFO L290 TraceCheckUtils]: 61: Hoare triple {7551#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 62: Hoare triple {7551#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 63: Hoare triple {7551#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 64: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___4~0#1); {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 65: Hoare triple {7551#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 66: Hoare triple {7551#false} assume 1 == ~t6_pc~0; {7551#false} is VALID [2022-02-21 04:21:59,775 INFO L290 TraceCheckUtils]: 67: Hoare triple {7551#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 68: Hoare triple {7551#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 69: Hoare triple {7551#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 70: Hoare triple {7551#false} assume !(0 != activate_threads_~tmp___5~0#1); {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 71: Hoare triple {7551#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 72: Hoare triple {7551#false} assume !(1 == ~t7_pc~0); {7551#false} is VALID [2022-02-21 04:21:59,776 INFO L290 TraceCheckUtils]: 73: Hoare triple {7551#false} is_transmit7_triggered_~__retres1~7#1 := 0; {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 74: Hoare triple {7551#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 75: Hoare triple {7551#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 76: Hoare triple {7551#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 77: Hoare triple {7551#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 78: Hoare triple {7551#false} assume !(1 == ~M_E~0); {7551#false} is VALID [2022-02-21 04:21:59,777 INFO L290 TraceCheckUtils]: 79: Hoare triple {7551#false} assume !(1 == ~T1_E~0); {7551#false} is VALID [2022-02-21 04:21:59,778 INFO L290 TraceCheckUtils]: 80: Hoare triple {7551#false} assume !(1 == ~T2_E~0); {7551#false} is VALID [2022-02-21 04:21:59,778 INFO L290 TraceCheckUtils]: 81: Hoare triple {7551#false} assume !(1 == ~T3_E~0); {7551#false} is VALID [2022-02-21 04:21:59,778 INFO L290 TraceCheckUtils]: 82: Hoare triple {7551#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,778 INFO L290 TraceCheckUtils]: 83: Hoare triple {7551#false} assume !(1 == ~T5_E~0); {7551#false} is VALID [2022-02-21 04:21:59,778 INFO L290 TraceCheckUtils]: 84: Hoare triple {7551#false} assume !(1 == ~T6_E~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 85: Hoare triple {7551#false} assume !(1 == ~T7_E~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 86: Hoare triple {7551#false} assume !(1 == ~E_M~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 87: Hoare triple {7551#false} assume !(1 == ~E_1~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 88: Hoare triple {7551#false} assume !(1 == ~E_2~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 89: Hoare triple {7551#false} assume !(1 == ~E_3~0); {7551#false} is VALID [2022-02-21 04:21:59,779 INFO L290 TraceCheckUtils]: 90: Hoare triple {7551#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7551#false} is VALID [2022-02-21 04:21:59,780 INFO L290 TraceCheckUtils]: 91: Hoare triple {7551#false} assume !(1 == ~E_5~0); {7551#false} is VALID [2022-02-21 04:21:59,780 INFO L290 TraceCheckUtils]: 92: Hoare triple {7551#false} assume !(1 == ~E_6~0); {7551#false} is VALID [2022-02-21 04:21:59,780 INFO L290 TraceCheckUtils]: 93: Hoare triple {7551#false} assume !(1 == ~E_7~0); {7551#false} is VALID [2022-02-21 04:21:59,780 INFO L290 TraceCheckUtils]: 94: Hoare triple {7551#false} assume { :end_inline_reset_delta_events } true; {7551#false} is VALID [2022-02-21 04:21:59,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,781 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,781 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354779766] [2022-02-21 04:21:59,781 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354779766] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,781 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,781 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,782 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004617614] [2022-02-21 04:21:59,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,782 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:21:59,782 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:21:59,783 INFO L85 PathProgramCache]: Analyzing trace with hash -2094216798, now seen corresponding path program 1 times [2022-02-21 04:21:59,783 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:21:59,783 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496573066] [2022-02-21 04:21:59,783 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:21:59,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:21:59,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:21:59,845 INFO L290 TraceCheckUtils]: 0: Hoare triple {7553#true} assume !false; {7553#true} is VALID [2022-02-21 04:21:59,845 INFO L290 TraceCheckUtils]: 1: Hoare triple {7553#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {7553#true} is VALID [2022-02-21 04:21:59,845 INFO L290 TraceCheckUtils]: 2: Hoare triple {7553#true} assume !false; {7553#true} is VALID [2022-02-21 04:21:59,845 INFO L290 TraceCheckUtils]: 3: Hoare triple {7553#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 4: Hoare triple {7553#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 5: Hoare triple {7553#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 6: Hoare triple {7553#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 7: Hoare triple {7553#true} assume !(0 != eval_~tmp~0#1); {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 8: Hoare triple {7553#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 9: Hoare triple {7553#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {7553#true} is VALID [2022-02-21 04:21:59,846 INFO L290 TraceCheckUtils]: 10: Hoare triple {7553#true} assume 0 == ~M_E~0;~M_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 11: Hoare triple {7553#true} assume !(0 == ~T1_E~0); {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 12: Hoare triple {7553#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 13: Hoare triple {7553#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 14: Hoare triple {7553#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 15: Hoare triple {7553#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,847 INFO L290 TraceCheckUtils]: 16: Hoare triple {7553#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {7553#true} is VALID [2022-02-21 04:21:59,848 INFO L290 TraceCheckUtils]: 17: Hoare triple {7553#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,848 INFO L290 TraceCheckUtils]: 18: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,848 INFO L290 TraceCheckUtils]: 19: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,849 INFO L290 TraceCheckUtils]: 20: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,849 INFO L290 TraceCheckUtils]: 21: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,849 INFO L290 TraceCheckUtils]: 22: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,850 INFO L290 TraceCheckUtils]: 23: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,850 INFO L290 TraceCheckUtils]: 24: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,850 INFO L290 TraceCheckUtils]: 25: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,851 INFO L290 TraceCheckUtils]: 26: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,851 INFO L290 TraceCheckUtils]: 27: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,851 INFO L290 TraceCheckUtils]: 28: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,852 INFO L290 TraceCheckUtils]: 29: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,852 INFO L290 TraceCheckUtils]: 30: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,852 INFO L290 TraceCheckUtils]: 31: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,853 INFO L290 TraceCheckUtils]: 32: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,853 INFO L290 TraceCheckUtils]: 33: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,853 INFO L290 TraceCheckUtils]: 34: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,854 INFO L290 TraceCheckUtils]: 35: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,854 INFO L290 TraceCheckUtils]: 36: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,854 INFO L290 TraceCheckUtils]: 37: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,855 INFO L290 TraceCheckUtils]: 38: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,855 INFO L290 TraceCheckUtils]: 39: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,855 INFO L290 TraceCheckUtils]: 40: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,856 INFO L290 TraceCheckUtils]: 41: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,856 INFO L290 TraceCheckUtils]: 42: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,856 INFO L290 TraceCheckUtils]: 43: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,857 INFO L290 TraceCheckUtils]: 44: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,857 INFO L290 TraceCheckUtils]: 45: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,857 INFO L290 TraceCheckUtils]: 46: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,858 INFO L290 TraceCheckUtils]: 47: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,858 INFO L290 TraceCheckUtils]: 48: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,858 INFO L290 TraceCheckUtils]: 49: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,859 INFO L290 TraceCheckUtils]: 50: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,859 INFO L290 TraceCheckUtils]: 51: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,859 INFO L290 TraceCheckUtils]: 52: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,859 INFO L290 TraceCheckUtils]: 53: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,860 INFO L290 TraceCheckUtils]: 54: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,860 INFO L290 TraceCheckUtils]: 55: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,860 INFO L290 TraceCheckUtils]: 56: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,861 INFO L290 TraceCheckUtils]: 57: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,861 INFO L290 TraceCheckUtils]: 58: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,861 INFO L290 TraceCheckUtils]: 59: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,862 INFO L290 TraceCheckUtils]: 60: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,862 INFO L290 TraceCheckUtils]: 61: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,862 INFO L290 TraceCheckUtils]: 62: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,863 INFO L290 TraceCheckUtils]: 63: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,863 INFO L290 TraceCheckUtils]: 64: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,868 INFO L290 TraceCheckUtils]: 65: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,869 INFO L290 TraceCheckUtils]: 66: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,869 INFO L290 TraceCheckUtils]: 67: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,869 INFO L290 TraceCheckUtils]: 68: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,870 INFO L290 TraceCheckUtils]: 69: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,875 INFO L290 TraceCheckUtils]: 70: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,875 INFO L290 TraceCheckUtils]: 71: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,876 INFO L290 TraceCheckUtils]: 72: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,876 INFO L290 TraceCheckUtils]: 73: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,877 INFO L290 TraceCheckUtils]: 74: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,877 INFO L290 TraceCheckUtils]: 75: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,877 INFO L290 TraceCheckUtils]: 76: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,878 INFO L290 TraceCheckUtils]: 77: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,878 INFO L290 TraceCheckUtils]: 78: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,878 INFO L290 TraceCheckUtils]: 79: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,879 INFO L290 TraceCheckUtils]: 80: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,879 INFO L290 TraceCheckUtils]: 81: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {7555#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:21:59,880 INFO L290 TraceCheckUtils]: 82: Hoare triple {7555#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {7554#false} is VALID [2022-02-21 04:21:59,880 INFO L290 TraceCheckUtils]: 83: Hoare triple {7554#false} assume 1 == ~E_M~0;~E_M~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,880 INFO L290 TraceCheckUtils]: 84: Hoare triple {7554#false} assume 1 == ~E_1~0;~E_1~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,880 INFO L290 TraceCheckUtils]: 85: Hoare triple {7554#false} assume 1 == ~E_2~0;~E_2~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,880 INFO L290 TraceCheckUtils]: 86: Hoare triple {7554#false} assume 1 == ~E_3~0;~E_3~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,881 INFO L290 TraceCheckUtils]: 87: Hoare triple {7554#false} assume 1 == ~E_4~0;~E_4~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,881 INFO L290 TraceCheckUtils]: 88: Hoare triple {7554#false} assume 1 == ~E_5~0;~E_5~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,881 INFO L290 TraceCheckUtils]: 89: Hoare triple {7554#false} assume 1 == ~E_6~0;~E_6~0 := 2; {7554#false} is VALID [2022-02-21 04:21:59,881 INFO L290 TraceCheckUtils]: 90: Hoare triple {7554#false} assume !(1 == ~E_7~0); {7554#false} is VALID [2022-02-21 04:21:59,881 INFO L290 TraceCheckUtils]: 91: Hoare triple {7554#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 92: Hoare triple {7554#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 93: Hoare triple {7554#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 94: Hoare triple {7554#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 95: Hoare triple {7554#false} assume !(0 == start_simulation_~tmp~3#1); {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 96: Hoare triple {7554#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {7554#false} is VALID [2022-02-21 04:21:59,883 INFO L290 TraceCheckUtils]: 97: Hoare triple {7554#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 98: Hoare triple {7554#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 99: Hoare triple {7554#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 100: Hoare triple {7554#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 101: Hoare triple {7554#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 102: Hoare triple {7554#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {7554#false} is VALID [2022-02-21 04:21:59,884 INFO L290 TraceCheckUtils]: 103: Hoare triple {7554#false} assume !(0 != start_simulation_~tmp___0~1#1); {7554#false} is VALID [2022-02-21 04:21:59,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:21:59,889 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:21:59,889 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496573066] [2022-02-21 04:21:59,889 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496573066] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:21:59,889 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:21:59,890 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:21:59,890 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068462265] [2022-02-21 04:21:59,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:21:59,890 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:21:59,891 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:21:59,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:21:59,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:21:59,891 INFO L87 Difference]: Start difference. First operand 835 states and 1248 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,654 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2022-02-21 04:22:00,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:00,654 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,730 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:00,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:00,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1247 transitions. [2022-02-21 04:22:00,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:22:00,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:22:00,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:00,794 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-02-21 04:22:00,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:22:00,804 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:00,806 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1247 transitions. Second operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,807 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1247 transitions. Second operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,809 INFO L87 Difference]: Start difference. First operand 835 states and 1247 transitions. Second operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,839 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2022-02-21 04:22:00,839 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,840 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,840 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,842 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1247 transitions. [2022-02-21 04:22:00,844 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1247 transitions. [2022-02-21 04:22:00,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:00,873 INFO L93 Difference]: Finished difference Result 835 states and 1247 transitions. [2022-02-21 04:22:00,873 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,874 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:00,874 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:00,874 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:00,874 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:00,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4934131736526945) internal successors, (1247), 834 states have internal predecessors, (1247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:00,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1247 transitions. [2022-02-21 04:22:00,904 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-02-21 04:22:00,904 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1247 transitions. [2022-02-21 04:22:00,905 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2022-02-21 04:22:00,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1247 transitions. [2022-02-21 04:22:00,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:00,908 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:00,908 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:00,910 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,910 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:00,910 INFO L791 eck$LassoCheckResult]: Stem: 9026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 9027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8480#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8481#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9201#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 8776#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8777#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8896#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8897#L563-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8689#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8476#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8477#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8649#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8650#L781 assume !(0 == ~M_E~0); 9101#L781-2 assume !(0 == ~T1_E~0); 9224#L786-1 assume !(0 == ~T2_E~0); 8437#L791-1 assume !(0 == ~T3_E~0); 8438#L796-1 assume !(0 == ~T4_E~0); 8963#L801-1 assume !(0 == ~T5_E~0); 8964#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8990#L811-1 assume !(0 == ~T7_E~0); 8655#L816-1 assume !(0 == ~E_M~0); 8656#L821-1 assume !(0 == ~E_1~0); 8465#L826-1 assume !(0 == ~E_2~0); 8466#L831-1 assume !(0 == ~E_3~0); 8773#L836-1 assume !(0 == ~E_4~0); 8774#L841-1 assume !(0 == ~E_5~0); 8608#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8609#L851-1 assume !(0 == ~E_7~0); 8631#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8632#L388 assume !(1 == ~m_pc~0); 8625#L388-2 is_master_triggered_~__retres1~0#1 := 0; 8626#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9074#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8484#L967 assume !(0 != activate_threads_~tmp~1#1); 8485#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8412#L407 assume 1 == ~t1_pc~0; 8413#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8420#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8391#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8392#L975 assume !(0 != activate_threads_~tmp___0~0#1); 9172#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8735#L426 assume !(1 == ~t2_pc~0); 8736#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9187#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9216#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9214#L983 assume !(0 != activate_threads_~tmp___1~0#1); 9215#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8815#L445 assume 1 == ~t3_pc~0; 8816#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9105#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8627#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8628#L991 assume !(0 != activate_threads_~tmp___2~0#1); 9042#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9013#L464 assume !(1 == ~t4_pc~0); 8634#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8505#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8506#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8826#L999 assume !(0 != activate_threads_~tmp___3~0#1); 8791#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8792#L483 assume 1 == ~t5_pc~0; 9010#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9152#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8945#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8946#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 8719#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8720#L502 assume 1 == ~t6_pc~0; 8988#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8536#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8537#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8929#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 8930#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9129#L521 assume !(1 == ~t7_pc~0); 9168#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8478#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8479#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8586#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9136#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9063#L869 assume !(1 == ~M_E~0); 8784#L869-2 assume !(1 == ~T1_E~0); 8785#L874-1 assume !(1 == ~T2_E~0); 9197#L879-1 assume !(1 == ~T3_E~0); 8865#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8400#L889-1 assume !(1 == ~T5_E~0); 8401#L894-1 assume !(1 == ~T6_E~0); 8662#L899-1 assume !(1 == ~T7_E~0); 9032#L904-1 assume !(1 == ~E_M~0); 8807#L909-1 assume !(1 == ~E_1~0); 8808#L914-1 assume !(1 == ~E_2~0); 8977#L919-1 assume !(1 == ~E_3~0); 8734#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8574#L929-1 assume !(1 == ~E_5~0); 8575#L934-1 assume !(1 == ~E_6~0); 8787#L939-1 assume !(1 == ~E_7~0); 8788#L944-1 assume { :end_inline_reset_delta_events } true; 8643#L1190-2 [2022-02-21 04:22:00,911 INFO L793 eck$LassoCheckResult]: Loop: 8643#L1190-2 assume !false; 8657#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8658#L756 assume !false; 8880#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9220#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8500#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9006#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8829#L653 assume !(0 != eval_~tmp~0#1); 8831#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8871#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8872#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8517#L781-5 assume !(0 == ~T1_E~0); 8518#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8838#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8461#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8462#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8721#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8722#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8904#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9091#L821-3 assume !(0 == ~E_1~0); 9188#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9037#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9038#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8618#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8619#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8928#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8512#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8513#L388-27 assume 1 == ~m_pc~0; 9163#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9165#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9134#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9135#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8692#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8693#L407-27 assume 1 == ~t1_pc~0; 9043#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9044#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8916#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8917#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8948#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8612#L426-27 assume !(1 == ~t2_pc~0); 8613#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8623#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8624#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9148#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9161#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8899#L445-27 assume 1 == ~t3_pc~0; 8877#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8458#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8459#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8879#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8982#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8713#L464-27 assume !(1 == ~t4_pc~0); 8456#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 8457#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8524#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8905#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8604#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8605#L483-27 assume 1 == ~t5_pc~0; 9110#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8514#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8515#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9124#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 9125#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9204#L502-27 assume 1 == ~t6_pc~0; 9205#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8925#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9174#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9060#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9061#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8402#L521-27 assume !(1 == ~t7_pc~0); 8403#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 8745#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8892#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8452#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8453#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8938#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9057#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8836#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8837#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8895#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8891#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8562#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8563#L899-3 assume !(1 == ~T7_E~0); 8590#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8591#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8538#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8539#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8580#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9049#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8978#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8979#L939-3 assume !(1 == ~E_7~0); 8596#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8597#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8418#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8844#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 8845#L1209 assume !(0 == start_simulation_~tmp~3#1); 8920#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8903#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8555#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8950#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 8951#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8446#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8447#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8642#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 8643#L1190-2 [2022-02-21 04:22:00,911 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2022-02-21 04:22:00,912 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,912 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250929198] [2022-02-21 04:22:00,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:00,938 INFO L290 TraceCheckUtils]: 0: Hoare triple {10899#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {10899#true} is VALID [2022-02-21 04:22:00,939 INFO L290 TraceCheckUtils]: 1: Hoare triple {10899#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,939 INFO L290 TraceCheckUtils]: 2: Hoare triple {10901#(= ~t4_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,940 INFO L290 TraceCheckUtils]: 3: Hoare triple {10901#(= ~t4_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,940 INFO L290 TraceCheckUtils]: 4: Hoare triple {10901#(= ~t4_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,941 INFO L290 TraceCheckUtils]: 5: Hoare triple {10901#(= ~t4_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,941 INFO L290 TraceCheckUtils]: 6: Hoare triple {10901#(= ~t4_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,941 INFO L290 TraceCheckUtils]: 7: Hoare triple {10901#(= ~t4_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {10901#(= ~t4_i~0 1)} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 8: Hoare triple {10901#(= ~t4_i~0 1)} assume !(1 == ~t4_i~0);~t4_st~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 9: Hoare triple {10900#false} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 10: Hoare triple {10900#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 11: Hoare triple {10900#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 12: Hoare triple {10900#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {10900#false} is VALID [2022-02-21 04:22:00,942 INFO L290 TraceCheckUtils]: 13: Hoare triple {10900#false} assume !(0 == ~M_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 14: Hoare triple {10900#false} assume !(0 == ~T1_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 15: Hoare triple {10900#false} assume !(0 == ~T2_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 16: Hoare triple {10900#false} assume !(0 == ~T3_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 17: Hoare triple {10900#false} assume !(0 == ~T4_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 18: Hoare triple {10900#false} assume !(0 == ~T5_E~0); {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 19: Hoare triple {10900#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10900#false} is VALID [2022-02-21 04:22:00,943 INFO L290 TraceCheckUtils]: 20: Hoare triple {10900#false} assume !(0 == ~T7_E~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 21: Hoare triple {10900#false} assume !(0 == ~E_M~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 22: Hoare triple {10900#false} assume !(0 == ~E_1~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 23: Hoare triple {10900#false} assume !(0 == ~E_2~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 24: Hoare triple {10900#false} assume !(0 == ~E_3~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 25: Hoare triple {10900#false} assume !(0 == ~E_4~0); {10900#false} is VALID [2022-02-21 04:22:00,944 INFO L290 TraceCheckUtils]: 26: Hoare triple {10900#false} assume !(0 == ~E_5~0); {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 27: Hoare triple {10900#false} assume 0 == ~E_6~0;~E_6~0 := 1; {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 28: Hoare triple {10900#false} assume !(0 == ~E_7~0); {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 29: Hoare triple {10900#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 30: Hoare triple {10900#false} assume !(1 == ~m_pc~0); {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 31: Hoare triple {10900#false} is_master_triggered_~__retres1~0#1 := 0; {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 32: Hoare triple {10900#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10900#false} is VALID [2022-02-21 04:22:00,945 INFO L290 TraceCheckUtils]: 33: Hoare triple {10900#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 34: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp~1#1); {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 35: Hoare triple {10900#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 36: Hoare triple {10900#false} assume 1 == ~t1_pc~0; {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 37: Hoare triple {10900#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 38: Hoare triple {10900#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10900#false} is VALID [2022-02-21 04:22:00,946 INFO L290 TraceCheckUtils]: 39: Hoare triple {10900#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 40: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___0~0#1); {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 41: Hoare triple {10900#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 42: Hoare triple {10900#false} assume !(1 == ~t2_pc~0); {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 43: Hoare triple {10900#false} is_transmit2_triggered_~__retres1~2#1 := 0; {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 44: Hoare triple {10900#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10900#false} is VALID [2022-02-21 04:22:00,947 INFO L290 TraceCheckUtils]: 45: Hoare triple {10900#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 46: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___1~0#1); {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 47: Hoare triple {10900#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 48: Hoare triple {10900#false} assume 1 == ~t3_pc~0; {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 49: Hoare triple {10900#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 50: Hoare triple {10900#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10900#false} is VALID [2022-02-21 04:22:00,948 INFO L290 TraceCheckUtils]: 51: Hoare triple {10900#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 52: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___2~0#1); {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 53: Hoare triple {10900#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 54: Hoare triple {10900#false} assume !(1 == ~t4_pc~0); {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 55: Hoare triple {10900#false} is_transmit4_triggered_~__retres1~4#1 := 0; {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 56: Hoare triple {10900#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 57: Hoare triple {10900#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10900#false} is VALID [2022-02-21 04:22:00,949 INFO L290 TraceCheckUtils]: 58: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___3~0#1); {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 59: Hoare triple {10900#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 60: Hoare triple {10900#false} assume 1 == ~t5_pc~0; {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 61: Hoare triple {10900#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 62: Hoare triple {10900#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 63: Hoare triple {10900#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10900#false} is VALID [2022-02-21 04:22:00,950 INFO L290 TraceCheckUtils]: 64: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___4~0#1); {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 65: Hoare triple {10900#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 66: Hoare triple {10900#false} assume 1 == ~t6_pc~0; {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 67: Hoare triple {10900#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 68: Hoare triple {10900#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 69: Hoare triple {10900#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10900#false} is VALID [2022-02-21 04:22:00,951 INFO L290 TraceCheckUtils]: 70: Hoare triple {10900#false} assume !(0 != activate_threads_~tmp___5~0#1); {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 71: Hoare triple {10900#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 72: Hoare triple {10900#false} assume !(1 == ~t7_pc~0); {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 73: Hoare triple {10900#false} is_transmit7_triggered_~__retres1~7#1 := 0; {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 74: Hoare triple {10900#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 75: Hoare triple {10900#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 76: Hoare triple {10900#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10900#false} is VALID [2022-02-21 04:22:00,952 INFO L290 TraceCheckUtils]: 77: Hoare triple {10900#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 78: Hoare triple {10900#false} assume !(1 == ~M_E~0); {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 79: Hoare triple {10900#false} assume !(1 == ~T1_E~0); {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 80: Hoare triple {10900#false} assume !(1 == ~T2_E~0); {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 81: Hoare triple {10900#false} assume !(1 == ~T3_E~0); {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 82: Hoare triple {10900#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,953 INFO L290 TraceCheckUtils]: 83: Hoare triple {10900#false} assume !(1 == ~T5_E~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 84: Hoare triple {10900#false} assume !(1 == ~T6_E~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 85: Hoare triple {10900#false} assume !(1 == ~T7_E~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 86: Hoare triple {10900#false} assume !(1 == ~E_M~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 87: Hoare triple {10900#false} assume !(1 == ~E_1~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 88: Hoare triple {10900#false} assume !(1 == ~E_2~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 89: Hoare triple {10900#false} assume !(1 == ~E_3~0); {10900#false} is VALID [2022-02-21 04:22:00,954 INFO L290 TraceCheckUtils]: 90: Hoare triple {10900#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10900#false} is VALID [2022-02-21 04:22:00,955 INFO L290 TraceCheckUtils]: 91: Hoare triple {10900#false} assume !(1 == ~E_5~0); {10900#false} is VALID [2022-02-21 04:22:00,955 INFO L290 TraceCheckUtils]: 92: Hoare triple {10900#false} assume !(1 == ~E_6~0); {10900#false} is VALID [2022-02-21 04:22:00,955 INFO L290 TraceCheckUtils]: 93: Hoare triple {10900#false} assume !(1 == ~E_7~0); {10900#false} is VALID [2022-02-21 04:22:00,955 INFO L290 TraceCheckUtils]: 94: Hoare triple {10900#false} assume { :end_inline_reset_delta_events } true; {10900#false} is VALID [2022-02-21 04:22:00,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:00,956 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:00,956 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250929198] [2022-02-21 04:22:00,956 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250929198] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:00,956 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:00,956 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:00,957 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2035440588] [2022-02-21 04:22:00,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:00,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:00,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:00,958 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 1 times [2022-02-21 04:22:00,958 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:00,958 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2112712843] [2022-02-21 04:22:00,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:00,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:00,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:01,019 INFO L290 TraceCheckUtils]: 0: Hoare triple {10902#true} assume !false; {10902#true} is VALID [2022-02-21 04:22:01,019 INFO L290 TraceCheckUtils]: 1: Hoare triple {10902#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 2: Hoare triple {10902#true} assume !false; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 3: Hoare triple {10902#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 4: Hoare triple {10902#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 5: Hoare triple {10902#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 6: Hoare triple {10902#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 7: Hoare triple {10902#true} assume !(0 != eval_~tmp~0#1); {10902#true} is VALID [2022-02-21 04:22:01,020 INFO L290 TraceCheckUtils]: 8: Hoare triple {10902#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 9: Hoare triple {10902#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 10: Hoare triple {10902#true} assume 0 == ~M_E~0;~M_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 11: Hoare triple {10902#true} assume !(0 == ~T1_E~0); {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 12: Hoare triple {10902#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 13: Hoare triple {10902#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,021 INFO L290 TraceCheckUtils]: 14: Hoare triple {10902#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,035 INFO L290 TraceCheckUtils]: 15: Hoare triple {10902#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,035 INFO L290 TraceCheckUtils]: 16: Hoare triple {10902#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {10902#true} is VALID [2022-02-21 04:22:01,036 INFO L290 TraceCheckUtils]: 17: Hoare triple {10902#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,036 INFO L290 TraceCheckUtils]: 18: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,037 INFO L290 TraceCheckUtils]: 19: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,037 INFO L290 TraceCheckUtils]: 20: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,037 INFO L290 TraceCheckUtils]: 21: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,038 INFO L290 TraceCheckUtils]: 22: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,039 INFO L290 TraceCheckUtils]: 23: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,040 INFO L290 TraceCheckUtils]: 24: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,040 INFO L290 TraceCheckUtils]: 25: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,040 INFO L290 TraceCheckUtils]: 26: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,041 INFO L290 TraceCheckUtils]: 27: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,041 INFO L290 TraceCheckUtils]: 28: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,041 INFO L290 TraceCheckUtils]: 29: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,042 INFO L290 TraceCheckUtils]: 30: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,042 INFO L290 TraceCheckUtils]: 31: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,042 INFO L290 TraceCheckUtils]: 32: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,043 INFO L290 TraceCheckUtils]: 33: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,043 INFO L290 TraceCheckUtils]: 34: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,043 INFO L290 TraceCheckUtils]: 35: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,044 INFO L290 TraceCheckUtils]: 36: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,044 INFO L290 TraceCheckUtils]: 37: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,044 INFO L290 TraceCheckUtils]: 38: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,045 INFO L290 TraceCheckUtils]: 39: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,045 INFO L290 TraceCheckUtils]: 40: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,045 INFO L290 TraceCheckUtils]: 41: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,046 INFO L290 TraceCheckUtils]: 42: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,046 INFO L290 TraceCheckUtils]: 43: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,046 INFO L290 TraceCheckUtils]: 44: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,047 INFO L290 TraceCheckUtils]: 45: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,047 INFO L290 TraceCheckUtils]: 46: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,047 INFO L290 TraceCheckUtils]: 47: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,048 INFO L290 TraceCheckUtils]: 48: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,048 INFO L290 TraceCheckUtils]: 49: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,048 INFO L290 TraceCheckUtils]: 50: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,049 INFO L290 TraceCheckUtils]: 51: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,049 INFO L290 TraceCheckUtils]: 52: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,049 INFO L290 TraceCheckUtils]: 53: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,050 INFO L290 TraceCheckUtils]: 54: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,050 INFO L290 TraceCheckUtils]: 55: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,050 INFO L290 TraceCheckUtils]: 56: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,051 INFO L290 TraceCheckUtils]: 57: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,051 INFO L290 TraceCheckUtils]: 58: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,051 INFO L290 TraceCheckUtils]: 59: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,052 INFO L290 TraceCheckUtils]: 60: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,052 INFO L290 TraceCheckUtils]: 61: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,052 INFO L290 TraceCheckUtils]: 62: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,053 INFO L290 TraceCheckUtils]: 63: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,053 INFO L290 TraceCheckUtils]: 64: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,053 INFO L290 TraceCheckUtils]: 65: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,054 INFO L290 TraceCheckUtils]: 66: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,054 INFO L290 TraceCheckUtils]: 67: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,054 INFO L290 TraceCheckUtils]: 68: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,055 INFO L290 TraceCheckUtils]: 69: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,055 INFO L290 TraceCheckUtils]: 70: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,055 INFO L290 TraceCheckUtils]: 71: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,056 INFO L290 TraceCheckUtils]: 72: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,056 INFO L290 TraceCheckUtils]: 73: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,056 INFO L290 TraceCheckUtils]: 74: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,057 INFO L290 TraceCheckUtils]: 75: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,057 INFO L290 TraceCheckUtils]: 76: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,057 INFO L290 TraceCheckUtils]: 77: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,058 INFO L290 TraceCheckUtils]: 78: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,058 INFO L290 TraceCheckUtils]: 79: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,059 INFO L290 TraceCheckUtils]: 80: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,060 INFO L290 TraceCheckUtils]: 81: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {10904#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:01,060 INFO L290 TraceCheckUtils]: 82: Hoare triple {10904#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {10903#false} is VALID [2022-02-21 04:22:01,060 INFO L290 TraceCheckUtils]: 83: Hoare triple {10903#false} assume 1 == ~E_M~0;~E_M~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,060 INFO L290 TraceCheckUtils]: 84: Hoare triple {10903#false} assume 1 == ~E_1~0;~E_1~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,060 INFO L290 TraceCheckUtils]: 85: Hoare triple {10903#false} assume 1 == ~E_2~0;~E_2~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,061 INFO L290 TraceCheckUtils]: 86: Hoare triple {10903#false} assume 1 == ~E_3~0;~E_3~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,061 INFO L290 TraceCheckUtils]: 87: Hoare triple {10903#false} assume 1 == ~E_4~0;~E_4~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,061 INFO L290 TraceCheckUtils]: 88: Hoare triple {10903#false} assume 1 == ~E_5~0;~E_5~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 89: Hoare triple {10903#false} assume 1 == ~E_6~0;~E_6~0 := 2; {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 90: Hoare triple {10903#false} assume !(1 == ~E_7~0); {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 91: Hoare triple {10903#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 92: Hoare triple {10903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 93: Hoare triple {10903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10903#false} is VALID [2022-02-21 04:22:01,062 INFO L290 TraceCheckUtils]: 94: Hoare triple {10903#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 95: Hoare triple {10903#false} assume !(0 == start_simulation_~tmp~3#1); {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 96: Hoare triple {10903#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 97: Hoare triple {10903#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 98: Hoare triple {10903#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 99: Hoare triple {10903#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 100: Hoare triple {10903#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {10903#false} is VALID [2022-02-21 04:22:01,063 INFO L290 TraceCheckUtils]: 101: Hoare triple {10903#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {10903#false} is VALID [2022-02-21 04:22:01,064 INFO L290 TraceCheckUtils]: 102: Hoare triple {10903#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {10903#false} is VALID [2022-02-21 04:22:01,064 INFO L290 TraceCheckUtils]: 103: Hoare triple {10903#false} assume !(0 != start_simulation_~tmp___0~1#1); {10903#false} is VALID [2022-02-21 04:22:01,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:01,065 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:01,065 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2112712843] [2022-02-21 04:22:01,065 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2112712843] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:01,066 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:01,066 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:01,066 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [263864278] [2022-02-21 04:22:01,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:01,066 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:01,067 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:01,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:01,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:01,068 INFO L87 Difference]: Start difference. First operand 835 states and 1247 transitions. cyclomatic complexity: 413 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,800 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2022-02-21 04:22:01,800 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:01,800 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,883 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:01,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1246 transitions. [2022-02-21 04:22:01,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:01,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1246 transitions. [2022-02-21 04:22:01,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:22:01,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:22:01,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1246 transitions. [2022-02-21 04:22:01,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:01,946 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-02-21 04:22:01,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1246 transitions. [2022-02-21 04:22:01,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:22:01,955 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:01,957 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1246 transitions. Second operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,959 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1246 transitions. Second operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,960 INFO L87 Difference]: Start difference. First operand 835 states and 1246 transitions. Second operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:01,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:01,989 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2022-02-21 04:22:01,989 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1246 transitions. [2022-02-21 04:22:01,990 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:01,990 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:01,992 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1246 transitions. [2022-02-21 04:22:01,994 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1246 transitions. [2022-02-21 04:22:02,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,023 INFO L93 Difference]: Finished difference Result 835 states and 1246 transitions. [2022-02-21 04:22:02,023 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1246 transitions. [2022-02-21 04:22:02,024 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:02,024 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:02,025 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:02,025 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:02,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4922155688622754) internal successors, (1246), 834 states have internal predecessors, (1246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1246 transitions. [2022-02-21 04:22:02,054 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-02-21 04:22:02,054 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1246 transitions. [2022-02-21 04:22:02,054 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2022-02-21 04:22:02,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1246 transitions. [2022-02-21 04:22:02,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:02,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:02,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:02,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:02,060 INFO L791 eck$LassoCheckResult]: Stem: 12375#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12376#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11829#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11830#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12550#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 12125#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12126#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12245#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12246#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12038#L568-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11825#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11826#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11995#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11996#L781 assume !(0 == ~M_E~0); 12450#L781-2 assume !(0 == ~T1_E~0); 12573#L786-1 assume !(0 == ~T2_E~0); 11786#L791-1 assume !(0 == ~T3_E~0); 11787#L796-1 assume !(0 == ~T4_E~0); 12312#L801-1 assume !(0 == ~T5_E~0); 12313#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12339#L811-1 assume !(0 == ~T7_E~0); 12004#L816-1 assume !(0 == ~E_M~0); 12005#L821-1 assume !(0 == ~E_1~0); 11814#L826-1 assume !(0 == ~E_2~0); 11815#L831-1 assume !(0 == ~E_3~0); 12122#L836-1 assume !(0 == ~E_4~0); 12123#L841-1 assume !(0 == ~E_5~0); 11957#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11958#L851-1 assume !(0 == ~E_7~0); 11980#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11981#L388 assume !(1 == ~m_pc~0); 11974#L388-2 is_master_triggered_~__retres1~0#1 := 0; 11975#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12423#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11833#L967 assume !(0 != activate_threads_~tmp~1#1); 11834#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11761#L407 assume 1 == ~t1_pc~0; 11762#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11766#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11740#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11741#L975 assume !(0 != activate_threads_~tmp___0~0#1); 12521#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12084#L426 assume !(1 == ~t2_pc~0); 12085#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12536#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12565#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12563#L983 assume !(0 != activate_threads_~tmp___1~0#1); 12564#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12164#L445 assume 1 == ~t3_pc~0; 12165#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12454#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11976#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11977#L991 assume !(0 != activate_threads_~tmp___2~0#1); 12391#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12362#L464 assume !(1 == ~t4_pc~0); 11983#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11854#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11855#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12175#L999 assume !(0 != activate_threads_~tmp___3~0#1); 12140#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12141#L483 assume 1 == ~t5_pc~0; 12359#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12501#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12294#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12295#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 12068#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12069#L502 assume 1 == ~t6_pc~0; 12336#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11885#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11886#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12278#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 12279#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12478#L521 assume !(1 == ~t7_pc~0); 12517#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11827#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11828#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11935#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12485#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12412#L869 assume !(1 == ~M_E~0); 12133#L869-2 assume !(1 == ~T1_E~0); 12134#L874-1 assume !(1 == ~T2_E~0); 12546#L879-1 assume !(1 == ~T3_E~0); 12214#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11749#L889-1 assume !(1 == ~T5_E~0); 11750#L894-1 assume !(1 == ~T6_E~0); 12011#L899-1 assume !(1 == ~T7_E~0); 12379#L904-1 assume !(1 == ~E_M~0); 12156#L909-1 assume !(1 == ~E_1~0); 12157#L914-1 assume !(1 == ~E_2~0); 12326#L919-1 assume !(1 == ~E_3~0); 12083#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11923#L929-1 assume !(1 == ~E_5~0); 11924#L934-1 assume !(1 == ~E_6~0); 12136#L939-1 assume !(1 == ~E_7~0); 12137#L944-1 assume { :end_inline_reset_delta_events } true; 11993#L1190-2 [2022-02-21 04:22:02,063 INFO L793 eck$LassoCheckResult]: Loop: 11993#L1190-2 assume !false; 12006#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12007#L756 assume !false; 12229#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12569#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11847#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12355#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12178#L653 assume !(0 != eval_~tmp~0#1); 12180#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12220#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12221#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11866#L781-5 assume !(0 == ~T1_E~0); 11867#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12187#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11810#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11811#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12070#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12071#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12253#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12440#L821-3 assume !(0 == ~E_1~0); 12537#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12386#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12387#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11967#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11968#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12277#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11861#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11862#L388-27 assume 1 == ~m_pc~0; 12512#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12514#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12483#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12484#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12041#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12042#L407-27 assume 1 == ~t1_pc~0; 12392#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12393#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12265#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12266#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12297#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11961#L426-27 assume !(1 == ~t2_pc~0); 11962#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 11972#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11973#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12497#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12510#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12248#L445-27 assume 1 == ~t3_pc~0; 12226#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11807#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11808#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12228#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12331#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12062#L464-27 assume !(1 == ~t4_pc~0); 11805#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 11806#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11873#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12254#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11953#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11954#L483-27 assume 1 == ~t5_pc~0; 12459#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11863#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11864#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12473#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 12474#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12553#L502-27 assume !(1 == ~t6_pc~0); 12273#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 12274#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12523#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12409#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12410#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11751#L521-27 assume !(1 == ~t7_pc~0); 11752#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 12094#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12241#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11801#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11802#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12289#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12406#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12185#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12186#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12244#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12240#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11911#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11912#L899-3 assume !(1 == ~T7_E~0); 11939#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11940#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11887#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11888#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11931#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12398#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12327#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12328#L939-3 assume !(1 == ~E_7~0); 11946#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11947#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11768#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12194#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 12195#L1209 assume !(0 == start_simulation_~tmp~3#1); 12269#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 12252#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11904#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12300#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 12301#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11795#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11796#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11992#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 11993#L1190-2 [2022-02-21 04:22:02,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:02,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2022-02-21 04:22:02,064 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:02,064 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142464865] [2022-02-21 04:22:02,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:02,065 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:02,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:02,105 INFO L290 TraceCheckUtils]: 0: Hoare triple {14248#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {14248#true} is VALID [2022-02-21 04:22:02,105 INFO L290 TraceCheckUtils]: 1: Hoare triple {14248#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,105 INFO L290 TraceCheckUtils]: 2: Hoare triple {14250#(= ~t5_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,106 INFO L290 TraceCheckUtils]: 3: Hoare triple {14250#(= ~t5_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,106 INFO L290 TraceCheckUtils]: 4: Hoare triple {14250#(= ~t5_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,106 INFO L290 TraceCheckUtils]: 5: Hoare triple {14250#(= ~t5_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,107 INFO L290 TraceCheckUtils]: 6: Hoare triple {14250#(= ~t5_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,107 INFO L290 TraceCheckUtils]: 7: Hoare triple {14250#(= ~t5_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 8: Hoare triple {14250#(= ~t5_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {14250#(= ~t5_i~0 1)} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 9: Hoare triple {14250#(= ~t5_i~0 1)} assume !(1 == ~t5_i~0);~t5_st~0 := 2; {14249#false} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 10: Hoare triple {14249#false} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {14249#false} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 11: Hoare triple {14249#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {14249#false} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 12: Hoare triple {14249#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {14249#false} is VALID [2022-02-21 04:22:02,108 INFO L290 TraceCheckUtils]: 13: Hoare triple {14249#false} assume !(0 == ~M_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 14: Hoare triple {14249#false} assume !(0 == ~T1_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 15: Hoare triple {14249#false} assume !(0 == ~T2_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 16: Hoare triple {14249#false} assume !(0 == ~T3_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 17: Hoare triple {14249#false} assume !(0 == ~T4_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 18: Hoare triple {14249#false} assume !(0 == ~T5_E~0); {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 19: Hoare triple {14249#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14249#false} is VALID [2022-02-21 04:22:02,109 INFO L290 TraceCheckUtils]: 20: Hoare triple {14249#false} assume !(0 == ~T7_E~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 21: Hoare triple {14249#false} assume !(0 == ~E_M~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 22: Hoare triple {14249#false} assume !(0 == ~E_1~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 23: Hoare triple {14249#false} assume !(0 == ~E_2~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 24: Hoare triple {14249#false} assume !(0 == ~E_3~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 25: Hoare triple {14249#false} assume !(0 == ~E_4~0); {14249#false} is VALID [2022-02-21 04:22:02,110 INFO L290 TraceCheckUtils]: 26: Hoare triple {14249#false} assume !(0 == ~E_5~0); {14249#false} is VALID [2022-02-21 04:22:02,118 INFO L290 TraceCheckUtils]: 27: Hoare triple {14249#false} assume 0 == ~E_6~0;~E_6~0 := 1; {14249#false} is VALID [2022-02-21 04:22:02,118 INFO L290 TraceCheckUtils]: 28: Hoare triple {14249#false} assume !(0 == ~E_7~0); {14249#false} is VALID [2022-02-21 04:22:02,118 INFO L290 TraceCheckUtils]: 29: Hoare triple {14249#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14249#false} is VALID [2022-02-21 04:22:02,118 INFO L290 TraceCheckUtils]: 30: Hoare triple {14249#false} assume !(1 == ~m_pc~0); {14249#false} is VALID [2022-02-21 04:22:02,118 INFO L290 TraceCheckUtils]: 31: Hoare triple {14249#false} is_master_triggered_~__retres1~0#1 := 0; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 32: Hoare triple {14249#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 33: Hoare triple {14249#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 34: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp~1#1); {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 35: Hoare triple {14249#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 36: Hoare triple {14249#false} assume 1 == ~t1_pc~0; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 37: Hoare triple {14249#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14249#false} is VALID [2022-02-21 04:22:02,119 INFO L290 TraceCheckUtils]: 38: Hoare triple {14249#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 39: Hoare triple {14249#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 40: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___0~0#1); {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 41: Hoare triple {14249#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 42: Hoare triple {14249#false} assume !(1 == ~t2_pc~0); {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 43: Hoare triple {14249#false} is_transmit2_triggered_~__retres1~2#1 := 0; {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 44: Hoare triple {14249#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14249#false} is VALID [2022-02-21 04:22:02,120 INFO L290 TraceCheckUtils]: 45: Hoare triple {14249#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 46: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___1~0#1); {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 47: Hoare triple {14249#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 48: Hoare triple {14249#false} assume 1 == ~t3_pc~0; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 49: Hoare triple {14249#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 50: Hoare triple {14249#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 51: Hoare triple {14249#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14249#false} is VALID [2022-02-21 04:22:02,121 INFO L290 TraceCheckUtils]: 52: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___2~0#1); {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 53: Hoare triple {14249#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 54: Hoare triple {14249#false} assume !(1 == ~t4_pc~0); {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 55: Hoare triple {14249#false} is_transmit4_triggered_~__retres1~4#1 := 0; {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 56: Hoare triple {14249#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 57: Hoare triple {14249#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 58: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___3~0#1); {14249#false} is VALID [2022-02-21 04:22:02,122 INFO L290 TraceCheckUtils]: 59: Hoare triple {14249#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 60: Hoare triple {14249#false} assume 1 == ~t5_pc~0; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 61: Hoare triple {14249#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 62: Hoare triple {14249#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 63: Hoare triple {14249#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 64: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___4~0#1); {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 65: Hoare triple {14249#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14249#false} is VALID [2022-02-21 04:22:02,123 INFO L290 TraceCheckUtils]: 66: Hoare triple {14249#false} assume 1 == ~t6_pc~0; {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 67: Hoare triple {14249#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 68: Hoare triple {14249#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 69: Hoare triple {14249#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 70: Hoare triple {14249#false} assume !(0 != activate_threads_~tmp___5~0#1); {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 71: Hoare triple {14249#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 72: Hoare triple {14249#false} assume !(1 == ~t7_pc~0); {14249#false} is VALID [2022-02-21 04:22:02,124 INFO L290 TraceCheckUtils]: 73: Hoare triple {14249#false} is_transmit7_triggered_~__retres1~7#1 := 0; {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 74: Hoare triple {14249#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 75: Hoare triple {14249#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 76: Hoare triple {14249#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 77: Hoare triple {14249#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 78: Hoare triple {14249#false} assume !(1 == ~M_E~0); {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 79: Hoare triple {14249#false} assume !(1 == ~T1_E~0); {14249#false} is VALID [2022-02-21 04:22:02,125 INFO L290 TraceCheckUtils]: 80: Hoare triple {14249#false} assume !(1 == ~T2_E~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 81: Hoare triple {14249#false} assume !(1 == ~T3_E~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 82: Hoare triple {14249#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 83: Hoare triple {14249#false} assume !(1 == ~T5_E~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 84: Hoare triple {14249#false} assume !(1 == ~T6_E~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 85: Hoare triple {14249#false} assume !(1 == ~T7_E~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 86: Hoare triple {14249#false} assume !(1 == ~E_M~0); {14249#false} is VALID [2022-02-21 04:22:02,126 INFO L290 TraceCheckUtils]: 87: Hoare triple {14249#false} assume !(1 == ~E_1~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 88: Hoare triple {14249#false} assume !(1 == ~E_2~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 89: Hoare triple {14249#false} assume !(1 == ~E_3~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 90: Hoare triple {14249#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 91: Hoare triple {14249#false} assume !(1 == ~E_5~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 92: Hoare triple {14249#false} assume !(1 == ~E_6~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 93: Hoare triple {14249#false} assume !(1 == ~E_7~0); {14249#false} is VALID [2022-02-21 04:22:02,127 INFO L290 TraceCheckUtils]: 94: Hoare triple {14249#false} assume { :end_inline_reset_delta_events } true; {14249#false} is VALID [2022-02-21 04:22:02,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:02,128 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:02,128 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1142464865] [2022-02-21 04:22:02,128 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1142464865] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:02,129 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:02,129 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:02,129 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22305986] [2022-02-21 04:22:02,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:02,129 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:02,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:02,130 INFO L85 PathProgramCache]: Analyzing trace with hash -624070302, now seen corresponding path program 1 times [2022-02-21 04:22:02,130 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:02,130 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393879468] [2022-02-21 04:22:02,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:02,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:02,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:02,182 INFO L290 TraceCheckUtils]: 0: Hoare triple {14251#true} assume !false; {14251#true} is VALID [2022-02-21 04:22:02,182 INFO L290 TraceCheckUtils]: 1: Hoare triple {14251#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 2: Hoare triple {14251#true} assume !false; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 3: Hoare triple {14251#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 4: Hoare triple {14251#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 5: Hoare triple {14251#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 6: Hoare triple {14251#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 7: Hoare triple {14251#true} assume !(0 != eval_~tmp~0#1); {14251#true} is VALID [2022-02-21 04:22:02,183 INFO L290 TraceCheckUtils]: 8: Hoare triple {14251#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 9: Hoare triple {14251#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 10: Hoare triple {14251#true} assume 0 == ~M_E~0;~M_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 11: Hoare triple {14251#true} assume !(0 == ~T1_E~0); {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 12: Hoare triple {14251#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 13: Hoare triple {14251#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 14: Hoare triple {14251#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,184 INFO L290 TraceCheckUtils]: 15: Hoare triple {14251#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,185 INFO L290 TraceCheckUtils]: 16: Hoare triple {14251#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {14251#true} is VALID [2022-02-21 04:22:02,185 INFO L290 TraceCheckUtils]: 17: Hoare triple {14251#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,185 INFO L290 TraceCheckUtils]: 18: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,186 INFO L290 TraceCheckUtils]: 19: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,186 INFO L290 TraceCheckUtils]: 20: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,186 INFO L290 TraceCheckUtils]: 21: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,187 INFO L290 TraceCheckUtils]: 22: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,187 INFO L290 TraceCheckUtils]: 23: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,187 INFO L290 TraceCheckUtils]: 24: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,188 INFO L290 TraceCheckUtils]: 25: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,188 INFO L290 TraceCheckUtils]: 26: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,189 INFO L290 TraceCheckUtils]: 27: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,189 INFO L290 TraceCheckUtils]: 28: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,189 INFO L290 TraceCheckUtils]: 29: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,190 INFO L290 TraceCheckUtils]: 30: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,190 INFO L290 TraceCheckUtils]: 31: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,190 INFO L290 TraceCheckUtils]: 32: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,191 INFO L290 TraceCheckUtils]: 33: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,191 INFO L290 TraceCheckUtils]: 34: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,191 INFO L290 TraceCheckUtils]: 35: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,192 INFO L290 TraceCheckUtils]: 36: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,192 INFO L290 TraceCheckUtils]: 37: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,192 INFO L290 TraceCheckUtils]: 38: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,193 INFO L290 TraceCheckUtils]: 39: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,193 INFO L290 TraceCheckUtils]: 40: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,193 INFO L290 TraceCheckUtils]: 41: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,194 INFO L290 TraceCheckUtils]: 42: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,194 INFO L290 TraceCheckUtils]: 43: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,194 INFO L290 TraceCheckUtils]: 44: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,195 INFO L290 TraceCheckUtils]: 45: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,195 INFO L290 TraceCheckUtils]: 46: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,196 INFO L290 TraceCheckUtils]: 47: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,196 INFO L290 TraceCheckUtils]: 48: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,196 INFO L290 TraceCheckUtils]: 49: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,197 INFO L290 TraceCheckUtils]: 50: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,197 INFO L290 TraceCheckUtils]: 51: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,197 INFO L290 TraceCheckUtils]: 52: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,198 INFO L290 TraceCheckUtils]: 53: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,198 INFO L290 TraceCheckUtils]: 54: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,198 INFO L290 TraceCheckUtils]: 55: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,199 INFO L290 TraceCheckUtils]: 56: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,199 INFO L290 TraceCheckUtils]: 57: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,199 INFO L290 TraceCheckUtils]: 58: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,200 INFO L290 TraceCheckUtils]: 59: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,200 INFO L290 TraceCheckUtils]: 60: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,200 INFO L290 TraceCheckUtils]: 61: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,201 INFO L290 TraceCheckUtils]: 62: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,201 INFO L290 TraceCheckUtils]: 63: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,201 INFO L290 TraceCheckUtils]: 64: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,202 INFO L290 TraceCheckUtils]: 65: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,202 INFO L290 TraceCheckUtils]: 66: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,202 INFO L290 TraceCheckUtils]: 67: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,203 INFO L290 TraceCheckUtils]: 68: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,203 INFO L290 TraceCheckUtils]: 69: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,203 INFO L290 TraceCheckUtils]: 70: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,204 INFO L290 TraceCheckUtils]: 71: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,204 INFO L290 TraceCheckUtils]: 72: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,204 INFO L290 TraceCheckUtils]: 73: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,205 INFO L290 TraceCheckUtils]: 74: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,205 INFO L290 TraceCheckUtils]: 75: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,205 INFO L290 TraceCheckUtils]: 76: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,207 INFO L290 TraceCheckUtils]: 77: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,207 INFO L290 TraceCheckUtils]: 78: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,208 INFO L290 TraceCheckUtils]: 79: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,208 INFO L290 TraceCheckUtils]: 80: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,208 INFO L290 TraceCheckUtils]: 81: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {14253#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 82: Hoare triple {14253#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {14252#false} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 83: Hoare triple {14252#false} assume 1 == ~E_M~0;~E_M~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 84: Hoare triple {14252#false} assume 1 == ~E_1~0;~E_1~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 85: Hoare triple {14252#false} assume 1 == ~E_2~0;~E_2~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 86: Hoare triple {14252#false} assume 1 == ~E_3~0;~E_3~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,209 INFO L290 TraceCheckUtils]: 87: Hoare triple {14252#false} assume 1 == ~E_4~0;~E_4~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 88: Hoare triple {14252#false} assume 1 == ~E_5~0;~E_5~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 89: Hoare triple {14252#false} assume 1 == ~E_6~0;~E_6~0 := 2; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 90: Hoare triple {14252#false} assume !(1 == ~E_7~0); {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 91: Hoare triple {14252#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 92: Hoare triple {14252#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 93: Hoare triple {14252#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14252#false} is VALID [2022-02-21 04:22:02,210 INFO L290 TraceCheckUtils]: 94: Hoare triple {14252#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 95: Hoare triple {14252#false} assume !(0 == start_simulation_~tmp~3#1); {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 96: Hoare triple {14252#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 97: Hoare triple {14252#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 98: Hoare triple {14252#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 99: Hoare triple {14252#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {14252#false} is VALID [2022-02-21 04:22:02,211 INFO L290 TraceCheckUtils]: 100: Hoare triple {14252#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {14252#false} is VALID [2022-02-21 04:22:02,212 INFO L290 TraceCheckUtils]: 101: Hoare triple {14252#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {14252#false} is VALID [2022-02-21 04:22:02,212 INFO L290 TraceCheckUtils]: 102: Hoare triple {14252#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {14252#false} is VALID [2022-02-21 04:22:02,212 INFO L290 TraceCheckUtils]: 103: Hoare triple {14252#false} assume !(0 != start_simulation_~tmp___0~1#1); {14252#false} is VALID [2022-02-21 04:22:02,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:02,213 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:02,213 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393879468] [2022-02-21 04:22:02,213 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393879468] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:02,213 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:02,213 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:02,213 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936177192] [2022-02-21 04:22:02,214 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:02,214 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:02,214 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:02,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:02,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:02,216 INFO L87 Difference]: Start difference. First operand 835 states and 1246 transitions. cyclomatic complexity: 412 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:02,888 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-02-21 04:22:02,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:02,889 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:02,962 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:02,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1245 transitions. [2022-02-21 04:22:02,994 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:03,023 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1245 transitions. [2022-02-21 04:22:03,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:22:03,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:22:03,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1245 transitions. [2022-02-21 04:22:03,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:03,026 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-02-21 04:22:03,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1245 transitions. [2022-02-21 04:22:03,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:22:03,036 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:03,037 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1245 transitions. Second operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,052 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1245 transitions. Second operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,054 INFO L87 Difference]: Start difference. First operand 835 states and 1245 transitions. Second operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:03,082 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-02-21 04:22:03,082 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1245 transitions. [2022-02-21 04:22:03,083 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:03,084 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:03,085 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1245 transitions. [2022-02-21 04:22:03,086 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1245 transitions. [2022-02-21 04:22:03,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:03,114 INFO L93 Difference]: Finished difference Result 835 states and 1245 transitions. [2022-02-21 04:22:03,114 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1245 transitions. [2022-02-21 04:22:03,115 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:03,116 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:03,116 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:03,116 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:03,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4910179640718564) internal successors, (1245), 834 states have internal predecessors, (1245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1245 transitions. [2022-02-21 04:22:03,145 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-02-21 04:22:03,145 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1245 transitions. [2022-02-21 04:22:03,145 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2022-02-21 04:22:03,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1245 transitions. [2022-02-21 04:22:03,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:03,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:03,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:03,149 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:03,149 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:03,150 INFO L791 eck$LassoCheckResult]: Stem: 15724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15178#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15179#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15899#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 15474#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15475#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15594#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15595#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15387#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15174#L573-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15175#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15347#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15348#L781 assume !(0 == ~M_E~0); 15800#L781-2 assume !(0 == ~T1_E~0); 15922#L786-1 assume !(0 == ~T2_E~0); 15138#L791-1 assume !(0 == ~T3_E~0); 15139#L796-1 assume !(0 == ~T4_E~0); 15662#L801-1 assume !(0 == ~T5_E~0); 15663#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15688#L811-1 assume !(0 == ~T7_E~0); 15353#L816-1 assume !(0 == ~E_M~0); 15354#L821-1 assume !(0 == ~E_1~0); 15163#L826-1 assume !(0 == ~E_2~0); 15164#L831-1 assume !(0 == ~E_3~0); 15471#L836-1 assume !(0 == ~E_4~0); 15472#L841-1 assume !(0 == ~E_5~0); 15308#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 15309#L851-1 assume !(0 == ~E_7~0); 15329#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15330#L388 assume !(1 == ~m_pc~0); 15323#L388-2 is_master_triggered_~__retres1~0#1 := 0; 15324#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15772#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15182#L967 assume !(0 != activate_threads_~tmp~1#1); 15183#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15110#L407 assume 1 == ~t1_pc~0; 15111#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15118#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15089#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15090#L975 assume !(0 != activate_threads_~tmp___0~0#1); 15870#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15433#L426 assume !(1 == ~t2_pc~0); 15434#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15885#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15914#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15912#L983 assume !(0 != activate_threads_~tmp___1~0#1); 15913#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15513#L445 assume 1 == ~t3_pc~0; 15514#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15803#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15325#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15326#L991 assume !(0 != activate_threads_~tmp___2~0#1); 15740#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15711#L464 assume !(1 == ~t4_pc~0); 15332#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15203#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15204#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15526#L999 assume !(0 != activate_threads_~tmp___3~0#1); 15489#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15490#L483 assume 1 == ~t5_pc~0; 15708#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15850#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15643#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15644#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 15419#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15420#L502 assume 1 == ~t6_pc~0; 15686#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15234#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15235#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15627#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 15628#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15827#L521 assume !(1 == ~t7_pc~0); 15866#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15176#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15177#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15284#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15834#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15761#L869 assume !(1 == ~M_E~0); 15482#L869-2 assume !(1 == ~T1_E~0); 15483#L874-1 assume !(1 == ~T2_E~0); 15895#L879-1 assume !(1 == ~T3_E~0); 15563#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15098#L889-1 assume !(1 == ~T5_E~0); 15099#L894-1 assume !(1 == ~T6_E~0); 15360#L899-1 assume !(1 == ~T7_E~0); 15728#L904-1 assume !(1 == ~E_M~0); 15505#L909-1 assume !(1 == ~E_1~0); 15506#L914-1 assume !(1 == ~E_2~0); 15675#L919-1 assume !(1 == ~E_3~0); 15432#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15272#L929-1 assume !(1 == ~E_5~0); 15273#L934-1 assume !(1 == ~E_6~0); 15485#L939-1 assume !(1 == ~E_7~0); 15486#L944-1 assume { :end_inline_reset_delta_events } true; 15342#L1190-2 [2022-02-21 04:22:03,151 INFO L793 eck$LassoCheckResult]: Loop: 15342#L1190-2 assume !false; 15355#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15356#L756 assume !false; 15578#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15918#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15196#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15704#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15527#L653 assume !(0 != eval_~tmp~0#1); 15529#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15569#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15570#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15215#L781-5 assume !(0 == ~T1_E~0); 15216#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15536#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15159#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15160#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15417#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15418#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15602#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15789#L821-3 assume !(0 == ~E_1~0); 15886#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15735#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15736#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15316#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15317#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15626#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15210#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15211#L388-27 assume 1 == ~m_pc~0; 15861#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15863#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15832#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15833#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15390#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15391#L407-27 assume 1 == ~t1_pc~0; 15741#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15742#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15614#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15615#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15646#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15310#L426-27 assume 1 == ~t2_pc~0; 15312#L427-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15321#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15322#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15846#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15859#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15597#L445-27 assume 1 == ~t3_pc~0; 15575#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15156#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15157#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15577#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15680#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15411#L464-27 assume !(1 == ~t4_pc~0); 15154#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 15155#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15222#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15603#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15302#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15303#L483-27 assume 1 == ~t5_pc~0; 15808#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15212#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15213#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15822#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 15823#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15902#L502-27 assume !(1 == ~t6_pc~0); 15622#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15623#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15872#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15758#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15759#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15100#L521-27 assume !(1 == ~t7_pc~0); 15101#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 15443#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15590#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15150#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15151#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15638#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15755#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15534#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15535#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15593#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15589#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15260#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15261#L899-3 assume !(1 == ~T7_E~0); 15288#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15289#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15236#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15237#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15280#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15747#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15676#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15677#L939-3 assume !(1 == ~E_7~0); 15295#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15296#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15116#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15543#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15544#L1209 assume !(0 == start_simulation_~tmp~3#1); 15618#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15601#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15253#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15649#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15650#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15144#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15145#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15341#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 15342#L1190-2 [2022-02-21 04:22:03,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,152 INFO L85 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2022-02-21 04:22:03,152 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,152 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593516087] [2022-02-21 04:22:03,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:03,187 INFO L290 TraceCheckUtils]: 0: Hoare triple {17597#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {17597#true} is VALID [2022-02-21 04:22:03,188 INFO L290 TraceCheckUtils]: 1: Hoare triple {17597#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,188 INFO L290 TraceCheckUtils]: 2: Hoare triple {17599#(= ~t6_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,189 INFO L290 TraceCheckUtils]: 3: Hoare triple {17599#(= ~t6_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,189 INFO L290 TraceCheckUtils]: 4: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,189 INFO L290 TraceCheckUtils]: 5: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,190 INFO L290 TraceCheckUtils]: 6: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,190 INFO L290 TraceCheckUtils]: 7: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,190 INFO L290 TraceCheckUtils]: 8: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,191 INFO L290 TraceCheckUtils]: 9: Hoare triple {17599#(= ~t6_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {17599#(= ~t6_i~0 1)} is VALID [2022-02-21 04:22:03,191 INFO L290 TraceCheckUtils]: 10: Hoare triple {17599#(= ~t6_i~0 1)} assume !(1 == ~t6_i~0);~t6_st~0 := 2; {17598#false} is VALID [2022-02-21 04:22:03,191 INFO L290 TraceCheckUtils]: 11: Hoare triple {17598#false} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {17598#false} is VALID [2022-02-21 04:22:03,191 INFO L290 TraceCheckUtils]: 12: Hoare triple {17598#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 13: Hoare triple {17598#false} assume !(0 == ~M_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {17598#false} assume !(0 == ~T1_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 15: Hoare triple {17598#false} assume !(0 == ~T2_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 16: Hoare triple {17598#false} assume !(0 == ~T3_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 17: Hoare triple {17598#false} assume !(0 == ~T4_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 18: Hoare triple {17598#false} assume !(0 == ~T5_E~0); {17598#false} is VALID [2022-02-21 04:22:03,192 INFO L290 TraceCheckUtils]: 19: Hoare triple {17598#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 20: Hoare triple {17598#false} assume !(0 == ~T7_E~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 21: Hoare triple {17598#false} assume !(0 == ~E_M~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 22: Hoare triple {17598#false} assume !(0 == ~E_1~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 23: Hoare triple {17598#false} assume !(0 == ~E_2~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 24: Hoare triple {17598#false} assume !(0 == ~E_3~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 25: Hoare triple {17598#false} assume !(0 == ~E_4~0); {17598#false} is VALID [2022-02-21 04:22:03,193 INFO L290 TraceCheckUtils]: 26: Hoare triple {17598#false} assume !(0 == ~E_5~0); {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 27: Hoare triple {17598#false} assume 0 == ~E_6~0;~E_6~0 := 1; {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 28: Hoare triple {17598#false} assume !(0 == ~E_7~0); {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 29: Hoare triple {17598#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 30: Hoare triple {17598#false} assume !(1 == ~m_pc~0); {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 31: Hoare triple {17598#false} is_master_triggered_~__retres1~0#1 := 0; {17598#false} is VALID [2022-02-21 04:22:03,194 INFO L290 TraceCheckUtils]: 32: Hoare triple {17598#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 33: Hoare triple {17598#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 34: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp~1#1); {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 35: Hoare triple {17598#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 36: Hoare triple {17598#false} assume 1 == ~t1_pc~0; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 37: Hoare triple {17598#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 38: Hoare triple {17598#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17598#false} is VALID [2022-02-21 04:22:03,195 INFO L290 TraceCheckUtils]: 39: Hoare triple {17598#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 40: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___0~0#1); {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 41: Hoare triple {17598#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 42: Hoare triple {17598#false} assume !(1 == ~t2_pc~0); {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 43: Hoare triple {17598#false} is_transmit2_triggered_~__retres1~2#1 := 0; {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 44: Hoare triple {17598#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 45: Hoare triple {17598#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17598#false} is VALID [2022-02-21 04:22:03,196 INFO L290 TraceCheckUtils]: 46: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___1~0#1); {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 47: Hoare triple {17598#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 48: Hoare triple {17598#false} assume 1 == ~t3_pc~0; {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 49: Hoare triple {17598#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 50: Hoare triple {17598#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 51: Hoare triple {17598#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 52: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___2~0#1); {17598#false} is VALID [2022-02-21 04:22:03,197 INFO L290 TraceCheckUtils]: 53: Hoare triple {17598#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 54: Hoare triple {17598#false} assume !(1 == ~t4_pc~0); {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 55: Hoare triple {17598#false} is_transmit4_triggered_~__retres1~4#1 := 0; {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 56: Hoare triple {17598#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 57: Hoare triple {17598#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 58: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___3~0#1); {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 59: Hoare triple {17598#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17598#false} is VALID [2022-02-21 04:22:03,198 INFO L290 TraceCheckUtils]: 60: Hoare triple {17598#false} assume 1 == ~t5_pc~0; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 61: Hoare triple {17598#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 62: Hoare triple {17598#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 63: Hoare triple {17598#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 64: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___4~0#1); {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 65: Hoare triple {17598#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 66: Hoare triple {17598#false} assume 1 == ~t6_pc~0; {17598#false} is VALID [2022-02-21 04:22:03,199 INFO L290 TraceCheckUtils]: 67: Hoare triple {17598#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 68: Hoare triple {17598#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 69: Hoare triple {17598#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 70: Hoare triple {17598#false} assume !(0 != activate_threads_~tmp___5~0#1); {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 71: Hoare triple {17598#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 72: Hoare triple {17598#false} assume !(1 == ~t7_pc~0); {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 73: Hoare triple {17598#false} is_transmit7_triggered_~__retres1~7#1 := 0; {17598#false} is VALID [2022-02-21 04:22:03,200 INFO L290 TraceCheckUtils]: 74: Hoare triple {17598#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 75: Hoare triple {17598#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 76: Hoare triple {17598#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 77: Hoare triple {17598#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 78: Hoare triple {17598#false} assume !(1 == ~M_E~0); {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 79: Hoare triple {17598#false} assume !(1 == ~T1_E~0); {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 80: Hoare triple {17598#false} assume !(1 == ~T2_E~0); {17598#false} is VALID [2022-02-21 04:22:03,201 INFO L290 TraceCheckUtils]: 81: Hoare triple {17598#false} assume !(1 == ~T3_E~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 82: Hoare triple {17598#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 83: Hoare triple {17598#false} assume !(1 == ~T5_E~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 84: Hoare triple {17598#false} assume !(1 == ~T6_E~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 85: Hoare triple {17598#false} assume !(1 == ~T7_E~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 86: Hoare triple {17598#false} assume !(1 == ~E_M~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 87: Hoare triple {17598#false} assume !(1 == ~E_1~0); {17598#false} is VALID [2022-02-21 04:22:03,202 INFO L290 TraceCheckUtils]: 88: Hoare triple {17598#false} assume !(1 == ~E_2~0); {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 89: Hoare triple {17598#false} assume !(1 == ~E_3~0); {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 90: Hoare triple {17598#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 91: Hoare triple {17598#false} assume !(1 == ~E_5~0); {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 92: Hoare triple {17598#false} assume !(1 == ~E_6~0); {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 93: Hoare triple {17598#false} assume !(1 == ~E_7~0); {17598#false} is VALID [2022-02-21 04:22:03,203 INFO L290 TraceCheckUtils]: 94: Hoare triple {17598#false} assume { :end_inline_reset_delta_events } true; {17598#false} is VALID [2022-02-21 04:22:03,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:03,204 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:03,204 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593516087] [2022-02-21 04:22:03,204 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593516087] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:03,204 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:03,205 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:03,205 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043438370] [2022-02-21 04:22:03,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:03,205 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:03,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:03,206 INFO L85 PathProgramCache]: Analyzing trace with hash -1001713119, now seen corresponding path program 1 times [2022-02-21 04:22:03,206 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:03,206 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [235166194] [2022-02-21 04:22:03,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:03,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:03,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:03,239 INFO L290 TraceCheckUtils]: 0: Hoare triple {17600#true} assume !false; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 1: Hoare triple {17600#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 2: Hoare triple {17600#true} assume !false; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 3: Hoare triple {17600#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 4: Hoare triple {17600#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 5: Hoare triple {17600#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 6: Hoare triple {17600#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 7: Hoare triple {17600#true} assume !(0 != eval_~tmp~0#1); {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 8: Hoare triple {17600#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 9: Hoare triple {17600#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {17600#true} is VALID [2022-02-21 04:22:03,240 INFO L290 TraceCheckUtils]: 10: Hoare triple {17600#true} assume 0 == ~M_E~0;~M_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 11: Hoare triple {17600#true} assume !(0 == ~T1_E~0); {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 12: Hoare triple {17600#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 13: Hoare triple {17600#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 14: Hoare triple {17600#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 15: Hoare triple {17600#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 16: Hoare triple {17600#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {17600#true} is VALID [2022-02-21 04:22:03,241 INFO L290 TraceCheckUtils]: 17: Hoare triple {17600#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,242 INFO L290 TraceCheckUtils]: 18: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,242 INFO L290 TraceCheckUtils]: 19: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,242 INFO L290 TraceCheckUtils]: 20: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,243 INFO L290 TraceCheckUtils]: 21: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,243 INFO L290 TraceCheckUtils]: 22: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,243 INFO L290 TraceCheckUtils]: 23: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,243 INFO L290 TraceCheckUtils]: 24: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,244 INFO L290 TraceCheckUtils]: 25: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,244 INFO L290 TraceCheckUtils]: 26: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,244 INFO L290 TraceCheckUtils]: 27: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,245 INFO L290 TraceCheckUtils]: 28: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,245 INFO L290 TraceCheckUtils]: 29: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,245 INFO L290 TraceCheckUtils]: 30: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,246 INFO L290 TraceCheckUtils]: 31: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,246 INFO L290 TraceCheckUtils]: 32: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,246 INFO L290 TraceCheckUtils]: 33: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,246 INFO L290 TraceCheckUtils]: 34: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,247 INFO L290 TraceCheckUtils]: 35: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,247 INFO L290 TraceCheckUtils]: 36: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,247 INFO L290 TraceCheckUtils]: 37: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,248 INFO L290 TraceCheckUtils]: 38: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,248 INFO L290 TraceCheckUtils]: 39: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t2_pc~0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,248 INFO L290 TraceCheckUtils]: 40: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,249 INFO L290 TraceCheckUtils]: 41: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,249 INFO L290 TraceCheckUtils]: 42: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,249 INFO L290 TraceCheckUtils]: 43: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,249 INFO L290 TraceCheckUtils]: 44: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,250 INFO L290 TraceCheckUtils]: 45: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,250 INFO L290 TraceCheckUtils]: 46: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,250 INFO L290 TraceCheckUtils]: 47: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,251 INFO L290 TraceCheckUtils]: 48: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,251 INFO L290 TraceCheckUtils]: 49: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,251 INFO L290 TraceCheckUtils]: 50: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,251 INFO L290 TraceCheckUtils]: 51: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,252 INFO L290 TraceCheckUtils]: 52: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,252 INFO L290 TraceCheckUtils]: 53: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,252 INFO L290 TraceCheckUtils]: 54: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,253 INFO L290 TraceCheckUtils]: 55: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,253 INFO L290 TraceCheckUtils]: 56: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,253 INFO L290 TraceCheckUtils]: 57: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,253 INFO L290 TraceCheckUtils]: 58: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,254 INFO L290 TraceCheckUtils]: 59: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,254 INFO L290 TraceCheckUtils]: 60: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,254 INFO L290 TraceCheckUtils]: 61: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,255 INFO L290 TraceCheckUtils]: 62: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,255 INFO L290 TraceCheckUtils]: 63: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,255 INFO L290 TraceCheckUtils]: 64: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,256 INFO L290 TraceCheckUtils]: 65: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,256 INFO L290 TraceCheckUtils]: 66: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,256 INFO L290 TraceCheckUtils]: 67: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,256 INFO L290 TraceCheckUtils]: 68: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,257 INFO L290 TraceCheckUtils]: 69: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,257 INFO L290 TraceCheckUtils]: 70: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,257 INFO L290 TraceCheckUtils]: 71: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,258 INFO L290 TraceCheckUtils]: 72: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,258 INFO L290 TraceCheckUtils]: 73: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,258 INFO L290 TraceCheckUtils]: 74: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,258 INFO L290 TraceCheckUtils]: 75: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,259 INFO L290 TraceCheckUtils]: 76: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,259 INFO L290 TraceCheckUtils]: 77: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,259 INFO L290 TraceCheckUtils]: 78: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,260 INFO L290 TraceCheckUtils]: 79: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,260 INFO L290 TraceCheckUtils]: 80: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,260 INFO L290 TraceCheckUtils]: 81: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {17602#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:03,260 INFO L290 TraceCheckUtils]: 82: Hoare triple {17602#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 83: Hoare triple {17601#false} assume 1 == ~E_M~0;~E_M~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 84: Hoare triple {17601#false} assume 1 == ~E_1~0;~E_1~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 85: Hoare triple {17601#false} assume 1 == ~E_2~0;~E_2~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 86: Hoare triple {17601#false} assume 1 == ~E_3~0;~E_3~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 87: Hoare triple {17601#false} assume 1 == ~E_4~0;~E_4~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 88: Hoare triple {17601#false} assume 1 == ~E_5~0;~E_5~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 89: Hoare triple {17601#false} assume 1 == ~E_6~0;~E_6~0 := 2; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 90: Hoare triple {17601#false} assume !(1 == ~E_7~0); {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 91: Hoare triple {17601#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17601#false} is VALID [2022-02-21 04:22:03,261 INFO L290 TraceCheckUtils]: 92: Hoare triple {17601#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 93: Hoare triple {17601#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 94: Hoare triple {17601#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 95: Hoare triple {17601#false} assume !(0 == start_simulation_~tmp~3#1); {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 96: Hoare triple {17601#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 97: Hoare triple {17601#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 98: Hoare triple {17601#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 99: Hoare triple {17601#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 100: Hoare triple {17601#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 101: Hoare triple {17601#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {17601#false} is VALID [2022-02-21 04:22:03,262 INFO L290 TraceCheckUtils]: 102: Hoare triple {17601#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {17601#false} is VALID [2022-02-21 04:22:03,263 INFO L290 TraceCheckUtils]: 103: Hoare triple {17601#false} assume !(0 != start_simulation_~tmp___0~1#1); {17601#false} is VALID [2022-02-21 04:22:03,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:03,263 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:03,263 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [235166194] [2022-02-21 04:22:03,263 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [235166194] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:03,264 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:03,264 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:03,264 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606264750] [2022-02-21 04:22:03,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:03,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:03,265 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:03,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:03,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:03,265 INFO L87 Difference]: Start difference. First operand 835 states and 1245 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:03,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:03,967 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2022-02-21 04:22:03,967 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:03,967 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,028 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:04,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:04,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1244 transitions. [2022-02-21 04:22:04,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:22:04,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:22:04,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:04,089 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-02-21 04:22:04,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:22:04,098 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:04,099 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1244 transitions. Second operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,101 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1244 transitions. Second operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,102 INFO L87 Difference]: Start difference. First operand 835 states and 1244 transitions. Second operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,130 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2022-02-21 04:22:04,130 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,131 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:04,131 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:04,133 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1244 transitions. [2022-02-21 04:22:04,134 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1244 transitions. [2022-02-21 04:22:04,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,162 INFO L93 Difference]: Finished difference Result 835 states and 1244 transitions. [2022-02-21 04:22:04,162 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,163 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:04,163 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:04,163 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:04,163 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:04,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.4898203592814372) internal successors, (1244), 834 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1244 transitions. [2022-02-21 04:22:04,192 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-02-21 04:22:04,192 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1244 transitions. [2022-02-21 04:22:04,193 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2022-02-21 04:22:04,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1244 transitions. [2022-02-21 04:22:04,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:04,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:04,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:04,197 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:04,197 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:04,198 INFO L791 eck$LassoCheckResult]: Stem: 19073#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 19074#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 18527#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18528#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19248#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 18823#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18824#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18943#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18944#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18736#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18523#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18524#L578-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18693#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18694#L781 assume !(0 == ~M_E~0); 19148#L781-2 assume !(0 == ~T1_E~0); 19271#L786-1 assume !(0 == ~T2_E~0); 18484#L791-1 assume !(0 == ~T3_E~0); 18485#L796-1 assume !(0 == ~T4_E~0); 19010#L801-1 assume !(0 == ~T5_E~0); 19011#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19037#L811-1 assume !(0 == ~T7_E~0); 18702#L816-1 assume !(0 == ~E_M~0); 18703#L821-1 assume !(0 == ~E_1~0); 18512#L826-1 assume !(0 == ~E_2~0); 18513#L831-1 assume !(0 == ~E_3~0); 18820#L836-1 assume !(0 == ~E_4~0); 18821#L841-1 assume !(0 == ~E_5~0); 18655#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 18656#L851-1 assume !(0 == ~E_7~0); 18678#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18679#L388 assume !(1 == ~m_pc~0); 18672#L388-2 is_master_triggered_~__retres1~0#1 := 0; 18673#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19121#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18531#L967 assume !(0 != activate_threads_~tmp~1#1); 18532#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18459#L407 assume 1 == ~t1_pc~0; 18460#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18464#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18438#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18439#L975 assume !(0 != activate_threads_~tmp___0~0#1); 19219#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18782#L426 assume !(1 == ~t2_pc~0); 18783#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 19234#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19263#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19261#L983 assume !(0 != activate_threads_~tmp___1~0#1); 19262#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18862#L445 assume 1 == ~t3_pc~0; 18863#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19152#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18674#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18675#L991 assume !(0 != activate_threads_~tmp___2~0#1); 19089#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19060#L464 assume !(1 == ~t4_pc~0); 18681#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18552#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18553#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18873#L999 assume !(0 != activate_threads_~tmp___3~0#1); 18838#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18839#L483 assume 1 == ~t5_pc~0; 19057#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19199#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18992#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18993#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 18766#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18767#L502 assume 1 == ~t6_pc~0; 19034#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18583#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18584#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18976#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 18977#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19176#L521 assume !(1 == ~t7_pc~0); 19215#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18525#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18526#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18633#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19183#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19110#L869 assume !(1 == ~M_E~0); 18831#L869-2 assume !(1 == ~T1_E~0); 18832#L874-1 assume !(1 == ~T2_E~0); 19244#L879-1 assume !(1 == ~T3_E~0); 18912#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18447#L889-1 assume !(1 == ~T5_E~0); 18448#L894-1 assume !(1 == ~T6_E~0); 18709#L899-1 assume !(1 == ~T7_E~0); 19077#L904-1 assume !(1 == ~E_M~0); 18854#L909-1 assume !(1 == ~E_1~0); 18855#L914-1 assume !(1 == ~E_2~0); 19024#L919-1 assume !(1 == ~E_3~0); 18781#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18621#L929-1 assume !(1 == ~E_5~0); 18622#L934-1 assume !(1 == ~E_6~0); 18834#L939-1 assume !(1 == ~E_7~0); 18835#L944-1 assume { :end_inline_reset_delta_events } true; 18691#L1190-2 [2022-02-21 04:22:04,198 INFO L793 eck$LassoCheckResult]: Loop: 18691#L1190-2 assume !false; 18704#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18705#L756 assume !false; 18927#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 19267#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18545#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19053#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18876#L653 assume !(0 != eval_~tmp~0#1); 18878#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18918#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18919#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18564#L781-5 assume !(0 == ~T1_E~0); 18565#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18885#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18508#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18509#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18768#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18769#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18951#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19138#L821-3 assume !(0 == ~E_1~0); 19235#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19084#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19085#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18665#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18666#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18975#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18559#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18560#L388-27 assume 1 == ~m_pc~0; 19210#L389-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19212#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19181#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19182#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18739#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18740#L407-27 assume 1 == ~t1_pc~0; 19090#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19091#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18963#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18964#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18995#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18659#L426-27 assume !(1 == ~t2_pc~0); 18660#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 18670#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18671#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19195#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19208#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18946#L445-27 assume 1 == ~t3_pc~0; 18924#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18505#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18506#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18926#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19029#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18760#L464-27 assume !(1 == ~t4_pc~0); 18503#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 18504#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18571#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18952#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18651#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18652#L483-27 assume 1 == ~t5_pc~0; 19157#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18561#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18562#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19171#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 19172#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19251#L502-27 assume 1 == ~t6_pc~0; 19252#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18972#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19221#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19107#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19108#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18449#L521-27 assume !(1 == ~t7_pc~0); 18450#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 18792#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18939#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18499#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18500#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18987#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19104#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18883#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18884#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18942#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18938#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18609#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18610#L899-3 assume !(1 == ~T7_E~0); 18637#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 18638#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18585#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18586#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18629#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19096#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19025#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19026#L939-3 assume !(1 == ~E_7~0); 18644#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 18645#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18466#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 18892#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 18893#L1209 assume !(0 == start_simulation_~tmp~3#1); 18967#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 18950#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 18602#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 18998#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 18999#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18493#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18494#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 18690#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 18691#L1190-2 [2022-02-21 04:22:04,199 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:04,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2022-02-21 04:22:04,199 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:04,199 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609868291] [2022-02-21 04:22:04,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:04,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:04,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:04,223 INFO L290 TraceCheckUtils]: 0: Hoare triple {20946#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {20946#true} is VALID [2022-02-21 04:22:04,223 INFO L290 TraceCheckUtils]: 1: Hoare triple {20946#true} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,224 INFO L290 TraceCheckUtils]: 2: Hoare triple {20948#(= ~t7_i~0 1)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,224 INFO L290 TraceCheckUtils]: 3: Hoare triple {20948#(= ~t7_i~0 1)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,224 INFO L290 TraceCheckUtils]: 4: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~m_i~0;~m_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,225 INFO L290 TraceCheckUtils]: 5: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,225 INFO L290 TraceCheckUtils]: 6: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,225 INFO L290 TraceCheckUtils]: 7: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,226 INFO L290 TraceCheckUtils]: 8: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,226 INFO L290 TraceCheckUtils]: 9: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,226 INFO L290 TraceCheckUtils]: 10: Hoare triple {20948#(= ~t7_i~0 1)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {20948#(= ~t7_i~0 1)} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 11: Hoare triple {20948#(= ~t7_i~0 1)} assume !(1 == ~t7_i~0);~t7_st~0 := 2; {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 12: Hoare triple {20947#false} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 13: Hoare triple {20947#false} assume !(0 == ~M_E~0); {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 14: Hoare triple {20947#false} assume !(0 == ~T1_E~0); {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 15: Hoare triple {20947#false} assume !(0 == ~T2_E~0); {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 16: Hoare triple {20947#false} assume !(0 == ~T3_E~0); {20947#false} is VALID [2022-02-21 04:22:04,227 INFO L290 TraceCheckUtils]: 17: Hoare triple {20947#false} assume !(0 == ~T4_E~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 18: Hoare triple {20947#false} assume !(0 == ~T5_E~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 19: Hoare triple {20947#false} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 20: Hoare triple {20947#false} assume !(0 == ~T7_E~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 21: Hoare triple {20947#false} assume !(0 == ~E_M~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 22: Hoare triple {20947#false} assume !(0 == ~E_1~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 23: Hoare triple {20947#false} assume !(0 == ~E_2~0); {20947#false} is VALID [2022-02-21 04:22:04,228 INFO L290 TraceCheckUtils]: 24: Hoare triple {20947#false} assume !(0 == ~E_3~0); {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 25: Hoare triple {20947#false} assume !(0 == ~E_4~0); {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 26: Hoare triple {20947#false} assume !(0 == ~E_5~0); {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 27: Hoare triple {20947#false} assume 0 == ~E_6~0;~E_6~0 := 1; {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 28: Hoare triple {20947#false} assume !(0 == ~E_7~0); {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 29: Hoare triple {20947#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 30: Hoare triple {20947#false} assume !(1 == ~m_pc~0); {20947#false} is VALID [2022-02-21 04:22:04,229 INFO L290 TraceCheckUtils]: 31: Hoare triple {20947#false} is_master_triggered_~__retres1~0#1 := 0; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 32: Hoare triple {20947#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 33: Hoare triple {20947#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 34: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp~1#1); {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 35: Hoare triple {20947#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 36: Hoare triple {20947#false} assume 1 == ~t1_pc~0; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 37: Hoare triple {20947#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20947#false} is VALID [2022-02-21 04:22:04,230 INFO L290 TraceCheckUtils]: 38: Hoare triple {20947#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 39: Hoare triple {20947#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 40: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___0~0#1); {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 41: Hoare triple {20947#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 42: Hoare triple {20947#false} assume !(1 == ~t2_pc~0); {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 43: Hoare triple {20947#false} is_transmit2_triggered_~__retres1~2#1 := 0; {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 44: Hoare triple {20947#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20947#false} is VALID [2022-02-21 04:22:04,231 INFO L290 TraceCheckUtils]: 45: Hoare triple {20947#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 46: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___1~0#1); {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 47: Hoare triple {20947#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 48: Hoare triple {20947#false} assume 1 == ~t3_pc~0; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 49: Hoare triple {20947#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 50: Hoare triple {20947#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 51: Hoare triple {20947#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20947#false} is VALID [2022-02-21 04:22:04,232 INFO L290 TraceCheckUtils]: 52: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___2~0#1); {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 53: Hoare triple {20947#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 54: Hoare triple {20947#false} assume !(1 == ~t4_pc~0); {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 55: Hoare triple {20947#false} is_transmit4_triggered_~__retres1~4#1 := 0; {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 56: Hoare triple {20947#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 57: Hoare triple {20947#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 58: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___3~0#1); {20947#false} is VALID [2022-02-21 04:22:04,233 INFO L290 TraceCheckUtils]: 59: Hoare triple {20947#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 60: Hoare triple {20947#false} assume 1 == ~t5_pc~0; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 61: Hoare triple {20947#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 62: Hoare triple {20947#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 63: Hoare triple {20947#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 64: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___4~0#1); {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 65: Hoare triple {20947#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20947#false} is VALID [2022-02-21 04:22:04,234 INFO L290 TraceCheckUtils]: 66: Hoare triple {20947#false} assume 1 == ~t6_pc~0; {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 67: Hoare triple {20947#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 68: Hoare triple {20947#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 69: Hoare triple {20947#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 70: Hoare triple {20947#false} assume !(0 != activate_threads_~tmp___5~0#1); {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 71: Hoare triple {20947#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 72: Hoare triple {20947#false} assume !(1 == ~t7_pc~0); {20947#false} is VALID [2022-02-21 04:22:04,235 INFO L290 TraceCheckUtils]: 73: Hoare triple {20947#false} is_transmit7_triggered_~__retres1~7#1 := 0; {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 74: Hoare triple {20947#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 75: Hoare triple {20947#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 76: Hoare triple {20947#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 77: Hoare triple {20947#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 78: Hoare triple {20947#false} assume !(1 == ~M_E~0); {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 79: Hoare triple {20947#false} assume !(1 == ~T1_E~0); {20947#false} is VALID [2022-02-21 04:22:04,236 INFO L290 TraceCheckUtils]: 80: Hoare triple {20947#false} assume !(1 == ~T2_E~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 81: Hoare triple {20947#false} assume !(1 == ~T3_E~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 82: Hoare triple {20947#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 83: Hoare triple {20947#false} assume !(1 == ~T5_E~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 84: Hoare triple {20947#false} assume !(1 == ~T6_E~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 85: Hoare triple {20947#false} assume !(1 == ~T7_E~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 86: Hoare triple {20947#false} assume !(1 == ~E_M~0); {20947#false} is VALID [2022-02-21 04:22:04,237 INFO L290 TraceCheckUtils]: 87: Hoare triple {20947#false} assume !(1 == ~E_1~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 88: Hoare triple {20947#false} assume !(1 == ~E_2~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 89: Hoare triple {20947#false} assume !(1 == ~E_3~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 90: Hoare triple {20947#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 91: Hoare triple {20947#false} assume !(1 == ~E_5~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 92: Hoare triple {20947#false} assume !(1 == ~E_6~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 93: Hoare triple {20947#false} assume !(1 == ~E_7~0); {20947#false} is VALID [2022-02-21 04:22:04,238 INFO L290 TraceCheckUtils]: 94: Hoare triple {20947#false} assume { :end_inline_reset_delta_events } true; {20947#false} is VALID [2022-02-21 04:22:04,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:04,239 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:04,239 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [609868291] [2022-02-21 04:22:04,239 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [609868291] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:04,239 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:04,240 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:04,240 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502312173] [2022-02-21 04:22:04,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:04,240 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:04,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:04,241 INFO L85 PathProgramCache]: Analyzing trace with hash -138895583, now seen corresponding path program 2 times [2022-02-21 04:22:04,241 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:04,241 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442308030] [2022-02-21 04:22:04,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:04,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:04,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:04,266 INFO L290 TraceCheckUtils]: 0: Hoare triple {20949#true} assume !false; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 1: Hoare triple {20949#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 2: Hoare triple {20949#true} assume !false; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 3: Hoare triple {20949#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 4: Hoare triple {20949#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 5: Hoare triple {20949#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 6: Hoare triple {20949#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {20949#true} is VALID [2022-02-21 04:22:04,267 INFO L290 TraceCheckUtils]: 7: Hoare triple {20949#true} assume !(0 != eval_~tmp~0#1); {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 8: Hoare triple {20949#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 9: Hoare triple {20949#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 10: Hoare triple {20949#true} assume 0 == ~M_E~0;~M_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 11: Hoare triple {20949#true} assume !(0 == ~T1_E~0); {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 12: Hoare triple {20949#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 13: Hoare triple {20949#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,268 INFO L290 TraceCheckUtils]: 14: Hoare triple {20949#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,269 INFO L290 TraceCheckUtils]: 15: Hoare triple {20949#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,269 INFO L290 TraceCheckUtils]: 16: Hoare triple {20949#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {20949#true} is VALID [2022-02-21 04:22:04,269 INFO L290 TraceCheckUtils]: 17: Hoare triple {20949#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,269 INFO L290 TraceCheckUtils]: 18: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,270 INFO L290 TraceCheckUtils]: 19: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,270 INFO L290 TraceCheckUtils]: 20: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,270 INFO L290 TraceCheckUtils]: 21: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,271 INFO L290 TraceCheckUtils]: 22: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,271 INFO L290 TraceCheckUtils]: 23: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,271 INFO L290 TraceCheckUtils]: 24: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,272 INFO L290 TraceCheckUtils]: 25: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,272 INFO L290 TraceCheckUtils]: 26: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,272 INFO L290 TraceCheckUtils]: 27: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~m_pc~0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,273 INFO L290 TraceCheckUtils]: 28: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,273 INFO L290 TraceCheckUtils]: 29: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,273 INFO L290 TraceCheckUtils]: 30: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,274 INFO L290 TraceCheckUtils]: 31: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,274 INFO L290 TraceCheckUtils]: 32: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,274 INFO L290 TraceCheckUtils]: 33: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,275 INFO L290 TraceCheckUtils]: 34: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,275 INFO L290 TraceCheckUtils]: 35: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,275 INFO L290 TraceCheckUtils]: 36: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,276 INFO L290 TraceCheckUtils]: 37: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,276 INFO L290 TraceCheckUtils]: 38: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,276 INFO L290 TraceCheckUtils]: 39: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,276 INFO L290 TraceCheckUtils]: 40: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,277 INFO L290 TraceCheckUtils]: 41: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,277 INFO L290 TraceCheckUtils]: 42: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,277 INFO L290 TraceCheckUtils]: 43: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,278 INFO L290 TraceCheckUtils]: 44: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,278 INFO L290 TraceCheckUtils]: 45: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,278 INFO L290 TraceCheckUtils]: 46: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,279 INFO L290 TraceCheckUtils]: 47: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,279 INFO L290 TraceCheckUtils]: 48: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,279 INFO L290 TraceCheckUtils]: 49: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,280 INFO L290 TraceCheckUtils]: 50: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,280 INFO L290 TraceCheckUtils]: 51: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,280 INFO L290 TraceCheckUtils]: 52: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,281 INFO L290 TraceCheckUtils]: 53: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,281 INFO L290 TraceCheckUtils]: 54: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,281 INFO L290 TraceCheckUtils]: 55: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,282 INFO L290 TraceCheckUtils]: 56: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,282 INFO L290 TraceCheckUtils]: 57: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,282 INFO L290 TraceCheckUtils]: 58: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,283 INFO L290 TraceCheckUtils]: 59: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,283 INFO L290 TraceCheckUtils]: 60: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,283 INFO L290 TraceCheckUtils]: 61: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,283 INFO L290 TraceCheckUtils]: 62: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,284 INFO L290 TraceCheckUtils]: 63: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,284 INFO L290 TraceCheckUtils]: 64: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,284 INFO L290 TraceCheckUtils]: 65: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,285 INFO L290 TraceCheckUtils]: 66: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,285 INFO L290 TraceCheckUtils]: 67: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,285 INFO L290 TraceCheckUtils]: 68: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,286 INFO L290 TraceCheckUtils]: 69: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,286 INFO L290 TraceCheckUtils]: 70: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,286 INFO L290 TraceCheckUtils]: 71: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,287 INFO L290 TraceCheckUtils]: 72: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,287 INFO L290 TraceCheckUtils]: 73: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,287 INFO L290 TraceCheckUtils]: 74: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,288 INFO L290 TraceCheckUtils]: 75: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,288 INFO L290 TraceCheckUtils]: 76: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,288 INFO L290 TraceCheckUtils]: 77: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,289 INFO L290 TraceCheckUtils]: 78: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,289 INFO L290 TraceCheckUtils]: 79: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,289 INFO L290 TraceCheckUtils]: 80: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,289 INFO L290 TraceCheckUtils]: 81: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {20951#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:04,290 INFO L290 TraceCheckUtils]: 82: Hoare triple {20951#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {20950#false} is VALID [2022-02-21 04:22:04,290 INFO L290 TraceCheckUtils]: 83: Hoare triple {20950#false} assume 1 == ~E_M~0;~E_M~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,290 INFO L290 TraceCheckUtils]: 84: Hoare triple {20950#false} assume 1 == ~E_1~0;~E_1~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,290 INFO L290 TraceCheckUtils]: 85: Hoare triple {20950#false} assume 1 == ~E_2~0;~E_2~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,290 INFO L290 TraceCheckUtils]: 86: Hoare triple {20950#false} assume 1 == ~E_3~0;~E_3~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 87: Hoare triple {20950#false} assume 1 == ~E_4~0;~E_4~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 88: Hoare triple {20950#false} assume 1 == ~E_5~0;~E_5~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 89: Hoare triple {20950#false} assume 1 == ~E_6~0;~E_6~0 := 2; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 90: Hoare triple {20950#false} assume !(1 == ~E_7~0); {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 91: Hoare triple {20950#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 92: Hoare triple {20950#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 93: Hoare triple {20950#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20950#false} is VALID [2022-02-21 04:22:04,291 INFO L290 TraceCheckUtils]: 94: Hoare triple {20950#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 95: Hoare triple {20950#false} assume !(0 == start_simulation_~tmp~3#1); {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 96: Hoare triple {20950#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 97: Hoare triple {20950#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 98: Hoare triple {20950#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 99: Hoare triple {20950#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 100: Hoare triple {20950#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {20950#false} is VALID [2022-02-21 04:22:04,292 INFO L290 TraceCheckUtils]: 101: Hoare triple {20950#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {20950#false} is VALID [2022-02-21 04:22:04,293 INFO L290 TraceCheckUtils]: 102: Hoare triple {20950#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {20950#false} is VALID [2022-02-21 04:22:04,293 INFO L290 TraceCheckUtils]: 103: Hoare triple {20950#false} assume !(0 != start_simulation_~tmp___0~1#1); {20950#false} is VALID [2022-02-21 04:22:04,293 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:04,293 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:04,294 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442308030] [2022-02-21 04:22:04,294 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442308030] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:04,294 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:04,294 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:04,294 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302575803] [2022-02-21 04:22:04,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:04,295 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:04,295 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:04,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-02-21 04:22:04,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-02-21 04:22:04,296 INFO L87 Difference]: Start difference. First operand 835 states and 1244 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:04,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:04,999 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2022-02-21 04:22:04,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-02-21 04:22:05,000 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,069 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:05,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:05,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 835 states to 835 states and 1243 transitions. [2022-02-21 04:22:05,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 835 [2022-02-21 04:22:05,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 835 [2022-02-21 04:22:05,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:05,127 INFO L681 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-02-21 04:22:05,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 835 to 835. [2022-02-21 04:22:05,136 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:05,138 INFO L82 GeneralOperation]: Start isEquivalent. First operand 835 states and 1243 transitions. Second operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,139 INFO L74 IsIncluded]: Start isIncluded. First operand 835 states and 1243 transitions. Second operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,140 INFO L87 Difference]: Start difference. First operand 835 states and 1243 transitions. Second operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:05,165 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2022-02-21 04:22:05,165 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,166 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:05,166 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:05,167 INFO L74 IsIncluded]: Start isIncluded. First operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1243 transitions. [2022-02-21 04:22:05,168 INFO L87 Difference]: Start difference. First operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 835 states and 1243 transitions. [2022-02-21 04:22:05,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:05,194 INFO L93 Difference]: Finished difference Result 835 states and 1243 transitions. [2022-02-21 04:22:05,194 INFO L276 IsEmpty]: Start isEmpty. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,197 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:05,197 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:05,197 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:05,197 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:05,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 835 states, 835 states have (on average 1.488622754491018) internal successors, (1243), 834 states have internal predecessors, (1243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:05,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 835 states to 835 states and 1243 transitions. [2022-02-21 04:22:05,223 INFO L704 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-02-21 04:22:05,223 INFO L587 BuchiCegarLoop]: Abstraction has 835 states and 1243 transitions. [2022-02-21 04:22:05,223 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2022-02-21 04:22:05,223 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 835 states and 1243 transitions. [2022-02-21 04:22:05,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 732 [2022-02-21 04:22:05,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:05,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:05,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:05,228 INFO L791 eck$LassoCheckResult]: Stem: 22422#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 22423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21876#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21877#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22597#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 22172#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22173#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22292#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22293#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22085#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21872#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21873#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22042#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22043#L781 assume !(0 == ~M_E~0); 22497#L781-2 assume !(0 == ~T1_E~0); 22620#L786-1 assume !(0 == ~T2_E~0); 21833#L791-1 assume !(0 == ~T3_E~0); 21834#L796-1 assume !(0 == ~T4_E~0); 22359#L801-1 assume !(0 == ~T5_E~0); 22360#L806-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22386#L811-1 assume !(0 == ~T7_E~0); 22051#L816-1 assume !(0 == ~E_M~0); 22052#L821-1 assume !(0 == ~E_1~0); 21861#L826-1 assume !(0 == ~E_2~0); 21862#L831-1 assume !(0 == ~E_3~0); 22169#L836-1 assume !(0 == ~E_4~0); 22170#L841-1 assume !(0 == ~E_5~0); 22004#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22005#L851-1 assume !(0 == ~E_7~0); 22027#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22028#L388 assume !(1 == ~m_pc~0); 22021#L388-2 is_master_triggered_~__retres1~0#1 := 0; 22022#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22470#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21880#L967 assume !(0 != activate_threads_~tmp~1#1); 21881#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21808#L407 assume 1 == ~t1_pc~0; 21809#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21813#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21787#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21788#L975 assume !(0 != activate_threads_~tmp___0~0#1); 22568#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22131#L426 assume !(1 == ~t2_pc~0); 22132#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22583#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22612#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22610#L983 assume !(0 != activate_threads_~tmp___1~0#1); 22611#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22211#L445 assume 1 == ~t3_pc~0; 22212#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22501#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22023#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22024#L991 assume !(0 != activate_threads_~tmp___2~0#1); 22438#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22409#L464 assume !(1 == ~t4_pc~0); 22030#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 21901#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21902#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22222#L999 assume !(0 != activate_threads_~tmp___3~0#1); 22187#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22188#L483 assume 1 == ~t5_pc~0; 22406#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22548#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22341#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22342#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 22115#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22116#L502 assume 1 == ~t6_pc~0; 22383#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21932#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21933#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22325#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 22326#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22525#L521 assume !(1 == ~t7_pc~0); 22564#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21874#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21875#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21982#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22532#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22459#L869 assume !(1 == ~M_E~0); 22180#L869-2 assume !(1 == ~T1_E~0); 22181#L874-1 assume !(1 == ~T2_E~0); 22593#L879-1 assume !(1 == ~T3_E~0); 22261#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21796#L889-1 assume !(1 == ~T5_E~0); 21797#L894-1 assume !(1 == ~T6_E~0); 22058#L899-1 assume !(1 == ~T7_E~0); 22426#L904-1 assume !(1 == ~E_M~0); 22203#L909-1 assume !(1 == ~E_1~0); 22204#L914-1 assume !(1 == ~E_2~0); 22373#L919-1 assume !(1 == ~E_3~0); 22130#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21970#L929-1 assume !(1 == ~E_5~0); 21971#L934-1 assume !(1 == ~E_6~0); 22183#L939-1 assume !(1 == ~E_7~0); 22184#L944-1 assume { :end_inline_reset_delta_events } true; 22040#L1190-2 [2022-02-21 04:22:05,231 INFO L793 eck$LassoCheckResult]: Loop: 22040#L1190-2 assume !false; 22053#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22054#L756 assume !false; 22276#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 22616#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21894#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22402#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22225#L653 assume !(0 != eval_~tmp~0#1); 22227#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22267#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22268#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21913#L781-5 assume !(0 == ~T1_E~0); 21914#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22234#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21857#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21858#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22117#L806-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22118#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22300#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22487#L821-3 assume !(0 == ~E_1~0); 22584#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22433#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22434#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22014#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22015#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22324#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21908#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21909#L388-27 assume !(1 == ~m_pc~0); 22560#L388-29 is_master_triggered_~__retres1~0#1 := 0; 22561#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22530#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22531#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22088#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22089#L407-27 assume 1 == ~t1_pc~0; 22439#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22440#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22312#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22313#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22344#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22008#L426-27 assume !(1 == ~t2_pc~0); 22009#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 22019#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22020#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22544#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22557#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22295#L445-27 assume 1 == ~t3_pc~0; 22273#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21854#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21855#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22275#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22378#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22109#L464-27 assume !(1 == ~t4_pc~0); 21852#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 21853#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21920#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22301#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22000#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22001#L483-27 assume 1 == ~t5_pc~0; 22506#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21910#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21911#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22520#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 22521#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22600#L502-27 assume !(1 == ~t6_pc~0); 22320#L502-29 is_transmit6_triggered_~__retres1~6#1 := 0; 22321#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22570#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22456#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22457#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21798#L521-27 assume !(1 == ~t7_pc~0); 21799#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 22141#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22288#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21848#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21849#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22336#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22453#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22232#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22233#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22291#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22287#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21958#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21959#L899-3 assume !(1 == ~T7_E~0); 21986#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21987#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21934#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21935#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21978#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22445#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22374#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22375#L939-3 assume !(1 == ~E_7~0); 21993#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21994#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21815#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22241#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 22242#L1209 assume !(0 == start_simulation_~tmp~3#1); 22316#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 22299#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21951#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 22347#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 22348#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21842#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21843#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 22039#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 22040#L1190-2 [2022-02-21 04:22:05,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,232 INFO L85 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2022-02-21 04:22:05,232 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,232 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165240753] [2022-02-21 04:22:05,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,264 INFO L290 TraceCheckUtils]: 0: Hoare triple {24295#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,265 INFO L290 TraceCheckUtils]: 1: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,265 INFO L290 TraceCheckUtils]: 3: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,266 INFO L290 TraceCheckUtils]: 4: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,266 INFO L290 TraceCheckUtils]: 6: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,267 INFO L290 TraceCheckUtils]: 7: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,267 INFO L290 TraceCheckUtils]: 8: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,267 INFO L290 TraceCheckUtils]: 9: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,268 INFO L290 TraceCheckUtils]: 10: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,268 INFO L290 TraceCheckUtils]: 11: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,268 INFO L290 TraceCheckUtils]: 12: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {24297#(= ~T6_E~0 ~M_E~0)} is VALID [2022-02-21 04:22:05,269 INFO L290 TraceCheckUtils]: 13: Hoare triple {24297#(= ~T6_E~0 ~M_E~0)} assume !(0 == ~M_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,269 INFO L290 TraceCheckUtils]: 14: Hoare triple {24298#(not (= ~T6_E~0 0))} assume !(0 == ~T1_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,269 INFO L290 TraceCheckUtils]: 15: Hoare triple {24298#(not (= ~T6_E~0 0))} assume !(0 == ~T2_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,270 INFO L290 TraceCheckUtils]: 16: Hoare triple {24298#(not (= ~T6_E~0 0))} assume !(0 == ~T3_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,270 INFO L290 TraceCheckUtils]: 17: Hoare triple {24298#(not (= ~T6_E~0 0))} assume !(0 == ~T4_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,270 INFO L290 TraceCheckUtils]: 18: Hoare triple {24298#(not (= ~T6_E~0 0))} assume !(0 == ~T5_E~0); {24298#(not (= ~T6_E~0 0))} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 19: Hoare triple {24298#(not (= ~T6_E~0 0))} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24296#false} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 20: Hoare triple {24296#false} assume !(0 == ~T7_E~0); {24296#false} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 21: Hoare triple {24296#false} assume !(0 == ~E_M~0); {24296#false} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 22: Hoare triple {24296#false} assume !(0 == ~E_1~0); {24296#false} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 23: Hoare triple {24296#false} assume !(0 == ~E_2~0); {24296#false} is VALID [2022-02-21 04:22:05,271 INFO L290 TraceCheckUtils]: 24: Hoare triple {24296#false} assume !(0 == ~E_3~0); {24296#false} is VALID [2022-02-21 04:22:05,272 INFO L290 TraceCheckUtils]: 25: Hoare triple {24296#false} assume !(0 == ~E_4~0); {24296#false} is VALID [2022-02-21 04:22:05,283 INFO L290 TraceCheckUtils]: 26: Hoare triple {24296#false} assume !(0 == ~E_5~0); {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 27: Hoare triple {24296#false} assume 0 == ~E_6~0;~E_6~0 := 1; {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 28: Hoare triple {24296#false} assume !(0 == ~E_7~0); {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 29: Hoare triple {24296#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 30: Hoare triple {24296#false} assume !(1 == ~m_pc~0); {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 31: Hoare triple {24296#false} is_master_triggered_~__retres1~0#1 := 0; {24296#false} is VALID [2022-02-21 04:22:05,284 INFO L290 TraceCheckUtils]: 32: Hoare triple {24296#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 33: Hoare triple {24296#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 34: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp~1#1); {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 35: Hoare triple {24296#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 36: Hoare triple {24296#false} assume 1 == ~t1_pc~0; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 37: Hoare triple {24296#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 38: Hoare triple {24296#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24296#false} is VALID [2022-02-21 04:22:05,285 INFO L290 TraceCheckUtils]: 39: Hoare triple {24296#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 40: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___0~0#1); {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 41: Hoare triple {24296#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 42: Hoare triple {24296#false} assume !(1 == ~t2_pc~0); {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 43: Hoare triple {24296#false} is_transmit2_triggered_~__retres1~2#1 := 0; {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 44: Hoare triple {24296#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 45: Hoare triple {24296#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24296#false} is VALID [2022-02-21 04:22:05,286 INFO L290 TraceCheckUtils]: 46: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___1~0#1); {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 47: Hoare triple {24296#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 48: Hoare triple {24296#false} assume 1 == ~t3_pc~0; {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 49: Hoare triple {24296#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 50: Hoare triple {24296#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 51: Hoare triple {24296#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 52: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___2~0#1); {24296#false} is VALID [2022-02-21 04:22:05,287 INFO L290 TraceCheckUtils]: 53: Hoare triple {24296#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 54: Hoare triple {24296#false} assume !(1 == ~t4_pc~0); {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 55: Hoare triple {24296#false} is_transmit4_triggered_~__retres1~4#1 := 0; {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 56: Hoare triple {24296#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 57: Hoare triple {24296#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 58: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___3~0#1); {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 59: Hoare triple {24296#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24296#false} is VALID [2022-02-21 04:22:05,288 INFO L290 TraceCheckUtils]: 60: Hoare triple {24296#false} assume 1 == ~t5_pc~0; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 61: Hoare triple {24296#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 62: Hoare triple {24296#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 63: Hoare triple {24296#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 64: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___4~0#1); {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 65: Hoare triple {24296#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 66: Hoare triple {24296#false} assume 1 == ~t6_pc~0; {24296#false} is VALID [2022-02-21 04:22:05,289 INFO L290 TraceCheckUtils]: 67: Hoare triple {24296#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 68: Hoare triple {24296#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 69: Hoare triple {24296#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 70: Hoare triple {24296#false} assume !(0 != activate_threads_~tmp___5~0#1); {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 71: Hoare triple {24296#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 72: Hoare triple {24296#false} assume !(1 == ~t7_pc~0); {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 73: Hoare triple {24296#false} is_transmit7_triggered_~__retres1~7#1 := 0; {24296#false} is VALID [2022-02-21 04:22:05,290 INFO L290 TraceCheckUtils]: 74: Hoare triple {24296#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 75: Hoare triple {24296#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 76: Hoare triple {24296#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 77: Hoare triple {24296#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 78: Hoare triple {24296#false} assume !(1 == ~M_E~0); {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 79: Hoare triple {24296#false} assume !(1 == ~T1_E~0); {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 80: Hoare triple {24296#false} assume !(1 == ~T2_E~0); {24296#false} is VALID [2022-02-21 04:22:05,291 INFO L290 TraceCheckUtils]: 81: Hoare triple {24296#false} assume !(1 == ~T3_E~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 82: Hoare triple {24296#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 83: Hoare triple {24296#false} assume !(1 == ~T5_E~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 84: Hoare triple {24296#false} assume !(1 == ~T6_E~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 85: Hoare triple {24296#false} assume !(1 == ~T7_E~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 86: Hoare triple {24296#false} assume !(1 == ~E_M~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 87: Hoare triple {24296#false} assume !(1 == ~E_1~0); {24296#false} is VALID [2022-02-21 04:22:05,292 INFO L290 TraceCheckUtils]: 88: Hoare triple {24296#false} assume !(1 == ~E_2~0); {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 89: Hoare triple {24296#false} assume !(1 == ~E_3~0); {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 90: Hoare triple {24296#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 91: Hoare triple {24296#false} assume !(1 == ~E_5~0); {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 92: Hoare triple {24296#false} assume !(1 == ~E_6~0); {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 93: Hoare triple {24296#false} assume !(1 == ~E_7~0); {24296#false} is VALID [2022-02-21 04:22:05,293 INFO L290 TraceCheckUtils]: 94: Hoare triple {24296#false} assume { :end_inline_reset_delta_events } true; {24296#false} is VALID [2022-02-21 04:22:05,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,294 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,294 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165240753] [2022-02-21 04:22:05,294 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165240753] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,295 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,296 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:05,296 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772636454] [2022-02-21 04:22:05,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,296 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:05,297 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:05,297 INFO L85 PathProgramCache]: Analyzing trace with hash 1828583203, now seen corresponding path program 1 times [2022-02-21 04:22:05,297 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:05,301 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282140735] [2022-02-21 04:22:05,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:05,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:05,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:05,328 INFO L290 TraceCheckUtils]: 0: Hoare triple {24299#true} assume !false; {24299#true} is VALID [2022-02-21 04:22:05,328 INFO L290 TraceCheckUtils]: 1: Hoare triple {24299#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {24299#true} is VALID [2022-02-21 04:22:05,328 INFO L290 TraceCheckUtils]: 2: Hoare triple {24299#true} assume !false; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 3: Hoare triple {24299#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 4: Hoare triple {24299#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 5: Hoare triple {24299#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 6: Hoare triple {24299#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 7: Hoare triple {24299#true} assume !(0 != eval_~tmp~0#1); {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 8: Hoare triple {24299#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {24299#true} is VALID [2022-02-21 04:22:05,329 INFO L290 TraceCheckUtils]: 9: Hoare triple {24299#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 10: Hoare triple {24299#true} assume 0 == ~M_E~0;~M_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 11: Hoare triple {24299#true} assume !(0 == ~T1_E~0); {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 12: Hoare triple {24299#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 13: Hoare triple {24299#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 14: Hoare triple {24299#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 15: Hoare triple {24299#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,330 INFO L290 TraceCheckUtils]: 16: Hoare triple {24299#true} assume 0 == ~T6_E~0;~T6_E~0 := 1; {24299#true} is VALID [2022-02-21 04:22:05,331 INFO L290 TraceCheckUtils]: 17: Hoare triple {24299#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,331 INFO L290 TraceCheckUtils]: 18: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,332 INFO L290 TraceCheckUtils]: 19: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,332 INFO L290 TraceCheckUtils]: 20: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,332 INFO L290 TraceCheckUtils]: 21: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,333 INFO L290 TraceCheckUtils]: 22: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,333 INFO L290 TraceCheckUtils]: 23: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,333 INFO L290 TraceCheckUtils]: 24: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,334 INFO L290 TraceCheckUtils]: 25: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,334 INFO L290 TraceCheckUtils]: 26: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,334 INFO L290 TraceCheckUtils]: 27: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,335 INFO L290 TraceCheckUtils]: 28: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,335 INFO L290 TraceCheckUtils]: 29: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,335 INFO L290 TraceCheckUtils]: 30: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,336 INFO L290 TraceCheckUtils]: 31: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,336 INFO L290 TraceCheckUtils]: 32: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,336 INFO L290 TraceCheckUtils]: 33: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,336 INFO L290 TraceCheckUtils]: 34: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,337 INFO L290 TraceCheckUtils]: 35: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,337 INFO L290 TraceCheckUtils]: 36: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,337 INFO L290 TraceCheckUtils]: 37: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,338 INFO L290 TraceCheckUtils]: 38: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,338 INFO L290 TraceCheckUtils]: 39: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,338 INFO L290 TraceCheckUtils]: 40: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,339 INFO L290 TraceCheckUtils]: 41: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,340 INFO L290 TraceCheckUtils]: 44: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,340 INFO L290 TraceCheckUtils]: 45: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,340 INFO L290 TraceCheckUtils]: 46: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,341 INFO L290 TraceCheckUtils]: 47: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,341 INFO L290 TraceCheckUtils]: 48: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,341 INFO L290 TraceCheckUtils]: 49: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,342 INFO L290 TraceCheckUtils]: 50: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,342 INFO L290 TraceCheckUtils]: 51: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,342 INFO L290 TraceCheckUtils]: 52: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,343 INFO L290 TraceCheckUtils]: 53: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,343 INFO L290 TraceCheckUtils]: 54: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,343 INFO L290 TraceCheckUtils]: 55: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,344 INFO L290 TraceCheckUtils]: 56: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,344 INFO L290 TraceCheckUtils]: 57: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,344 INFO L290 TraceCheckUtils]: 58: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,345 INFO L290 TraceCheckUtils]: 59: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,345 INFO L290 TraceCheckUtils]: 60: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,345 INFO L290 TraceCheckUtils]: 61: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,346 INFO L290 TraceCheckUtils]: 62: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,346 INFO L290 TraceCheckUtils]: 63: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t6_pc~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,346 INFO L290 TraceCheckUtils]: 64: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_~__retres1~6#1 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,347 INFO L290 TraceCheckUtils]: 65: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,347 INFO L290 TraceCheckUtils]: 66: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,347 INFO L290 TraceCheckUtils]: 67: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,348 INFO L290 TraceCheckUtils]: 68: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,348 INFO L290 TraceCheckUtils]: 69: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,348 INFO L290 TraceCheckUtils]: 70: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,349 INFO L290 TraceCheckUtils]: 71: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,349 INFO L290 TraceCheckUtils]: 72: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,349 INFO L290 TraceCheckUtils]: 73: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,350 INFO L290 TraceCheckUtils]: 74: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,350 INFO L290 TraceCheckUtils]: 75: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,350 INFO L290 TraceCheckUtils]: 76: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,351 INFO L290 TraceCheckUtils]: 77: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,351 INFO L290 TraceCheckUtils]: 78: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,351 INFO L290 TraceCheckUtils]: 79: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,352 INFO L290 TraceCheckUtils]: 80: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,352 INFO L290 TraceCheckUtils]: 81: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {24301#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:05,352 INFO L290 TraceCheckUtils]: 82: Hoare triple {24301#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 83: Hoare triple {24300#false} assume 1 == ~E_M~0;~E_M~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 84: Hoare triple {24300#false} assume 1 == ~E_1~0;~E_1~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 85: Hoare triple {24300#false} assume 1 == ~E_2~0;~E_2~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 86: Hoare triple {24300#false} assume 1 == ~E_3~0;~E_3~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 87: Hoare triple {24300#false} assume 1 == ~E_4~0;~E_4~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 88: Hoare triple {24300#false} assume 1 == ~E_5~0;~E_5~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,353 INFO L290 TraceCheckUtils]: 89: Hoare triple {24300#false} assume 1 == ~E_6~0;~E_6~0 := 2; {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 90: Hoare triple {24300#false} assume !(1 == ~E_7~0); {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 91: Hoare triple {24300#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 92: Hoare triple {24300#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 93: Hoare triple {24300#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 94: Hoare triple {24300#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 95: Hoare triple {24300#false} assume !(0 == start_simulation_~tmp~3#1); {24300#false} is VALID [2022-02-21 04:22:05,354 INFO L290 TraceCheckUtils]: 96: Hoare triple {24300#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 97: Hoare triple {24300#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 98: Hoare triple {24300#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 99: Hoare triple {24300#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 100: Hoare triple {24300#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 101: Hoare triple {24300#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 102: Hoare triple {24300#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {24300#false} is VALID [2022-02-21 04:22:05,355 INFO L290 TraceCheckUtils]: 103: Hoare triple {24300#false} assume !(0 != start_simulation_~tmp___0~1#1); {24300#false} is VALID [2022-02-21 04:22:05,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:05,356 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:05,358 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282140735] [2022-02-21 04:22:05,359 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282140735] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:05,359 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:05,360 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:05,360 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815683281] [2022-02-21 04:22:05,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:05,360 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:05,360 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:05,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:05,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:05,361 INFO L87 Difference]: Start difference. First operand 835 states and 1243 transitions. cyclomatic complexity: 409 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,084 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2022-02-21 04:22:07,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:07,084 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,144 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:07,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,204 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-02-21 04:22:07,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-02-21 04:22:07,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1509 [2022-02-21 04:22:07,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1509 [2022-02-21 04:22:07,284 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:07,286 INFO L681 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-02-21 04:22:07,288 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1509 to 1509. [2022-02-21 04:22:07,311 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:07,313 INFO L82 GeneralOperation]: Start isEquivalent. First operand 1509 states and 2238 transitions. Second operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,314 INFO L74 IsIncluded]: Start isIncluded. First operand 1509 states and 2238 transitions. Second operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,317 INFO L87 Difference]: Start difference. First operand 1509 states and 2238 transitions. Second operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,391 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2022-02-21 04:22:07,391 INFO L276 IsEmpty]: Start isEmpty. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,394 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:07,394 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:07,396 INFO L74 IsIncluded]: Start isIncluded. First operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,398 INFO L87 Difference]: Start difference. First operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:07,476 INFO L93 Difference]: Finished difference Result 1509 states and 2238 transitions. [2022-02-21 04:22:07,476 INFO L276 IsEmpty]: Start isEmpty. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,478 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:07,478 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:07,478 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:07,478 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:07,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1509 states, 1509 states have (on average 1.4831013916500995) internal successors, (2238), 1508 states have internal predecessors, (2238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:07,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1509 states to 1509 states and 2238 transitions. [2022-02-21 04:22:07,553 INFO L704 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-02-21 04:22:07,554 INFO L587 BuchiCegarLoop]: Abstraction has 1509 states and 2238 transitions. [2022-02-21 04:22:07,554 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2022-02-21 04:22:07,554 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1509 states and 2238 transitions. [2022-02-21 04:22:07,558 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1390 [2022-02-21 04:22:07,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:07,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:07,559 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:07,560 INFO L791 eck$LassoCheckResult]: Stem: 26467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 26468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 25902#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25903#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26659#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 26204#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26205#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26326#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26327#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26114#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25898#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25899#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26072#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26073#L781 assume !(0 == ~M_E~0); 26548#L781-2 assume !(0 == ~T1_E~0); 26694#L786-1 assume !(0 == ~T2_E~0); 25862#L791-1 assume !(0 == ~T3_E~0); 25863#L796-1 assume !(0 == ~T4_E~0); 26399#L801-1 assume !(0 == ~T5_E~0); 26400#L806-1 assume !(0 == ~T6_E~0); 26426#L811-1 assume !(0 == ~T7_E~0); 26078#L816-1 assume !(0 == ~E_M~0); 26079#L821-1 assume !(0 == ~E_1~0); 25887#L826-1 assume !(0 == ~E_2~0); 25888#L831-1 assume !(0 == ~E_3~0); 26201#L836-1 assume !(0 == ~E_4~0); 26202#L841-1 assume !(0 == ~E_5~0); 26033#L846-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26034#L851-1 assume !(0 == ~E_7~0); 26054#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26055#L388 assume !(1 == ~m_pc~0); 26048#L388-2 is_master_triggered_~__retres1~0#1 := 0; 26049#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26519#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25906#L967 assume !(0 != activate_threads_~tmp~1#1); 25907#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25834#L407 assume 1 == ~t1_pc~0; 25835#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25842#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25813#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25814#L975 assume !(0 != activate_threads_~tmp___0~0#1); 26625#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26163#L426 assume !(1 == ~t2_pc~0); 26164#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26640#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26681#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26677#L983 assume !(0 != activate_threads_~tmp___1~0#1); 26678#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26243#L445 assume 1 == ~t3_pc~0; 26244#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26551#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26050#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26051#L991 assume !(0 != activate_threads_~tmp___2~0#1); 26483#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26453#L464 assume !(1 == ~t4_pc~0); 26057#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25927#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25928#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26256#L999 assume !(0 != activate_threads_~tmp___3~0#1); 26219#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26220#L483 assume 1 == ~t5_pc~0; 26449#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26601#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26381#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26382#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 26149#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26150#L502 assume 1 == ~t6_pc~0; 26424#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25958#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25959#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26362#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 26363#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26577#L521 assume !(1 == ~t7_pc~0); 26621#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25900#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25901#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26009#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26584#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26508#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 26212#L869-2 assume !(1 == ~T1_E~0); 26213#L874-1 assume !(1 == ~T2_E~0); 26654#L879-1 assume !(1 == ~T3_E~0); 26294#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25822#L889-1 assume !(1 == ~T5_E~0); 25823#L894-1 assume !(1 == ~T6_E~0); 26088#L899-1 assume !(1 == ~T7_E~0); 26473#L904-1 assume !(1 == ~E_M~0); 26235#L909-1 assume !(1 == ~E_1~0); 26236#L914-1 assume !(1 == ~E_2~0); 26413#L919-1 assume !(1 == ~E_3~0); 26162#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 25997#L929-1 assume !(1 == ~E_5~0); 25998#L934-1 assume !(1 == ~E_6~0); 26661#L939-1 assume !(1 == ~E_7~0); 26576#L944-1 assume { :end_inline_reset_delta_events } true; 26067#L1190-2 [2022-02-21 04:22:07,560 INFO L793 eck$LassoCheckResult]: Loop: 26067#L1190-2 assume !false; 26709#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26708#L756 assume !false; 26707#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26687#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 25922#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26685#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26686#L653 assume !(0 != eval_~tmp~0#1); 26698#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26300#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26301#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26697#L781-5 assume !(0 == ~T1_E~0); 27010#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27009#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27008#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27007#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27006#L806-3 assume !(0 == ~T6_E~0); 27005#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27004#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27003#L821-3 assume !(0 == ~E_1~0); 27002#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27001#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27000#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26999#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26998#L846-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26997#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26996#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26995#L388-27 assume !(1 == ~m_pc~0); 26993#L388-29 is_master_triggered_~__retres1~0#1 := 0; 26992#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26991#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26990#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26989#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26988#L407-27 assume 1 == ~t1_pc~0; 26986#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26985#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26984#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26983#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26982#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26981#L426-27 assume !(1 == ~t2_pc~0); 26979#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 26978#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26977#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26976#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26975#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26974#L445-27 assume 1 == ~t3_pc~0; 26972#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26971#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26970#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26969#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26968#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26967#L464-27 assume !(1 == ~t4_pc~0); 26965#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 26964#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26963#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26962#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26961#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26960#L483-27 assume 1 == ~t5_pc~0; 26958#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26957#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26956#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26955#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 26954#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26953#L502-27 assume 1 == ~t6_pc~0; 26951#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26950#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26949#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26948#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26947#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26946#L521-27 assume !(1 == ~t7_pc~0); 26944#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 26943#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26942#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26941#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26940#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26939#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26649#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26938#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26937#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26936#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26935#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26934#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25985#L899-3 assume !(1 == ~T7_E~0); 26933#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26932#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26931#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26930#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26929#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26928#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26927#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26926#L939-3 assume !(1 == ~E_7~0); 26925#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26864#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26858#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26857#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 26856#L1209 assume !(0 == start_simulation_~tmp~3#1); 26364#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 26853#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26847#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 26846#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 26845#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26844#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26843#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 26066#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 26067#L1190-2 [2022-02-21 04:22:07,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:07,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1207876549, now seen corresponding path program 1 times [2022-02-21 04:22:07,561 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:07,561 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267204930] [2022-02-21 04:22:07,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:07,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:07,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,597 INFO L290 TraceCheckUtils]: 0: Hoare triple {30343#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,597 INFO L290 TraceCheckUtils]: 1: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,598 INFO L290 TraceCheckUtils]: 2: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,598 INFO L290 TraceCheckUtils]: 3: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,598 INFO L290 TraceCheckUtils]: 4: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,599 INFO L290 TraceCheckUtils]: 5: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,599 INFO L290 TraceCheckUtils]: 6: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,599 INFO L290 TraceCheckUtils]: 7: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,600 INFO L290 TraceCheckUtils]: 8: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,600 INFO L290 TraceCheckUtils]: 9: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,600 INFO L290 TraceCheckUtils]: 10: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,601 INFO L290 TraceCheckUtils]: 11: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,601 INFO L290 TraceCheckUtils]: 12: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {30345#(= ~E_6~0 ~M_E~0)} is VALID [2022-02-21 04:22:07,601 INFO L290 TraceCheckUtils]: 13: Hoare triple {30345#(= ~E_6~0 ~M_E~0)} assume !(0 == ~M_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,602 INFO L290 TraceCheckUtils]: 14: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T1_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,602 INFO L290 TraceCheckUtils]: 15: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T2_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,602 INFO L290 TraceCheckUtils]: 16: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T3_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,602 INFO L290 TraceCheckUtils]: 17: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T4_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,603 INFO L290 TraceCheckUtils]: 18: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T5_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,603 INFO L290 TraceCheckUtils]: 19: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T6_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,603 INFO L290 TraceCheckUtils]: 20: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~T7_E~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,604 INFO L290 TraceCheckUtils]: 21: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_M~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,604 INFO L290 TraceCheckUtils]: 22: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_1~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,604 INFO L290 TraceCheckUtils]: 23: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_2~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,604 INFO L290 TraceCheckUtils]: 24: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_3~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,605 INFO L290 TraceCheckUtils]: 25: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_4~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,605 INFO L290 TraceCheckUtils]: 26: Hoare triple {30346#(not (= ~E_6~0 0))} assume !(0 == ~E_5~0); {30346#(not (= ~E_6~0 0))} is VALID [2022-02-21 04:22:07,605 INFO L290 TraceCheckUtils]: 27: Hoare triple {30346#(not (= ~E_6~0 0))} assume 0 == ~E_6~0;~E_6~0 := 1; {30344#false} is VALID [2022-02-21 04:22:07,605 INFO L290 TraceCheckUtils]: 28: Hoare triple {30344#false} assume !(0 == ~E_7~0); {30344#false} is VALID [2022-02-21 04:22:07,605 INFO L290 TraceCheckUtils]: 29: Hoare triple {30344#false} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 30: Hoare triple {30344#false} assume !(1 == ~m_pc~0); {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 31: Hoare triple {30344#false} is_master_triggered_~__retres1~0#1 := 0; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 32: Hoare triple {30344#false} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 33: Hoare triple {30344#false} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 34: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp~1#1); {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 35: Hoare triple {30344#false} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 36: Hoare triple {30344#false} assume 1 == ~t1_pc~0; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 37: Hoare triple {30344#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 38: Hoare triple {30344#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30344#false} is VALID [2022-02-21 04:22:07,606 INFO L290 TraceCheckUtils]: 39: Hoare triple {30344#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 40: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___0~0#1); {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 41: Hoare triple {30344#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 42: Hoare triple {30344#false} assume !(1 == ~t2_pc~0); {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 43: Hoare triple {30344#false} is_transmit2_triggered_~__retres1~2#1 := 0; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 44: Hoare triple {30344#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 45: Hoare triple {30344#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 46: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___1~0#1); {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 47: Hoare triple {30344#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 48: Hoare triple {30344#false} assume 1 == ~t3_pc~0; {30344#false} is VALID [2022-02-21 04:22:07,607 INFO L290 TraceCheckUtils]: 49: Hoare triple {30344#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 50: Hoare triple {30344#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 51: Hoare triple {30344#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 52: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___2~0#1); {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 53: Hoare triple {30344#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 54: Hoare triple {30344#false} assume !(1 == ~t4_pc~0); {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 55: Hoare triple {30344#false} is_transmit4_triggered_~__retres1~4#1 := 0; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 56: Hoare triple {30344#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 57: Hoare triple {30344#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 58: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___3~0#1); {30344#false} is VALID [2022-02-21 04:22:07,608 INFO L290 TraceCheckUtils]: 59: Hoare triple {30344#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 60: Hoare triple {30344#false} assume 1 == ~t5_pc~0; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 61: Hoare triple {30344#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 62: Hoare triple {30344#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 63: Hoare triple {30344#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 64: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___4~0#1); {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 65: Hoare triple {30344#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 66: Hoare triple {30344#false} assume 1 == ~t6_pc~0; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 67: Hoare triple {30344#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30344#false} is VALID [2022-02-21 04:22:07,609 INFO L290 TraceCheckUtils]: 68: Hoare triple {30344#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 69: Hoare triple {30344#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 70: Hoare triple {30344#false} assume !(0 != activate_threads_~tmp___5~0#1); {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 71: Hoare triple {30344#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 72: Hoare triple {30344#false} assume !(1 == ~t7_pc~0); {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 73: Hoare triple {30344#false} is_transmit7_triggered_~__retres1~7#1 := 0; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 74: Hoare triple {30344#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 75: Hoare triple {30344#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 76: Hoare triple {30344#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 77: Hoare triple {30344#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30344#false} is VALID [2022-02-21 04:22:07,610 INFO L290 TraceCheckUtils]: 78: Hoare triple {30344#false} assume 1 == ~M_E~0;~M_E~0 := 2; {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 79: Hoare triple {30344#false} assume !(1 == ~T1_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 80: Hoare triple {30344#false} assume !(1 == ~T2_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 81: Hoare triple {30344#false} assume !(1 == ~T3_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 82: Hoare triple {30344#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 83: Hoare triple {30344#false} assume !(1 == ~T5_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 84: Hoare triple {30344#false} assume !(1 == ~T6_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 85: Hoare triple {30344#false} assume !(1 == ~T7_E~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 86: Hoare triple {30344#false} assume !(1 == ~E_M~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 87: Hoare triple {30344#false} assume !(1 == ~E_1~0); {30344#false} is VALID [2022-02-21 04:22:07,611 INFO L290 TraceCheckUtils]: 88: Hoare triple {30344#false} assume !(1 == ~E_2~0); {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 89: Hoare triple {30344#false} assume !(1 == ~E_3~0); {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 90: Hoare triple {30344#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 91: Hoare triple {30344#false} assume !(1 == ~E_5~0); {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 92: Hoare triple {30344#false} assume !(1 == ~E_6~0); {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 93: Hoare triple {30344#false} assume !(1 == ~E_7~0); {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L290 TraceCheckUtils]: 94: Hoare triple {30344#false} assume { :end_inline_reset_delta_events } true; {30344#false} is VALID [2022-02-21 04:22:07,612 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,612 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,613 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267204930] [2022-02-21 04:22:07,613 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267204930] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,613 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,613 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:07,613 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1839482272] [2022-02-21 04:22:07,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,614 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:07,614 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:07,614 INFO L85 PathProgramCache]: Analyzing trace with hash 1319064224, now seen corresponding path program 1 times [2022-02-21 04:22:07,614 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:07,614 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935766751] [2022-02-21 04:22:07,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:07,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:07,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:07,646 INFO L290 TraceCheckUtils]: 0: Hoare triple {30347#true} assume !false; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 1: Hoare triple {30347#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 2: Hoare triple {30347#true} assume !false; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 3: Hoare triple {30347#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 4: Hoare triple {30347#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 5: Hoare triple {30347#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 6: Hoare triple {30347#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 7: Hoare triple {30347#true} assume !(0 != eval_~tmp~0#1); {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 8: Hoare triple {30347#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {30347#true} is VALID [2022-02-21 04:22:07,647 INFO L290 TraceCheckUtils]: 9: Hoare triple {30347#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 10: Hoare triple {30347#true} assume 0 == ~M_E~0;~M_E~0 := 1; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 11: Hoare triple {30347#true} assume !(0 == ~T1_E~0); {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 12: Hoare triple {30347#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 13: Hoare triple {30347#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 14: Hoare triple {30347#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 15: Hoare triple {30347#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {30347#true} is VALID [2022-02-21 04:22:07,648 INFO L290 TraceCheckUtils]: 16: Hoare triple {30347#true} assume !(0 == ~T6_E~0); {30347#true} is VALID [2022-02-21 04:22:07,649 INFO L290 TraceCheckUtils]: 17: Hoare triple {30347#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,649 INFO L290 TraceCheckUtils]: 18: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,649 INFO L290 TraceCheckUtils]: 19: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,649 INFO L290 TraceCheckUtils]: 20: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,650 INFO L290 TraceCheckUtils]: 21: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,650 INFO L290 TraceCheckUtils]: 22: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,650 INFO L290 TraceCheckUtils]: 23: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,650 INFO L290 TraceCheckUtils]: 24: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_6~0;~E_6~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,651 INFO L290 TraceCheckUtils]: 25: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,651 INFO L290 TraceCheckUtils]: 26: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,651 INFO L290 TraceCheckUtils]: 27: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,652 INFO L290 TraceCheckUtils]: 28: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,652 INFO L290 TraceCheckUtils]: 29: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,652 INFO L290 TraceCheckUtils]: 30: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,652 INFO L290 TraceCheckUtils]: 31: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,653 INFO L290 TraceCheckUtils]: 32: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,653 INFO L290 TraceCheckUtils]: 33: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,653 INFO L290 TraceCheckUtils]: 34: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,654 INFO L290 TraceCheckUtils]: 35: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,654 INFO L290 TraceCheckUtils]: 36: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,654 INFO L290 TraceCheckUtils]: 37: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,654 INFO L290 TraceCheckUtils]: 38: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,655 INFO L290 TraceCheckUtils]: 39: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,655 INFO L290 TraceCheckUtils]: 40: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,655 INFO L290 TraceCheckUtils]: 41: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,656 INFO L290 TraceCheckUtils]: 42: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,656 INFO L290 TraceCheckUtils]: 43: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,656 INFO L290 TraceCheckUtils]: 44: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,656 INFO L290 TraceCheckUtils]: 45: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,657 INFO L290 TraceCheckUtils]: 46: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,657 INFO L290 TraceCheckUtils]: 47: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,657 INFO L290 TraceCheckUtils]: 48: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,658 INFO L290 TraceCheckUtils]: 49: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,658 INFO L290 TraceCheckUtils]: 50: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,658 INFO L290 TraceCheckUtils]: 51: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,658 INFO L290 TraceCheckUtils]: 52: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,659 INFO L290 TraceCheckUtils]: 53: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,659 INFO L290 TraceCheckUtils]: 54: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,659 INFO L290 TraceCheckUtils]: 55: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,660 INFO L290 TraceCheckUtils]: 56: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,660 INFO L290 TraceCheckUtils]: 57: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,660 INFO L290 TraceCheckUtils]: 58: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,660 INFO L290 TraceCheckUtils]: 59: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,661 INFO L290 TraceCheckUtils]: 60: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,661 INFO L290 TraceCheckUtils]: 61: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,661 INFO L290 TraceCheckUtils]: 62: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,662 INFO L290 TraceCheckUtils]: 63: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,662 INFO L290 TraceCheckUtils]: 64: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,662 INFO L290 TraceCheckUtils]: 65: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,662 INFO L290 TraceCheckUtils]: 66: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,663 INFO L290 TraceCheckUtils]: 67: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,663 INFO L290 TraceCheckUtils]: 68: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,663 INFO L290 TraceCheckUtils]: 69: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,664 INFO L290 TraceCheckUtils]: 70: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,664 INFO L290 TraceCheckUtils]: 71: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,664 INFO L290 TraceCheckUtils]: 72: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,664 INFO L290 TraceCheckUtils]: 73: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,665 INFO L290 TraceCheckUtils]: 74: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,665 INFO L290 TraceCheckUtils]: 75: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,665 INFO L290 TraceCheckUtils]: 76: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,666 INFO L290 TraceCheckUtils]: 77: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,666 INFO L290 TraceCheckUtils]: 78: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,666 INFO L290 TraceCheckUtils]: 79: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,666 INFO L290 TraceCheckUtils]: 80: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 81: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {30349#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 82: Hoare triple {30349#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {30348#false} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 83: Hoare triple {30348#false} assume 1 == ~E_M~0;~E_M~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 84: Hoare triple {30348#false} assume 1 == ~E_1~0;~E_1~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 85: Hoare triple {30348#false} assume 1 == ~E_2~0;~E_2~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,667 INFO L290 TraceCheckUtils]: 86: Hoare triple {30348#false} assume 1 == ~E_3~0;~E_3~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 87: Hoare triple {30348#false} assume 1 == ~E_4~0;~E_4~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 88: Hoare triple {30348#false} assume 1 == ~E_5~0;~E_5~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 89: Hoare triple {30348#false} assume 1 == ~E_6~0;~E_6~0 := 2; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 90: Hoare triple {30348#false} assume !(1 == ~E_7~0); {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 91: Hoare triple {30348#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 92: Hoare triple {30348#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 93: Hoare triple {30348#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 94: Hoare triple {30348#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 95: Hoare triple {30348#false} assume !(0 == start_simulation_~tmp~3#1); {30348#false} is VALID [2022-02-21 04:22:07,668 INFO L290 TraceCheckUtils]: 96: Hoare triple {30348#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 97: Hoare triple {30348#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 98: Hoare triple {30348#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 99: Hoare triple {30348#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 100: Hoare triple {30348#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 101: Hoare triple {30348#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 102: Hoare triple {30348#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {30348#false} is VALID [2022-02-21 04:22:07,669 INFO L290 TraceCheckUtils]: 103: Hoare triple {30348#false} assume !(0 != start_simulation_~tmp___0~1#1); {30348#false} is VALID [2022-02-21 04:22:07,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:07,670 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:07,670 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935766751] [2022-02-21 04:22:07,670 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935766751] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:07,670 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:07,670 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:07,670 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704276541] [2022-02-21 04:22:07,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:07,671 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:07,671 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:07,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:07,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:07,672 INFO L87 Difference]: Start difference. First operand 1509 states and 2238 transitions. cyclomatic complexity: 731 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:09,347 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2022-02-21 04:22:09,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:09,348 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,425 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:09,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2723 states and 4027 transitions. [2022-02-21 04:22:09,587 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-02-21 04:22:09,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2723 states to 2723 states and 4027 transitions. [2022-02-21 04:22:09,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2723 [2022-02-21 04:22:09,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2723 [2022-02-21 04:22:09,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2723 states and 4027 transitions. [2022-02-21 04:22:09,847 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:09,847 INFO L681 BuchiCegarLoop]: Abstraction has 2723 states and 4027 transitions. [2022-02-21 04:22:09,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2723 states and 4027 transitions. [2022-02-21 04:22:09,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2723 to 2721. [2022-02-21 04:22:09,880 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:09,884 INFO L82 GeneralOperation]: Start isEquivalent. First operand 2723 states and 4027 transitions. Second operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,886 INFO L74 IsIncluded]: Start isIncluded. First operand 2723 states and 4027 transitions. Second operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:09,888 INFO L87 Difference]: Start difference. First operand 2723 states and 4027 transitions. Second operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,114 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2022-02-21 04:22:10,114 INFO L276 IsEmpty]: Start isEmpty. Operand 2723 states and 4027 transitions. [2022-02-21 04:22:10,117 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,117 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,121 INFO L74 IsIncluded]: Start isIncluded. First operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2723 states and 4027 transitions. [2022-02-21 04:22:10,123 INFO L87 Difference]: Start difference. First operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 2723 states and 4027 transitions. [2022-02-21 04:22:10,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:10,350 INFO L93 Difference]: Finished difference Result 2723 states and 4027 transitions. [2022-02-21 04:22:10,350 INFO L276 IsEmpty]: Start isEmpty. Operand 2723 states and 4027 transitions. [2022-02-21 04:22:10,353 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:10,353 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:10,353 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:10,353 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:10,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2721 states, 2721 states have (on average 1.4792355751561925) internal successors, (4025), 2720 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:10,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2721 states to 2721 states and 4025 transitions. [2022-02-21 04:22:10,520 INFO L704 BuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-02-21 04:22:10,520 INFO L587 BuchiCegarLoop]: Abstraction has 2721 states and 4025 transitions. [2022-02-21 04:22:10,520 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2022-02-21 04:22:10,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2721 states and 4025 transitions. [2022-02-21 04:22:10,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2590 [2022-02-21 04:22:10,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:10,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:10,526 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,526 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:10,526 INFO L791 eck$LassoCheckResult]: Stem: 33729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 33730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 33164#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33165#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33923#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 33469#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33470#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33590#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33591#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33378#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33160#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33161#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33335#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33336#L781 assume !(0 == ~M_E~0); 33812#L781-2 assume !(0 == ~T1_E~0); 33953#L786-1 assume !(0 == ~T2_E~0); 33121#L791-1 assume !(0 == ~T3_E~0); 33122#L796-1 assume !(0 == ~T4_E~0); 33659#L801-1 assume !(0 == ~T5_E~0); 33660#L806-1 assume !(0 == ~T6_E~0); 33687#L811-1 assume !(0 == ~T7_E~0); 33342#L816-1 assume !(0 == ~E_M~0); 33343#L821-1 assume !(0 == ~E_1~0); 33149#L826-1 assume !(0 == ~E_2~0); 33150#L831-1 assume !(0 == ~E_3~0); 33466#L836-1 assume !(0 == ~E_4~0); 33467#L841-1 assume !(0 == ~E_5~0); 33294#L846-1 assume !(0 == ~E_6~0); 33295#L851-1 assume !(0 == ~E_7~0); 33317#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33318#L388 assume !(1 == ~m_pc~0); 33311#L388-2 is_master_triggered_~__retres1~0#1 := 0; 33312#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33783#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33168#L967 assume !(0 != activate_threads_~tmp~1#1); 33169#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33096#L407 assume 1 == ~t1_pc~0; 33097#L408 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33104#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33075#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33076#L975 assume !(0 != activate_threads_~tmp___0~0#1); 33887#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33427#L426 assume !(1 == ~t2_pc~0); 33428#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33906#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33942#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33940#L983 assume !(0 != activate_threads_~tmp___1~0#1); 33941#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33509#L445 assume 1 == ~t3_pc~0; 33510#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33816#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33313#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33314#L991 assume !(0 != activate_threads_~tmp___2~0#1); 33746#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33715#L464 assume !(1 == ~t4_pc~0); 33320#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 33189#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33190#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33520#L999 assume !(0 != activate_threads_~tmp___3~0#1); 33484#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33485#L483 assume 1 == ~t5_pc~0; 33712#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33866#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33640#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33641#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 33410#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33411#L502 assume 1 == ~t6_pc~0; 33685#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33220#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33221#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33623#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 33624#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33842#L521 assume !(1 == ~t7_pc~0); 33883#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33162#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33163#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33271#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33849#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33769#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 33477#L869-2 assume !(1 == ~T1_E~0); 33478#L874-1 assume !(1 == ~T2_E~0); 33937#L879-1 assume !(1 == ~T3_E~0); 33559#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33084#L889-1 assume !(1 == ~T5_E~0); 33085#L894-1 assume !(1 == ~T6_E~0); 34043#L899-1 assume !(1 == ~T7_E~0); 34041#L904-1 assume !(1 == ~E_M~0); 34040#L909-1 assume !(1 == ~E_1~0); 34039#L914-1 assume !(1 == ~E_2~0); 33694#L919-1 assume !(1 == ~E_3~0); 33695#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 33259#L929-1 assume !(1 == ~E_5~0); 33260#L934-1 assume !(1 == ~E_6~0); 33992#L939-1 assume !(1 == ~E_7~0); 33985#L944-1 assume { :end_inline_reset_delta_events } true; 33980#L1190-2 [2022-02-21 04:22:10,527 INFO L793 eck$LassoCheckResult]: Loop: 33980#L1190-2 assume !false; 33975#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33974#L756 assume !false; 33973#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 33972#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 33964#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 33963#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 33961#L653 assume !(0 != eval_~tmp~0#1); 33960#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33959#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33957#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33958#L781-5 assume !(0 == ~T1_E~0); 34638#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34636#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34633#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34631#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34629#L806-3 assume !(0 == ~T6_E~0); 34627#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34625#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34623#L821-3 assume !(0 == ~E_1~0); 34620#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 34618#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34616#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 34614#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34612#L846-3 assume !(0 == ~E_6~0); 34610#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 34607#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34605#L388-27 assume !(1 == ~m_pc~0); 34602#L388-29 is_master_triggered_~__retres1~0#1 := 0; 34600#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34598#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34597#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34596#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34593#L407-27 assume 1 == ~t1_pc~0; 34586#L408-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34584#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34582#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34580#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34577#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34575#L426-27 assume !(1 == ~t2_pc~0); 34572#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 34570#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34568#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34566#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34563#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34561#L445-27 assume 1 == ~t3_pc~0; 34558#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34557#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34556#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34554#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34551#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34549#L464-27 assume !(1 == ~t4_pc~0); 34546#L464-29 is_transmit4_triggered_~__retres1~4#1 := 0; 34509#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34489#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34487#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34454#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34451#L483-27 assume 1 == ~t5_pc~0; 34428#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34426#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34424#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34422#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 34420#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34418#L502-27 assume 1 == ~t6_pc~0; 34413#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34411#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34410#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34407#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34378#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34377#L521-27 assume !(1 == ~t7_pc~0); 34356#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 34354#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34337#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34335#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34333#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34331#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33913#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34309#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34307#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34304#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34302#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34280#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33247#L899-3 assume !(1 == ~T7_E~0); 34251#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34224#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34222#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34220#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34198#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34173#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34171#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34167#L939-3 assume !(1 == ~E_7~0); 34165#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34117#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34111#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34110#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 34109#L1209 assume !(0 == start_simulation_~tmp~3#1); 33625#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 34054#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 34026#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 34021#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 34006#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34002#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33993#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 33986#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 33980#L1190-2 [2022-02-21 04:22:10,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,528 INFO L85 PathProgramCache]: Analyzing trace with hash -253936391, now seen corresponding path program 1 times [2022-02-21 04:22:10,528 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,528 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986199480] [2022-02-21 04:22:10,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,529 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,557 INFO L290 TraceCheckUtils]: 0: Hoare triple {41245#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,557 INFO L290 TraceCheckUtils]: 1: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,558 INFO L290 TraceCheckUtils]: 2: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,558 INFO L290 TraceCheckUtils]: 3: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,558 INFO L290 TraceCheckUtils]: 4: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,559 INFO L290 TraceCheckUtils]: 5: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,559 INFO L290 TraceCheckUtils]: 6: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,560 INFO L290 TraceCheckUtils]: 7: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,560 INFO L290 TraceCheckUtils]: 8: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,560 INFO L290 TraceCheckUtils]: 9: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,561 INFO L290 TraceCheckUtils]: 10: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,561 INFO L290 TraceCheckUtils]: 11: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,561 INFO L290 TraceCheckUtils]: 12: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,562 INFO L290 TraceCheckUtils]: 13: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~M_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,562 INFO L290 TraceCheckUtils]: 14: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T1_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,563 INFO L290 TraceCheckUtils]: 15: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T2_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,563 INFO L290 TraceCheckUtils]: 16: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T3_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,563 INFO L290 TraceCheckUtils]: 17: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T4_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,564 INFO L290 TraceCheckUtils]: 18: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T5_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,564 INFO L290 TraceCheckUtils]: 19: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T6_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,565 INFO L290 TraceCheckUtils]: 20: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~T7_E~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,565 INFO L290 TraceCheckUtils]: 21: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_M~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,565 INFO L290 TraceCheckUtils]: 22: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_1~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,566 INFO L290 TraceCheckUtils]: 23: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_2~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,566 INFO L290 TraceCheckUtils]: 24: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_3~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,566 INFO L290 TraceCheckUtils]: 25: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_4~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,567 INFO L290 TraceCheckUtils]: 26: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_5~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,567 INFO L290 TraceCheckUtils]: 27: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_6~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,568 INFO L290 TraceCheckUtils]: 28: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(0 == ~E_7~0); {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,568 INFO L290 TraceCheckUtils]: 29: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41247#(= ~m_pc~0 ~t1_pc~0)} is VALID [2022-02-21 04:22:10,568 INFO L290 TraceCheckUtils]: 30: Hoare triple {41247#(= ~m_pc~0 ~t1_pc~0)} assume !(1 == ~m_pc~0); {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,569 INFO L290 TraceCheckUtils]: 31: Hoare triple {41248#(not (= ~t1_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,569 INFO L290 TraceCheckUtils]: 32: Hoare triple {41248#(not (= ~t1_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,569 INFO L290 TraceCheckUtils]: 33: Hoare triple {41248#(not (= ~t1_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,570 INFO L290 TraceCheckUtils]: 34: Hoare triple {41248#(not (= ~t1_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,570 INFO L290 TraceCheckUtils]: 35: Hoare triple {41248#(not (= ~t1_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41248#(not (= ~t1_pc~0 1))} is VALID [2022-02-21 04:22:10,570 INFO L290 TraceCheckUtils]: 36: Hoare triple {41248#(not (= ~t1_pc~0 1))} assume 1 == ~t1_pc~0; {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 37: Hoare triple {41246#false} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 38: Hoare triple {41246#false} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 39: Hoare triple {41246#false} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 40: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___0~0#1); {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 41: Hoare triple {41246#false} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 42: Hoare triple {41246#false} assume !(1 == ~t2_pc~0); {41246#false} is VALID [2022-02-21 04:22:10,571 INFO L290 TraceCheckUtils]: 43: Hoare triple {41246#false} is_transmit2_triggered_~__retres1~2#1 := 0; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 44: Hoare triple {41246#false} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 45: Hoare triple {41246#false} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 46: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___1~0#1); {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 47: Hoare triple {41246#false} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 48: Hoare triple {41246#false} assume 1 == ~t3_pc~0; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 49: Hoare triple {41246#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {41246#false} is VALID [2022-02-21 04:22:10,572 INFO L290 TraceCheckUtils]: 50: Hoare triple {41246#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 51: Hoare triple {41246#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 52: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___2~0#1); {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 53: Hoare triple {41246#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 54: Hoare triple {41246#false} assume !(1 == ~t4_pc~0); {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 55: Hoare triple {41246#false} is_transmit4_triggered_~__retres1~4#1 := 0; {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 56: Hoare triple {41246#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41246#false} is VALID [2022-02-21 04:22:10,573 INFO L290 TraceCheckUtils]: 57: Hoare triple {41246#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 58: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___3~0#1); {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 59: Hoare triple {41246#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 60: Hoare triple {41246#false} assume 1 == ~t5_pc~0; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 61: Hoare triple {41246#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 62: Hoare triple {41246#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 63: Hoare triple {41246#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {41246#false} is VALID [2022-02-21 04:22:10,574 INFO L290 TraceCheckUtils]: 64: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___4~0#1); {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 65: Hoare triple {41246#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 66: Hoare triple {41246#false} assume 1 == ~t6_pc~0; {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 67: Hoare triple {41246#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 68: Hoare triple {41246#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 69: Hoare triple {41246#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {41246#false} is VALID [2022-02-21 04:22:10,575 INFO L290 TraceCheckUtils]: 70: Hoare triple {41246#false} assume !(0 != activate_threads_~tmp___5~0#1); {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 71: Hoare triple {41246#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 72: Hoare triple {41246#false} assume !(1 == ~t7_pc~0); {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 73: Hoare triple {41246#false} is_transmit7_triggered_~__retres1~7#1 := 0; {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 74: Hoare triple {41246#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 75: Hoare triple {41246#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 76: Hoare triple {41246#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {41246#false} is VALID [2022-02-21 04:22:10,576 INFO L290 TraceCheckUtils]: 77: Hoare triple {41246#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 78: Hoare triple {41246#false} assume 1 == ~M_E~0;~M_E~0 := 2; {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 79: Hoare triple {41246#false} assume !(1 == ~T1_E~0); {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 80: Hoare triple {41246#false} assume !(1 == ~T2_E~0); {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 81: Hoare triple {41246#false} assume !(1 == ~T3_E~0); {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 82: Hoare triple {41246#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 83: Hoare triple {41246#false} assume !(1 == ~T5_E~0); {41246#false} is VALID [2022-02-21 04:22:10,577 INFO L290 TraceCheckUtils]: 84: Hoare triple {41246#false} assume !(1 == ~T6_E~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 85: Hoare triple {41246#false} assume !(1 == ~T7_E~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 86: Hoare triple {41246#false} assume !(1 == ~E_M~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 87: Hoare triple {41246#false} assume !(1 == ~E_1~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 88: Hoare triple {41246#false} assume !(1 == ~E_2~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 89: Hoare triple {41246#false} assume !(1 == ~E_3~0); {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 90: Hoare triple {41246#false} assume 1 == ~E_4~0;~E_4~0 := 2; {41246#false} is VALID [2022-02-21 04:22:10,578 INFO L290 TraceCheckUtils]: 91: Hoare triple {41246#false} assume !(1 == ~E_5~0); {41246#false} is VALID [2022-02-21 04:22:10,579 INFO L290 TraceCheckUtils]: 92: Hoare triple {41246#false} assume !(1 == ~E_6~0); {41246#false} is VALID [2022-02-21 04:22:10,579 INFO L290 TraceCheckUtils]: 93: Hoare triple {41246#false} assume !(1 == ~E_7~0); {41246#false} is VALID [2022-02-21 04:22:10,579 INFO L290 TraceCheckUtils]: 94: Hoare triple {41246#false} assume { :end_inline_reset_delta_events } true; {41246#false} is VALID [2022-02-21 04:22:10,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,579 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,580 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986199480] [2022-02-21 04:22:10,580 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986199480] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,580 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,580 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,580 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613216264] [2022-02-21 04:22:10,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,582 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:10,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:10,582 INFO L85 PathProgramCache]: Analyzing trace with hash 176561758, now seen corresponding path program 1 times [2022-02-21 04:22:10,582 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:10,584 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445371217] [2022-02-21 04:22:10,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:10,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:10,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:10,618 INFO L290 TraceCheckUtils]: 0: Hoare triple {41249#true} assume !false; {41249#true} is VALID [2022-02-21 04:22:10,618 INFO L290 TraceCheckUtils]: 1: Hoare triple {41249#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {41249#true} is VALID [2022-02-21 04:22:10,618 INFO L290 TraceCheckUtils]: 2: Hoare triple {41249#true} assume !false; {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 3: Hoare triple {41249#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 4: Hoare triple {41249#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 5: Hoare triple {41249#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 6: Hoare triple {41249#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 7: Hoare triple {41249#true} assume !(0 != eval_~tmp~0#1); {41249#true} is VALID [2022-02-21 04:22:10,619 INFO L290 TraceCheckUtils]: 8: Hoare triple {41249#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 9: Hoare triple {41249#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 10: Hoare triple {41249#true} assume 0 == ~M_E~0;~M_E~0 := 1; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 11: Hoare triple {41249#true} assume !(0 == ~T1_E~0); {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 12: Hoare triple {41249#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 13: Hoare triple {41249#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 14: Hoare triple {41249#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {41249#true} is VALID [2022-02-21 04:22:10,620 INFO L290 TraceCheckUtils]: 15: Hoare triple {41249#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {41249#true} is VALID [2022-02-21 04:22:10,621 INFO L290 TraceCheckUtils]: 16: Hoare triple {41249#true} assume !(0 == ~T6_E~0); {41249#true} is VALID [2022-02-21 04:22:10,621 INFO L290 TraceCheckUtils]: 17: Hoare triple {41249#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,621 INFO L290 TraceCheckUtils]: 18: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,622 INFO L290 TraceCheckUtils]: 19: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,622 INFO L290 TraceCheckUtils]: 20: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,622 INFO L290 TraceCheckUtils]: 21: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,623 INFO L290 TraceCheckUtils]: 22: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,623 INFO L290 TraceCheckUtils]: 23: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,623 INFO L290 TraceCheckUtils]: 24: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,624 INFO L290 TraceCheckUtils]: 25: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,624 INFO L290 TraceCheckUtils]: 26: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,624 INFO L290 TraceCheckUtils]: 27: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,625 INFO L290 TraceCheckUtils]: 28: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,625 INFO L290 TraceCheckUtils]: 29: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,625 INFO L290 TraceCheckUtils]: 30: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,626 INFO L290 TraceCheckUtils]: 31: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,626 INFO L290 TraceCheckUtils]: 32: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,627 INFO L290 TraceCheckUtils]: 33: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t1_pc~0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,627 INFO L290 TraceCheckUtils]: 34: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,627 INFO L290 TraceCheckUtils]: 35: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,628 INFO L290 TraceCheckUtils]: 36: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,628 INFO L290 TraceCheckUtils]: 37: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,628 INFO L290 TraceCheckUtils]: 38: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,629 INFO L290 TraceCheckUtils]: 39: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,629 INFO L290 TraceCheckUtils]: 40: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,629 INFO L290 TraceCheckUtils]: 41: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,630 INFO L290 TraceCheckUtils]: 42: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,630 INFO L290 TraceCheckUtils]: 43: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,630 INFO L290 TraceCheckUtils]: 44: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,631 INFO L290 TraceCheckUtils]: 45: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,631 INFO L290 TraceCheckUtils]: 46: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,631 INFO L290 TraceCheckUtils]: 47: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,632 INFO L290 TraceCheckUtils]: 48: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,632 INFO L290 TraceCheckUtils]: 49: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,633 INFO L290 TraceCheckUtils]: 50: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,633 INFO L290 TraceCheckUtils]: 51: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t4_pc~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,633 INFO L290 TraceCheckUtils]: 52: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_~__retres1~4#1 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,634 INFO L290 TraceCheckUtils]: 53: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,634 INFO L290 TraceCheckUtils]: 54: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,634 INFO L290 TraceCheckUtils]: 55: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,635 INFO L290 TraceCheckUtils]: 56: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,635 INFO L290 TraceCheckUtils]: 57: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,635 INFO L290 TraceCheckUtils]: 58: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,636 INFO L290 TraceCheckUtils]: 59: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,636 INFO L290 TraceCheckUtils]: 60: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,636 INFO L290 TraceCheckUtils]: 61: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,637 INFO L290 TraceCheckUtils]: 62: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,637 INFO L290 TraceCheckUtils]: 63: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,637 INFO L290 TraceCheckUtils]: 64: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,638 INFO L290 TraceCheckUtils]: 65: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,638 INFO L290 TraceCheckUtils]: 66: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,639 INFO L290 TraceCheckUtils]: 67: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,639 INFO L290 TraceCheckUtils]: 68: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,639 INFO L290 TraceCheckUtils]: 69: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,640 INFO L290 TraceCheckUtils]: 70: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,640 INFO L290 TraceCheckUtils]: 71: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,640 INFO L290 TraceCheckUtils]: 72: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,641 INFO L290 TraceCheckUtils]: 73: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,641 INFO L290 TraceCheckUtils]: 74: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,641 INFO L290 TraceCheckUtils]: 75: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,642 INFO L290 TraceCheckUtils]: 76: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,642 INFO L290 TraceCheckUtils]: 77: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,642 INFO L290 TraceCheckUtils]: 78: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,643 INFO L290 TraceCheckUtils]: 79: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,643 INFO L290 TraceCheckUtils]: 80: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,643 INFO L290 TraceCheckUtils]: 81: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {41251#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 82: Hoare triple {41251#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {41250#false} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 83: Hoare triple {41250#false} assume 1 == ~E_M~0;~E_M~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 84: Hoare triple {41250#false} assume 1 == ~E_1~0;~E_1~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 85: Hoare triple {41250#false} assume 1 == ~E_2~0;~E_2~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 86: Hoare triple {41250#false} assume 1 == ~E_3~0;~E_3~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,644 INFO L290 TraceCheckUtils]: 87: Hoare triple {41250#false} assume 1 == ~E_4~0;~E_4~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,645 INFO L290 TraceCheckUtils]: 88: Hoare triple {41250#false} assume 1 == ~E_5~0;~E_5~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,645 INFO L290 TraceCheckUtils]: 89: Hoare triple {41250#false} assume 1 == ~E_6~0;~E_6~0 := 2; {41250#false} is VALID [2022-02-21 04:22:10,645 INFO L290 TraceCheckUtils]: 90: Hoare triple {41250#false} assume !(1 == ~E_7~0); {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 91: Hoare triple {41250#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 92: Hoare triple {41250#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 93: Hoare triple {41250#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 94: Hoare triple {41250#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 95: Hoare triple {41250#false} assume !(0 == start_simulation_~tmp~3#1); {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 96: Hoare triple {41250#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {41250#false} is VALID [2022-02-21 04:22:10,647 INFO L290 TraceCheckUtils]: 97: Hoare triple {41250#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 98: Hoare triple {41250#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 99: Hoare triple {41250#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 100: Hoare triple {41250#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 101: Hoare triple {41250#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 102: Hoare triple {41250#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {41250#false} is VALID [2022-02-21 04:22:10,648 INFO L290 TraceCheckUtils]: 103: Hoare triple {41250#false} assume !(0 != start_simulation_~tmp___0~1#1); {41250#false} is VALID [2022-02-21 04:22:10,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:10,649 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:10,649 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445371217] [2022-02-21 04:22:10,649 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445371217] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:10,649 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:10,650 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:10,650 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386727075] [2022-02-21 04:22:10,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:10,650 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:10,650 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:10,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:10,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:10,651 INFO L87 Difference]: Start difference. First operand 2721 states and 4025 transitions. cyclomatic complexity: 1308 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:13,910 INFO L93 Difference]: Finished difference Result 7498 states and 10918 transitions. [2022-02-21 04:22:13,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:13,910 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:13,966 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:13,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7498 states and 10918 transitions. [2022-02-21 04:22:15,127 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7117 [2022-02-21 04:22:16,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7498 states to 7498 states and 10918 transitions. [2022-02-21 04:22:16,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7498 [2022-02-21 04:22:16,325 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7498 [2022-02-21 04:22:16,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7498 states and 10918 transitions. [2022-02-21 04:22:16,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:16,333 INFO L681 BuchiCegarLoop]: Abstraction has 7498 states and 10918 transitions. [2022-02-21 04:22:16,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7498 states and 10918 transitions. [2022-02-21 04:22:16,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7498 to 7066. [2022-02-21 04:22:16,446 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:16,456 INFO L82 GeneralOperation]: Start isEquivalent. First operand 7498 states and 10918 transitions. Second operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,464 INFO L74 IsIncluded]: Start isIncluded. First operand 7498 states and 10918 transitions. Second operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:16,473 INFO L87 Difference]: Start difference. First operand 7498 states and 10918 transitions. Second operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:17,738 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:17,738 INFO L93 Difference]: Finished difference Result 7498 states and 10918 transitions. [2022-02-21 04:22:17,738 INFO L276 IsEmpty]: Start isEmpty. Operand 7498 states and 10918 transitions. [2022-02-21 04:22:17,745 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:17,745 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:17,755 INFO L74 IsIncluded]: Start isIncluded. First operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7498 states and 10918 transitions. [2022-02-21 04:22:17,762 INFO L87 Difference]: Start difference. First operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 7498 states and 10918 transitions. [2022-02-21 04:22:18,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:18,969 INFO L93 Difference]: Finished difference Result 7498 states and 10918 transitions. [2022-02-21 04:22:18,969 INFO L276 IsEmpty]: Start isEmpty. Operand 7498 states and 10918 transitions. [2022-02-21 04:22:18,976 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:18,977 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:18,977 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-02-21 04:22:18,977 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-02-21 04:22:18,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7066 states, 7066 states have (on average 1.4613642796490236) internal successors, (10326), 7065 states have internal predecessors, (10326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:20,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7066 states to 7066 states and 10326 transitions. [2022-02-21 04:22:20,072 INFO L704 BuchiCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-02-21 04:22:20,072 INFO L587 BuchiCegarLoop]: Abstraction has 7066 states and 10326 transitions. [2022-02-21 04:22:20,072 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2022-02-21 04:22:20,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7066 states and 10326 transitions. [2022-02-21 04:22:20,086 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6917 [2022-02-21 04:22:20,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2022-02-21 04:22:20,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2022-02-21 04:22:20,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:20,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-02-21 04:22:20,088 INFO L791 eck$LassoCheckResult]: Stem: 49462#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 49463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 48839#L1153 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48840#L541 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49748#L548 assume 1 == ~m_i~0;~m_st~0 := 0; 49153#L548-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49154#L553-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49286#L558-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49287#L563-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49060#L568-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48835#L573-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48836#L578-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49014#L583-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49015#L781 assume !(0 == ~M_E~0); 49568#L781-2 assume !(0 == ~T1_E~0); 49842#L786-1 assume !(0 == ~T2_E~0); 48796#L791-1 assume !(0 == ~T3_E~0); 48797#L796-1 assume !(0 == ~T4_E~0); 49374#L801-1 assume !(0 == ~T5_E~0); 49375#L806-1 assume !(0 == ~T6_E~0); 49417#L811-1 assume !(0 == ~T7_E~0); 49024#L816-1 assume !(0 == ~E_M~0); 49025#L821-1 assume !(0 == ~E_1~0); 48824#L826-1 assume !(0 == ~E_2~0); 48825#L831-1 assume !(0 == ~E_3~0); 49150#L836-1 assume !(0 == ~E_4~0); 49151#L841-1 assume !(0 == ~E_5~0); 48974#L846-1 assume !(0 == ~E_6~0); 48975#L851-1 assume !(0 == ~E_7~0); 48999#L856-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49000#L388 assume !(1 == ~m_pc~0); 48993#L388-2 is_master_triggered_~__retres1~0#1 := 0; 48994#L399 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49528#L400 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48843#L967 assume !(0 != activate_threads_~tmp~1#1); 48844#L967-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48773#L407 assume !(1 == ~t1_pc~0); 48774#L407-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48777#L418 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48752#L419 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48753#L975 assume !(0 != activate_threads_~tmp___0~0#1); 49684#L975-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49109#L426 assume !(1 == ~t2_pc~0); 49110#L426-2 is_transmit2_triggered_~__retres1~2#1 := 0; 49712#L437 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49796#L438 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49789#L983 assume !(0 != activate_threads_~tmp___1~0#1); 49790#L983-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49192#L445 assume 1 == ~t3_pc~0; 49193#L446 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49575#L456 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48995#L457 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48996#L991 assume !(0 != activate_threads_~tmp___2~0#1); 49484#L991-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49447#L464 assume !(1 == ~t4_pc~0); 49002#L464-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48864#L475 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48865#L476 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49203#L999 assume !(0 != activate_threads_~tmp___3~0#1); 49168#L999-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49169#L483 assume 1 == ~t5_pc~0; 49444#L484 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49655#L494 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49353#L495 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49354#L1007 assume !(0 != activate_threads_~tmp___4~0#1); 49093#L1007-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49094#L502 assume 1 == ~t6_pc~0; 49414#L503 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48898#L513 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48899#L514 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49330#L1015 assume !(0 != activate_threads_~tmp___5~0#1); 49331#L1015-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49619#L521 assume !(1 == ~t7_pc~0); 49680#L521-2 is_transmit7_triggered_~__retres1~7#1 := 0; 48837#L532 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48838#L533 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48951#L1023 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49631#L1023-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49515#L869 assume 1 == ~M_E~0;~M_E~0 := 2; 49516#L869-2 assume !(1 == ~T1_E~0); 52842#L874-1 assume !(1 == ~T2_E~0); 52841#L879-1 assume !(1 == ~T3_E~0); 52840#L884-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52839#L889-1 assume !(1 == ~T5_E~0); 52838#L894-1 assume !(1 == ~T6_E~0); 52837#L899-1 assume !(1 == ~T7_E~0); 52836#L904-1 assume !(1 == ~E_M~0); 52835#L909-1 assume !(1 == ~E_1~0); 52834#L914-1 assume !(1 == ~E_2~0); 49425#L919-1 assume !(1 == ~E_3~0); 49108#L924-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48938#L929-1 assume !(1 == ~E_5~0); 48939#L934-1 assume !(1 == ~E_6~0); 49751#L939-1 assume !(1 == ~E_7~0); 53835#L944-1 assume { :end_inline_reset_delta_events } true; 53829#L1190-2 [2022-02-21 04:22:20,089 INFO L793 eck$LassoCheckResult]: Loop: 53829#L1190-2 assume !false; 53824#L1191 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53823#L756 assume !false; 53822#L649 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53821#L596 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53813#L638 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53812#L639 eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 53810#L653 assume !(0 != eval_~tmp~0#1); 53809#L771 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53808#L541-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53805#L781-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53806#L781-5 assume !(0 == ~T1_E~0); 54404#L786-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54403#L791-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54402#L796-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54401#L801-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54400#L806-3 assume !(0 == ~T6_E~0); 54399#L811-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54398#L816-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54397#L821-3 assume !(0 == ~E_1~0); 54396#L826-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54395#L831-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54394#L836-3 assume 0 == ~E_4~0;~E_4~0 := 1; 54393#L841-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54392#L846-3 assume !(0 == ~E_6~0); 54391#L851-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54390#L856-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50911#L388-27 assume !(1 == ~m_pc~0); 50910#L388-29 is_master_triggered_~__retres1~0#1 := 0; 50909#L399-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50908#L400-9 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50907#L967-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 50906#L967-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50905#L407-27 assume !(1 == ~t1_pc~0); 50903#L407-29 is_transmit1_triggered_~__retres1~1#1 := 0; 50901#L418-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50899#L419-9 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50896#L975-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 50894#L975-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50892#L426-27 assume !(1 == ~t2_pc~0); 50889#L426-29 is_transmit2_triggered_~__retres1~2#1 := 0; 50886#L437-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50884#L438-9 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 50882#L983-27 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50879#L983-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50877#L445-27 assume 1 == ~t3_pc~0; 50817#L446-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50815#L456-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50813#L457-9 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 50809#L991-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50794#L991-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50783#L464-27 assume 1 == ~t4_pc~0; 50784#L465-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54273#L475-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54271#L476-9 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 54269#L999-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54267#L999-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54265#L483-27 assume 1 == ~t5_pc~0; 54093#L484-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54091#L494-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54089#L495-9 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54087#L1007-27 assume !(0 != activate_threads_~tmp___4~0#1); 54085#L1007-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54084#L502-27 assume 1 == ~t6_pc~0; 54080#L503-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54078#L513-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54075#L514-9 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53948#L1015-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53945#L1015-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53942#L521-27 assume !(1 == ~t7_pc~0); 53938#L521-29 is_transmit7_triggered_~__retres1~7#1 := 0; 53935#L532-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53931#L533-9 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53928#L1023-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53925#L1023-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53923#L869-3 assume 1 == ~M_E~0;~M_E~0 := 2; 50529#L869-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53920#L874-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53917#L879-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53915#L884-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53914#L889-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53913#L894-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 50506#L899-3 assume !(1 == ~T7_E~0); 50507#L904-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50498#L909-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50499#L914-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53902#L919-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50484#L924-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50485#L929-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53896#L934-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53893#L939-3 assume !(1 == ~E_7~0); 53892#L944-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53888#L596-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53880#L638-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53878#L639-1 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 53876#L1209 assume !(0 == start_simulation_~tmp~3#1); 49334#L1209-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 53871#L596-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 53862#L638-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 53860#L639-2 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 53858#L1164 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53857#L1171 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53843#L1172 start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 53836#L1222 assume !(0 != start_simulation_~tmp___0~1#1); 53829#L1190-2 [2022-02-21 04:22:20,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:20,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1285267206, now seen corresponding path program 1 times [2022-02-21 04:22:20,090 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:20,090 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936450044] [2022-02-21 04:22:20,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:20,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:20,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:20,116 INFO L290 TraceCheckUtils]: 0: Hoare triple {70817#true} assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,117 INFO L290 TraceCheckUtils]: 1: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,117 INFO L290 TraceCheckUtils]: 2: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,117 INFO L290 TraceCheckUtils]: 3: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,118 INFO L290 TraceCheckUtils]: 4: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~m_i~0;~m_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,118 INFO L290 TraceCheckUtils]: 5: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t1_i~0;~t1_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,119 INFO L290 TraceCheckUtils]: 6: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t2_i~0;~t2_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,119 INFO L290 TraceCheckUtils]: 7: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t3_i~0;~t3_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,119 INFO L290 TraceCheckUtils]: 8: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t4_i~0;~t4_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,120 INFO L290 TraceCheckUtils]: 9: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t5_i~0;~t5_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,120 INFO L290 TraceCheckUtils]: 10: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t6_i~0;~t6_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,121 INFO L290 TraceCheckUtils]: 11: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume 1 == ~t7_i~0;~t7_st~0 := 0; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,121 INFO L290 TraceCheckUtils]: 12: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,121 INFO L290 TraceCheckUtils]: 13: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~M_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,122 INFO L290 TraceCheckUtils]: 14: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T1_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,122 INFO L290 TraceCheckUtils]: 15: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T2_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,122 INFO L290 TraceCheckUtils]: 16: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T3_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,123 INFO L290 TraceCheckUtils]: 17: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T4_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,123 INFO L290 TraceCheckUtils]: 18: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T5_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,124 INFO L290 TraceCheckUtils]: 19: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T6_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,124 INFO L290 TraceCheckUtils]: 20: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~T7_E~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,124 INFO L290 TraceCheckUtils]: 21: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_M~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,125 INFO L290 TraceCheckUtils]: 22: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_1~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,125 INFO L290 TraceCheckUtils]: 23: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_2~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,126 INFO L290 TraceCheckUtils]: 24: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_3~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,126 INFO L290 TraceCheckUtils]: 25: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_4~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,126 INFO L290 TraceCheckUtils]: 26: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_5~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,127 INFO L290 TraceCheckUtils]: 27: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_6~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,127 INFO L290 TraceCheckUtils]: 28: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(0 == ~E_7~0); {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,127 INFO L290 TraceCheckUtils]: 29: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70819#(= ~m_pc~0 ~t3_pc~0)} is VALID [2022-02-21 04:22:20,128 INFO L290 TraceCheckUtils]: 30: Hoare triple {70819#(= ~m_pc~0 ~t3_pc~0)} assume !(1 == ~m_pc~0); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,128 INFO L290 TraceCheckUtils]: 31: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_master_triggered_~__retres1~0#1 := 0; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,128 INFO L290 TraceCheckUtils]: 32: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,129 INFO L290 TraceCheckUtils]: 33: Hoare triple {70820#(not (= ~t3_pc~0 1))} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,129 INFO L290 TraceCheckUtils]: 34: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp~1#1); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,130 INFO L290 TraceCheckUtils]: 35: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,130 INFO L290 TraceCheckUtils]: 36: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume !(1 == ~t1_pc~0); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,130 INFO L290 TraceCheckUtils]: 37: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_transmit1_triggered_~__retres1~1#1 := 0; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,131 INFO L290 TraceCheckUtils]: 38: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,131 INFO L290 TraceCheckUtils]: 39: Hoare triple {70820#(not (= ~t3_pc~0 1))} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,131 INFO L290 TraceCheckUtils]: 40: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___0~0#1); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,132 INFO L290 TraceCheckUtils]: 41: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,132 INFO L290 TraceCheckUtils]: 42: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume !(1 == ~t2_pc~0); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,132 INFO L290 TraceCheckUtils]: 43: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_transmit2_triggered_~__retres1~2#1 := 0; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,133 INFO L290 TraceCheckUtils]: 44: Hoare triple {70820#(not (= ~t3_pc~0 1))} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,133 INFO L290 TraceCheckUtils]: 45: Hoare triple {70820#(not (= ~t3_pc~0 1))} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,133 INFO L290 TraceCheckUtils]: 46: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume !(0 != activate_threads_~tmp___1~0#1); {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,134 INFO L290 TraceCheckUtils]: 47: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70820#(not (= ~t3_pc~0 1))} is VALID [2022-02-21 04:22:20,134 INFO L290 TraceCheckUtils]: 48: Hoare triple {70820#(not (= ~t3_pc~0 1))} assume 1 == ~t3_pc~0; {70818#false} is VALID [2022-02-21 04:22:20,134 INFO L290 TraceCheckUtils]: 49: Hoare triple {70818#false} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70818#false} is VALID [2022-02-21 04:22:20,134 INFO L290 TraceCheckUtils]: 50: Hoare triple {70818#false} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70818#false} is VALID [2022-02-21 04:22:20,134 INFO L290 TraceCheckUtils]: 51: Hoare triple {70818#false} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 52: Hoare triple {70818#false} assume !(0 != activate_threads_~tmp___2~0#1); {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 53: Hoare triple {70818#false} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 54: Hoare triple {70818#false} assume !(1 == ~t4_pc~0); {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 55: Hoare triple {70818#false} is_transmit4_triggered_~__retres1~4#1 := 0; {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 56: Hoare triple {70818#false} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 57: Hoare triple {70818#false} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70818#false} is VALID [2022-02-21 04:22:20,135 INFO L290 TraceCheckUtils]: 58: Hoare triple {70818#false} assume !(0 != activate_threads_~tmp___3~0#1); {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 59: Hoare triple {70818#false} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 60: Hoare triple {70818#false} assume 1 == ~t5_pc~0; {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 61: Hoare triple {70818#false} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 62: Hoare triple {70818#false} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 63: Hoare triple {70818#false} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 64: Hoare triple {70818#false} assume !(0 != activate_threads_~tmp___4~0#1); {70818#false} is VALID [2022-02-21 04:22:20,136 INFO L290 TraceCheckUtils]: 65: Hoare triple {70818#false} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 66: Hoare triple {70818#false} assume 1 == ~t6_pc~0; {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 67: Hoare triple {70818#false} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 68: Hoare triple {70818#false} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 69: Hoare triple {70818#false} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 70: Hoare triple {70818#false} assume !(0 != activate_threads_~tmp___5~0#1); {70818#false} is VALID [2022-02-21 04:22:20,137 INFO L290 TraceCheckUtils]: 71: Hoare triple {70818#false} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 72: Hoare triple {70818#false} assume !(1 == ~t7_pc~0); {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 73: Hoare triple {70818#false} is_transmit7_triggered_~__retres1~7#1 := 0; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 74: Hoare triple {70818#false} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 75: Hoare triple {70818#false} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 76: Hoare triple {70818#false} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 77: Hoare triple {70818#false} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70818#false} is VALID [2022-02-21 04:22:20,138 INFO L290 TraceCheckUtils]: 78: Hoare triple {70818#false} assume 1 == ~M_E~0;~M_E~0 := 2; {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 79: Hoare triple {70818#false} assume !(1 == ~T1_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 80: Hoare triple {70818#false} assume !(1 == ~T2_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 81: Hoare triple {70818#false} assume !(1 == ~T3_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 82: Hoare triple {70818#false} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 83: Hoare triple {70818#false} assume !(1 == ~T5_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 84: Hoare triple {70818#false} assume !(1 == ~T6_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 85: Hoare triple {70818#false} assume !(1 == ~T7_E~0); {70818#false} is VALID [2022-02-21 04:22:20,139 INFO L290 TraceCheckUtils]: 86: Hoare triple {70818#false} assume !(1 == ~E_M~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 87: Hoare triple {70818#false} assume !(1 == ~E_1~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 88: Hoare triple {70818#false} assume !(1 == ~E_2~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 89: Hoare triple {70818#false} assume !(1 == ~E_3~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 90: Hoare triple {70818#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 91: Hoare triple {70818#false} assume !(1 == ~E_5~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 92: Hoare triple {70818#false} assume !(1 == ~E_6~0); {70818#false} is VALID [2022-02-21 04:22:20,140 INFO L290 TraceCheckUtils]: 93: Hoare triple {70818#false} assume !(1 == ~E_7~0); {70818#false} is VALID [2022-02-21 04:22:20,141 INFO L290 TraceCheckUtils]: 94: Hoare triple {70818#false} assume { :end_inline_reset_delta_events } true; {70818#false} is VALID [2022-02-21 04:22:20,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:20,141 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:20,141 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936450044] [2022-02-21 04:22:20,141 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936450044] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:20,142 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:20,142 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:20,142 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435303507] [2022-02-21 04:22:20,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:20,142 INFO L796 eck$LassoCheckResult]: stem already infeasible [2022-02-21 04:22:20,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-02-21 04:22:20,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1504980962, now seen corresponding path program 1 times [2022-02-21 04:22:20,143 INFO L126 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-02-21 04:22:20,143 INFO L338 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052826077] [2022-02-21 04:22:20,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-02-21 04:22:20,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-02-21 04:22:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-02-21 04:22:20,213 INFO L290 TraceCheckUtils]: 0: Hoare triple {70821#true} assume !false; {70821#true} is VALID [2022-02-21 04:22:20,213 INFO L290 TraceCheckUtils]: 1: Hoare triple {70821#true} start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; {70821#true} is VALID [2022-02-21 04:22:20,213 INFO L290 TraceCheckUtils]: 2: Hoare triple {70821#true} assume !false; {70821#true} is VALID [2022-02-21 04:22:20,213 INFO L290 TraceCheckUtils]: 3: Hoare triple {70821#true} assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70821#true} is VALID [2022-02-21 04:22:20,214 INFO L290 TraceCheckUtils]: 4: Hoare triple {70821#true} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70821#true} is VALID [2022-02-21 04:22:20,214 INFO L290 TraceCheckUtils]: 5: Hoare triple {70821#true} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70821#true} is VALID [2022-02-21 04:22:20,215 INFO L290 TraceCheckUtils]: 6: Hoare triple {70821#true} eval_#t~ret6#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; {70821#true} is VALID [2022-02-21 04:22:20,215 INFO L290 TraceCheckUtils]: 7: Hoare triple {70821#true} assume !(0 != eval_~tmp~0#1); {70821#true} is VALID [2022-02-21 04:22:20,215 INFO L290 TraceCheckUtils]: 8: Hoare triple {70821#true} assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 9: Hoare triple {70821#true} assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 10: Hoare triple {70821#true} assume 0 == ~M_E~0;~M_E~0 := 1; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 11: Hoare triple {70821#true} assume !(0 == ~T1_E~0); {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 12: Hoare triple {70821#true} assume 0 == ~T2_E~0;~T2_E~0 := 1; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 13: Hoare triple {70821#true} assume 0 == ~T3_E~0;~T3_E~0 := 1; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 14: Hoare triple {70821#true} assume 0 == ~T4_E~0;~T4_E~0 := 1; {70821#true} is VALID [2022-02-21 04:22:20,216 INFO L290 TraceCheckUtils]: 15: Hoare triple {70821#true} assume 0 == ~T5_E~0;~T5_E~0 := 1; {70821#true} is VALID [2022-02-21 04:22:20,217 INFO L290 TraceCheckUtils]: 16: Hoare triple {70821#true} assume !(0 == ~T6_E~0); {70821#true} is VALID [2022-02-21 04:22:20,217 INFO L290 TraceCheckUtils]: 17: Hoare triple {70821#true} assume 0 == ~T7_E~0;~T7_E~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,218 INFO L290 TraceCheckUtils]: 18: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_M~0;~E_M~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,218 INFO L290 TraceCheckUtils]: 19: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_1~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,218 INFO L290 TraceCheckUtils]: 20: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_2~0;~E_2~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,219 INFO L290 TraceCheckUtils]: 21: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_3~0;~E_3~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,219 INFO L290 TraceCheckUtils]: 22: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_4~0;~E_4~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,219 INFO L290 TraceCheckUtils]: 23: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_5~0;~E_5~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,220 INFO L290 TraceCheckUtils]: 24: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 == ~E_6~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,220 INFO L290 TraceCheckUtils]: 25: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 == ~E_7~0;~E_7~0 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,220 INFO L290 TraceCheckUtils]: 26: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,221 INFO L290 TraceCheckUtils]: 27: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~m_pc~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,221 INFO L290 TraceCheckUtils]: 28: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_~__retres1~0#1 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,222 INFO L290 TraceCheckUtils]: 29: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,222 INFO L290 TraceCheckUtils]: 30: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret15#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,222 INFO L290 TraceCheckUtils]: 31: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,223 INFO L290 TraceCheckUtils]: 32: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,223 INFO L290 TraceCheckUtils]: 33: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t1_pc~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,223 INFO L290 TraceCheckUtils]: 34: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_~__retres1~1#1 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,224 INFO L290 TraceCheckUtils]: 35: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,224 INFO L290 TraceCheckUtils]: 36: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,225 INFO L290 TraceCheckUtils]: 37: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,225 INFO L290 TraceCheckUtils]: 38: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,225 INFO L290 TraceCheckUtils]: 39: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t2_pc~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,226 INFO L290 TraceCheckUtils]: 40: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_~__retres1~2#1 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,226 INFO L290 TraceCheckUtils]: 41: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,226 INFO L290 TraceCheckUtils]: 42: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,227 INFO L290 TraceCheckUtils]: 43: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,227 INFO L290 TraceCheckUtils]: 44: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,227 INFO L290 TraceCheckUtils]: 45: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t3_pc~0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,228 INFO L290 TraceCheckUtils]: 46: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,228 INFO L290 TraceCheckUtils]: 47: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,229 INFO L290 TraceCheckUtils]: 48: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,229 INFO L290 TraceCheckUtils]: 49: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,229 INFO L290 TraceCheckUtils]: 50: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,230 INFO L290 TraceCheckUtils]: 51: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t4_pc~0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,230 INFO L290 TraceCheckUtils]: 52: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,230 INFO L290 TraceCheckUtils]: 53: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,231 INFO L290 TraceCheckUtils]: 54: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,231 INFO L290 TraceCheckUtils]: 55: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,232 INFO L290 TraceCheckUtils]: 56: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,232 INFO L290 TraceCheckUtils]: 57: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t5_pc~0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,232 INFO L290 TraceCheckUtils]: 58: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,233 INFO L290 TraceCheckUtils]: 59: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,233 INFO L290 TraceCheckUtils]: 60: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,233 INFO L290 TraceCheckUtils]: 61: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(0 != activate_threads_~tmp___4~0#1); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,234 INFO L290 TraceCheckUtils]: 62: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,234 INFO L290 TraceCheckUtils]: 63: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~t6_pc~0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,234 INFO L290 TraceCheckUtils]: 64: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,235 INFO L290 TraceCheckUtils]: 65: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,235 INFO L290 TraceCheckUtils]: 66: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,236 INFO L290 TraceCheckUtils]: 67: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,236 INFO L290 TraceCheckUtils]: 68: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,236 INFO L290 TraceCheckUtils]: 69: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~t7_pc~0); {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,237 INFO L290 TraceCheckUtils]: 70: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_~__retres1~7#1 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,237 INFO L290 TraceCheckUtils]: 71: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,237 INFO L290 TraceCheckUtils]: 72: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,238 INFO L290 TraceCheckUtils]: 73: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,238 INFO L290 TraceCheckUtils]: 74: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,238 INFO L290 TraceCheckUtils]: 75: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~M_E~0;~M_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,239 INFO L290 TraceCheckUtils]: 76: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T1_E~0;~T1_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,239 INFO L290 TraceCheckUtils]: 77: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T2_E~0;~T2_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,240 INFO L290 TraceCheckUtils]: 78: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T3_E~0;~T3_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,240 INFO L290 TraceCheckUtils]: 79: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T4_E~0;~T4_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,240 INFO L290 TraceCheckUtils]: 80: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T5_E~0;~T5_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,241 INFO L290 TraceCheckUtils]: 81: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume 1 == ~T6_E~0;~T6_E~0 := 2; {70823#(= (+ (- 1) ~T7_E~0) 0)} is VALID [2022-02-21 04:22:20,241 INFO L290 TraceCheckUtils]: 82: Hoare triple {70823#(= (+ (- 1) ~T7_E~0) 0)} assume !(1 == ~T7_E~0); {70822#false} is VALID [2022-02-21 04:22:20,241 INFO L290 TraceCheckUtils]: 83: Hoare triple {70822#false} assume 1 == ~E_M~0;~E_M~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,241 INFO L290 TraceCheckUtils]: 84: Hoare triple {70822#false} assume 1 == ~E_1~0;~E_1~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 85: Hoare triple {70822#false} assume 1 == ~E_2~0;~E_2~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 86: Hoare triple {70822#false} assume 1 == ~E_3~0;~E_3~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 87: Hoare triple {70822#false} assume 1 == ~E_4~0;~E_4~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 88: Hoare triple {70822#false} assume 1 == ~E_5~0;~E_5~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 89: Hoare triple {70822#false} assume 1 == ~E_6~0;~E_6~0 := 2; {70822#false} is VALID [2022-02-21 04:22:20,242 INFO L290 TraceCheckUtils]: 90: Hoare triple {70822#false} assume !(1 == ~E_7~0); {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 91: Hoare triple {70822#false} assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 92: Hoare triple {70822#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 93: Hoare triple {70822#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 94: Hoare triple {70822#false} start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 95: Hoare triple {70822#false} assume !(0 == start_simulation_~tmp~3#1); {70822#false} is VALID [2022-02-21 04:22:20,243 INFO L290 TraceCheckUtils]: 96: Hoare triple {70822#false} assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 97: Hoare triple {70822#false} assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 98: Hoare triple {70822#false} exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 99: Hoare triple {70822#false} stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 100: Hoare triple {70822#false} assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 101: Hoare triple {70822#false} stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; {70822#false} is VALID [2022-02-21 04:22:20,244 INFO L290 TraceCheckUtils]: 102: Hoare triple {70822#false} start_simulation_#t~ret25#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; {70822#false} is VALID [2022-02-21 04:22:20,245 INFO L290 TraceCheckUtils]: 103: Hoare triple {70822#false} assume !(0 != start_simulation_~tmp___0~1#1); {70822#false} is VALID [2022-02-21 04:22:20,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-02-21 04:22:20,245 INFO L144 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-02-21 04:22:20,245 INFO L338 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052826077] [2022-02-21 04:22:20,246 INFO L165 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052826077] provided 1 perfect and 0 imperfect interpolant sequences [2022-02-21 04:22:20,246 INFO L191 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-02-21 04:22:20,246 INFO L204 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-02-21 04:22:20,246 INFO L118 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1134346036] [2022-02-21 04:22:20,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-02-21 04:22:20,247 INFO L808 eck$LassoCheckResult]: loop already infeasible [2022-02-21 04:22:20,247 INFO L108 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-02-21 04:22:20,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-02-21 04:22:20,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-02-21 04:22:20,248 INFO L87 Difference]: Start difference. First operand 7066 states and 10326 transitions. cyclomatic complexity: 3268 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:29,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:29,957 INFO L93 Difference]: Finished difference Result 19679 states and 28431 transitions. [2022-02-21 04:22:29,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-02-21 04:22:29,957 INFO L86 InductivityCheck]: Starting indutivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 23.75) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:30,013 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-02-21 04:22:30,013 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19679 states and 28431 transitions. [2022-02-21 04:22:38,185 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18975 [2022-02-21 04:22:46,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19679 states to 19679 states and 28431 transitions. [2022-02-21 04:22:46,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19679 [2022-02-21 04:22:46,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19679 [2022-02-21 04:22:46,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19679 states and 28431 transitions. [2022-02-21 04:22:46,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2022-02-21 04:22:46,346 INFO L681 BuchiCegarLoop]: Abstraction has 19679 states and 28431 transitions. [2022-02-21 04:22:46,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19679 states and 28431 transitions. [2022-02-21 04:22:46,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19679 to 18731. [2022-02-21 04:22:46,611 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-02-21 04:22:46,636 INFO L82 GeneralOperation]: Start isEquivalent. First operand 19679 states and 28431 transitions. Second operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:46,662 INFO L74 IsIncluded]: Start isIncluded. First operand 19679 states and 28431 transitions. Second operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:46,686 INFO L87 Difference]: Start difference. First operand 19679 states and 28431 transitions. Second operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-02-21 04:22:54,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-02-21 04:22:54,483 INFO L93 Difference]: Finished difference Result 19679 states and 28431 transitions. [2022-02-21 04:22:54,483 INFO L276 IsEmpty]: Start isEmpty. Operand 19679 states and 28431 transitions. [2022-02-21 04:22:54,501 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-02-21 04:22:54,501 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-02-21 04:22:54,526 INFO L74 IsIncluded]: Start isIncluded. First operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 19679 states and 28431 transitions. [2022-02-21 04:22:54,546 INFO L87 Difference]: Start difference. First operand has 18731 states, 18731 states have (on average 1.4497357322086382) internal successors, (27155), 18730 states have internal predecessors, (27155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand 19679 states and 28431 transitions.